2 * QEMU Malta board support
4 * Copyright (c) 2006 Aurelien Jarno
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
34 #include "mips_cpudevs.h"
36 #include "vmware_vga.h"
37 #include "qemu-char.h"
39 #include "arch_init.h"
42 #include "mips-bios.h"
46 #include "mc146818rtc.h"
49 #include "exec-memory.h"
50 #include "sysbus.h" /* SysBusDevice */
52 //#define DEBUG_BOARD_INIT
54 #define ENVP_ADDR 0x80002000l
55 #define ENVP_NB_ENTRIES 16
56 #define ENVP_ENTRY_SIZE 256
62 MemoryRegion iomem_lo
; /* 0 - 0x900 */
63 MemoryRegion iomem_hi
; /* 0xa00 - 0x100000 */
71 CharDriverState
*display
;
81 static ISADevice
*pit
;
83 static struct _loaderparams
{
85 const char *kernel_filename
;
86 const char *kernel_cmdline
;
87 const char *initrd_filename
;
91 static void malta_fpga_update_display(void *opaque
)
95 MaltaFPGAState
*s
= opaque
;
97 for (i
= 7 ; i
>= 0 ; i
--) {
98 if (s
->leds
& (1 << i
))
105 qemu_chr_fe_printf(s
->display
, "\e[H\n\n|\e[32m%-8.8s\e[00m|\r\n", leds_text
);
106 qemu_chr_fe_printf(s
->display
, "\n\n\n\n|\e[31m%-8.8s\e[00m|", s
->display_text
);
110 * EEPROM 24C01 / 24C02 emulation.
112 * Emulation for serial EEPROMs:
113 * 24C01 - 1024 bit (128 x 8)
114 * 24C02 - 2048 bit (256 x 8)
116 * Typical device names include Microchip 24C02SC or SGS Thomson ST24C02.
122 # define logout(fmt, ...) fprintf(stderr, "MALTA\t%-24s" fmt, __func__, ## __VA_ARGS__)
124 # define logout(fmt, ...) ((void)0)
127 struct _eeprom24c0x_t
{
136 uint8_t contents
[256];
139 typedef struct _eeprom24c0x_t eeprom24c0x_t
;
141 static eeprom24c0x_t eeprom
= {
143 /* 00000000: */ 0x80,0x08,0x04,0x0D,0x0A,0x01,0x40,0x00,
144 /* 00000008: */ 0x01,0x75,0x54,0x00,0x82,0x08,0x00,0x01,
145 /* 00000010: */ 0x8F,0x04,0x02,0x01,0x01,0x00,0x0E,0x00,
146 /* 00000018: */ 0x00,0x00,0x00,0x14,0x0F,0x14,0x2D,0x40,
147 /* 00000020: */ 0x15,0x08,0x15,0x08,0x00,0x00,0x00,0x00,
148 /* 00000028: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
149 /* 00000030: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
150 /* 00000038: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x12,0xD0,
151 /* 00000040: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
152 /* 00000048: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
153 /* 00000050: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
154 /* 00000058: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
155 /* 00000060: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
156 /* 00000068: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
157 /* 00000070: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
158 /* 00000078: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x64,0xF4,
162 static uint8_t eeprom24c0x_read(void)
164 logout("%u: scl = %u, sda = %u, data = 0x%02x\n",
165 eeprom
.tick
, eeprom
.scl
, eeprom
.sda
, eeprom
.data
);
169 static void eeprom24c0x_write(int scl
, int sda
)
171 if (eeprom
.scl
&& scl
&& (eeprom
.sda
!= sda
)) {
172 logout("%u: scl = %u->%u, sda = %u->%u i2c %s\n",
173 eeprom
.tick
, eeprom
.scl
, scl
, eeprom
.sda
, sda
, sda
? "stop" : "start");
178 } else if (eeprom
.tick
== 0 && !eeprom
.ack
) {
179 /* Waiting for start. */
180 logout("%u: scl = %u->%u, sda = %u->%u wait for i2c start\n",
181 eeprom
.tick
, eeprom
.scl
, scl
, eeprom
.sda
, sda
);
182 } else if (!eeprom
.scl
&& scl
) {
183 logout("%u: scl = %u->%u, sda = %u->%u trigger bit\n",
184 eeprom
.tick
, eeprom
.scl
, scl
, eeprom
.sda
, sda
);
186 logout("\ti2c ack bit = 0\n");
189 } else if (eeprom
.sda
== sda
) {
190 uint8_t bit
= (sda
!= 0);
191 logout("\ti2c bit = %d\n", bit
);
192 if (eeprom
.tick
< 9) {
193 eeprom
.command
<<= 1;
194 eeprom
.command
+= bit
;
196 if (eeprom
.tick
== 9) {
197 logout("\tcommand 0x%04x, %s\n", eeprom
.command
, bit
? "read" : "write");
200 } else if (eeprom
.tick
< 17) {
201 if (eeprom
.command
& 1) {
202 sda
= ((eeprom
.data
& 0x80) != 0);
204 eeprom
.address
<<= 1;
205 eeprom
.address
+= bit
;
208 if (eeprom
.tick
== 17) {
209 eeprom
.data
= eeprom
.contents
[eeprom
.address
];
210 logout("\taddress 0x%04x, data 0x%02x\n", eeprom
.address
, eeprom
.data
);
214 } else if (eeprom
.tick
>= 17) {
218 logout("\tsda changed with raising scl\n");
221 logout("%u: scl = %u->%u, sda = %u->%u\n", eeprom
.tick
, eeprom
.scl
, scl
, eeprom
.sda
, sda
);
227 static uint64_t malta_fpga_read(void *opaque
, target_phys_addr_t addr
,
230 MaltaFPGAState
*s
= opaque
;
234 saddr
= (addr
& 0xfffff);
238 /* SWITCH Register */
240 val
= 0x00000000; /* All switches closed */
243 /* STATUS Register */
245 #ifdef TARGET_WORDS_BIGENDIAN
257 /* LEDBAR Register */
262 /* BRKRES Register */
267 /* UART Registers are handled directly by the serial device */
274 /* XXX: implement a real I2C controller */
278 /* IN = OUT until a real I2C control is implemented */
285 /* I2CINP Register */
287 val
= ((s
->i2cin
& ~1) | eeprom24c0x_read());
295 /* I2COUT Register */
300 /* I2CSEL Register */
307 printf ("malta_fpga_read: Bad register offset 0x" TARGET_FMT_lx
"\n",
315 static void malta_fpga_write(void *opaque
, target_phys_addr_t addr
,
316 uint64_t val
, unsigned size
)
318 MaltaFPGAState
*s
= opaque
;
321 saddr
= (addr
& 0xfffff);
325 /* SWITCH Register */
333 /* LEDBAR Register */
334 /* XXX: implement a 8-LED array */
336 s
->leds
= val
& 0xff;
339 /* ASCIIWORD Register */
341 snprintf(s
->display_text
, 9, "%08X", (uint32_t)val
);
342 malta_fpga_update_display(s
);
345 /* ASCIIPOS0 to ASCIIPOS7 Registers */
354 s
->display_text
[(saddr
- 0x00418) >> 3] = (char) val
;
355 malta_fpga_update_display(s
);
358 /* SOFTRES Register */
361 qemu_system_reset_request ();
364 /* BRKRES Register */
369 /* UART Registers are handled directly by the serial device */
373 s
->gpout
= val
& 0xff;
378 s
->i2coe
= val
& 0x03;
381 /* I2COUT Register */
383 eeprom24c0x_write(val
& 0x02, val
& 0x01);
387 /* I2CSEL Register */
389 s
->i2csel
= val
& 0x01;
394 printf ("malta_fpga_write: Bad register offset 0x" TARGET_FMT_lx
"\n",
401 static const MemoryRegionOps malta_fpga_ops
= {
402 .read
= malta_fpga_read
,
403 .write
= malta_fpga_write
,
404 .endianness
= DEVICE_NATIVE_ENDIAN
,
407 static void malta_fpga_reset(void *opaque
)
409 MaltaFPGAState
*s
= opaque
;
419 s
->display_text
[8] = '\0';
420 snprintf(s
->display_text
, 9, " ");
423 static void malta_fpga_led_init(CharDriverState
*chr
)
425 qemu_chr_fe_printf(chr
, "\e[HMalta LEDBAR\r\n");
426 qemu_chr_fe_printf(chr
, "+--------+\r\n");
427 qemu_chr_fe_printf(chr
, "+ +\r\n");
428 qemu_chr_fe_printf(chr
, "+--------+\r\n");
429 qemu_chr_fe_printf(chr
, "\n");
430 qemu_chr_fe_printf(chr
, "Malta ASCII\r\n");
431 qemu_chr_fe_printf(chr
, "+--------+\r\n");
432 qemu_chr_fe_printf(chr
, "+ +\r\n");
433 qemu_chr_fe_printf(chr
, "+--------+\r\n");
436 static MaltaFPGAState
*malta_fpga_init(MemoryRegion
*address_space
,
437 target_phys_addr_t base
, qemu_irq uart_irq
, CharDriverState
*uart_chr
)
441 s
= (MaltaFPGAState
*)g_malloc0(sizeof(MaltaFPGAState
));
443 memory_region_init_io(&s
->iomem
, &malta_fpga_ops
, s
,
444 "malta-fpga", 0x100000);
445 memory_region_init_alias(&s
->iomem_lo
, "malta-fpga",
446 &s
->iomem
, 0, 0x900);
447 memory_region_init_alias(&s
->iomem_hi
, "malta-fpga",
448 &s
->iomem
, 0xa00, 0x10000-0xa00);
450 memory_region_add_subregion(address_space
, base
, &s
->iomem_lo
);
451 memory_region_add_subregion(address_space
, base
+ 0xa00, &s
->iomem_hi
);
453 s
->display
= qemu_chr_new("fpga", "vc:320x200", malta_fpga_led_init
);
455 s
->uart
= serial_mm_init(address_space
, base
+ 0x900, 3, uart_irq
,
456 230400, uart_chr
, DEVICE_NATIVE_ENDIAN
);
459 qemu_register_reset(malta_fpga_reset
, s
);
464 /* Network support */
465 static void network_init(void)
469 for(i
= 0; i
< nb_nics
; i
++) {
470 NICInfo
*nd
= &nd_table
[i
];
471 const char *default_devaddr
= NULL
;
473 if (i
== 0 && (!nd
->model
|| strcmp(nd
->model
, "pcnet") == 0))
474 /* The malta board has a PCNet card using PCI SLOT 11 */
475 default_devaddr
= "0b";
477 pci_nic_init_nofail(nd
, "pcnet", default_devaddr
);
481 /* ROM and pseudo bootloader
483 The following code implements a very very simple bootloader. It first
484 loads the registers a0 to a3 to the values expected by the OS, and
485 then jump at the kernel address.
487 The bootloader should pass the locations of the kernel arguments and
488 environment variables tables. Those tables contain the 32-bit address
489 of NULL terminated strings. The environment variables table should be
490 terminated by a NULL address.
492 For a simpler implementation, the number of kernel arguments is fixed
493 to two (the name of the kernel and the command line), and the two
494 tables are actually the same one.
496 The registers a0 to a3 should contain the following values:
497 a0 - number of kernel arguments
498 a1 - 32-bit address of the kernel arguments table
499 a2 - 32-bit address of the environment variables table
500 a3 - RAM size in bytes
503 static void write_bootloader (CPUMIPSState
*env
, uint8_t *base
,
504 int64_t kernel_entry
)
508 /* Small bootloader */
509 p
= (uint32_t *)base
;
510 stl_raw(p
++, 0x0bf00160); /* j 0x1fc00580 */
511 stl_raw(p
++, 0x00000000); /* nop */
513 /* YAMON service vector */
514 stl_raw(base
+ 0x500, 0xbfc00580); /* start: */
515 stl_raw(base
+ 0x504, 0xbfc0083c); /* print_count: */
516 stl_raw(base
+ 0x520, 0xbfc00580); /* start: */
517 stl_raw(base
+ 0x52c, 0xbfc00800); /* flush_cache: */
518 stl_raw(base
+ 0x534, 0xbfc00808); /* print: */
519 stl_raw(base
+ 0x538, 0xbfc00800); /* reg_cpu_isr: */
520 stl_raw(base
+ 0x53c, 0xbfc00800); /* unred_cpu_isr: */
521 stl_raw(base
+ 0x540, 0xbfc00800); /* reg_ic_isr: */
522 stl_raw(base
+ 0x544, 0xbfc00800); /* unred_ic_isr: */
523 stl_raw(base
+ 0x548, 0xbfc00800); /* reg_esr: */
524 stl_raw(base
+ 0x54c, 0xbfc00800); /* unreg_esr: */
525 stl_raw(base
+ 0x550, 0xbfc00800); /* getchar: */
526 stl_raw(base
+ 0x554, 0xbfc00800); /* syscon_read: */
529 /* Second part of the bootloader */
530 p
= (uint32_t *) (base
+ 0x580);
531 stl_raw(p
++, 0x24040002); /* addiu a0, zero, 2 */
532 stl_raw(p
++, 0x3c1d0000 | (((ENVP_ADDR
- 64) >> 16) & 0xffff)); /* lui sp, high(ENVP_ADDR) */
533 stl_raw(p
++, 0x37bd0000 | ((ENVP_ADDR
- 64) & 0xffff)); /* ori sp, sp, low(ENVP_ADDR) */
534 stl_raw(p
++, 0x3c050000 | ((ENVP_ADDR
>> 16) & 0xffff)); /* lui a1, high(ENVP_ADDR) */
535 stl_raw(p
++, 0x34a50000 | (ENVP_ADDR
& 0xffff)); /* ori a1, a1, low(ENVP_ADDR) */
536 stl_raw(p
++, 0x3c060000 | (((ENVP_ADDR
+ 8) >> 16) & 0xffff)); /* lui a2, high(ENVP_ADDR + 8) */
537 stl_raw(p
++, 0x34c60000 | ((ENVP_ADDR
+ 8) & 0xffff)); /* ori a2, a2, low(ENVP_ADDR + 8) */
538 stl_raw(p
++, 0x3c070000 | (loaderparams
.ram_size
>> 16)); /* lui a3, high(ram_size) */
539 stl_raw(p
++, 0x34e70000 | (loaderparams
.ram_size
& 0xffff)); /* ori a3, a3, low(ram_size) */
541 /* Load BAR registers as done by YAMON */
542 stl_raw(p
++, 0x3c09b400); /* lui t1, 0xb400 */
544 #ifdef TARGET_WORDS_BIGENDIAN
545 stl_raw(p
++, 0x3c08df00); /* lui t0, 0xdf00 */
547 stl_raw(p
++, 0x340800df); /* ori t0, r0, 0x00df */
549 stl_raw(p
++, 0xad280068); /* sw t0, 0x0068(t1) */
551 stl_raw(p
++, 0x3c09bbe0); /* lui t1, 0xbbe0 */
553 #ifdef TARGET_WORDS_BIGENDIAN
554 stl_raw(p
++, 0x3c08c000); /* lui t0, 0xc000 */
556 stl_raw(p
++, 0x340800c0); /* ori t0, r0, 0x00c0 */
558 stl_raw(p
++, 0xad280048); /* sw t0, 0x0048(t1) */
559 #ifdef TARGET_WORDS_BIGENDIAN
560 stl_raw(p
++, 0x3c084000); /* lui t0, 0x4000 */
562 stl_raw(p
++, 0x34080040); /* ori t0, r0, 0x0040 */
564 stl_raw(p
++, 0xad280050); /* sw t0, 0x0050(t1) */
566 #ifdef TARGET_WORDS_BIGENDIAN
567 stl_raw(p
++, 0x3c088000); /* lui t0, 0x8000 */
569 stl_raw(p
++, 0x34080080); /* ori t0, r0, 0x0080 */
571 stl_raw(p
++, 0xad280058); /* sw t0, 0x0058(t1) */
572 #ifdef TARGET_WORDS_BIGENDIAN
573 stl_raw(p
++, 0x3c083f00); /* lui t0, 0x3f00 */
575 stl_raw(p
++, 0x3408003f); /* ori t0, r0, 0x003f */
577 stl_raw(p
++, 0xad280060); /* sw t0, 0x0060(t1) */
579 #ifdef TARGET_WORDS_BIGENDIAN
580 stl_raw(p
++, 0x3c08c100); /* lui t0, 0xc100 */
582 stl_raw(p
++, 0x340800c1); /* ori t0, r0, 0x00c1 */
584 stl_raw(p
++, 0xad280080); /* sw t0, 0x0080(t1) */
585 #ifdef TARGET_WORDS_BIGENDIAN
586 stl_raw(p
++, 0x3c085e00); /* lui t0, 0x5e00 */
588 stl_raw(p
++, 0x3408005e); /* ori t0, r0, 0x005e */
590 stl_raw(p
++, 0xad280088); /* sw t0, 0x0088(t1) */
592 /* Jump to kernel code */
593 stl_raw(p
++, 0x3c1f0000 | ((kernel_entry
>> 16) & 0xffff)); /* lui ra, high(kernel_entry) */
594 stl_raw(p
++, 0x37ff0000 | (kernel_entry
& 0xffff)); /* ori ra, ra, low(kernel_entry) */
595 stl_raw(p
++, 0x03e00008); /* jr ra */
596 stl_raw(p
++, 0x00000000); /* nop */
598 /* YAMON subroutines */
599 p
= (uint32_t *) (base
+ 0x800);
600 stl_raw(p
++, 0x03e00008); /* jr ra */
601 stl_raw(p
++, 0x24020000); /* li v0,0 */
602 /* 808 YAMON print */
603 stl_raw(p
++, 0x03e06821); /* move t5,ra */
604 stl_raw(p
++, 0x00805821); /* move t3,a0 */
605 stl_raw(p
++, 0x00a05021); /* move t2,a1 */
606 stl_raw(p
++, 0x91440000); /* lbu a0,0(t2) */
607 stl_raw(p
++, 0x254a0001); /* addiu t2,t2,1 */
608 stl_raw(p
++, 0x10800005); /* beqz a0,834 */
609 stl_raw(p
++, 0x00000000); /* nop */
610 stl_raw(p
++, 0x0ff0021c); /* jal 870 */
611 stl_raw(p
++, 0x00000000); /* nop */
612 stl_raw(p
++, 0x08000205); /* j 814 */
613 stl_raw(p
++, 0x00000000); /* nop */
614 stl_raw(p
++, 0x01a00008); /* jr t5 */
615 stl_raw(p
++, 0x01602021); /* move a0,t3 */
616 /* 0x83c YAMON print_count */
617 stl_raw(p
++, 0x03e06821); /* move t5,ra */
618 stl_raw(p
++, 0x00805821); /* move t3,a0 */
619 stl_raw(p
++, 0x00a05021); /* move t2,a1 */
620 stl_raw(p
++, 0x00c06021); /* move t4,a2 */
621 stl_raw(p
++, 0x91440000); /* lbu a0,0(t2) */
622 stl_raw(p
++, 0x0ff0021c); /* jal 870 */
623 stl_raw(p
++, 0x00000000); /* nop */
624 stl_raw(p
++, 0x254a0001); /* addiu t2,t2,1 */
625 stl_raw(p
++, 0x258cffff); /* addiu t4,t4,-1 */
626 stl_raw(p
++, 0x1580fffa); /* bnez t4,84c */
627 stl_raw(p
++, 0x00000000); /* nop */
628 stl_raw(p
++, 0x01a00008); /* jr t5 */
629 stl_raw(p
++, 0x01602021); /* move a0,t3 */
631 stl_raw(p
++, 0x3c08b800); /* lui t0,0xb400 */
632 stl_raw(p
++, 0x350803f8); /* ori t0,t0,0x3f8 */
633 stl_raw(p
++, 0x91090005); /* lbu t1,5(t0) */
634 stl_raw(p
++, 0x00000000); /* nop */
635 stl_raw(p
++, 0x31290040); /* andi t1,t1,0x40 */
636 stl_raw(p
++, 0x1120fffc); /* beqz t1,878 <outch+0x8> */
637 stl_raw(p
++, 0x00000000); /* nop */
638 stl_raw(p
++, 0x03e00008); /* jr ra */
639 stl_raw(p
++, 0xa1040000); /* sb a0,0(t0) */
643 static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t* prom_buf
, int index
,
644 const char *string
, ...)
649 if (index
>= ENVP_NB_ENTRIES
)
652 if (string
== NULL
) {
657 table_addr
= sizeof(int32_t) * ENVP_NB_ENTRIES
+ index
* ENVP_ENTRY_SIZE
;
658 prom_buf
[index
] = tswap32(ENVP_ADDR
+ table_addr
);
660 va_start(ap
, string
);
661 vsnprintf((char *)prom_buf
+ table_addr
, ENVP_ENTRY_SIZE
, string
, ap
);
666 static int64_t load_kernel (void)
668 int64_t kernel_entry
, kernel_high
;
670 ram_addr_t initrd_offset
;
676 #ifdef TARGET_WORDS_BIGENDIAN
682 if (load_elf(loaderparams
.kernel_filename
, cpu_mips_kseg0_to_phys
, NULL
,
683 (uint64_t *)&kernel_entry
, NULL
, (uint64_t *)&kernel_high
,
684 big_endian
, ELF_MACHINE
, 1) < 0) {
685 fprintf(stderr
, "qemu: could not load kernel '%s'\n",
686 loaderparams
.kernel_filename
);
693 if (loaderparams
.initrd_filename
) {
694 initrd_size
= get_image_size (loaderparams
.initrd_filename
);
695 if (initrd_size
> 0) {
696 initrd_offset
= (kernel_high
+ ~TARGET_PAGE_MASK
) & TARGET_PAGE_MASK
;
697 if (initrd_offset
+ initrd_size
> ram_size
) {
699 "qemu: memory too small for initial ram disk '%s'\n",
700 loaderparams
.initrd_filename
);
703 initrd_size
= load_image_targphys(loaderparams
.initrd_filename
,
705 ram_size
- initrd_offset
);
707 if (initrd_size
== (target_ulong
) -1) {
708 fprintf(stderr
, "qemu: could not load initial ram disk '%s'\n",
709 loaderparams
.initrd_filename
);
714 /* Setup prom parameters. */
715 prom_size
= ENVP_NB_ENTRIES
* (sizeof(int32_t) + ENVP_ENTRY_SIZE
);
716 prom_buf
= g_malloc(prom_size
);
718 prom_set(prom_buf
, prom_index
++, "%s", loaderparams
.kernel_filename
);
719 if (initrd_size
> 0) {
720 prom_set(prom_buf
, prom_index
++, "rd_start=0x%" PRIx64
" rd_size=%li %s",
721 cpu_mips_phys_to_kseg0(NULL
, initrd_offset
), initrd_size
,
722 loaderparams
.kernel_cmdline
);
724 prom_set(prom_buf
, prom_index
++, "%s", loaderparams
.kernel_cmdline
);
727 prom_set(prom_buf
, prom_index
++, "memsize");
728 prom_set(prom_buf
, prom_index
++, "%i", loaderparams
.ram_size
);
729 prom_set(prom_buf
, prom_index
++, "modetty0");
730 prom_set(prom_buf
, prom_index
++, "38400n8r");
731 prom_set(prom_buf
, prom_index
++, NULL
);
733 rom_add_blob_fixed("prom", prom_buf
, prom_size
,
734 cpu_mips_kseg0_to_phys(NULL
, ENVP_ADDR
));
739 static void malta_mips_config(CPUMIPSState
*env
)
741 env
->mvp
->CP0_MVPConf0
|= ((smp_cpus
- 1) << CP0MVPC0_PVPE
) |
742 ((smp_cpus
* env
->nr_threads
- 1) << CP0MVPC0_PTC
);
745 static void main_cpu_reset(void *opaque
)
747 CPUMIPSState
*env
= opaque
;
748 cpu_state_reset(env
);
750 /* The bootloader does not need to be rewritten as it is located in a
751 read only location. The kernel location and the arguments table
752 location does not change. */
753 if (loaderparams
.kernel_filename
) {
754 env
->CP0_Status
&= ~((1 << CP0St_BEV
) | (1 << CP0St_ERL
));
757 malta_mips_config(env
);
760 static void cpu_request_exit(void *opaque
, int irq
, int level
)
762 CPUMIPSState
*env
= cpu_single_env
;
770 void mips_malta_init (ram_addr_t ram_size
,
771 const char *boot_device
,
772 const char *kernel_filename
, const char *kernel_cmdline
,
773 const char *initrd_filename
, const char *cpu_model
)
777 MemoryRegion
*system_memory
= get_system_memory();
778 MemoryRegion
*ram
= g_new(MemoryRegion
, 1);
779 MemoryRegion
*bios
, *bios_alias
= g_new(MemoryRegion
, 1);
780 target_long bios_size
= 0x400000;
781 int64_t kernel_entry
;
786 qemu_irq
*cpu_exit_irq
;
791 DriveInfo
*hd
[MAX_IDE_BUS
* MAX_IDE_DEVS
];
792 DriveInfo
*fd
[MAX_FD
];
794 int fl_sectors
= bios_size
>> 16;
797 DeviceState
*dev
= qdev_create(NULL
, "mips-malta");
798 MaltaState
*s
= DO_UPCAST(MaltaState
, busdev
.qdev
, dev
);
800 qdev_init_nofail(dev
);
802 /* Make sure the first 3 serial ports are associated with a device. */
803 for(i
= 0; i
< 3; i
++) {
804 if (!serial_hds
[i
]) {
806 snprintf(label
, sizeof(label
), "serial%d", i
);
807 serial_hds
[i
] = qemu_chr_new(label
, "null", NULL
);
812 if (cpu_model
== NULL
) {
820 for (i
= 0; i
< smp_cpus
; i
++) {
821 env
= cpu_init(cpu_model
);
823 fprintf(stderr
, "Unable to find CPU definition\n");
826 /* Init internal devices */
827 cpu_mips_irq_init_cpu(env
);
828 cpu_mips_clock_init(env
);
829 qemu_register_reset(main_cpu_reset
, env
);
834 if (ram_size
> (256 << 20)) {
836 "qemu: Too much memory for this machine: %d MB, maximum 256 MB\n",
837 ((unsigned int)ram_size
/ (1 << 20)));
840 memory_region_init_ram(ram
, "mips_malta.ram", ram_size
);
841 vmstate_register_ram_global(ram
);
842 memory_region_add_subregion(system_memory
, 0, ram
);
844 #ifdef TARGET_WORDS_BIGENDIAN
850 malta_fpga_init(system_memory
, 0x1f000000LL
, env
->irq
[2], serial_hds
[2]);
852 /* Load firmware in flash / BIOS. */
853 dinfo
= drive_get(IF_PFLASH
, 0, fl_idx
);
854 #ifdef DEBUG_BOARD_INIT
856 printf("Register parallel flash %d size " TARGET_FMT_lx
" at "
857 "addr %08llx '%s' %x\n",
858 fl_idx
, bios_size
, 0x1e000000LL
,
859 bdrv_get_device_name(dinfo
->bdrv
), fl_sectors
);
862 fl
= pflash_cfi01_register(0x1e000000LL
, NULL
, "mips_malta.bios",
863 BIOS_SIZE
, dinfo
? dinfo
->bdrv
: NULL
,
865 4, 0x0000, 0x0000, 0x0000, 0x0000, be
);
866 bios
= pflash_cfi01_get_memory(fl
);
868 if (kernel_filename
) {
869 /* Write a small bootloader to the flash location. */
870 loaderparams
.ram_size
= ram_size
;
871 loaderparams
.kernel_filename
= kernel_filename
;
872 loaderparams
.kernel_cmdline
= kernel_cmdline
;
873 loaderparams
.initrd_filename
= initrd_filename
;
874 kernel_entry
= load_kernel();
875 write_bootloader(env
, memory_region_get_ram_ptr(bios
), kernel_entry
);
877 /* Load firmware from flash. */
879 /* Load a BIOS image. */
880 if (bios_name
== NULL
) {
881 bios_name
= BIOS_FILENAME
;
883 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
885 bios_size
= load_image_targphys(filename
, 0x1e000000LL
,
891 if ((bios_size
< 0 || bios_size
> BIOS_SIZE
) && !kernel_filename
) {
893 "qemu: Could not load MIPS bios '%s', and no -kernel argument was specified\n",
898 /* In little endian mode the 32bit words in the bios are swapped,
899 a neat trick which allows bi-endian firmware. */
900 #ifndef TARGET_WORDS_BIGENDIAN
902 uint32_t *addr
= memory_region_get_ram_ptr(bios
);
903 uint32_t *end
= addr
+ bios_size
;
912 /* Map the BIOS at a 2nd physical location, as on the real board. */
913 memory_region_init_alias(bios_alias
, "bios.1fc", bios
, 0, BIOS_SIZE
);
914 memory_region_add_subregion(system_memory
, 0x1fc00000LL
, bios_alias
);
916 /* Board ID = 0x420 (Malta Board with CoreLV)
917 XXX: theoretically 0x1e000010 should map to flash and 0x1fc00010 should
918 map to the board ID. */
919 stl_p(memory_region_get_ram_ptr(bios
) + 0x10, 0x00000420);
921 /* Init internal devices */
922 cpu_mips_irq_init_cpu(env
);
923 cpu_mips_clock_init(env
);
926 * We have a circular dependency problem: pci_bus depends on isa_irq,
927 * isa_irq is provided by i8259, i8259 depends on ISA, ISA depends
928 * on piix4, and piix4 depends on pci_bus. To stop the cycle we have
929 * qemu_irq_proxy() adds an extra bit of indirection, allowing us
930 * to resolve the isa_irq -> i8259 dependency after i8259 is initialized.
932 isa_irq
= qemu_irq_proxy(&s
->i8259
, 16);
935 pci_bus
= gt64120_register(isa_irq
);
938 ide_drive_get(hd
, MAX_IDE_BUS
);
940 piix4_devfn
= piix4_init(pci_bus
, &isa_bus
, 80);
942 /* Interrupt controller */
943 /* The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2 */
944 s
->i8259
= i8259_init(isa_bus
, env
->irq
[2]);
946 isa_bus_irqs(isa_bus
, s
->i8259
);
947 pci_piix4_ide_init(pci_bus
, hd
, piix4_devfn
+ 1);
948 pci_create_simple(pci_bus
, piix4_devfn
+ 2, "piix4-usb-uhci");
949 smbus
= piix4_pm_init(pci_bus
, piix4_devfn
+ 3, 0x1100,
950 isa_get_irq(NULL
, 9), NULL
, 0);
951 /* TODO: Populate SPD eeprom data. */
952 smbus_eeprom_init(smbus
, 8, NULL
, 0);
953 pit
= pit_init(isa_bus
, 0x40, 0, NULL
);
954 cpu_exit_irq
= qemu_allocate_irqs(cpu_request_exit
, NULL
, 1);
955 DMA_init(0, cpu_exit_irq
);
958 isa_create_simple(isa_bus
, "i8042");
960 rtc_init(isa_bus
, 2000, NULL
);
961 serial_isa_init(isa_bus
, 0, serial_hds
[0]);
962 serial_isa_init(isa_bus
, 1, serial_hds
[1]);
964 parallel_init(isa_bus
, 0, parallel_hds
[0]);
965 for(i
= 0; i
< MAX_FD
; i
++) {
966 fd
[i
] = drive_get(IF_FLOPPY
, 0, i
);
968 fdctrl_init_isa(isa_bus
, fd
);
971 audio_init(isa_bus
, pci_bus
);
976 /* Optional PCI video card */
977 if (cirrus_vga_enabled
) {
978 pci_cirrus_vga_init(pci_bus
);
979 } else if (vmsvga_enabled
) {
980 pci_vmsvga_init(pci_bus
);
981 } else if (std_vga_enabled
) {
982 pci_vga_init(pci_bus
);
986 static int mips_malta_sysbus_device_init(SysBusDevice
*sysbusdev
)
991 static void mips_malta_class_init(ObjectClass
*klass
, void *data
)
993 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
995 k
->init
= mips_malta_sysbus_device_init
;
998 static TypeInfo mips_malta_device
= {
999 .name
= "mips-malta",
1000 .parent
= TYPE_SYS_BUS_DEVICE
,
1001 .instance_size
= sizeof(MaltaState
),
1002 .class_init
= mips_malta_class_init
,
1005 static QEMUMachine mips_malta_machine
= {
1007 .desc
= "MIPS Malta Core LV",
1008 .init
= mips_malta_init
,
1013 static void mips_malta_register_types(void)
1015 type_register_static(&mips_malta_device
);
1018 static void mips_malta_machine_init(void)
1020 qemu_register_machine(&mips_malta_machine
);
1023 type_init(mips_malta_register_types
)
1024 machine_init(mips_malta_machine_init
);