hw/gt64xxx.c

   1 /*
   2  * QEMU GT64120 PCI host
   3  *
   4  * Copyright (c) 2006,2007 Aurelien Jarno
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw.h"
  26 #include "mips.h"
  27 #include "pci.h"
  28 #include "pci_host.h"
  29 #include "pc.h"
  30 #include "exec-memory.h"
  31
  32 //#define DEBUG
  33
  34 #ifdef DEBUG
  35 #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__)
  36 #else
  37 #define DPRINTF(fmt, ...)
  38 #endif
  39
  40 #define GT_REGS                 (0x1000 >> 2)
  41
  42 /* CPU Configuration */
  43 #define GT_CPU                  (0x000 >> 2)
  44 #define GT_MULTI                (0x120 >> 2)
  45
  46 /* CPU Address Decode */
  47 #define GT_SCS10LD              (0x008 >> 2)
  48 #define GT_SCS10HD              (0x010 >> 2)
  49 #define GT_SCS32LD              (0x018 >> 2)
  50 #define GT_SCS32HD              (0x020 >> 2)
  51 #define GT_CS20LD               (0x028 >> 2)
  52 #define GT_CS20HD               (0x030 >> 2)
  53 #define GT_CS3BOOTLD            (0x038 >> 2)
  54 #define GT_CS3BOOTHD            (0x040 >> 2)
  55 #define GT_PCI0IOLD             (0x048 >> 2)
  56 #define GT_PCI0IOHD             (0x050 >> 2)
  57 #define GT_PCI0M0LD             (0x058 >> 2)
  58 #define GT_PCI0M0HD             (0x060 >> 2)
  59 #define GT_PCI0M1LD             (0x080 >> 2)
  60 #define GT_PCI0M1HD             (0x088 >> 2)
  61 #define GT_PCI1IOLD             (0x090 >> 2)
  62 #define GT_PCI1IOHD             (0x098 >> 2)
  63 #define GT_PCI1M0LD             (0x0a0 >> 2)
  64 #define GT_PCI1M0HD             (0x0a8 >> 2)
  65 #define GT_PCI1M1LD             (0x0b0 >> 2)
  66 #define GT_PCI1M1HD             (0x0b8 >> 2)
  67 #define GT_ISD                  (0x068 >> 2)
  68
  69 #define GT_SCS10AR              (0x0d0 >> 2)
  70 #define GT_SCS32AR              (0x0d8 >> 2)
  71 #define GT_CS20R                (0x0e0 >> 2)
  72 #define GT_CS3BOOTR             (0x0e8 >> 2)
  73
  74 #define GT_PCI0IOREMAP          (0x0f0 >> 2)
  75 #define GT_PCI0M0REMAP          (0x0f8 >> 2)
  76 #define GT_PCI0M1REMAP          (0x100 >> 2)
  77 #define GT_PCI1IOREMAP          (0x108 >> 2)
  78 #define GT_PCI1M0REMAP          (0x110 >> 2)
  79 #define GT_PCI1M1REMAP          (0x118 >> 2)
  80
  81 /* CPU Error Report */
  82 #define GT_CPUERR_ADDRLO        (0x070 >> 2)
  83 #define GT_CPUERR_ADDRHI        (0x078 >> 2)
  84 #define GT_CPUERR_DATALO        (0x128 >> 2)            /* GT-64120A only  */
  85 #define GT_CPUERR_DATAHI        (0x130 >> 2)            /* GT-64120A only  */
  86 #define GT_CPUERR_PARITY        (0x138 >> 2)            /* GT-64120A only  */
  87
  88 /* CPU Sync Barrier */
  89 #define GT_PCI0SYNC             (0x0c0 >> 2)
  90 #define GT_PCI1SYNC             (0x0c8 >> 2)
  91
  92 /* SDRAM and Device Address Decode */
  93 #define GT_SCS0LD               (0x400 >> 2)
  94 #define GT_SCS0HD               (0x404 >> 2)
  95 #define GT_SCS1LD               (0x408 >> 2)
  96 #define GT_SCS1HD               (0x40c >> 2)
  97 #define GT_SCS2LD               (0x410 >> 2)
  98 #define GT_SCS2HD               (0x414 >> 2)
  99 #define GT_SCS3LD               (0x418 >> 2)
 100 #define GT_SCS3HD               (0x41c >> 2)
 101 #define GT_CS0LD                (0x420 >> 2)
 102 #define GT_CS0HD                (0x424 >> 2)
 103 #define GT_CS1LD                (0x428 >> 2)
 104 #define GT_CS1HD                (0x42c >> 2)
 105 #define GT_CS2LD                (0x430 >> 2)
 106 #define GT_CS2HD                (0x434 >> 2)
 107 #define GT_CS3LD                (0x438 >> 2)
 108 #define GT_CS3HD                (0x43c >> 2)
 109 #define GT_BOOTLD               (0x440 >> 2)
 110 #define GT_BOOTHD               (0x444 >> 2)
 111 #define GT_ADERR                (0x470 >> 2)
 112
 113 /* SDRAM Configuration */
 114 #define GT_SDRAM_CFG            (0x448 >> 2)
 115 #define GT_SDRAM_OPMODE         (0x474 >> 2)
 116 #define GT_SDRAM_BM             (0x478 >> 2)
 117 #define GT_SDRAM_ADDRDECODE     (0x47c >> 2)
 118
 119 /* SDRAM Parameters */
 120 #define GT_SDRAM_B0             (0x44c >> 2)
 121 #define GT_SDRAM_B1             (0x450 >> 2)
 122 #define GT_SDRAM_B2             (0x454 >> 2)
 123 #define GT_SDRAM_B3             (0x458 >> 2)
 124
 125 /* Device Parameters */
 126 #define GT_DEV_B0               (0x45c >> 2)
 127 #define GT_DEV_B1               (0x460 >> 2)
 128 #define GT_DEV_B2               (0x464 >> 2)
 129 #define GT_DEV_B3               (0x468 >> 2)
 130 #define GT_DEV_BOOT             (0x46c >> 2)
 131
 132 /* ECC */
 133 #define GT_ECC_ERRDATALO        (0x480 >> 2)            /* GT-64120A only  */
 134 #define GT_ECC_ERRDATAHI        (0x484 >> 2)            /* GT-64120A only  */
 135 #define GT_ECC_MEM              (0x488 >> 2)            /* GT-64120A only  */
 136 #define GT_ECC_CALC             (0x48c >> 2)            /* GT-64120A only  */
 137 #define GT_ECC_ERRADDR          (0x490 >> 2)            /* GT-64120A only  */
 138
 139 /* DMA Record */
 140 #define GT_DMA0_CNT             (0x800 >> 2)
 141 #define GT_DMA1_CNT             (0x804 >> 2)
 142 #define GT_DMA2_CNT             (0x808 >> 2)
 143 #define GT_DMA3_CNT             (0x80c >> 2)
 144 #define GT_DMA0_SA              (0x810 >> 2)
 145 #define GT_DMA1_SA              (0x814 >> 2)
 146 #define GT_DMA2_SA              (0x818 >> 2)
 147 #define GT_DMA3_SA              (0x81c >> 2)
 148 #define GT_DMA0_DA              (0x820 >> 2)
 149 #define GT_DMA1_DA              (0x824 >> 2)
 150 #define GT_DMA2_DA              (0x828 >> 2)
 151 #define GT_DMA3_DA              (0x82c >> 2)
 152 #define GT_DMA0_NEXT            (0x830 >> 2)
 153 #define GT_DMA1_NEXT            (0x834 >> 2)
 154 #define GT_DMA2_NEXT            (0x838 >> 2)
 155 #define GT_DMA3_NEXT            (0x83c >> 2)
 156 #define GT_DMA0_CUR             (0x870 >> 2)
 157 #define GT_DMA1_CUR             (0x874 >> 2)
 158 #define GT_DMA2_CUR             (0x878 >> 2)
 159 #define GT_DMA3_CUR             (0x87c >> 2)
 160
 161 /* DMA Channel Control */
 162 #define GT_DMA0_CTRL            (0x840 >> 2)
 163 #define GT_DMA1_CTRL            (0x844 >> 2)
 164 #define GT_DMA2_CTRL            (0x848 >> 2)
 165 #define GT_DMA3_CTRL            (0x84c >> 2)
 166
 167 /* DMA Arbiter */
 168 #define GT_DMA_ARB              (0x860 >> 2)
 169
 170 /* Timer/Counter */
 171 #define GT_TC0                  (0x850 >> 2)
 172 #define GT_TC1                  (0x854 >> 2)
 173 #define GT_TC2                  (0x858 >> 2)
 174 #define GT_TC3                  (0x85c >> 2)
 175 #define GT_TC_CONTROL           (0x864 >> 2)
 176
 177 /* PCI Internal */
 178 #define GT_PCI0_CMD             (0xc00 >> 2)
 179 #define GT_PCI0_TOR             (0xc04 >> 2)
 180 #define GT_PCI0_BS_SCS10        (0xc08 >> 2)
 181 #define GT_PCI0_BS_SCS32        (0xc0c >> 2)
 182 #define GT_PCI0_BS_CS20         (0xc10 >> 2)
 183 #define GT_PCI0_BS_CS3BT        (0xc14 >> 2)
 184 #define GT_PCI1_IACK            (0xc30 >> 2)
 185 #define GT_PCI0_IACK            (0xc34 >> 2)
 186 #define GT_PCI0_BARE            (0xc3c >> 2)
 187 #define GT_PCI0_PREFMBR         (0xc40 >> 2)
 188 #define GT_PCI0_SCS10_BAR       (0xc48 >> 2)
 189 #define GT_PCI0_SCS32_BAR       (0xc4c >> 2)
 190 #define GT_PCI0_CS20_BAR        (0xc50 >> 2)
 191 #define GT_PCI0_CS3BT_BAR       (0xc54 >> 2)
 192 #define GT_PCI0_SSCS10_BAR      (0xc58 >> 2)
 193 #define GT_PCI0_SSCS32_BAR      (0xc5c >> 2)
 194 #define GT_PCI0_SCS3BT_BAR      (0xc64 >> 2)
 195 #define GT_PCI1_CMD             (0xc80 >> 2)
 196 #define GT_PCI1_TOR             (0xc84 >> 2)
 197 #define GT_PCI1_BS_SCS10        (0xc88 >> 2)
 198 #define GT_PCI1_BS_SCS32        (0xc8c >> 2)
 199 #define GT_PCI1_BS_CS20         (0xc90 >> 2)
 200 #define GT_PCI1_BS_CS3BT        (0xc94 >> 2)
 201 #define GT_PCI1_BARE            (0xcbc >> 2)
 202 #define GT_PCI1_PREFMBR         (0xcc0 >> 2)
 203 #define GT_PCI1_SCS10_BAR       (0xcc8 >> 2)
 204 #define GT_PCI1_SCS32_BAR       (0xccc >> 2)
 205 #define GT_PCI1_CS20_BAR        (0xcd0 >> 2)
 206 #define GT_PCI1_CS3BT_BAR       (0xcd4 >> 2)
 207 #define GT_PCI1_SSCS10_BAR      (0xcd8 >> 2)
 208 #define GT_PCI1_SSCS32_BAR      (0xcdc >> 2)
 209 #define GT_PCI1_SCS3BT_BAR      (0xce4 >> 2)
 210 #define GT_PCI1_CFGADDR         (0xcf0 >> 2)
 211 #define GT_PCI1_CFGDATA         (0xcf4 >> 2)
 212 #define GT_PCI0_CFGADDR         (0xcf8 >> 2)
 213 #define GT_PCI0_CFGDATA         (0xcfc >> 2)
 214
 215 /* Interrupts */
 216 #define GT_INTRCAUSE            (0xc18 >> 2)
 217 #define GT_INTRMASK             (0xc1c >> 2)
 218 #define GT_PCI0_ICMASK          (0xc24 >> 2)
 219 #define GT_PCI0_SERR0MASK       (0xc28 >> 2)
 220 #define GT_CPU_INTSEL           (0xc70 >> 2)
 221 #define GT_PCI0_INTSEL          (0xc74 >> 2)
 222 #define GT_HINTRCAUSE           (0xc98 >> 2)
 223 #define GT_HINTRMASK            (0xc9c >> 2)
 224 #define GT_PCI0_HICMASK         (0xca4 >> 2)
 225 #define GT_PCI1_SERR1MASK       (0xca8 >> 2)
 226
 227 #define PCI_MAPPING_ENTRY(regname)            \
 228     target_phys_addr_t regname ##_start;      \
 229     target_phys_addr_t regname ##_length;     \
 230     MemoryRegion regname ##_mem
 231
 232 typedef struct GT64120State {
 233     SysBusDevice busdev;
 234     PCIHostState pci;
 235     uint32_t regs[GT_REGS];
 236     PCI_MAPPING_ENTRY(PCI0IO);
 237     PCI_MAPPING_ENTRY(ISD);
 238 } GT64120State;
 239
 240 /* Adjust range to avoid touching space which isn't mappable via PCI */
 241 /* XXX: Hardcoded values for Malta: 0x1e000000 - 0x1f100000
 242                                     0x1fc00000 - 0x1fd00000  */
 243 static void check_reserved_space (target_phys_addr_t *start,
 244                                   target_phys_addr_t *length)
 245 {
 246     target_phys_addr_t begin = *start;
 247     target_phys_addr_t end = *start + *length;
 248
 249     if (end >= 0x1e000000LL && end < 0x1f100000LL)
 250         end = 0x1e000000LL;
 251     if (begin >= 0x1e000000LL && begin < 0x1f100000LL)
 252         begin = 0x1f100000LL;
 253     if (end >= 0x1fc00000LL && end < 0x1fd00000LL)
 254         end = 0x1fc00000LL;
 255     if (begin >= 0x1fc00000LL && begin < 0x1fd00000LL)
 256         begin = 0x1fd00000LL;
 257     /* XXX: This is broken when a reserved range splits the requested range */
 258     if (end >= 0x1f100000LL && begin < 0x1e000000LL)
 259         end = 0x1e000000LL;
 260     if (end >= 0x1fd00000LL && begin < 0x1fc00000LL)
 261         end = 0x1fc00000LL;
 262
 263     *start = begin;
 264     *length = end - begin;
 265 }
 266
 267 static void gt64120_isd_mapping(GT64120State *s)
 268 {
 269     target_phys_addr_t start = s->regs[GT_ISD] << 21;
 270     target_phys_addr_t length = 0x1000;
 271
 272     if (s->ISD_length) {
 273         memory_region_del_subregion(get_system_memory(), &s->ISD_mem);
 274     }
 275     check_reserved_space(&start, &length);
 276     length = 0x1000;
 277     /* Map new address */
 278     DPRINTF("ISD: "TARGET_FMT_plx"@"TARGET_FMT_plx" -> "TARGET_FMT_plx"@"TARGET_FMT_plx", %x\n", s->ISD_length, s->ISD_start,
 279             length, start, s->ISD_handle);
 280     s->ISD_start = start;
 281     s->ISD_length = length;
 282     memory_region_add_subregion(get_system_memory(), s->ISD_start, &s->ISD_mem);
 283 }
 284
 285 static void gt64120_pci_mapping(GT64120State *s)
 286 {
 287     /* Update IO mapping */
 288     if ((s->regs[GT_PCI0IOLD] & 0x7f) <= s->regs[GT_PCI0IOHD])
 289     {
 290       /* Unmap old IO address */
 291       if (s->PCI0IO_length)
 292       {
 293           memory_region_del_subregion(get_system_memory(), &s->PCI0IO_mem);
 294           memory_region_destroy(&s->PCI0IO_mem);
 295       }
 296       /* Map new IO address */
 297       s->PCI0IO_start = s->regs[GT_PCI0IOLD] << 21;
 298       s->PCI0IO_length = ((s->regs[GT_PCI0IOHD] + 1) - (s->regs[GT_PCI0IOLD] & 0x7f)) << 21;
 299       isa_mem_base = s->PCI0IO_start;
 300       isa_mmio_init(s->PCI0IO_start, s->PCI0IO_length);
 301     }
 302 }
 303
 304 static void gt64120_writel (void *opaque, target_phys_addr_t addr,
 305                             uint64_t val, unsigned size)
 306 {
 307     GT64120State *s = opaque;
 308     uint32_t saddr;
 309
 310     if (!(s->regs[GT_CPU] & 0x00001000))
 311         val = bswap32(val);
 312
 313     saddr = (addr & 0xfff) >> 2;
 314     switch (saddr) {
 315
 316     /* CPU Configuration */
 317     case GT_CPU:
 318         s->regs[GT_CPU] = val;
 319         break;
 320     case GT_MULTI:
 321         /* Read-only register as only one GT64xxx is present on the CPU bus */
 322         break;
 323
 324     /* CPU Address Decode */
 325     case GT_PCI0IOLD:
 326         s->regs[GT_PCI0IOLD]    = val & 0x00007fff;
 327         s->regs[GT_PCI0IOREMAP] = val & 0x000007ff;
 328         gt64120_pci_mapping(s);
 329         break;
 330     case GT_PCI0M0LD:
 331         s->regs[GT_PCI0M0LD]    = val & 0x00007fff;
 332         s->regs[GT_PCI0M0REMAP] = val & 0x000007ff;
 333         break;
 334     case GT_PCI0M1LD:
 335         s->regs[GT_PCI0M1LD]    = val & 0x00007fff;
 336         s->regs[GT_PCI0M1REMAP] = val & 0x000007ff;
 337         break;
 338     case GT_PCI1IOLD:
 339         s->regs[GT_PCI1IOLD]    = val & 0x00007fff;
 340         s->regs[GT_PCI1IOREMAP] = val & 0x000007ff;
 341         break;
 342     case GT_PCI1M0LD:
 343         s->regs[GT_PCI1M0LD]    = val & 0x00007fff;
 344         s->regs[GT_PCI1M0REMAP] = val & 0x000007ff;
 345         break;
 346     case GT_PCI1M1LD:
 347         s->regs[GT_PCI1M1LD]    = val & 0x00007fff;
 348         s->regs[GT_PCI1M1REMAP] = val & 0x000007ff;
 349         break;
 350     case GT_PCI0IOHD:
 351         s->regs[saddr] = val & 0x0000007f;
 352         gt64120_pci_mapping(s);
 353         break;
 354     case GT_PCI0M0HD:
 355     case GT_PCI0M1HD:
 356     case GT_PCI1IOHD:
 357     case GT_PCI1M0HD:
 358     case GT_PCI1M1HD:
 359         s->regs[saddr] = val & 0x0000007f;
 360         break;
 361     case GT_ISD:
 362         s->regs[saddr] = val & 0x00007fff;
 363         gt64120_isd_mapping(s);
 364         break;
 365
 366     case GT_PCI0IOREMAP:
 367     case GT_PCI0M0REMAP:
 368     case GT_PCI0M1REMAP:
 369     case GT_PCI1IOREMAP:
 370     case GT_PCI1M0REMAP:
 371     case GT_PCI1M1REMAP:
 372         s->regs[saddr] = val & 0x000007ff;
 373         break;
 374
 375     /* CPU Error Report */
 376     case GT_CPUERR_ADDRLO:
 377     case GT_CPUERR_ADDRHI:
 378     case GT_CPUERR_DATALO:
 379     case GT_CPUERR_DATAHI:
 380     case GT_CPUERR_PARITY:
 381         /* Read-only registers, do nothing */
 382         break;
 383
 384     /* CPU Sync Barrier */
 385     case GT_PCI0SYNC:
 386     case GT_PCI1SYNC:
 387         /* Read-only registers, do nothing */
 388         break;
 389
 390     /* SDRAM and Device Address Decode */
 391     case GT_SCS0LD:
 392     case GT_SCS0HD:
 393     case GT_SCS1LD:
 394     case GT_SCS1HD:
 395     case GT_SCS2LD:
 396     case GT_SCS2HD:
 397     case GT_SCS3LD:
 398     case GT_SCS3HD:
 399     case GT_CS0LD:
 400     case GT_CS0HD:
 401     case GT_CS1LD:
 402     case GT_CS1HD:
 403     case GT_CS2LD:
 404     case GT_CS2HD:
 405     case GT_CS3LD:
 406     case GT_CS3HD:
 407     case GT_BOOTLD:
 408     case GT_BOOTHD:
 409     case GT_ADERR:
 410     /* SDRAM Configuration */
 411     case GT_SDRAM_CFG:
 412     case GT_SDRAM_OPMODE:
 413     case GT_SDRAM_BM:
 414     case GT_SDRAM_ADDRDECODE:
 415         /* Accept and ignore SDRAM interleave configuration */
 416         s->regs[saddr] = val;
 417         break;
 418
 419     /* Device Parameters */
 420     case GT_DEV_B0:
 421     case GT_DEV_B1:
 422     case GT_DEV_B2:
 423     case GT_DEV_B3:
 424     case GT_DEV_BOOT:
 425         /* Not implemented */
 426         DPRINTF ("Unimplemented device register offset 0x%x\n", saddr << 2);
 427         break;
 428
 429     /* ECC */
 430     case GT_ECC_ERRDATALO:
 431     case GT_ECC_ERRDATAHI:
 432     case GT_ECC_MEM:
 433     case GT_ECC_CALC:
 434     case GT_ECC_ERRADDR:
 435         /* Read-only registers, do nothing */
 436         break;
 437
 438     /* DMA Record */
 439     case GT_DMA0_CNT:
 440     case GT_DMA1_CNT:
 441     case GT_DMA2_CNT:
 442     case GT_DMA3_CNT:
 443     case GT_DMA0_SA:
 444     case GT_DMA1_SA:
 445     case GT_DMA2_SA:
 446     case GT_DMA3_SA:
 447     case GT_DMA0_DA:
 448     case GT_DMA1_DA:
 449     case GT_DMA2_DA:
 450     case GT_DMA3_DA:
 451     case GT_DMA0_NEXT:
 452     case GT_DMA1_NEXT:
 453     case GT_DMA2_NEXT:
 454     case GT_DMA3_NEXT:
 455     case GT_DMA0_CUR:
 456     case GT_DMA1_CUR:
 457     case GT_DMA2_CUR:
 458     case GT_DMA3_CUR:
 459         /* Not implemented */
 460         DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
 461         break;
 462
 463     /* DMA Channel Control */
 464     case GT_DMA0_CTRL:
 465     case GT_DMA1_CTRL:
 466     case GT_DMA2_CTRL:
 467     case GT_DMA3_CTRL:
 468         /* Not implemented */
 469         DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
 470         break;
 471
 472     /* DMA Arbiter */
 473     case GT_DMA_ARB:
 474         /* Not implemented */
 475         DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
 476         break;
 477
 478     /* Timer/Counter */
 479     case GT_TC0:
 480     case GT_TC1:
 481     case GT_TC2:
 482     case GT_TC3:
 483     case GT_TC_CONTROL:
 484         /* Not implemented */
 485         DPRINTF ("Unimplemented timer register offset 0x%x\n", saddr << 2);
 486         break;
 487
 488     /* PCI Internal */
 489     case GT_PCI0_CMD:
 490     case GT_PCI1_CMD:
 491         s->regs[saddr] = val & 0x0401fc0f;
 492         break;
 493     case GT_PCI0_TOR:
 494     case GT_PCI0_BS_SCS10:
 495     case GT_PCI0_BS_SCS32:
 496     case GT_PCI0_BS_CS20:
 497     case GT_PCI0_BS_CS3BT:
 498     case GT_PCI1_IACK:
 499     case GT_PCI0_IACK:
 500     case GT_PCI0_BARE:
 501     case GT_PCI0_PREFMBR:
 502     case GT_PCI0_SCS10_BAR:
 503     case GT_PCI0_SCS32_BAR:
 504     case GT_PCI0_CS20_BAR:
 505     case GT_PCI0_CS3BT_BAR:
 506     case GT_PCI0_SSCS10_BAR:
 507     case GT_PCI0_SSCS32_BAR:
 508     case GT_PCI0_SCS3BT_BAR:
 509     case GT_PCI1_TOR:
 510     case GT_PCI1_BS_SCS10:
 511     case GT_PCI1_BS_SCS32:
 512     case GT_PCI1_BS_CS20:
 513     case GT_PCI1_BS_CS3BT:
 514     case GT_PCI1_BARE:
 515     case GT_PCI1_PREFMBR:
 516     case GT_PCI1_SCS10_BAR:
 517     case GT_PCI1_SCS32_BAR:
 518     case GT_PCI1_CS20_BAR:
 519     case GT_PCI1_CS3BT_BAR:
 520     case GT_PCI1_SSCS10_BAR:
 521     case GT_PCI1_SSCS32_BAR:
 522     case GT_PCI1_SCS3BT_BAR:
 523     case GT_PCI1_CFGADDR:
 524     case GT_PCI1_CFGDATA:
 525         /* not implemented */
 526         break;
 527     case GT_PCI0_CFGADDR:
 528         s->pci.config_reg = val & 0x80fffffc;
 529         break;
 530     case GT_PCI0_CFGDATA:
 531         if (!(s->regs[GT_PCI0_CMD] & 1) && (s->pci.config_reg & 0x00fff800))
 532             val = bswap32(val);
 533         if (s->pci.config_reg & (1u << 31))
 534             pci_data_write(s->pci.bus, s->pci.config_reg, val, 4);
 535         break;
 536
 537     /* Interrupts */
 538     case GT_INTRCAUSE:
 539         /* not really implemented */
 540         s->regs[saddr] = ~(~(s->regs[saddr]) | ~(val & 0xfffffffe));
 541         s->regs[saddr] |= !!(s->regs[saddr] & 0xfffffffe);
 542         DPRINTF("INTRCAUSE %x\n", val);
 543         break;
 544     case GT_INTRMASK:
 545         s->regs[saddr] = val & 0x3c3ffffe;
 546         DPRINTF("INTRMASK %x\n", val);
 547         break;
 548     case GT_PCI0_ICMASK:
 549         s->regs[saddr] = val & 0x03fffffe;
 550         DPRINTF("ICMASK %x\n", val);
 551         break;
 552     case GT_PCI0_SERR0MASK:
 553         s->regs[saddr] = val & 0x0000003f;
 554         DPRINTF("SERR0MASK %x\n", val);
 555         break;
 556
 557     /* Reserved when only PCI_0 is configured. */
 558     case GT_HINTRCAUSE:
 559     case GT_CPU_INTSEL:
 560     case GT_PCI0_INTSEL:
 561     case GT_HINTRMASK:
 562     case GT_PCI0_HICMASK:
 563     case GT_PCI1_SERR1MASK:
 564         /* not implemented */
 565         break;
 566
 567     /* SDRAM Parameters */
 568     case GT_SDRAM_B0:
 569     case GT_SDRAM_B1:
 570     case GT_SDRAM_B2:
 571     case GT_SDRAM_B3:
 572         /* We don't simulate electrical parameters of the SDRAM.
 573            Accept, but ignore the values. */
 574         s->regs[saddr] = val;
 575         break;
 576
 577     default:
 578         DPRINTF ("Bad register offset 0x%x\n", (int)addr);
 579         break;
 580     }
 581 }
 582
 583 static uint64_t gt64120_readl (void *opaque,
 584                                target_phys_addr_t addr, unsigned size)
 585 {
 586     GT64120State *s = opaque;
 587     uint32_t val;
 588     uint32_t saddr;
 589
 590     saddr = (addr & 0xfff) >> 2;
 591     switch (saddr) {
 592
 593     /* CPU Configuration */
 594     case GT_MULTI:
 595         /* Only one GT64xxx is present on the CPU bus, return
 596            the initial value */
 597         val = s->regs[saddr];
 598         break;
 599
 600     /* CPU Error Report */
 601     case GT_CPUERR_ADDRLO:
 602     case GT_CPUERR_ADDRHI:
 603     case GT_CPUERR_DATALO:
 604     case GT_CPUERR_DATAHI:
 605     case GT_CPUERR_PARITY:
 606         /* Emulated memory has no error, always return the initial
 607            values */
 608         val = s->regs[saddr];
 609         break;
 610
 611     /* CPU Sync Barrier */
 612     case GT_PCI0SYNC:
 613     case GT_PCI1SYNC:
 614         /* Reading those register should empty all FIFO on the PCI
 615            bus, which are not emulated. The return value should be
 616            a random value that should be ignored. */
 617         val = 0xc000ffee;
 618         break;
 619
 620     /* ECC */
 621     case GT_ECC_ERRDATALO:
 622     case GT_ECC_ERRDATAHI:
 623     case GT_ECC_MEM:
 624     case GT_ECC_CALC:
 625     case GT_ECC_ERRADDR:
 626         /* Emulated memory has no error, always return the initial
 627            values */
 628         val = s->regs[saddr];
 629         break;
 630
 631     case GT_CPU:
 632     case GT_SCS10LD:
 633     case GT_SCS10HD:
 634     case GT_SCS32LD:
 635     case GT_SCS32HD:
 636     case GT_CS20LD:
 637     case GT_CS20HD:
 638     case GT_CS3BOOTLD:
 639     case GT_CS3BOOTHD:
 640     case GT_SCS10AR:
 641     case GT_SCS32AR:
 642     case GT_CS20R:
 643     case GT_CS3BOOTR:
 644     case GT_PCI0IOLD:
 645     case GT_PCI0M0LD:
 646     case GT_PCI0M1LD:
 647     case GT_PCI1IOLD:
 648     case GT_PCI1M0LD:
 649     case GT_PCI1M1LD:
 650     case GT_PCI0IOHD:
 651     case GT_PCI0M0HD:
 652     case GT_PCI0M1HD:
 653     case GT_PCI1IOHD:
 654     case GT_PCI1M0HD:
 655     case GT_PCI1M1HD:
 656     case GT_PCI0IOREMAP:
 657     case GT_PCI0M0REMAP:
 658     case GT_PCI0M1REMAP:
 659     case GT_PCI1IOREMAP:
 660     case GT_PCI1M0REMAP:
 661     case GT_PCI1M1REMAP:
 662     case GT_ISD:
 663         val = s->regs[saddr];
 664         break;
 665     case GT_PCI0_IACK:
 666         /* Read the IRQ number */
 667         val = pic_read_irq(isa_pic);
 668         break;
 669
 670     /* SDRAM and Device Address Decode */
 671     case GT_SCS0LD:
 672     case GT_SCS0HD:
 673     case GT_SCS1LD:
 674     case GT_SCS1HD:
 675     case GT_SCS2LD:
 676     case GT_SCS2HD:
 677     case GT_SCS3LD:
 678     case GT_SCS3HD:
 679     case GT_CS0LD:
 680     case GT_CS0HD:
 681     case GT_CS1LD:
 682     case GT_CS1HD:
 683     case GT_CS2LD:
 684     case GT_CS2HD:
 685     case GT_CS3LD:
 686     case GT_CS3HD:
 687     case GT_BOOTLD:
 688     case GT_BOOTHD:
 689     case GT_ADERR:
 690         val = s->regs[saddr];
 691         break;
 692
 693     /* SDRAM Configuration */
 694     case GT_SDRAM_CFG:
 695     case GT_SDRAM_OPMODE:
 696     case GT_SDRAM_BM:
 697     case GT_SDRAM_ADDRDECODE:
 698         val = s->regs[saddr];
 699         break;
 700
 701     /* SDRAM Parameters */
 702     case GT_SDRAM_B0:
 703     case GT_SDRAM_B1:
 704     case GT_SDRAM_B2:
 705     case GT_SDRAM_B3:
 706         /* We don't simulate electrical parameters of the SDRAM.
 707            Just return the last written value. */
 708         val = s->regs[saddr];
 709         break;
 710
 711     /* Device Parameters */
 712     case GT_DEV_B0:
 713     case GT_DEV_B1:
 714     case GT_DEV_B2:
 715     case GT_DEV_B3:
 716     case GT_DEV_BOOT:
 717         val = s->regs[saddr];
 718         break;
 719
 720     /* DMA Record */
 721     case GT_DMA0_CNT:
 722     case GT_DMA1_CNT:
 723     case GT_DMA2_CNT:
 724     case GT_DMA3_CNT:
 725     case GT_DMA0_SA:
 726     case GT_DMA1_SA:
 727     case GT_DMA2_SA:
 728     case GT_DMA3_SA:
 729     case GT_DMA0_DA:
 730     case GT_DMA1_DA:
 731     case GT_DMA2_DA:
 732     case GT_DMA3_DA:
 733     case GT_DMA0_NEXT:
 734     case GT_DMA1_NEXT:
 735     case GT_DMA2_NEXT:
 736     case GT_DMA3_NEXT:
 737     case GT_DMA0_CUR:
 738     case GT_DMA1_CUR:
 739     case GT_DMA2_CUR:
 740     case GT_DMA3_CUR:
 741         val = s->regs[saddr];
 742         break;
 743
 744     /* DMA Channel Control */
 745     case GT_DMA0_CTRL:
 746     case GT_DMA1_CTRL:
 747     case GT_DMA2_CTRL:
 748     case GT_DMA3_CTRL:
 749         val = s->regs[saddr];
 750         break;
 751
 752     /* DMA Arbiter */
 753     case GT_DMA_ARB:
 754         val = s->regs[saddr];
 755         break;
 756
 757     /* Timer/Counter */
 758     case GT_TC0:
 759     case GT_TC1:
 760     case GT_TC2:
 761     case GT_TC3:
 762     case GT_TC_CONTROL:
 763         val = s->regs[saddr];
 764         break;
 765
 766     /* PCI Internal */
 767     case GT_PCI0_CFGADDR:
 768         val = s->pci.config_reg;
 769         break;
 770     case GT_PCI0_CFGDATA:
 771         if (!(s->pci.config_reg & (1 << 31)))
 772             val = 0xffffffff;
 773         else
 774             val = pci_data_read(s->pci.bus, s->pci.config_reg, 4);
 775         if (!(s->regs[GT_PCI0_CMD] & 1) && (s->pci.config_reg & 0x00fff800))
 776             val = bswap32(val);
 777         break;
 778
 779     case GT_PCI0_CMD:
 780     case GT_PCI0_TOR:
 781     case GT_PCI0_BS_SCS10:
 782     case GT_PCI0_BS_SCS32:
 783     case GT_PCI0_BS_CS20:
 784     case GT_PCI0_BS_CS3BT:
 785     case GT_PCI1_IACK:
 786     case GT_PCI0_BARE:
 787     case GT_PCI0_PREFMBR:
 788     case GT_PCI0_SCS10_BAR:
 789     case GT_PCI0_SCS32_BAR:
 790     case GT_PCI0_CS20_BAR:
 791     case GT_PCI0_CS3BT_BAR:
 792     case GT_PCI0_SSCS10_BAR:
 793     case GT_PCI0_SSCS32_BAR:
 794     case GT_PCI0_SCS3BT_BAR:
 795     case GT_PCI1_CMD:
 796     case GT_PCI1_TOR:
 797     case GT_PCI1_BS_SCS10:
 798     case GT_PCI1_BS_SCS32:
 799     case GT_PCI1_BS_CS20:
 800     case GT_PCI1_BS_CS3BT:
 801     case GT_PCI1_BARE:
 802     case GT_PCI1_PREFMBR:
 803     case GT_PCI1_SCS10_BAR:
 804     case GT_PCI1_SCS32_BAR:
 805     case GT_PCI1_CS20_BAR:
 806     case GT_PCI1_CS3BT_BAR:
 807     case GT_PCI1_SSCS10_BAR:
 808     case GT_PCI1_SSCS32_BAR:
 809     case GT_PCI1_SCS3BT_BAR:
 810     case GT_PCI1_CFGADDR:
 811     case GT_PCI1_CFGDATA:
 812         val = s->regs[saddr];
 813         break;
 814
 815     /* Interrupts */
 816     case GT_INTRCAUSE:
 817         val = s->regs[saddr];
 818         DPRINTF("INTRCAUSE %x\n", val);
 819         break;
 820     case GT_INTRMASK:
 821         val = s->regs[saddr];
 822         DPRINTF("INTRMASK %x\n", val);
 823         break;
 824     case GT_PCI0_ICMASK:
 825         val = s->regs[saddr];
 826         DPRINTF("ICMASK %x\n", val);
 827         break;
 828     case GT_PCI0_SERR0MASK:
 829         val = s->regs[saddr];
 830         DPRINTF("SERR0MASK %x\n", val);
 831         break;
 832
 833     /* Reserved when only PCI_0 is configured. */
 834     case GT_HINTRCAUSE:
 835     case GT_CPU_INTSEL:
 836     case GT_PCI0_INTSEL:
 837     case GT_HINTRMASK:
 838     case GT_PCI0_HICMASK:
 839     case GT_PCI1_SERR1MASK:
 840         val = s->regs[saddr];
 841         break;
 842
 843     default:
 844         val = s->regs[saddr];
 845         DPRINTF ("Bad register offset 0x%x\n", (int)addr);
 846         break;
 847     }
 848
 849     if (!(s->regs[GT_CPU] & 0x00001000))
 850         val = bswap32(val);
 851
 852     return val;
 853 }
 854
 855 static const MemoryRegionOps isd_mem_ops = {
 856     .read = gt64120_readl,
 857     .write = gt64120_writel,
 858     .endianness = DEVICE_NATIVE_ENDIAN,
 859 };
 860
 861 static int gt64120_pci_map_irq(PCIDevice *pci_dev, int irq_num)
 862 {
 863     int slot;
 864
 865     slot = (pci_dev->devfn >> 3);
 866
 867     switch (slot) {
 868       /* PIIX4 USB */
 869       case 10:
 870         return 3;
 871       /* AMD 79C973 Ethernet */
 872       case 11:
 873         return 1;
 874       /* Crystal 4281 Sound */
 875       case 12:
 876         return 2;
 877       /* PCI slot 1 to 4 */
 878       case 18 ... 21:
 879         return ((slot - 18) + irq_num) & 0x03;
 880       /* Unknown device, don't do any translation */
 881       default:
 882         return irq_num;
 883     }
 884 }
 885
 886 static int pci_irq_levels[4];
 887
 888 static void gt64120_pci_set_irq(void *opaque, int irq_num, int level)
 889 {
 890     int i, pic_irq, pic_level;
 891     qemu_irq *pic = opaque;
 892
 893     pci_irq_levels[irq_num] = level;
 894
 895     /* now we change the pic irq level according to the piix irq mappings */
 896     /* XXX: optimize */
 897     pic_irq = piix4_dev->config[0x60 + irq_num];
 898     if (pic_irq < 16) {
 899         /* The pic level is the logical OR of all the PCI irqs mapped
 900            to it */
 901         pic_level = 0;
 902         for (i = 0; i < 4; i++) {
 903             if (pic_irq == piix4_dev->config[0x60 + i])
 904                 pic_level |= pci_irq_levels[i];
 905         }
 906         qemu_set_irq(pic[pic_irq], pic_level);
 907     }
 908 }
 909
 910
 911 static void gt64120_reset(void *opaque)
 912 {
 913     GT64120State *s = opaque;
 914
 915     /* FIXME: Malta specific hw assumptions ahead */
 916
 917     /* CPU Configuration */
 918 #ifdef TARGET_WORDS_BIGENDIAN
 919     s->regs[GT_CPU]           = 0x00000000;
 920 #else
 921     s->regs[GT_CPU]           = 0x00001000;
 922 #endif
 923     s->regs[GT_MULTI]         = 0x00000003;
 924
 925     /* CPU Address decode */
 926     s->regs[GT_SCS10LD]       = 0x00000000;
 927     s->regs[GT_SCS10HD]       = 0x00000007;
 928     s->regs[GT_SCS32LD]       = 0x00000008;
 929     s->regs[GT_SCS32HD]       = 0x0000000f;
 930     s->regs[GT_CS20LD]        = 0x000000e0;
 931     s->regs[GT_CS20HD]        = 0x00000070;
 932     s->regs[GT_CS3BOOTLD]     = 0x000000f8;
 933     s->regs[GT_CS3BOOTHD]     = 0x0000007f;
 934
 935     s->regs[GT_PCI0IOLD]      = 0x00000080;
 936     s->regs[GT_PCI0IOHD]      = 0x0000000f;
 937     s->regs[GT_PCI0M0LD]      = 0x00000090;
 938     s->regs[GT_PCI0M0HD]      = 0x0000001f;
 939     s->regs[GT_ISD]           = 0x000000a0;
 940     s->regs[GT_PCI0M1LD]      = 0x00000790;
 941     s->regs[GT_PCI0M1HD]      = 0x0000001f;
 942     s->regs[GT_PCI1IOLD]      = 0x00000100;
 943     s->regs[GT_PCI1IOHD]      = 0x0000000f;
 944     s->regs[GT_PCI1M0LD]      = 0x00000110;
 945     s->regs[GT_PCI1M0HD]      = 0x0000001f;
 946     s->regs[GT_PCI1M1LD]      = 0x00000120;
 947     s->regs[GT_PCI1M1HD]      = 0x0000002f;
 948
 949     s->regs[GT_SCS10AR]       = 0x00000000;
 950     s->regs[GT_SCS32AR]       = 0x00000008;
 951     s->regs[GT_CS20R]         = 0x000000e0;
 952     s->regs[GT_CS3BOOTR]      = 0x000000f8;
 953
 954     s->regs[GT_PCI0IOREMAP]   = 0x00000080;
 955     s->regs[GT_PCI0M0REMAP]   = 0x00000090;
 956     s->regs[GT_PCI0M1REMAP]   = 0x00000790;
 957     s->regs[GT_PCI1IOREMAP]   = 0x00000100;
 958     s->regs[GT_PCI1M0REMAP]   = 0x00000110;
 959     s->regs[GT_PCI1M1REMAP]   = 0x00000120;
 960
 961     /* CPU Error Report */
 962     s->regs[GT_CPUERR_ADDRLO] = 0x00000000;
 963     s->regs[GT_CPUERR_ADDRHI] = 0x00000000;
 964     s->regs[GT_CPUERR_DATALO] = 0xffffffff;
 965     s->regs[GT_CPUERR_DATAHI] = 0xffffffff;
 966     s->regs[GT_CPUERR_PARITY] = 0x000000ff;
 967
 968     /* CPU Sync Barrier */
 969     s->regs[GT_PCI0SYNC]      = 0x00000000;
 970     s->regs[GT_PCI1SYNC]      = 0x00000000;
 971
 972     /* SDRAM and Device Address Decode */
 973     s->regs[GT_SCS0LD]        = 0x00000000;
 974     s->regs[GT_SCS0HD]        = 0x00000007;
 975     s->regs[GT_SCS1LD]        = 0x00000008;
 976     s->regs[GT_SCS1HD]        = 0x0000000f;
 977     s->regs[GT_SCS2LD]        = 0x00000010;
 978     s->regs[GT_SCS2HD]        = 0x00000017;
 979     s->regs[GT_SCS3LD]        = 0x00000018;
 980     s->regs[GT_SCS3HD]        = 0x0000001f;
 981     s->regs[GT_CS0LD]         = 0x000000c0;
 982     s->regs[GT_CS0HD]         = 0x000000c7;
 983     s->regs[GT_CS1LD]         = 0x000000c8;
 984     s->regs[GT_CS1HD]         = 0x000000cf;
 985     s->regs[GT_CS2LD]         = 0x000000d0;
 986     s->regs[GT_CS2HD]         = 0x000000df;
 987     s->regs[GT_CS3LD]         = 0x000000f0;
 988     s->regs[GT_CS3HD]         = 0x000000fb;
 989     s->regs[GT_BOOTLD]        = 0x000000fc;
 990     s->regs[GT_BOOTHD]        = 0x000000ff;
 991     s->regs[GT_ADERR]         = 0xffffffff;
 992
 993     /* SDRAM Configuration */
 994     s->regs[GT_SDRAM_CFG]     = 0x00000200;
 995     s->regs[GT_SDRAM_OPMODE]  = 0x00000000;
 996     s->regs[GT_SDRAM_BM]      = 0x00000007;
 997     s->regs[GT_SDRAM_ADDRDECODE] = 0x00000002;
 998
 999     /* SDRAM Parameters */
1000     s->regs[GT_SDRAM_B0]      = 0x00000005;
1001     s->regs[GT_SDRAM_B1]      = 0x00000005;
1002     s->regs[GT_SDRAM_B2]      = 0x00000005;
1003     s->regs[GT_SDRAM_B3]      = 0x00000005;
1004
1005     /* ECC */
1006     s->regs[GT_ECC_ERRDATALO] = 0x00000000;
1007     s->regs[GT_ECC_ERRDATAHI] = 0x00000000;
1008     s->regs[GT_ECC_MEM]       = 0x00000000;
1009     s->regs[GT_ECC_CALC]      = 0x00000000;
1010     s->regs[GT_ECC_ERRADDR]   = 0x00000000;
1011
1012     /* Device Parameters */
1013     s->regs[GT_DEV_B0]        = 0x386fffff;
1014     s->regs[GT_DEV_B1]        = 0x386fffff;
1015     s->regs[GT_DEV_B2]        = 0x386fffff;
1016     s->regs[GT_DEV_B3]        = 0x386fffff;
1017     s->regs[GT_DEV_BOOT]      = 0x146fffff;
1018
1019     /* DMA registers are all zeroed at reset */
1020
1021     /* Timer/Counter */
1022     s->regs[GT_TC0]           = 0xffffffff;
1023     s->regs[GT_TC1]           = 0x00ffffff;
1024     s->regs[GT_TC2]           = 0x00ffffff;
1025     s->regs[GT_TC3]           = 0x00ffffff;
1026     s->regs[GT_TC_CONTROL]    = 0x00000000;
1027
1028     /* PCI Internal */
1029 #ifdef TARGET_WORDS_BIGENDIAN
1030     s->regs[GT_PCI0_CMD]      = 0x00000000;
1031 #else
1032     s->regs[GT_PCI0_CMD]      = 0x00010001;
1033 #endif
1034     s->regs[GT_PCI0_TOR]      = 0x0000070f;
1035     s->regs[GT_PCI0_BS_SCS10] = 0x00fff000;
1036     s->regs[GT_PCI0_BS_SCS32] = 0x00fff000;
1037     s->regs[GT_PCI0_BS_CS20]  = 0x01fff000;
1038     s->regs[GT_PCI0_BS_CS3BT] = 0x00fff000;
1039     s->regs[GT_PCI1_IACK]     = 0x00000000;
1040     s->regs[GT_PCI0_IACK]     = 0x00000000;
1041     s->regs[GT_PCI0_BARE]     = 0x0000000f;
1042     s->regs[GT_PCI0_PREFMBR]  = 0x00000040;
1043     s->regs[GT_PCI0_SCS10_BAR] = 0x00000000;
1044     s->regs[GT_PCI0_SCS32_BAR] = 0x01000000;
1045     s->regs[GT_PCI0_CS20_BAR] = 0x1c000000;
1046     s->regs[GT_PCI0_CS3BT_BAR] = 0x1f000000;
1047     s->regs[GT_PCI0_SSCS10_BAR] = 0x00000000;
1048     s->regs[GT_PCI0_SSCS32_BAR] = 0x01000000;
1049     s->regs[GT_PCI0_SCS3BT_BAR] = 0x1f000000;
1050 #ifdef TARGET_WORDS_BIGENDIAN
1051     s->regs[GT_PCI1_CMD]      = 0x00000000;
1052 #else
1053     s->regs[GT_PCI1_CMD]      = 0x00010001;
1054 #endif
1055     s->regs[GT_PCI1_TOR]      = 0x0000070f;
1056     s->regs[GT_PCI1_BS_SCS10] = 0x00fff000;
1057     s->regs[GT_PCI1_BS_SCS32] = 0x00fff000;
1058     s->regs[GT_PCI1_BS_CS20]  = 0x01fff000;
1059     s->regs[GT_PCI1_BS_CS3BT] = 0x00fff000;
1060     s->regs[GT_PCI1_BARE]     = 0x0000000f;
1061     s->regs[GT_PCI1_PREFMBR]  = 0x00000040;
1062     s->regs[GT_PCI1_SCS10_BAR] = 0x00000000;
1063     s->regs[GT_PCI1_SCS32_BAR] = 0x01000000;
1064     s->regs[GT_PCI1_CS20_BAR] = 0x1c000000;
1065     s->regs[GT_PCI1_CS3BT_BAR] = 0x1f000000;
1066     s->regs[GT_PCI1_SSCS10_BAR] = 0x00000000;
1067     s->regs[GT_PCI1_SSCS32_BAR] = 0x01000000;
1068     s->regs[GT_PCI1_SCS3BT_BAR] = 0x1f000000;
1069     s->regs[GT_PCI1_CFGADDR]  = 0x00000000;
1070     s->regs[GT_PCI1_CFGDATA]  = 0x00000000;
1071     s->regs[GT_PCI0_CFGADDR]  = 0x00000000;
1072
1073     /* Interrupt registers are all zeroed at reset */
1074
1075     gt64120_isd_mapping(s);
1076     gt64120_pci_mapping(s);
1077 }
1078
1079 PCIBus *gt64120_register(qemu_irq *pic)
1080 {
1081     SysBusDevice *s;
1082     GT64120State *d;
1083     DeviceState *dev;
1084
1085     dev = qdev_create(NULL, "gt64120");
1086     qdev_init_nofail(dev);
1087     s = sysbus_from_qdev(dev);
1088     d = FROM_SYSBUS(GT64120State, s);
1089     d->pci.bus = pci_register_bus(&d->busdev.qdev, "pci",
1090                                   gt64120_pci_set_irq, gt64120_pci_map_irq,
1091                                   pic,
1092                                   get_system_memory(),
1093                                   get_system_io(),
1094                                   PCI_DEVFN(18, 0), 4);
1095     memory_region_init_io(&d->ISD_mem, &isd_mem_ops, d, "isd-mem", 0x1000);
1096
1097     pci_create_simple(d->pci.bus, PCI_DEVFN(0, 0), "gt64120_pci");
1098     return d->pci.bus;
1099 }
1100
1101 static int gt64120_init(SysBusDevice *dev)
1102 {
1103     GT64120State *s;
1104
1105     s = FROM_SYSBUS(GT64120State, dev);
1106
1107     /* FIXME: This value is computed from registers during reset, but some
1108        devices (e.g. VGA card) need to know it when they are registered.
1109        This also mean that changing the register to change the mapping
1110        does not fully work. */
1111     isa_mem_base = 0x10000000;
1112     qemu_register_reset(gt64120_reset, s);
1113     return 0;
1114 }
1115
1116 static int gt64120_pci_init(PCIDevice *d)
1117 {
1118     /* FIXME: Malta specific hw assumptions ahead */
1119     pci_set_word(d->config + PCI_COMMAND, 0);
1120     pci_set_word(d->config + PCI_STATUS,
1121                  PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM);
1122     pci_config_set_prog_interface(d->config, 0);
1123     pci_set_long(d->config + PCI_BASE_ADDRESS_0, 0x00000008);
1124     pci_set_long(d->config + PCI_BASE_ADDRESS_1, 0x01000008);
1125     pci_set_long(d->config + PCI_BASE_ADDRESS_2, 0x1c000000);
1126     pci_set_long(d->config + PCI_BASE_ADDRESS_3, 0x1f000000);
1127     pci_set_long(d->config + PCI_BASE_ADDRESS_4, 0x14000000);
1128     pci_set_long(d->config + PCI_BASE_ADDRESS_5, 0x14000001);
1129     pci_set_byte(d->config + 0x3d, 0x01);
1130
1131     return 0;
1132 }
1133
1134 static PCIDeviceInfo gt64120_pci_info = {
1135     .qdev.name = "gt64120_pci",
1136     .qdev.size = sizeof(PCIDevice),
1137     .init      = gt64120_pci_init,
1138     .vendor_id = PCI_VENDOR_ID_MARVELL,
1139     .device_id = PCI_DEVICE_ID_MARVELL_GT6412X,
1140     .revision  = 0x10,
1141     .class_id  = PCI_CLASS_BRIDGE_HOST,
1142 };
1143
1144 static void gt64120_pci_register_devices(void)
1145 {
1146     sysbus_register_dev("gt64120", sizeof(GT64120State),
1147                         gt64120_init);
1148     pci_qdev_register(&gt64120_pci_info);
1149 }
1150
1151 device_init(gt64120_pci_register_devices)