hw/arm/virt.c

   1 /*
   2  * ARM mach-virt emulation
   3  *
   4  * Copyright (c) 2013 Linaro Limited
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2 or later, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * Emulate a virtual board which works by passing Linux all the information
  19  * it needs about what devices are present via the device tree.
  20  * There are some restrictions about what we can do here:
  21  *  + we can only present devices whose Linux drivers will work based
  22  *    purely on the device tree with no platform data at all
  23  *  + we want to present a very stripped-down minimalist platform,
  24  *    both because this reduces the security attack surface from the guest
  25  *    and also because it reduces our exposure to being broken when
  26  *    the kernel updates its device tree bindings and requires further
  27  *    information in a device binding that we aren't providing.
  28  * This is essentially the same approach kvmtool uses.
  29  */
  30
  31 #include "hw/sysbus.h"
  32 #include "hw/arm/arm.h"
  33 #include "hw/arm/primecell.h"
  34 #include "hw/devices.h"
  35 #include "net/net.h"
  36 #include "sysemu/device_tree.h"
  37 #include "sysemu/sysemu.h"
  38 #include "sysemu/kvm.h"
  39 #include "hw/boards.h"
  40 #include "exec/address-spaces.h"
  41 #include "qemu/bitops.h"
  42 #include "qemu/error-report.h"
  43
  44 #define NUM_VIRTIO_TRANSPORTS 32
  45
  46 /* Number of external interrupt lines to configure the GIC with */
  47 #define NUM_IRQS 128
  48
  49 #define GIC_FDT_IRQ_TYPE_SPI 0
  50 #define GIC_FDT_IRQ_TYPE_PPI 1
  51
  52 #define GIC_FDT_IRQ_FLAGS_EDGE_LO_HI 1
  53 #define GIC_FDT_IRQ_FLAGS_EDGE_HI_LO 2
  54 #define GIC_FDT_IRQ_FLAGS_LEVEL_HI 4
  55 #define GIC_FDT_IRQ_FLAGS_LEVEL_LO 8
  56
  57 #define GIC_FDT_IRQ_PPI_CPU_START 8
  58 #define GIC_FDT_IRQ_PPI_CPU_WIDTH 8
  59
  60 enum {
  61     VIRT_FLASH,
  62     VIRT_MEM,
  63     VIRT_CPUPERIPHS,
  64     VIRT_GIC_DIST,
  65     VIRT_GIC_CPU,
  66     VIRT_UART,
  67     VIRT_MMIO,
  68     VIRT_RTC,
  69 };
  70
  71 typedef struct MemMapEntry {
  72     hwaddr base;
  73     hwaddr size;
  74 } MemMapEntry;
  75
  76 typedef struct VirtBoardInfo {
  77     struct arm_boot_info bootinfo;
  78     const char *cpu_model;
  79     const MemMapEntry *memmap;
  80     const int *irqmap;
  81     int smp_cpus;
  82     void *fdt;
  83     int fdt_size;
  84     uint32_t clock_phandle;
  85 } VirtBoardInfo;
  86
  87 /* Addresses and sizes of our components.
  88  * 0..128MB is space for a flash device so we can run bootrom code such as UEFI.
  89  * 128MB..256MB is used for miscellaneous device I/O.
  90  * 256MB..1GB is reserved for possible future PCI support (ie where the
  91  * PCI memory window will go if we add a PCI host controller).
  92  * 1GB and up is RAM (which may happily spill over into the
  93  * high memory region beyond 4GB).
  94  * This represents a compromise between how much RAM can be given to
  95  * a 32 bit VM and leaving space for expansion and in particular for PCI.
  96  * Note that devices should generally be placed at multiples of 0x10000,
  97  * to accommodate guests using 64K pages.
  98  */
  99 static const MemMapEntry a15memmap[] = {
 100     /* Space up to 0x8000000 is reserved for a boot ROM */
 101     [VIRT_FLASH] =      {          0, 0x08000000 },
 102     [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 },
 103     /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */
 104     [VIRT_GIC_DIST] =   { 0x08000000, 0x00010000 },
 105     [VIRT_GIC_CPU] =    { 0x08010000, 0x00010000 },
 106     [VIRT_UART] =       { 0x09000000, 0x00001000 },
 107     [VIRT_RTC] =        { 0x09010000, 0x00001000 },
 108     [VIRT_MMIO] =       { 0x0a000000, 0x00000200 },
 109     /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
 110     /* 0x10000000 .. 0x40000000 reserved for PCI */
 111     [VIRT_MEM] =        { 0x40000000, 30ULL * 1024 * 1024 * 1024 },
 112 };
 113
 114 static const int a15irqmap[] = {
 115     [VIRT_UART] = 1,
 116     [VIRT_RTC] = 2,
 117     [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
 118 };
 119
 120 static VirtBoardInfo machines[] = {
 121     {
 122         .cpu_model = "cortex-a15",
 123         .memmap = a15memmap,
 124         .irqmap = a15irqmap,
 125     },
 126     {
 127         .cpu_model = "cortex-a57",
 128         .memmap = a15memmap,
 129         .irqmap = a15irqmap,
 130     },
 131     {
 132         .cpu_model = "host",
 133         .memmap = a15memmap,
 134         .irqmap = a15irqmap,
 135     },
 136 };
 137
 138 static VirtBoardInfo *find_machine_info(const char *cpu)
 139 {
 140     int i;
 141
 142     for (i = 0; i < ARRAY_SIZE(machines); i++) {
 143         if (strcmp(cpu, machines[i].cpu_model) == 0) {
 144             return &machines[i];
 145         }
 146     }
 147     return NULL;
 148 }
 149
 150 static void create_fdt(VirtBoardInfo *vbi)
 151 {
 152     void *fdt = create_device_tree(&vbi->fdt_size);
 153
 154     if (!fdt) {
 155         error_report("create_device_tree() failed");
 156         exit(1);
 157     }
 158
 159     vbi->fdt = fdt;
 160
 161     /* Header */
 162     qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt");
 163     qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
 164     qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
 165
 166     /*
 167      * /chosen and /memory nodes must exist for load_dtb
 168      * to fill in necessary properties later
 169      */
 170     qemu_fdt_add_subnode(fdt, "/chosen");
 171     qemu_fdt_add_subnode(fdt, "/memory");
 172     qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory");
 173
 174     /* Clock node, for the benefit of the UART. The kernel device tree
 175      * binding documentation claims the PL011 node clock properties are
 176      * optional but in practice if you omit them the kernel refuses to
 177      * probe for the device.
 178      */
 179     vbi->clock_phandle = qemu_fdt_alloc_phandle(fdt);
 180     qemu_fdt_add_subnode(fdt, "/apb-pclk");
 181     qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock");
 182     qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0);
 183     qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000);
 184     qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names",
 185                                 "clk24mhz");
 186     qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vbi->clock_phandle);
 187
 188 }
 189
 190 static void fdt_add_psci_node(const VirtBoardInfo *vbi)
 191 {
 192     void *fdt = vbi->fdt;
 193     ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0));
 194
 195     /* No PSCI for TCG yet */
 196     if (kvm_enabled()) {
 197         qemu_fdt_add_subnode(fdt, "/psci");
 198         if (armcpu->psci_version == 2) {
 199             const char comp[] = "arm,psci-0.2\0arm,psci";
 200             qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp));
 201         } else {
 202             qemu_fdt_setprop_string(fdt, "/psci", "compatible", "arm,psci");
 203         }
 204
 205         qemu_fdt_setprop_string(fdt, "/psci", "method", "hvc");
 206         qemu_fdt_setprop_cell(fdt, "/psci", "cpu_suspend",
 207                                   PSCI_FN_CPU_SUSPEND);
 208         qemu_fdt_setprop_cell(fdt, "/psci", "cpu_off", PSCI_FN_CPU_OFF);
 209         qemu_fdt_setprop_cell(fdt, "/psci", "cpu_on", PSCI_FN_CPU_ON);
 210         qemu_fdt_setprop_cell(fdt, "/psci", "migrate", PSCI_FN_MIGRATE);
 211     }
 212 }
 213
 214 static void fdt_add_timer_nodes(const VirtBoardInfo *vbi)
 215 {
 216     /* Note that on A15 h/w these interrupts are level-triggered,
 217      * but for the GIC implementation provided by both QEMU and KVM
 218      * they are edge-triggered.
 219      */
 220     uint32_t irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI;
 221
 222     irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
 223                          GIC_FDT_IRQ_PPI_CPU_WIDTH, (1 << vbi->smp_cpus) - 1);
 224
 225     qemu_fdt_add_subnode(vbi->fdt, "/timer");
 226     qemu_fdt_setprop_string(vbi->fdt, "/timer",
 227                                 "compatible", "arm,armv7-timer");
 228     qemu_fdt_setprop_cells(vbi->fdt, "/timer", "interrupts",
 229                                GIC_FDT_IRQ_TYPE_PPI, 13, irqflags,
 230                                GIC_FDT_IRQ_TYPE_PPI, 14, irqflags,
 231                                GIC_FDT_IRQ_TYPE_PPI, 11, irqflags,
 232                                GIC_FDT_IRQ_TYPE_PPI, 10, irqflags);
 233 }
 234
 235 static void fdt_add_cpu_nodes(const VirtBoardInfo *vbi)
 236 {
 237     int cpu;
 238
 239     qemu_fdt_add_subnode(vbi->fdt, "/cpus");
 240     qemu_fdt_setprop_cell(vbi->fdt, "/cpus", "#address-cells", 0x1);
 241     qemu_fdt_setprop_cell(vbi->fdt, "/cpus", "#size-cells", 0x0);
 242
 243     for (cpu = vbi->smp_cpus - 1; cpu >= 0; cpu--) {
 244         char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
 245         ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
 246
 247         qemu_fdt_add_subnode(vbi->fdt, nodename);
 248         qemu_fdt_setprop_string(vbi->fdt, nodename, "device_type", "cpu");
 249         qemu_fdt_setprop_string(vbi->fdt, nodename, "compatible",
 250                                     armcpu->dtb_compatible);
 251
 252         if (vbi->smp_cpus > 1) {
 253             qemu_fdt_setprop_string(vbi->fdt, nodename,
 254                                         "enable-method", "psci");
 255         }
 256
 257         qemu_fdt_setprop_cell(vbi->fdt, nodename, "reg", cpu);
 258         g_free(nodename);
 259     }
 260 }
 261
 262 static void fdt_add_gic_node(const VirtBoardInfo *vbi)
 263 {
 264     uint32_t gic_phandle;
 265
 266     gic_phandle = qemu_fdt_alloc_phandle(vbi->fdt);
 267     qemu_fdt_setprop_cell(vbi->fdt, "/", "interrupt-parent", gic_phandle);
 268
 269     qemu_fdt_add_subnode(vbi->fdt, "/intc");
 270     /* 'cortex-a15-gic' means 'GIC v2' */
 271     qemu_fdt_setprop_string(vbi->fdt, "/intc", "compatible",
 272                             "arm,cortex-a15-gic");
 273     qemu_fdt_setprop_cell(vbi->fdt, "/intc", "#interrupt-cells", 3);
 274     qemu_fdt_setprop(vbi->fdt, "/intc", "interrupt-controller", NULL, 0);
 275     qemu_fdt_setprop_sized_cells(vbi->fdt, "/intc", "reg",
 276                                      2, vbi->memmap[VIRT_GIC_DIST].base,
 277                                      2, vbi->memmap[VIRT_GIC_DIST].size,
 278                                      2, vbi->memmap[VIRT_GIC_CPU].base,
 279                                      2, vbi->memmap[VIRT_GIC_CPU].size);
 280     qemu_fdt_setprop_cell(vbi->fdt, "/intc", "phandle", gic_phandle);
 281 }
 282
 283 static void create_gic(const VirtBoardInfo *vbi, qemu_irq *pic)
 284 {
 285     /* We create a standalone GIC v2 */
 286     DeviceState *gicdev;
 287     SysBusDevice *gicbusdev;
 288     const char *gictype = "arm_gic";
 289     int i;
 290
 291     if (kvm_irqchip_in_kernel()) {
 292         gictype = "kvm-arm-gic";
 293     }
 294
 295     gicdev = qdev_create(NULL, gictype);
 296     qdev_prop_set_uint32(gicdev, "revision", 2);
 297     qdev_prop_set_uint32(gicdev, "num-cpu", smp_cpus);
 298     /* Note that the num-irq property counts both internal and external
 299      * interrupts; there are always 32 of the former (mandated by GIC spec).
 300      */
 301     qdev_prop_set_uint32(gicdev, "num-irq", NUM_IRQS + 32);
 302     qdev_init_nofail(gicdev);
 303     gicbusdev = SYS_BUS_DEVICE(gicdev);
 304     sysbus_mmio_map(gicbusdev, 0, vbi->memmap[VIRT_GIC_DIST].base);
 305     sysbus_mmio_map(gicbusdev, 1, vbi->memmap[VIRT_GIC_CPU].base);
 306
 307     /* Wire the outputs from each CPU's generic timer to the
 308      * appropriate GIC PPI inputs, and the GIC's IRQ output to
 309      * the CPU's IRQ input.
 310      */
 311     for (i = 0; i < smp_cpus; i++) {
 312         DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
 313         int ppibase = NUM_IRQS + i * 32;
 314         /* physical timer; we wire it up to the non-secure timer's ID,
 315          * since a real A15 always has TrustZone but QEMU doesn't.
 316          */
 317         qdev_connect_gpio_out(cpudev, 0,
 318                               qdev_get_gpio_in(gicdev, ppibase + 30));
 319         /* virtual timer */
 320         qdev_connect_gpio_out(cpudev, 1,
 321                               qdev_get_gpio_in(gicdev, ppibase + 27));
 322
 323         sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
 324     }
 325
 326     for (i = 0; i < NUM_IRQS; i++) {
 327         pic[i] = qdev_get_gpio_in(gicdev, i);
 328     }
 329
 330     fdt_add_gic_node(vbi);
 331 }
 332
 333 static void create_uart(const VirtBoardInfo *vbi, qemu_irq *pic)
 334 {
 335     char *nodename;
 336     hwaddr base = vbi->memmap[VIRT_UART].base;
 337     hwaddr size = vbi->memmap[VIRT_UART].size;
 338     int irq = vbi->irqmap[VIRT_UART];
 339     const char compat[] = "arm,pl011\0arm,primecell";
 340     const char clocknames[] = "uartclk\0apb_pclk";
 341
 342     sysbus_create_simple("pl011", base, pic[irq]);
 343
 344     nodename = g_strdup_printf("/pl011@%" PRIx64, base);
 345     qemu_fdt_add_subnode(vbi->fdt, nodename);
 346     /* Note that we can't use setprop_string because of the embedded NUL */
 347     qemu_fdt_setprop(vbi->fdt, nodename, "compatible",
 348                          compat, sizeof(compat));
 349     qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg",
 350                                      2, base, 2, size);
 351     qemu_fdt_setprop_cells(vbi->fdt, nodename, "interrupts",
 352                                GIC_FDT_IRQ_TYPE_SPI, irq,
 353                                GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
 354     qemu_fdt_setprop_cells(vbi->fdt, nodename, "clocks",
 355                                vbi->clock_phandle, vbi->clock_phandle);
 356     qemu_fdt_setprop(vbi->fdt, nodename, "clock-names",
 357                          clocknames, sizeof(clocknames));
 358     g_free(nodename);
 359 }
 360
 361 static void create_rtc(const VirtBoardInfo *vbi, qemu_irq *pic)
 362 {
 363     char *nodename;
 364     hwaddr base = vbi->memmap[VIRT_RTC].base;
 365     hwaddr size = vbi->memmap[VIRT_RTC].size;
 366     int irq = vbi->irqmap[VIRT_RTC];
 367     const char compat[] = "arm,pl031\0arm,primecell";
 368
 369     sysbus_create_simple("pl031", base, pic[irq]);
 370
 371     nodename = g_strdup_printf("/pl031@%" PRIx64, base);
 372     qemu_fdt_add_subnode(vbi->fdt, nodename);
 373     qemu_fdt_setprop(vbi->fdt, nodename, "compatible", compat, sizeof(compat));
 374     qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg",
 375                                  2, base, 2, size);
 376     qemu_fdt_setprop_cells(vbi->fdt, nodename, "interrupts",
 377                            GIC_FDT_IRQ_TYPE_SPI, irq,
 378                            GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
 379     qemu_fdt_setprop_cell(vbi->fdt, nodename, "clocks", vbi->clock_phandle);
 380     qemu_fdt_setprop_string(vbi->fdt, nodename, "clock-names", "apb_pclk");
 381     g_free(nodename);
 382 }
 383
 384 static void create_virtio_devices(const VirtBoardInfo *vbi, qemu_irq *pic)
 385 {
 386     int i;
 387     hwaddr size = vbi->memmap[VIRT_MMIO].size;
 388
 389     /* Note that we have to create the transports in forwards order
 390      * so that command line devices are inserted lowest address first,
 391      * and then add dtb nodes in reverse order so that they appear in
 392      * the finished device tree lowest address first.
 393      */
 394     for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) {
 395         int irq = vbi->irqmap[VIRT_MMIO] + i;
 396         hwaddr base = vbi->memmap[VIRT_MMIO].base + i * size;
 397
 398         sysbus_create_simple("virtio-mmio", base, pic[irq]);
 399     }
 400
 401     for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) {
 402         char *nodename;
 403         int irq = vbi->irqmap[VIRT_MMIO] + i;
 404         hwaddr base = vbi->memmap[VIRT_MMIO].base + i * size;
 405
 406         nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base);
 407         qemu_fdt_add_subnode(vbi->fdt, nodename);
 408         qemu_fdt_setprop_string(vbi->fdt, nodename,
 409                                 "compatible", "virtio,mmio");
 410         qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg",
 411                                      2, base, 2, size);
 412         qemu_fdt_setprop_cells(vbi->fdt, nodename, "interrupts",
 413                                GIC_FDT_IRQ_TYPE_SPI, irq,
 414                                GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
 415         g_free(nodename);
 416     }
 417 }
 418
 419 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size)
 420 {
 421     const VirtBoardInfo *board = (const VirtBoardInfo *)binfo;
 422
 423     *fdt_size = board->fdt_size;
 424     return board->fdt;
 425 }
 426
 427 static void machvirt_init(MachineState *machine)
 428 {
 429     qemu_irq pic[NUM_IRQS];
 430     MemoryRegion *sysmem = get_system_memory();
 431     int n;
 432     MemoryRegion *ram = g_new(MemoryRegion, 1);
 433     const char *cpu_model = machine->cpu_model;
 434     VirtBoardInfo *vbi;
 435
 436     if (!cpu_model) {
 437         cpu_model = "cortex-a15";
 438     }
 439
 440     vbi = find_machine_info(cpu_model);
 441
 442     if (!vbi) {
 443         error_report("mach-virt: CPU %s not supported", cpu_model);
 444         exit(1);
 445     }
 446
 447     vbi->smp_cpus = smp_cpus;
 448
 449     /*
 450      * Only supported method of starting secondary CPUs is PSCI and
 451      * PSCI is not yet supported with TCG, so limit smp_cpus to 1
 452      * if we're not using KVM.
 453      */
 454     if (!kvm_enabled() && smp_cpus > 1) {
 455         error_report("mach-virt: must enable KVM to use multiple CPUs");
 456         exit(1);
 457     }
 458
 459     if (machine->ram_size > vbi->memmap[VIRT_MEM].size) {
 460         error_report("mach-virt: cannot model more than 30GB RAM");
 461         exit(1);
 462     }
 463
 464     create_fdt(vbi);
 465     fdt_add_timer_nodes(vbi);
 466
 467     for (n = 0; n < smp_cpus; n++) {
 468         ObjectClass *oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
 469         Object *cpuobj;
 470
 471         if (!oc) {
 472             fprintf(stderr, "Unable to find CPU definition\n");
 473             exit(1);
 474         }
 475         cpuobj = object_new(object_class_get_name(oc));
 476
 477         /* Secondary CPUs start in PSCI powered-down state */
 478         if (n > 0) {
 479             object_property_set_bool(cpuobj, true, "start-powered-off", NULL);
 480         }
 481
 482         if (object_property_find(cpuobj, "reset-cbar", NULL)) {
 483             object_property_set_int(cpuobj, vbi->memmap[VIRT_CPUPERIPHS].base,
 484                                     "reset-cbar", &error_abort);
 485         }
 486
 487         object_property_set_bool(cpuobj, true, "realized", NULL);
 488     }
 489     fdt_add_cpu_nodes(vbi);
 490     fdt_add_psci_node(vbi);
 491
 492     memory_region_init_ram(ram, NULL, "mach-virt.ram", machine->ram_size);
 493     vmstate_register_ram_global(ram);
 494     memory_region_add_subregion(sysmem, vbi->memmap[VIRT_MEM].base, ram);
 495
 496     create_gic(vbi, pic);
 497
 498     create_uart(vbi, pic);
 499
 500     create_rtc(vbi, pic);
 501
 502     /* Create mmio transports, so the user can create virtio backends
 503      * (which will be automatically plugged in to the transports). If
 504      * no backend is created the transport will just sit harmlessly idle.
 505      */
 506     create_virtio_devices(vbi, pic);
 507
 508     vbi->bootinfo.ram_size = machine->ram_size;
 509     vbi->bootinfo.kernel_filename = machine->kernel_filename;
 510     vbi->bootinfo.kernel_cmdline = machine->kernel_cmdline;
 511     vbi->bootinfo.initrd_filename = machine->initrd_filename;
 512     vbi->bootinfo.nb_cpus = smp_cpus;
 513     vbi->bootinfo.board_id = -1;
 514     vbi->bootinfo.loader_start = vbi->memmap[VIRT_MEM].base;
 515     vbi->bootinfo.get_dtb = machvirt_dtb;
 516     arm_load_kernel(ARM_CPU(first_cpu), &vbi->bootinfo);
 517 }
 518
 519 static QEMUMachine machvirt_a15_machine = {
 520     .name = "virt",
 521     .desc = "ARM Virtual Machine",
 522     .init = machvirt_init,
 523     .max_cpus = 4,
 524 };
 525
 526 static void machvirt_machine_init(void)
 527 {
 528     qemu_register_machine(&machvirt_a15_machine);
 529 }
 530
 531 machine_init(machvirt_machine_init);