target/hppa/cpu.h

   1 /*
   2  * PA-RISC emulation cpu definitions for qemu.
   3  *
   4  * Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef HPPA_CPU_H
  21 #define HPPA_CPU_H
  22
  23 #include "qemu-common.h"
  24 #include "cpu-qom.h"
  25
  26 #define TARGET_LONG_BITS            32
  27 #define TARGET_VIRT_ADDR_SPACE_BITS 32
  28 #define TARGET_REGISTER_BITS        32
  29 #define TARGET_PHYS_ADDR_SPACE_BITS 32
  30
  31 #define CPUArchState struct CPUHPPAState
  32
  33 #include "exec/cpu-defs.h"
  34 #include "fpu/softfloat.h"
  35
  36 #define TARGET_PAGE_BITS 12
  37
  38 #define ALIGNED_ONLY
  39 #define NB_MMU_MODES     5
  40 #define MMU_KERNEL_IDX   0
  41 #define MMU_USER_IDX     3
  42 #define MMU_PHYS_IDX     4
  43 #define TARGET_INSN_START_EXTRA_WORDS 1
  44
  45 /* Hardware exceptions, interupts, faults, and traps.  */
  46 #define EXCP_HPMC                1  /* high priority machine check */
  47 #define EXCP_POWER_FAIL          2
  48 #define EXCP_RC                  3  /* recovery counter */
  49 #define EXCP_EXT_INTERRUPT       4  /* external interrupt */
  50 #define EXCP_LPMC                5  /* low priority machine check */
  51 #define EXCP_ITLB_MISS           6  /* itlb miss / instruction page fault */
  52 #define EXCP_IMP                 7  /* instruction memory protection trap */
  53 #define EXCP_ILL                 8  /* illegal instruction trap */
  54 #define EXCP_BREAK               9  /* break instruction */
  55 #define EXCP_PRIV_OPR            10 /* privileged operation trap */
  56 #define EXCP_PRIV_REG            11 /* privileged register trap */
  57 #define EXCP_OVERFLOW            12 /* signed overflow trap */
  58 #define EXCP_COND                13 /* trap-on-condition */
  59 #define EXCP_ASSIST              14 /* assist exception trap */
  60 #define EXCP_DTLB_MISS           15 /* dtlb miss / data page fault */
  61 #define EXCP_NA_ITLB_MISS        16 /* non-access itlb miss */
  62 #define EXCP_NA_DTLB_MISS        17 /* non-access dtlb miss */
  63 #define EXCP_DMP                 18 /* data memory protection trap */
  64 #define EXCP_DMB                 19 /* data memory break trap */
  65 #define EXCP_TLB_DIRTY           20 /* tlb dirty bit trap */
  66 #define EXCP_PAGE_REF            21 /* page reference trap */
  67 #define EXCP_ASSIST_EMU          22 /* assist emulation trap */
  68 #define EXCP_HPT                 23 /* high-privilege transfer trap */
  69 #define EXCP_LPT                 24 /* low-privilege transfer trap */
  70 #define EXCP_TB                  25 /* taken branch trap */
  71 #define EXCP_DMAR                26 /* data memory access rights trap */
  72 #define EXCP_DMPI                27 /* data memory protection id trap */
  73 #define EXCP_UNALIGN             28 /* unaligned data reference trap */
  74 #define EXCP_PER_INTERRUPT       29 /* performance monitor interrupt */
  75
  76 /* Exceptions for linux-user emulation.  */
  77 #define EXCP_SYSCALL             30
  78 #define EXCP_SYSCALL_LWS         31
  79
  80 /* Taken from Linux kernel: arch/parisc/include/asm/psw.h */
  81 #define PSW_I            0x00000001
  82 #define PSW_D            0x00000002
  83 #define PSW_P            0x00000004
  84 #define PSW_Q            0x00000008
  85 #define PSW_R            0x00000010
  86 #define PSW_F            0x00000020
  87 #define PSW_G            0x00000040 /* PA1.x only */
  88 #define PSW_O            0x00000080 /* PA2.0 only */
  89 #define PSW_CB           0x0000ff00
  90 #define PSW_M            0x00010000
  91 #define PSW_V            0x00020000
  92 #define PSW_C            0x00040000
  93 #define PSW_B            0x00080000
  94 #define PSW_X            0x00100000
  95 #define PSW_N            0x00200000
  96 #define PSW_L            0x00400000
  97 #define PSW_H            0x00800000
  98 #define PSW_T            0x01000000
  99 #define PSW_S            0x02000000
 100 #define PSW_E            0x04000000
 101 #ifdef TARGET_HPPA64
 102 #define PSW_W            0x08000000 /* PA2.0 only */
 103 #else
 104 #define PSW_W            0
 105 #endif
 106 #define PSW_Z            0x40000000 /* PA1.x only */
 107 #define PSW_Y            0x80000000 /* PA1.x only */
 108
 109 #define PSW_SM (PSW_W | PSW_E | PSW_O | PSW_G | PSW_F \
 110                | PSW_R | PSW_Q | PSW_P | PSW_D | PSW_I)
 111
 112 /* ssm/rsm instructions number PSW_W and PSW_E differently */
 113 #define PSW_SM_I         PSW_I      /* Enable External Interrupts */
 114 #define PSW_SM_D         PSW_D
 115 #define PSW_SM_P         PSW_P
 116 #define PSW_SM_Q         PSW_Q      /* Enable Interrupt State Collection */
 117 #define PSW_SM_R         PSW_R      /* Enable Recover Counter Trap */
 118 #ifdef TARGET_HPPA64
 119 #define PSW_SM_E         0x100
 120 #define PSW_SM_W         0x200      /* PA2.0 only : Enable Wide Mode */
 121 #else
 122 #define PSW_SM_E         0
 123 #define PSW_SM_W         0
 124 #endif
 125
 126 #define CR_RC            0
 127 #define CR_SCRCCR        10
 128 #define CR_SAR           11
 129 #define CR_IVA           14
 130 #define CR_EIEM          15
 131 #define CR_IT            16
 132 #define CR_IIASQ         17
 133 #define CR_IIAOQ         18
 134 #define CR_IIR           19
 135 #define CR_ISR           20
 136 #define CR_IOR           21
 137 #define CR_IPSW          22
 138 #define CR_EIRR          23
 139
 140 typedef struct CPUHPPAState CPUHPPAState;
 141
 142 #if TARGET_REGISTER_BITS == 32
 143 typedef uint32_t target_ureg;
 144 typedef int32_t  target_sreg;
 145 #define TREG_FMT_lx   "%08"PRIx32
 146 #define TREG_FMT_ld   "%"PRId32
 147 #else
 148 typedef uint64_t target_ureg;
 149 typedef int64_t  target_sreg;
 150 #define TREG_FMT_lx   "%016"PRIx64
 151 #define TREG_FMT_ld   "%"PRId64
 152 #endif
 153
 154 struct CPUHPPAState {
 155     target_ureg gr[32];
 156     uint64_t fr[32];
 157     uint64_t sr[8];          /* stored shifted into place for gva */
 158
 159     target_ureg psw;         /* All psw bits except the following:  */
 160     target_ureg psw_n;       /* boolean */
 161     target_sreg psw_v;       /* in most significant bit */
 162
 163     /* Splitting the carry-borrow field into the MSB and "the rest", allows
 164      * for "the rest" to be deleted when it is unused, but the MSB is in use.
 165      * In addition, it's easier to compute carry-in for bit B+1 than it is to
 166      * compute carry-out for bit B (3 vs 4 insns for addition, assuming the
 167      * host has the appropriate add-with-carry insn to compute the msb).
 168      * Therefore the carry bits are stored as: cb_msb : cb & 0x11111110.
 169      */
 170     target_ureg psw_cb;      /* in least significant bit of next nibble */
 171     target_ureg psw_cb_msb;  /* boolean */
 172
 173     target_ureg iaoq_f;      /* front */
 174     target_ureg iaoq_b;      /* back, aka next instruction */
 175
 176     uint32_t fr0_shadow;     /* flags, c, ca/cq, rm, d, enables */
 177     float_status fp_status;
 178
 179     target_ureg cr[32];      /* control registers */
 180     target_ureg cr_back[2];  /* back of cr17/cr18 */
 181     target_ureg shadow[7];   /* shadow registers */
 182
 183     /* Those resources are used only in QEMU core */
 184     CPU_COMMON
 185 };
 186
 187 /**
 188  * HPPACPU:
 189  * @env: #CPUHPPAState
 190  *
 191  * An HPPA CPU.
 192  */
 193 struct HPPACPU {
 194     /*< private >*/
 195     CPUState parent_obj;
 196     /*< public >*/
 197
 198     CPUHPPAState env;
 199 };
 200
 201 static inline HPPACPU *hppa_env_get_cpu(CPUHPPAState *env)
 202 {
 203     return container_of(env, HPPACPU, env);
 204 }
 205
 206 #define ENV_GET_CPU(e)  CPU(hppa_env_get_cpu(e))
 207 #define ENV_OFFSET      offsetof(HPPACPU, env)
 208
 209 #include "exec/cpu-all.h"
 210
 211 static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch)
 212 {
 213 #ifdef CONFIG_USER_ONLY
 214     return MMU_USER_IDX;
 215 #else
 216     if (env->psw & (ifetch ? PSW_C : PSW_D)) {
 217         return env->iaoq_f & 3;
 218     }
 219     return MMU_PHYS_IDX;  /* mmu disabled */
 220 #endif
 221 }
 222
 223 void hppa_translate_init(void);
 224
 225 #define cpu_init(cpu_model) cpu_generic_init(TYPE_HPPA_CPU, cpu_model)
 226
 227 void hppa_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 228
 229 static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, target_ulong *pc,
 230                                         target_ulong *cs_base,
 231                                         uint32_t *pflags)
 232 {
 233     *pc = env->iaoq_f;
 234     *cs_base = env->iaoq_b;
 235     /* ??? E, T, H, L, B, P bits need to be here, when implemented.  */
 236     *pflags = (env->psw & (PSW_W | PSW_C | PSW_D))
 237             | env->psw_n * PSW_N;
 238 }
 239
 240 target_ureg cpu_hppa_get_psw(CPUHPPAState *env);
 241 void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg);
 242 void cpu_hppa_loaded_fr0(CPUHPPAState *env);
 243
 244 #define cpu_signal_handler cpu_hppa_signal_handler
 245
 246 int cpu_hppa_signal_handler(int host_signum, void *pinfo, void *puc);
 247 int hppa_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size,
 248                               int rw, int midx);
 249 hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr);
 250 int hppa_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
 251 int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 252 void hppa_cpu_do_interrupt(CPUState *cpu);
 253 bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req);
 254 void hppa_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function, int);
 255
 256 #endif /* HPPA_CPU_H */