tcg/s390/tcg-target.h

   1 /*
   2  * Tiny Code Generator for QEMU
   3  *
   4  * Copyright (c) 2009 Ulrich Hecht <uli@suse.de>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #define TCG_TARGET_S390 1
  25
  26 #ifdef __s390x__
  27 #define TCG_TARGET_REG_BITS 64
  28 #else
  29 #define TCG_TARGET_REG_BITS 32
  30 #endif
  31
  32 #define TCG_TARGET_WORDS_BIGENDIAN
  33
  34 typedef enum TCGReg {
  35     TCG_REG_R0 = 0,
  36     TCG_REG_R1,
  37     TCG_REG_R2,
  38     TCG_REG_R3,
  39     TCG_REG_R4,
  40     TCG_REG_R5,
  41     TCG_REG_R6,
  42     TCG_REG_R7,
  43     TCG_REG_R8,
  44     TCG_REG_R9,
  45     TCG_REG_R10,
  46     TCG_REG_R11,
  47     TCG_REG_R12,
  48     TCG_REG_R13,
  49     TCG_REG_R14,
  50     TCG_REG_R15
  51 } TCGReg;
  52
  53 #define TCG_TARGET_NB_REGS 16
  54
  55 /* optional instructions */
  56 #define TCG_TARGET_HAS_div2_i32         1
  57 #define TCG_TARGET_HAS_rot_i32          1
  58 #define TCG_TARGET_HAS_ext8s_i32        1
  59 #define TCG_TARGET_HAS_ext16s_i32       1
  60 #define TCG_TARGET_HAS_ext8u_i32        1
  61 #define TCG_TARGET_HAS_ext16u_i32       1
  62 #define TCG_TARGET_HAS_bswap16_i32      1
  63 #define TCG_TARGET_HAS_bswap32_i32      1
  64 #define TCG_TARGET_HAS_not_i32          0
  65 #define TCG_TARGET_HAS_neg_i32          1
  66 #define TCG_TARGET_HAS_andc_i32         0
  67 #define TCG_TARGET_HAS_orc_i32          0
  68 #define TCG_TARGET_HAS_eqv_i32          0
  69 #define TCG_TARGET_HAS_nand_i32         0
  70 #define TCG_TARGET_HAS_nor_i32          0
  71 #define TCG_TARGET_HAS_deposit_i32      0
  72
  73 #if TCG_TARGET_REG_BITS == 64
  74 #define TCG_TARGET_HAS_div2_i64         1
  75 #define TCG_TARGET_HAS_rot_i64          1
  76 #define TCG_TARGET_HAS_ext8s_i64        1
  77 #define TCG_TARGET_HAS_ext16s_i64       1
  78 #define TCG_TARGET_HAS_ext32s_i64       1
  79 #define TCG_TARGET_HAS_ext8u_i64        1
  80 #define TCG_TARGET_HAS_ext16u_i64       1
  81 #define TCG_TARGET_HAS_ext32u_i64       1
  82 #define TCG_TARGET_HAS_bswap16_i64      1
  83 #define TCG_TARGET_HAS_bswap32_i64      1
  84 #define TCG_TARGET_HAS_bswap64_i64      1
  85 #define TCG_TARGET_HAS_not_i64          0
  86 #define TCG_TARGET_HAS_neg_i64          1
  87 #define TCG_TARGET_HAS_andc_i64         0
  88 #define TCG_TARGET_HAS_orc_i64          0
  89 #define TCG_TARGET_HAS_eqv_i64          0
  90 #define TCG_TARGET_HAS_nand_i64         0
  91 #define TCG_TARGET_HAS_nor_i64          0
  92 #define TCG_TARGET_HAS_deposit_i64      0
  93 #endif
  94
  95 #define TCG_TARGET_HAS_GUEST_BASE
  96
  97 /* used for function call generation */
  98 #define TCG_REG_CALL_STACK              TCG_REG_R15
  99 #define TCG_TARGET_STACK_ALIGN          8
 100 #define TCG_TARGET_CALL_STACK_OFFSET    0
 101
 102 #define TCG_TARGET_EXTEND_ARGS 1
 103
 104 enum {
 105     /* Note: must be synced with dyngen-exec.h */
 106     TCG_AREG0 = TCG_REG_R10,
 107 };
 108
 109 static inline void flush_icache_range(unsigned long start, unsigned long stop)
 110 {
 111 }