target-arm/cpu.c

   1 /*
   2  * QEMU ARM CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qapi/error.h"
  23 #include "cpu.h"
  24 #include "internals.h"
  25 #include "qemu-common.h"
  26 #include "exec/exec-all.h"
  27 #include "hw/qdev-properties.h"
  28 #if !defined(CONFIG_USER_ONLY)
  29 #include "hw/loader.h"
  30 #endif
  31 #include "hw/arm/arm.h"
  32 #include "sysemu/sysemu.h"
  33 #include "sysemu/kvm.h"
  34 #include "kvm_arm.h"
  35
  36 static void arm_cpu_set_pc(CPUState *cs, vaddr value)
  37 {
  38     ARMCPU *cpu = ARM_CPU(cs);
  39
  40     cpu->env.regs[15] = value;
  41 }
  42
  43 static bool arm_cpu_has_work(CPUState *cs)
  44 {
  45     ARMCPU *cpu = ARM_CPU(cs);
  46
  47     return !cpu->powered_off
  48         && cs->interrupt_request &
  49         (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
  50          | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ
  51          | CPU_INTERRUPT_EXITTB);
  52 }
  53
  54 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHook *hook,
  55                                  void *opaque)
  56 {
  57     /* We currently only support registering a single hook function */
  58     assert(!cpu->el_change_hook);
  59     cpu->el_change_hook = hook;
  60     cpu->el_change_hook_opaque = opaque;
  61 }
  62
  63 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
  64 {
  65     /* Reset a single ARMCPRegInfo register */
  66     ARMCPRegInfo *ri = value;
  67     ARMCPU *cpu = opaque;
  68
  69     if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) {
  70         return;
  71     }
  72
  73     if (ri->resetfn) {
  74         ri->resetfn(&cpu->env, ri);
  75         return;
  76     }
  77
  78     /* A zero offset is never possible as it would be regs[0]
  79      * so we use it to indicate that reset is being handled elsewhere.
  80      * This is basically only used for fields in non-core coprocessors
  81      * (like the pxa2xx ones).
  82      */
  83     if (!ri->fieldoffset) {
  84         return;
  85     }
  86
  87     if (cpreg_field_is_64bit(ri)) {
  88         CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
  89     } else {
  90         CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
  91     }
  92 }
  93
  94 static void cp_reg_check_reset(gpointer key, gpointer value,  gpointer opaque)
  95 {
  96     /* Purely an assertion check: we've already done reset once,
  97      * so now check that running the reset for the cpreg doesn't
  98      * change its value. This traps bugs where two different cpregs
  99      * both try to reset the same state field but to different values.
 100      */
 101     ARMCPRegInfo *ri = value;
 102     ARMCPU *cpu = opaque;
 103     uint64_t oldvalue, newvalue;
 104
 105     if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) {
 106         return;
 107     }
 108
 109     oldvalue = read_raw_cp_reg(&cpu->env, ri);
 110     cp_reg_reset(key, value, opaque);
 111     newvalue = read_raw_cp_reg(&cpu->env, ri);
 112     assert(oldvalue == newvalue);
 113 }
 114
 115 /* CPUClass::reset() */
 116 static void arm_cpu_reset(CPUState *s)
 117 {
 118     ARMCPU *cpu = ARM_CPU(s);
 119     ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
 120     CPUARMState *env = &cpu->env;
 121
 122     acc->parent_reset(s);
 123
 124     memset(env, 0, offsetof(CPUARMState, features));
 125     g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
 126     g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu);
 127
 128     env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
 129     env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
 130     env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
 131     env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2;
 132
 133     cpu->powered_off = cpu->start_powered_off;
 134     s->halted = cpu->start_powered_off;
 135
 136     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 137         env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
 138     }
 139
 140     if (arm_feature(env, ARM_FEATURE_AARCH64)) {
 141         /* 64 bit CPUs always start in 64 bit mode */
 142         env->aarch64 = 1;
 143 #if defined(CONFIG_USER_ONLY)
 144         env->pstate = PSTATE_MODE_EL0t;
 145         /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
 146         env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE;
 147         /* and to the FP/Neon instructions */
 148         env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3);
 149 #else
 150         /* Reset into the highest available EL */
 151         if (arm_feature(env, ARM_FEATURE_EL3)) {
 152             env->pstate = PSTATE_MODE_EL3h;
 153         } else if (arm_feature(env, ARM_FEATURE_EL2)) {
 154             env->pstate = PSTATE_MODE_EL2h;
 155         } else {
 156             env->pstate = PSTATE_MODE_EL1h;
 157         }
 158         env->pc = cpu->rvbar;
 159 #endif
 160     } else {
 161 #if defined(CONFIG_USER_ONLY)
 162         /* Userspace expects access to cp10 and cp11 for FP/Neon */
 163         env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf);
 164 #endif
 165     }
 166
 167 #if defined(CONFIG_USER_ONLY)
 168     env->uncached_cpsr = ARM_CPU_MODE_USR;
 169     /* For user mode we must enable access to coprocessors */
 170     env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
 171     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 172         env->cp15.c15_cpar = 3;
 173     } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
 174         env->cp15.c15_cpar = 1;
 175     }
 176 #else
 177     /* SVC mode with interrupts disabled.  */
 178     env->uncached_cpsr = ARM_CPU_MODE_SVC;
 179     env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
 180     /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
 181      * clear at reset. Initial SP and PC are loaded from ROM.
 182      */
 183     if (IS_M(env)) {
 184         uint32_t initial_msp; /* Loaded from 0x0 */
 185         uint32_t initial_pc; /* Loaded from 0x4 */
 186         uint8_t *rom;
 187
 188         env->daif &= ~PSTATE_I;
 189         rom = rom_ptr(0);
 190         if (rom) {
 191             /* Address zero is covered by ROM which hasn't yet been
 192              * copied into physical memory.
 193              */
 194             initial_msp = ldl_p(rom);
 195             initial_pc = ldl_p(rom + 4);
 196         } else {
 197             /* Address zero not covered by a ROM blob, or the ROM blob
 198              * is in non-modifiable memory and this is a second reset after
 199              * it got copied into memory. In the latter case, rom_ptr
 200              * will return a NULL pointer and we should use ldl_phys instead.
 201              */
 202             initial_msp = ldl_phys(s->as, 0);
 203             initial_pc = ldl_phys(s->as, 4);
 204         }
 205
 206         env->regs[13] = initial_msp & 0xFFFFFFFC;
 207         env->regs[15] = initial_pc & ~1;
 208         env->thumb = initial_pc & 1;
 209     }
 210
 211     /* AArch32 has a hard highvec setting of 0xFFFF0000.  If we are currently
 212      * executing as AArch32 then check if highvecs are enabled and
 213      * adjust the PC accordingly.
 214      */
 215     if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
 216         env->regs[15] = 0xFFFF0000;
 217     }
 218
 219     env->vfp.xregs[ARM_VFP_FPEXC] = 0;
 220 #endif
 221     set_flush_to_zero(1, &env->vfp.standard_fp_status);
 222     set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
 223     set_default_nan_mode(1, &env->vfp.standard_fp_status);
 224     set_float_detect_tininess(float_tininess_before_rounding,
 225                               &env->vfp.fp_status);
 226     set_float_detect_tininess(float_tininess_before_rounding,
 227                               &env->vfp.standard_fp_status);
 228     tlb_flush(s, 1);
 229
 230 #ifndef CONFIG_USER_ONLY
 231     if (kvm_enabled()) {
 232         kvm_arm_reset_vcpu(cpu);
 233     }
 234 #endif
 235
 236     hw_breakpoint_update_all(cpu);
 237     hw_watchpoint_update_all(cpu);
 238 }
 239
 240 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 241 {
 242     CPUClass *cc = CPU_GET_CLASS(cs);
 243     CPUARMState *env = cs->env_ptr;
 244     uint32_t cur_el = arm_current_el(env);
 245     bool secure = arm_is_secure(env);
 246     uint32_t target_el;
 247     uint32_t excp_idx;
 248     bool ret = false;
 249
 250     if (interrupt_request & CPU_INTERRUPT_FIQ) {
 251         excp_idx = EXCP_FIQ;
 252         target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
 253         if (arm_excp_unmasked(cs, excp_idx, target_el)) {
 254             cs->exception_index = excp_idx;
 255             env->exception.target_el = target_el;
 256             cc->do_interrupt(cs);
 257             ret = true;
 258         }
 259     }
 260     if (interrupt_request & CPU_INTERRUPT_HARD) {
 261         excp_idx = EXCP_IRQ;
 262         target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
 263         if (arm_excp_unmasked(cs, excp_idx, target_el)) {
 264             cs->exception_index = excp_idx;
 265             env->exception.target_el = target_el;
 266             cc->do_interrupt(cs);
 267             ret = true;
 268         }
 269     }
 270     if (interrupt_request & CPU_INTERRUPT_VIRQ) {
 271         excp_idx = EXCP_VIRQ;
 272         target_el = 1;
 273         if (arm_excp_unmasked(cs, excp_idx, target_el)) {
 274             cs->exception_index = excp_idx;
 275             env->exception.target_el = target_el;
 276             cc->do_interrupt(cs);
 277             ret = true;
 278         }
 279     }
 280     if (interrupt_request & CPU_INTERRUPT_VFIQ) {
 281         excp_idx = EXCP_VFIQ;
 282         target_el = 1;
 283         if (arm_excp_unmasked(cs, excp_idx, target_el)) {
 284             cs->exception_index = excp_idx;
 285             env->exception.target_el = target_el;
 286             cc->do_interrupt(cs);
 287             ret = true;
 288         }
 289     }
 290
 291     return ret;
 292 }
 293
 294 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 295 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 296 {
 297     CPUClass *cc = CPU_GET_CLASS(cs);
 298     ARMCPU *cpu = ARM_CPU(cs);
 299     CPUARMState *env = &cpu->env;
 300     bool ret = false;
 301
 302
 303     if (interrupt_request & CPU_INTERRUPT_FIQ
 304         && !(env->daif & PSTATE_F)) {
 305         cs->exception_index = EXCP_FIQ;
 306         cc->do_interrupt(cs);
 307         ret = true;
 308     }
 309     /* ARMv7-M interrupt return works by loading a magic value
 310      * into the PC.  On real hardware the load causes the
 311      * return to occur.  The qemu implementation performs the
 312      * jump normally, then does the exception return when the
 313      * CPU tries to execute code at the magic address.
 314      * This will cause the magic PC value to be pushed to
 315      * the stack if an interrupt occurred at the wrong time.
 316      * We avoid this by disabling interrupts when
 317      * pc contains a magic address.
 318      */
 319     if (interrupt_request & CPU_INTERRUPT_HARD
 320         && !(env->daif & PSTATE_I)
 321         && (env->regs[15] < 0xfffffff0)) {
 322         cs->exception_index = EXCP_IRQ;
 323         cc->do_interrupt(cs);
 324         ret = true;
 325     }
 326     return ret;
 327 }
 328 #endif
 329
 330 #ifndef CONFIG_USER_ONLY
 331 static void arm_cpu_set_irq(void *opaque, int irq, int level)
 332 {
 333     ARMCPU *cpu = opaque;
 334     CPUARMState *env = &cpu->env;
 335     CPUState *cs = CPU(cpu);
 336     static const int mask[] = {
 337         [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD,
 338         [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ,
 339         [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ,
 340         [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ
 341     };
 342
 343     switch (irq) {
 344     case ARM_CPU_VIRQ:
 345     case ARM_CPU_VFIQ:
 346         assert(arm_feature(env, ARM_FEATURE_EL2));
 347         /* fall through */
 348     case ARM_CPU_IRQ:
 349     case ARM_CPU_FIQ:
 350         if (level) {
 351             cpu_interrupt(cs, mask[irq]);
 352         } else {
 353             cpu_reset_interrupt(cs, mask[irq]);
 354         }
 355         break;
 356     default:
 357         g_assert_not_reached();
 358     }
 359 }
 360
 361 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
 362 {
 363 #ifdef CONFIG_KVM
 364     ARMCPU *cpu = opaque;
 365     CPUState *cs = CPU(cpu);
 366     int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT;
 367
 368     switch (irq) {
 369     case ARM_CPU_IRQ:
 370         kvm_irq |= KVM_ARM_IRQ_CPU_IRQ;
 371         break;
 372     case ARM_CPU_FIQ:
 373         kvm_irq |= KVM_ARM_IRQ_CPU_FIQ;
 374         break;
 375     default:
 376         g_assert_not_reached();
 377     }
 378     kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT;
 379     kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0);
 380 #endif
 381 }
 382
 383 static bool arm_cpu_virtio_is_big_endian(CPUState *cs)
 384 {
 385     ARMCPU *cpu = ARM_CPU(cs);
 386     CPUARMState *env = &cpu->env;
 387
 388     cpu_synchronize_state(cs);
 389     return arm_cpu_data_is_big_endian(env);
 390 }
 391
 392 #endif
 393
 394 static inline void set_feature(CPUARMState *env, int feature)
 395 {
 396     env->features |= 1ULL << feature;
 397 }
 398
 399 static inline void unset_feature(CPUARMState *env, int feature)
 400 {
 401     env->features &= ~(1ULL << feature);
 402 }
 403
 404 static int
 405 print_insn_thumb1(bfd_vma pc, disassemble_info *info)
 406 {
 407   return print_insn_arm(pc | 1, info);
 408 }
 409
 410 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
 411 {
 412     ARMCPU *ac = ARM_CPU(cpu);
 413     CPUARMState *env = &ac->env;
 414
 415     if (is_a64(env)) {
 416         /* We might not be compiled with the A64 disassembler
 417          * because it needs a C++ compiler. Leave print_insn
 418          * unset in this case to use the caller default behaviour.
 419          */
 420 #if defined(CONFIG_ARM_A64_DIS)
 421         info->print_insn = print_insn_arm_a64;
 422 #endif
 423     } else if (env->thumb) {
 424         info->print_insn = print_insn_thumb1;
 425     } else {
 426         info->print_insn = print_insn_arm;
 427     }
 428     if (bswap_code(arm_sctlr_b(env))) {
 429 #ifdef TARGET_WORDS_BIGENDIAN
 430         info->endian = BFD_ENDIAN_LITTLE;
 431 #else
 432         info->endian = BFD_ENDIAN_BIG;
 433 #endif
 434     }
 435 }
 436
 437 static void arm_cpu_initfn(Object *obj)
 438 {
 439     CPUState *cs = CPU(obj);
 440     ARMCPU *cpu = ARM_CPU(obj);
 441     static bool inited;
 442
 443     cs->env_ptr = &cpu->env;
 444     cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
 445                                          g_free, g_free);
 446
 447 #ifndef CONFIG_USER_ONLY
 448     /* Our inbound IRQ and FIQ lines */
 449     if (kvm_enabled()) {
 450         /* VIRQ and VFIQ are unused with KVM but we add them to maintain
 451          * the same interface as non-KVM CPUs.
 452          */
 453         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4);
 454     } else {
 455         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4);
 456     }
 457
 458     cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 459                                                 arm_gt_ptimer_cb, cpu);
 460     cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 461                                                 arm_gt_vtimer_cb, cpu);
 462     cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 463                                                 arm_gt_htimer_cb, cpu);
 464     cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 465                                                 arm_gt_stimer_cb, cpu);
 466     qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
 467                        ARRAY_SIZE(cpu->gt_timer_outputs));
 468 #endif
 469
 470     /* DTB consumers generally don't in fact care what the 'compatible'
 471      * string is, so always provide some string and trust that a hypothetical
 472      * picky DTB consumer will also provide a helpful error message.
 473      */
 474     cpu->dtb_compatible = "qemu,unknown";
 475     cpu->psci_version = 1; /* By default assume PSCI v0.1 */
 476     cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
 477
 478     if (tcg_enabled()) {
 479         cpu->psci_version = 2; /* TCG implements PSCI 0.2 */
 480         if (!inited) {
 481             inited = true;
 482             arm_translate_init();
 483         }
 484     }
 485 }
 486
 487 static Property arm_cpu_reset_cbar_property =
 488             DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
 489
 490 static Property arm_cpu_reset_hivecs_property =
 491             DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
 492
 493 static Property arm_cpu_rvbar_property =
 494             DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0);
 495
 496 static Property arm_cpu_has_el3_property =
 497             DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true);
 498
 499 static Property arm_cpu_has_mpu_property =
 500             DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true);
 501
 502 static Property arm_cpu_pmsav7_dregion_property =
 503             DEFINE_PROP_UINT32("pmsav7-dregion", ARMCPU, pmsav7_dregion, 16);
 504
 505 static void arm_cpu_post_init(Object *obj)
 506 {
 507     ARMCPU *cpu = ARM_CPU(obj);
 508
 509     if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
 510         arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
 511         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property,
 512                                  &error_abort);
 513     }
 514
 515     if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
 516         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property,
 517                                  &error_abort);
 518     }
 519
 520     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
 521         qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property,
 522                                  &error_abort);
 523     }
 524
 525     if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
 526         /* Add the has_el3 state CPU property only if EL3 is allowed.  This will
 527          * prevent "has_el3" from existing on CPUs which cannot support EL3.
 528          */
 529         qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property,
 530                                  &error_abort);
 531
 532 #ifndef CONFIG_USER_ONLY
 533         object_property_add_link(obj, "secure-memory",
 534                                  TYPE_MEMORY_REGION,
 535                                  (Object **)&cpu->secure_memory,
 536                                  qdev_prop_allow_set_link_before_realize,
 537                                  OBJ_PROP_LINK_UNREF_ON_RELEASE,
 538                                  &error_abort);
 539 #endif
 540     }
 541
 542     if (arm_feature(&cpu->env, ARM_FEATURE_MPU)) {
 543         qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property,
 544                                  &error_abort);
 545         if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
 546             qdev_property_add_static(DEVICE(obj),
 547                                      &arm_cpu_pmsav7_dregion_property,
 548                                      &error_abort);
 549         }
 550     }
 551
 552 }
 553
 554 static void arm_cpu_finalizefn(Object *obj)
 555 {
 556     ARMCPU *cpu = ARM_CPU(obj);
 557     g_hash_table_destroy(cpu->cp_regs);
 558 }
 559
 560 static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
 561 {
 562     CPUState *cs = CPU(dev);
 563     ARMCPU *cpu = ARM_CPU(dev);
 564     ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
 565     CPUARMState *env = &cpu->env;
 566     int pagebits;
 567     Error *local_err = NULL;
 568
 569     cpu_exec_realizefn(cs, &local_err);
 570     if (local_err != NULL) {
 571         error_propagate(errp, local_err);
 572         return;
 573     }
 574
 575     /* Some features automatically imply others: */
 576     if (arm_feature(env, ARM_FEATURE_V8)) {
 577         set_feature(env, ARM_FEATURE_V7);
 578         set_feature(env, ARM_FEATURE_ARM_DIV);
 579         set_feature(env, ARM_FEATURE_LPAE);
 580     }
 581     if (arm_feature(env, ARM_FEATURE_V7)) {
 582         set_feature(env, ARM_FEATURE_VAPA);
 583         set_feature(env, ARM_FEATURE_THUMB2);
 584         set_feature(env, ARM_FEATURE_MPIDR);
 585         if (!arm_feature(env, ARM_FEATURE_M)) {
 586             set_feature(env, ARM_FEATURE_V6K);
 587         } else {
 588             set_feature(env, ARM_FEATURE_V6);
 589         }
 590     }
 591     if (arm_feature(env, ARM_FEATURE_V6K)) {
 592         set_feature(env, ARM_FEATURE_V6);
 593         set_feature(env, ARM_FEATURE_MVFR);
 594     }
 595     if (arm_feature(env, ARM_FEATURE_V6)) {
 596         set_feature(env, ARM_FEATURE_V5);
 597         if (!arm_feature(env, ARM_FEATURE_M)) {
 598             set_feature(env, ARM_FEATURE_AUXCR);
 599         }
 600     }
 601     if (arm_feature(env, ARM_FEATURE_V5)) {
 602         set_feature(env, ARM_FEATURE_V4T);
 603     }
 604     if (arm_feature(env, ARM_FEATURE_M)) {
 605         set_feature(env, ARM_FEATURE_THUMB_DIV);
 606     }
 607     if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
 608         set_feature(env, ARM_FEATURE_THUMB_DIV);
 609     }
 610     if (arm_feature(env, ARM_FEATURE_VFP4)) {
 611         set_feature(env, ARM_FEATURE_VFP3);
 612         set_feature(env, ARM_FEATURE_VFP_FP16);
 613     }
 614     if (arm_feature(env, ARM_FEATURE_VFP3)) {
 615         set_feature(env, ARM_FEATURE_VFP);
 616     }
 617     if (arm_feature(env, ARM_FEATURE_LPAE)) {
 618         set_feature(env, ARM_FEATURE_V7MP);
 619         set_feature(env, ARM_FEATURE_PXN);
 620     }
 621     if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
 622         set_feature(env, ARM_FEATURE_CBAR);
 623     }
 624     if (arm_feature(env, ARM_FEATURE_THUMB2) &&
 625         !arm_feature(env, ARM_FEATURE_M)) {
 626         set_feature(env, ARM_FEATURE_THUMB_DSP);
 627     }
 628
 629     if (arm_feature(env, ARM_FEATURE_V7) &&
 630         !arm_feature(env, ARM_FEATURE_M) &&
 631         !arm_feature(env, ARM_FEATURE_MPU)) {
 632         /* v7VMSA drops support for the old ARMv5 tiny pages, so we
 633          * can use 4K pages.
 634          */
 635         pagebits = 12;
 636     } else {
 637         /* For CPUs which might have tiny 1K pages, or which have an
 638          * MPU and might have small region sizes, stick with 1K pages.
 639          */
 640         pagebits = 10;
 641     }
 642     if (!set_preferred_target_page_bits(pagebits)) {
 643         /* This can only ever happen for hotplugging a CPU, or if
 644          * the board code incorrectly creates a CPU which it has
 645          * promised via minimum_page_size that it will not.
 646          */
 647         error_setg(errp, "This CPU requires a smaller page size than the "
 648                    "system is using");
 649         return;
 650     }
 651
 652     /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
 653      * We don't support setting cluster ID ([16..23]) (known as Aff2
 654      * in later ARM ARM versions), or any of the higher affinity level fields,
 655      * so these bits always RAZ.
 656      */
 657     if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) {
 658         uint32_t Aff1 = cs->cpu_index / ARM_DEFAULT_CPUS_PER_CLUSTER;
 659         uint32_t Aff0 = cs->cpu_index % ARM_DEFAULT_CPUS_PER_CLUSTER;
 660         cpu->mp_affinity = (Aff1 << ARM_AFF1_SHIFT) | Aff0;
 661     }
 662
 663     if (cpu->reset_hivecs) {
 664             cpu->reset_sctlr |= (1 << 13);
 665     }
 666
 667     if (!cpu->has_el3) {
 668         /* If the has_el3 CPU property is disabled then we need to disable the
 669          * feature.
 670          */
 671         unset_feature(env, ARM_FEATURE_EL3);
 672
 673         /* Disable the security extension feature bits in the processor feature
 674          * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
 675          */
 676         cpu->id_pfr1 &= ~0xf0;
 677         cpu->id_aa64pfr0 &= ~0xf000;
 678     }
 679
 680     if (!arm_feature(env, ARM_FEATURE_EL2)) {
 681         /* Disable the hypervisor feature bits in the processor feature
 682          * registers if we don't have EL2. These are id_pfr1[15:12] and
 683          * id_aa64pfr0_el1[11:8].
 684          */
 685         cpu->id_aa64pfr0 &= ~0xf00;
 686         cpu->id_pfr1 &= ~0xf000;
 687     }
 688
 689     if (!cpu->has_mpu) {
 690         unset_feature(env, ARM_FEATURE_MPU);
 691     }
 692
 693     if (arm_feature(env, ARM_FEATURE_MPU) &&
 694         arm_feature(env, ARM_FEATURE_V7)) {
 695         uint32_t nr = cpu->pmsav7_dregion;
 696
 697         if (nr > 0xff) {
 698             error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr);
 699             return;
 700         }
 701
 702         if (nr) {
 703             env->pmsav7.drbar = g_new0(uint32_t, nr);
 704             env->pmsav7.drsr = g_new0(uint32_t, nr);
 705             env->pmsav7.dracr = g_new0(uint32_t, nr);
 706         }
 707     }
 708
 709     register_cp_regs_for_features(cpu);
 710     arm_cpu_register_gdb_regs_for_features(cpu);
 711
 712     init_cpreg_list(cpu);
 713
 714 #ifndef CONFIG_USER_ONLY
 715     if (cpu->has_el3) {
 716         cs->num_ases = 2;
 717     } else {
 718         cs->num_ases = 1;
 719     }
 720
 721     if (cpu->has_el3) {
 722         AddressSpace *as;
 723
 724         if (!cpu->secure_memory) {
 725             cpu->secure_memory = cs->memory;
 726         }
 727         as = address_space_init_shareable(cpu->secure_memory,
 728                                           "cpu-secure-memory");
 729         cpu_address_space_init(cs, as, ARMASIdx_S);
 730     }
 731     cpu_address_space_init(cs,
 732                            address_space_init_shareable(cs->memory,
 733                                                         "cpu-memory"),
 734                            ARMASIdx_NS);
 735 #endif
 736
 737     qemu_init_vcpu(cs);
 738     cpu_reset(cs);
 739
 740     acc->parent_realize(dev, errp);
 741 }
 742
 743 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
 744 {
 745     ObjectClass *oc;
 746     char *typename;
 747     char **cpuname;
 748
 749     if (!cpu_model) {
 750         return NULL;
 751     }
 752
 753     cpuname = g_strsplit(cpu_model, ",", 1);
 754     typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpuname[0]);
 755     oc = object_class_by_name(typename);
 756     g_strfreev(cpuname);
 757     g_free(typename);
 758     if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
 759         object_class_is_abstract(oc)) {
 760         return NULL;
 761     }
 762     return oc;
 763 }
 764
 765 /* CPU models. These are not needed for the AArch64 linux-user build. */
 766 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 767
 768 static void arm926_initfn(Object *obj)
 769 {
 770     ARMCPU *cpu = ARM_CPU(obj);
 771
 772     cpu->dtb_compatible = "arm,arm926";
 773     set_feature(&cpu->env, ARM_FEATURE_V5);
 774     set_feature(&cpu->env, ARM_FEATURE_VFP);
 775     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 776     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 777     cpu->midr = 0x41069265;
 778     cpu->reset_fpsid = 0x41011090;
 779     cpu->ctr = 0x1dd20d2;
 780     cpu->reset_sctlr = 0x00090078;
 781 }
 782
 783 static void arm946_initfn(Object *obj)
 784 {
 785     ARMCPU *cpu = ARM_CPU(obj);
 786
 787     cpu->dtb_compatible = "arm,arm946";
 788     set_feature(&cpu->env, ARM_FEATURE_V5);
 789     set_feature(&cpu->env, ARM_FEATURE_MPU);
 790     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 791     cpu->midr = 0x41059461;
 792     cpu->ctr = 0x0f004006;
 793     cpu->reset_sctlr = 0x00000078;
 794 }
 795
 796 static void arm1026_initfn(Object *obj)
 797 {
 798     ARMCPU *cpu = ARM_CPU(obj);
 799
 800     cpu->dtb_compatible = "arm,arm1026";
 801     set_feature(&cpu->env, ARM_FEATURE_V5);
 802     set_feature(&cpu->env, ARM_FEATURE_VFP);
 803     set_feature(&cpu->env, ARM_FEATURE_AUXCR);
 804     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 805     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 806     cpu->midr = 0x4106a262;
 807     cpu->reset_fpsid = 0x410110a0;
 808     cpu->ctr = 0x1dd20d2;
 809     cpu->reset_sctlr = 0x00090078;
 810     cpu->reset_auxcr = 1;
 811     {
 812         /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
 813         ARMCPRegInfo ifar = {
 814             .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 815             .access = PL1_RW,
 816             .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
 817             .resetvalue = 0
 818         };
 819         define_one_arm_cp_reg(cpu, &ifar);
 820     }
 821 }
 822
 823 static void arm1136_r2_initfn(Object *obj)
 824 {
 825     ARMCPU *cpu = ARM_CPU(obj);
 826     /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
 827      * older core than plain "arm1136". In particular this does not
 828      * have the v6K features.
 829      * These ID register values are correct for 1136 but may be wrong
 830      * for 1136_r2 (in particular r0p2 does not actually implement most
 831      * of the ID registers).
 832      */
 833
 834     cpu->dtb_compatible = "arm,arm1136";
 835     set_feature(&cpu->env, ARM_FEATURE_V6);
 836     set_feature(&cpu->env, ARM_FEATURE_VFP);
 837     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 838     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 839     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 840     cpu->midr = 0x4107b362;
 841     cpu->reset_fpsid = 0x410120b4;
 842     cpu->mvfr0 = 0x11111111;
 843     cpu->mvfr1 = 0x00000000;
 844     cpu->ctr = 0x1dd20d2;
 845     cpu->reset_sctlr = 0x00050078;
 846     cpu->id_pfr0 = 0x111;
 847     cpu->id_pfr1 = 0x1;
 848     cpu->id_dfr0 = 0x2;
 849     cpu->id_afr0 = 0x3;
 850     cpu->id_mmfr0 = 0x01130003;
 851     cpu->id_mmfr1 = 0x10030302;
 852     cpu->id_mmfr2 = 0x01222110;
 853     cpu->id_isar0 = 0x00140011;
 854     cpu->id_isar1 = 0x12002111;
 855     cpu->id_isar2 = 0x11231111;
 856     cpu->id_isar3 = 0x01102131;
 857     cpu->id_isar4 = 0x141;
 858     cpu->reset_auxcr = 7;
 859 }
 860
 861 static void arm1136_initfn(Object *obj)
 862 {
 863     ARMCPU *cpu = ARM_CPU(obj);
 864
 865     cpu->dtb_compatible = "arm,arm1136";
 866     set_feature(&cpu->env, ARM_FEATURE_V6K);
 867     set_feature(&cpu->env, ARM_FEATURE_V6);
 868     set_feature(&cpu->env, ARM_FEATURE_VFP);
 869     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 870     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 871     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 872     cpu->midr = 0x4117b363;
 873     cpu->reset_fpsid = 0x410120b4;
 874     cpu->mvfr0 = 0x11111111;
 875     cpu->mvfr1 = 0x00000000;
 876     cpu->ctr = 0x1dd20d2;
 877     cpu->reset_sctlr = 0x00050078;
 878     cpu->id_pfr0 = 0x111;
 879     cpu->id_pfr1 = 0x1;
 880     cpu->id_dfr0 = 0x2;
 881     cpu->id_afr0 = 0x3;
 882     cpu->id_mmfr0 = 0x01130003;
 883     cpu->id_mmfr1 = 0x10030302;
 884     cpu->id_mmfr2 = 0x01222110;
 885     cpu->id_isar0 = 0x00140011;
 886     cpu->id_isar1 = 0x12002111;
 887     cpu->id_isar2 = 0x11231111;
 888     cpu->id_isar3 = 0x01102131;
 889     cpu->id_isar4 = 0x141;
 890     cpu->reset_auxcr = 7;
 891 }
 892
 893 static void arm1176_initfn(Object *obj)
 894 {
 895     ARMCPU *cpu = ARM_CPU(obj);
 896
 897     cpu->dtb_compatible = "arm,arm1176";
 898     set_feature(&cpu->env, ARM_FEATURE_V6K);
 899     set_feature(&cpu->env, ARM_FEATURE_VFP);
 900     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 901     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 902     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 903     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 904     set_feature(&cpu->env, ARM_FEATURE_EL3);
 905     cpu->midr = 0x410fb767;
 906     cpu->reset_fpsid = 0x410120b5;
 907     cpu->mvfr0 = 0x11111111;
 908     cpu->mvfr1 = 0x00000000;
 909     cpu->ctr = 0x1dd20d2;
 910     cpu->reset_sctlr = 0x00050078;
 911     cpu->id_pfr0 = 0x111;
 912     cpu->id_pfr1 = 0x11;
 913     cpu->id_dfr0 = 0x33;
 914     cpu->id_afr0 = 0;
 915     cpu->id_mmfr0 = 0x01130003;
 916     cpu->id_mmfr1 = 0x10030302;
 917     cpu->id_mmfr2 = 0x01222100;
 918     cpu->id_isar0 = 0x0140011;
 919     cpu->id_isar1 = 0x12002111;
 920     cpu->id_isar2 = 0x11231121;
 921     cpu->id_isar3 = 0x01102131;
 922     cpu->id_isar4 = 0x01141;
 923     cpu->reset_auxcr = 7;
 924 }
 925
 926 static void arm11mpcore_initfn(Object *obj)
 927 {
 928     ARMCPU *cpu = ARM_CPU(obj);
 929
 930     cpu->dtb_compatible = "arm,arm11mpcore";
 931     set_feature(&cpu->env, ARM_FEATURE_V6K);
 932     set_feature(&cpu->env, ARM_FEATURE_VFP);
 933     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 934     set_feature(&cpu->env, ARM_FEATURE_MPIDR);
 935     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 936     cpu->midr = 0x410fb022;
 937     cpu->reset_fpsid = 0x410120b4;
 938     cpu->mvfr0 = 0x11111111;
 939     cpu->mvfr1 = 0x00000000;
 940     cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
 941     cpu->id_pfr0 = 0x111;
 942     cpu->id_pfr1 = 0x1;
 943     cpu->id_dfr0 = 0;
 944     cpu->id_afr0 = 0x2;
 945     cpu->id_mmfr0 = 0x01100103;
 946     cpu->id_mmfr1 = 0x10020302;
 947     cpu->id_mmfr2 = 0x01222000;
 948     cpu->id_isar0 = 0x00100011;
 949     cpu->id_isar1 = 0x12002111;
 950     cpu->id_isar2 = 0x11221011;
 951     cpu->id_isar3 = 0x01102131;
 952     cpu->id_isar4 = 0x141;
 953     cpu->reset_auxcr = 1;
 954 }
 955
 956 static void cortex_m3_initfn(Object *obj)
 957 {
 958     ARMCPU *cpu = ARM_CPU(obj);
 959     set_feature(&cpu->env, ARM_FEATURE_V7);
 960     set_feature(&cpu->env, ARM_FEATURE_M);
 961     cpu->midr = 0x410fc231;
 962 }
 963
 964 static void cortex_m4_initfn(Object *obj)
 965 {
 966     ARMCPU *cpu = ARM_CPU(obj);
 967
 968     set_feature(&cpu->env, ARM_FEATURE_V7);
 969     set_feature(&cpu->env, ARM_FEATURE_M);
 970     set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
 971     cpu->midr = 0x410fc240; /* r0p0 */
 972 }
 973 static void arm_v7m_class_init(ObjectClass *oc, void *data)
 974 {
 975     CPUClass *cc = CPU_CLASS(oc);
 976
 977 #ifndef CONFIG_USER_ONLY
 978     cc->do_interrupt = arm_v7m_cpu_do_interrupt;
 979 #endif
 980
 981     cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
 982 }
 983
 984 static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
 985     /* Dummy the TCM region regs for the moment */
 986     { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
 987       .access = PL1_RW, .type = ARM_CP_CONST },
 988     { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
 989       .access = PL1_RW, .type = ARM_CP_CONST },
 990     REGINFO_SENTINEL
 991 };
 992
 993 static void cortex_r5_initfn(Object *obj)
 994 {
 995     ARMCPU *cpu = ARM_CPU(obj);
 996
 997     set_feature(&cpu->env, ARM_FEATURE_V7);
 998     set_feature(&cpu->env, ARM_FEATURE_THUMB_DIV);
 999     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
1000     set_feature(&cpu->env, ARM_FEATURE_V7MP);
1001     set_feature(&cpu->env, ARM_FEATURE_MPU);
1002     cpu->midr = 0x411fc153; /* r1p3 */
1003     cpu->id_pfr0 = 0x0131;
1004     cpu->id_pfr1 = 0x001;
1005     cpu->id_dfr0 = 0x010400;
1006     cpu->id_afr0 = 0x0;
1007     cpu->id_mmfr0 = 0x0210030;
1008     cpu->id_mmfr1 = 0x00000000;
1009     cpu->id_mmfr2 = 0x01200000;
1010     cpu->id_mmfr3 = 0x0211;
1011     cpu->id_isar0 = 0x2101111;
1012     cpu->id_isar1 = 0x13112111;
1013     cpu->id_isar2 = 0x21232141;
1014     cpu->id_isar3 = 0x01112131;
1015     cpu->id_isar4 = 0x0010142;
1016     cpu->id_isar5 = 0x0;
1017     cpu->mp_is_up = true;
1018     define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
1019 }
1020
1021 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
1022     { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
1023       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1024     { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
1025       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1026     REGINFO_SENTINEL
1027 };
1028
1029 static void cortex_a8_initfn(Object *obj)
1030 {
1031     ARMCPU *cpu = ARM_CPU(obj);
1032
1033     cpu->dtb_compatible = "arm,cortex-a8";
1034     set_feature(&cpu->env, ARM_FEATURE_V7);
1035     set_feature(&cpu->env, ARM_FEATURE_VFP3);
1036     set_feature(&cpu->env, ARM_FEATURE_NEON);
1037     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1038     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1039     set_feature(&cpu->env, ARM_FEATURE_EL3);
1040     cpu->midr = 0x410fc080;
1041     cpu->reset_fpsid = 0x410330c0;
1042     cpu->mvfr0 = 0x11110222;
1043     cpu->mvfr1 = 0x00011100;
1044     cpu->ctr = 0x82048004;
1045     cpu->reset_sctlr = 0x00c50078;
1046     cpu->id_pfr0 = 0x1031;
1047     cpu->id_pfr1 = 0x11;
1048     cpu->id_dfr0 = 0x400;
1049     cpu->id_afr0 = 0;
1050     cpu->id_mmfr0 = 0x31100003;
1051     cpu->id_mmfr1 = 0x20000000;
1052     cpu->id_mmfr2 = 0x01202000;
1053     cpu->id_mmfr3 = 0x11;
1054     cpu->id_isar0 = 0x00101111;
1055     cpu->id_isar1 = 0x12112111;
1056     cpu->id_isar2 = 0x21232031;
1057     cpu->id_isar3 = 0x11112131;
1058     cpu->id_isar4 = 0x00111142;
1059     cpu->dbgdidr = 0x15141000;
1060     cpu->clidr = (1 << 27) | (2 << 24) | 3;
1061     cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
1062     cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
1063     cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
1064     cpu->reset_auxcr = 2;
1065     define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
1066 }
1067
1068 static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
1069     /* power_control should be set to maximum latency. Again,
1070      * default to 0 and set by private hook
1071      */
1072     { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
1073       .access = PL1_RW, .resetvalue = 0,
1074       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
1075     { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
1076       .access = PL1_RW, .resetvalue = 0,
1077       .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
1078     { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
1079       .access = PL1_RW, .resetvalue = 0,
1080       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
1081     { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
1082       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1083     /* TLB lockdown control */
1084     { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
1085       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
1086     { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
1087       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
1088     { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
1089       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1090     { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
1091       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1092     { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
1093       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1094     REGINFO_SENTINEL
1095 };
1096
1097 static void cortex_a9_initfn(Object *obj)
1098 {
1099     ARMCPU *cpu = ARM_CPU(obj);
1100
1101     cpu->dtb_compatible = "arm,cortex-a9";
1102     set_feature(&cpu->env, ARM_FEATURE_V7);
1103     set_feature(&cpu->env, ARM_FEATURE_VFP3);
1104     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
1105     set_feature(&cpu->env, ARM_FEATURE_NEON);
1106     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1107     set_feature(&cpu->env, ARM_FEATURE_EL3);
1108     /* Note that A9 supports the MP extensions even for
1109      * A9UP and single-core A9MP (which are both different
1110      * and valid configurations; we don't model A9UP).
1111      */
1112     set_feature(&cpu->env, ARM_FEATURE_V7MP);
1113     set_feature(&cpu->env, ARM_FEATURE_CBAR);
1114     cpu->midr = 0x410fc090;
1115     cpu->reset_fpsid = 0x41033090;
1116     cpu->mvfr0 = 0x11110222;
1117     cpu->mvfr1 = 0x01111111;
1118     cpu->ctr = 0x80038003;
1119     cpu->reset_sctlr = 0x00c50078;
1120     cpu->id_pfr0 = 0x1031;
1121     cpu->id_pfr1 = 0x11;
1122     cpu->id_dfr0 = 0x000;
1123     cpu->id_afr0 = 0;
1124     cpu->id_mmfr0 = 0x00100103;
1125     cpu->id_mmfr1 = 0x20000000;
1126     cpu->id_mmfr2 = 0x01230000;
1127     cpu->id_mmfr3 = 0x00002111;
1128     cpu->id_isar0 = 0x00101111;
1129     cpu->id_isar1 = 0x13112111;
1130     cpu->id_isar2 = 0x21232041;
1131     cpu->id_isar3 = 0x11112131;
1132     cpu->id_isar4 = 0x00111142;
1133     cpu->dbgdidr = 0x35141000;
1134     cpu->clidr = (1 << 27) | (1 << 24) | 3;
1135     cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
1136     cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
1137     define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
1138 }
1139
1140 #ifndef CONFIG_USER_ONLY
1141 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1142 {
1143     /* Linux wants the number of processors from here.
1144      * Might as well set the interrupt-controller bit too.
1145      */
1146     return ((smp_cpus - 1) << 24) | (1 << 23);
1147 }
1148 #endif
1149
1150 static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
1151 #ifndef CONFIG_USER_ONLY
1152     { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
1153       .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
1154       .writefn = arm_cp_write_ignore, },
1155 #endif
1156     { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
1157       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1158     REGINFO_SENTINEL
1159 };
1160
1161 static void cortex_a7_initfn(Object *obj)
1162 {
1163     ARMCPU *cpu = ARM_CPU(obj);
1164
1165     cpu->dtb_compatible = "arm,cortex-a7";
1166     set_feature(&cpu->env, ARM_FEATURE_V7);
1167     set_feature(&cpu->env, ARM_FEATURE_VFP4);
1168     set_feature(&cpu->env, ARM_FEATURE_NEON);
1169     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1170     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
1171     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
1172     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1173     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
1174     set_feature(&cpu->env, ARM_FEATURE_LPAE);
1175     set_feature(&cpu->env, ARM_FEATURE_EL3);
1176     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7;
1177     cpu->midr = 0x410fc075;
1178     cpu->reset_fpsid = 0x41023075;
1179     cpu->mvfr0 = 0x10110222;
1180     cpu->mvfr1 = 0x11111111;
1181     cpu->ctr = 0x84448003;
1182     cpu->reset_sctlr = 0x00c50078;
1183     cpu->id_pfr0 = 0x00001131;
1184     cpu->id_pfr1 = 0x00011011;
1185     cpu->id_dfr0 = 0x02010555;
1186     cpu->pmceid0 = 0x00000000;
1187     cpu->pmceid1 = 0x00000000;
1188     cpu->id_afr0 = 0x00000000;
1189     cpu->id_mmfr0 = 0x10101105;
1190     cpu->id_mmfr1 = 0x40000000;
1191     cpu->id_mmfr2 = 0x01240000;
1192     cpu->id_mmfr3 = 0x02102211;
1193     cpu->id_isar0 = 0x01101110;
1194     cpu->id_isar1 = 0x13112111;
1195     cpu->id_isar2 = 0x21232041;
1196     cpu->id_isar3 = 0x11112131;
1197     cpu->id_isar4 = 0x10011142;
1198     cpu->dbgdidr = 0x3515f005;
1199     cpu->clidr = 0x0a200023;
1200     cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
1201     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
1202     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
1203     define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */
1204 }
1205
1206 static void cortex_a15_initfn(Object *obj)
1207 {
1208     ARMCPU *cpu = ARM_CPU(obj);
1209
1210     cpu->dtb_compatible = "arm,cortex-a15";
1211     set_feature(&cpu->env, ARM_FEATURE_V7);
1212     set_feature(&cpu->env, ARM_FEATURE_VFP4);
1213     set_feature(&cpu->env, ARM_FEATURE_NEON);
1214     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1215     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
1216     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
1217     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1218     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
1219     set_feature(&cpu->env, ARM_FEATURE_LPAE);
1220     set_feature(&cpu->env, ARM_FEATURE_EL3);
1221     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
1222     cpu->midr = 0x412fc0f1;
1223     cpu->reset_fpsid = 0x410430f0;
1224     cpu->mvfr0 = 0x10110222;
1225     cpu->mvfr1 = 0x11111111;
1226     cpu->ctr = 0x8444c004;
1227     cpu->reset_sctlr = 0x00c50078;
1228     cpu->id_pfr0 = 0x00001131;
1229     cpu->id_pfr1 = 0x00011011;
1230     cpu->id_dfr0 = 0x02010555;
1231     cpu->pmceid0 = 0x0000000;
1232     cpu->pmceid1 = 0x00000000;
1233     cpu->id_afr0 = 0x00000000;
1234     cpu->id_mmfr0 = 0x10201105;
1235     cpu->id_mmfr1 = 0x20000000;
1236     cpu->id_mmfr2 = 0x01240000;
1237     cpu->id_mmfr3 = 0x02102211;
1238     cpu->id_isar0 = 0x02101110;
1239     cpu->id_isar1 = 0x13112111;
1240     cpu->id_isar2 = 0x21232041;
1241     cpu->id_isar3 = 0x11112131;
1242     cpu->id_isar4 = 0x10011142;
1243     cpu->dbgdidr = 0x3515f021;
1244     cpu->clidr = 0x0a200023;
1245     cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
1246     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
1247     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
1248     define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
1249 }
1250
1251 static void ti925t_initfn(Object *obj)
1252 {
1253     ARMCPU *cpu = ARM_CPU(obj);
1254     set_feature(&cpu->env, ARM_FEATURE_V4T);
1255     set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
1256     cpu->midr = ARM_CPUID_TI925T;
1257     cpu->ctr = 0x5109149;
1258     cpu->reset_sctlr = 0x00000070;
1259 }
1260
1261 static void sa1100_initfn(Object *obj)
1262 {
1263     ARMCPU *cpu = ARM_CPU(obj);
1264
1265     cpu->dtb_compatible = "intel,sa1100";
1266     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
1267     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1268     cpu->midr = 0x4401A11B;
1269     cpu->reset_sctlr = 0x00000070;
1270 }
1271
1272 static void sa1110_initfn(Object *obj)
1273 {
1274     ARMCPU *cpu = ARM_CPU(obj);
1275     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
1276     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1277     cpu->midr = 0x6901B119;
1278     cpu->reset_sctlr = 0x00000070;
1279 }
1280
1281 static void pxa250_initfn(Object *obj)
1282 {
1283     ARMCPU *cpu = ARM_CPU(obj);
1284
1285     cpu->dtb_compatible = "marvell,xscale";
1286     set_feature(&cpu->env, ARM_FEATURE_V5);
1287     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1288     cpu->midr = 0x69052100;
1289     cpu->ctr = 0xd172172;
1290     cpu->reset_sctlr = 0x00000078;
1291 }
1292
1293 static void pxa255_initfn(Object *obj)
1294 {
1295     ARMCPU *cpu = ARM_CPU(obj);
1296
1297     cpu->dtb_compatible = "marvell,xscale";
1298     set_feature(&cpu->env, ARM_FEATURE_V5);
1299     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1300     cpu->midr = 0x69052d00;
1301     cpu->ctr = 0xd172172;
1302     cpu->reset_sctlr = 0x00000078;
1303 }
1304
1305 static void pxa260_initfn(Object *obj)
1306 {
1307     ARMCPU *cpu = ARM_CPU(obj);
1308
1309     cpu->dtb_compatible = "marvell,xscale";
1310     set_feature(&cpu->env, ARM_FEATURE_V5);
1311     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1312     cpu->midr = 0x69052903;
1313     cpu->ctr = 0xd172172;
1314     cpu->reset_sctlr = 0x00000078;
1315 }
1316
1317 static void pxa261_initfn(Object *obj)
1318 {
1319     ARMCPU *cpu = ARM_CPU(obj);
1320
1321     cpu->dtb_compatible = "marvell,xscale";
1322     set_feature(&cpu->env, ARM_FEATURE_V5);
1323     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1324     cpu->midr = 0x69052d05;
1325     cpu->ctr = 0xd172172;
1326     cpu->reset_sctlr = 0x00000078;
1327 }
1328
1329 static void pxa262_initfn(Object *obj)
1330 {
1331     ARMCPU *cpu = ARM_CPU(obj);
1332
1333     cpu->dtb_compatible = "marvell,xscale";
1334     set_feature(&cpu->env, ARM_FEATURE_V5);
1335     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1336     cpu->midr = 0x69052d06;
1337     cpu->ctr = 0xd172172;
1338     cpu->reset_sctlr = 0x00000078;
1339 }
1340
1341 static void pxa270a0_initfn(Object *obj)
1342 {
1343     ARMCPU *cpu = ARM_CPU(obj);
1344
1345     cpu->dtb_compatible = "marvell,xscale";
1346     set_feature(&cpu->env, ARM_FEATURE_V5);
1347     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1348     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1349     cpu->midr = 0x69054110;
1350     cpu->ctr = 0xd172172;
1351     cpu->reset_sctlr = 0x00000078;
1352 }
1353
1354 static void pxa270a1_initfn(Object *obj)
1355 {
1356     ARMCPU *cpu = ARM_CPU(obj);
1357
1358     cpu->dtb_compatible = "marvell,xscale";
1359     set_feature(&cpu->env, ARM_FEATURE_V5);
1360     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1361     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1362     cpu->midr = 0x69054111;
1363     cpu->ctr = 0xd172172;
1364     cpu->reset_sctlr = 0x00000078;
1365 }
1366
1367 static void pxa270b0_initfn(Object *obj)
1368 {
1369     ARMCPU *cpu = ARM_CPU(obj);
1370
1371     cpu->dtb_compatible = "marvell,xscale";
1372     set_feature(&cpu->env, ARM_FEATURE_V5);
1373     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1374     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1375     cpu->midr = 0x69054112;
1376     cpu->ctr = 0xd172172;
1377     cpu->reset_sctlr = 0x00000078;
1378 }
1379
1380 static void pxa270b1_initfn(Object *obj)
1381 {
1382     ARMCPU *cpu = ARM_CPU(obj);
1383
1384     cpu->dtb_compatible = "marvell,xscale";
1385     set_feature(&cpu->env, ARM_FEATURE_V5);
1386     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1387     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1388     cpu->midr = 0x69054113;
1389     cpu->ctr = 0xd172172;
1390     cpu->reset_sctlr = 0x00000078;
1391 }
1392
1393 static void pxa270c0_initfn(Object *obj)
1394 {
1395     ARMCPU *cpu = ARM_CPU(obj);
1396
1397     cpu->dtb_compatible = "marvell,xscale";
1398     set_feature(&cpu->env, ARM_FEATURE_V5);
1399     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1400     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1401     cpu->midr = 0x69054114;
1402     cpu->ctr = 0xd172172;
1403     cpu->reset_sctlr = 0x00000078;
1404 }
1405
1406 static void pxa270c5_initfn(Object *obj)
1407 {
1408     ARMCPU *cpu = ARM_CPU(obj);
1409
1410     cpu->dtb_compatible = "marvell,xscale";
1411     set_feature(&cpu->env, ARM_FEATURE_V5);
1412     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1413     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1414     cpu->midr = 0x69054117;
1415     cpu->ctr = 0xd172172;
1416     cpu->reset_sctlr = 0x00000078;
1417 }
1418
1419 #ifdef CONFIG_USER_ONLY
1420 static void arm_any_initfn(Object *obj)
1421 {
1422     ARMCPU *cpu = ARM_CPU(obj);
1423     set_feature(&cpu->env, ARM_FEATURE_V8);
1424     set_feature(&cpu->env, ARM_FEATURE_VFP4);
1425     set_feature(&cpu->env, ARM_FEATURE_NEON);
1426     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1427     set_feature(&cpu->env, ARM_FEATURE_V8_AES);
1428     set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
1429     set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
1430     set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
1431     set_feature(&cpu->env, ARM_FEATURE_CRC);
1432     cpu->midr = 0xffffffff;
1433 }
1434 #endif
1435
1436 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
1437
1438 typedef struct ARMCPUInfo {
1439     const char *name;
1440     void (*initfn)(Object *obj);
1441     void (*class_init)(ObjectClass *oc, void *data);
1442 } ARMCPUInfo;
1443
1444 static const ARMCPUInfo arm_cpus[] = {
1445 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1446     { .name = "arm926",      .initfn = arm926_initfn },
1447     { .name = "arm946",      .initfn = arm946_initfn },
1448     { .name = "arm1026",     .initfn = arm1026_initfn },
1449     /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
1450      * older core than plain "arm1136". In particular this does not
1451      * have the v6K features.
1452      */
1453     { .name = "arm1136-r2",  .initfn = arm1136_r2_initfn },
1454     { .name = "arm1136",     .initfn = arm1136_initfn },
1455     { .name = "arm1176",     .initfn = arm1176_initfn },
1456     { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
1457     { .name = "cortex-m3",   .initfn = cortex_m3_initfn,
1458                              .class_init = arm_v7m_class_init },
1459     { .name = "cortex-m4",   .initfn = cortex_m4_initfn,
1460                              .class_init = arm_v7m_class_init },
1461     { .name = "cortex-r5",   .initfn = cortex_r5_initfn },
1462     { .name = "cortex-a7",   .initfn = cortex_a7_initfn },
1463     { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
1464     { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
1465     { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
1466     { .name = "ti925t",      .initfn = ti925t_initfn },
1467     { .name = "sa1100",      .initfn = sa1100_initfn },
1468     { .name = "sa1110",      .initfn = sa1110_initfn },
1469     { .name = "pxa250",      .initfn = pxa250_initfn },
1470     { .name = "pxa255",      .initfn = pxa255_initfn },
1471     { .name = "pxa260",      .initfn = pxa260_initfn },
1472     { .name = "pxa261",      .initfn = pxa261_initfn },
1473     { .name = "pxa262",      .initfn = pxa262_initfn },
1474     /* "pxa270" is an alias for "pxa270-a0" */
1475     { .name = "pxa270",      .initfn = pxa270a0_initfn },
1476     { .name = "pxa270-a0",   .initfn = pxa270a0_initfn },
1477     { .name = "pxa270-a1",   .initfn = pxa270a1_initfn },
1478     { .name = "pxa270-b0",   .initfn = pxa270b0_initfn },
1479     { .name = "pxa270-b1",   .initfn = pxa270b1_initfn },
1480     { .name = "pxa270-c0",   .initfn = pxa270c0_initfn },
1481     { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
1482 #ifdef CONFIG_USER_ONLY
1483     { .name = "any",         .initfn = arm_any_initfn },
1484 #endif
1485 #endif
1486     { .name = NULL }
1487 };
1488
1489 static Property arm_cpu_properties[] = {
1490     DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),
1491     DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0),
1492     DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0),
1493     DEFINE_PROP_UINT64("mp-affinity", ARMCPU,
1494                         mp_affinity, ARM64_AFFINITY_INVALID),
1495     DEFINE_PROP_END_OF_LIST()
1496 };
1497
1498 #ifdef CONFIG_USER_ONLY
1499 static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
1500                                     int mmu_idx)
1501 {
1502     ARMCPU *cpu = ARM_CPU(cs);
1503     CPUARMState *env = &cpu->env;
1504
1505     env->exception.vaddress = address;
1506     if (rw == 2) {
1507         cs->exception_index = EXCP_PREFETCH_ABORT;
1508     } else {
1509         cs->exception_index = EXCP_DATA_ABORT;
1510     }
1511     return 1;
1512 }
1513 #endif
1514
1515 static gchar *arm_gdb_arch_name(CPUState *cs)
1516 {
1517     ARMCPU *cpu = ARM_CPU(cs);
1518     CPUARMState *env = &cpu->env;
1519
1520     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
1521         return g_strdup("iwmmxt");
1522     }
1523     return g_strdup("arm");
1524 }
1525
1526 static void arm_cpu_class_init(ObjectClass *oc, void *data)
1527 {
1528     ARMCPUClass *acc = ARM_CPU_CLASS(oc);
1529     CPUClass *cc = CPU_CLASS(acc);
1530     DeviceClass *dc = DEVICE_CLASS(oc);
1531
1532     acc->parent_realize = dc->realize;
1533     dc->realize = arm_cpu_realizefn;
1534     dc->props = arm_cpu_properties;
1535
1536     acc->parent_reset = cc->reset;
1537     cc->reset = arm_cpu_reset;
1538
1539     cc->class_by_name = arm_cpu_class_by_name;
1540     cc->has_work = arm_cpu_has_work;
1541     cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
1542     cc->dump_state = arm_cpu_dump_state;
1543     cc->set_pc = arm_cpu_set_pc;
1544     cc->gdb_read_register = arm_cpu_gdb_read_register;
1545     cc->gdb_write_register = arm_cpu_gdb_write_register;
1546 #ifdef CONFIG_USER_ONLY
1547     cc->handle_mmu_fault = arm_cpu_handle_mmu_fault;
1548 #else
1549     cc->do_interrupt = arm_cpu_do_interrupt;
1550     cc->do_unaligned_access = arm_cpu_do_unaligned_access;
1551     cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
1552     cc->asidx_from_attrs = arm_asidx_from_attrs;
1553     cc->vmsd = &vmstate_arm_cpu;
1554     cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian;
1555     cc->write_elf64_note = arm_cpu_write_elf64_note;
1556     cc->write_elf32_note = arm_cpu_write_elf32_note;
1557 #endif
1558     cc->gdb_num_core_regs = 26;
1559     cc->gdb_core_xml_file = "arm-core.xml";
1560     cc->gdb_arch_name = arm_gdb_arch_name;
1561     cc->gdb_stop_before_watchpoint = true;
1562     cc->debug_excp_handler = arm_debug_excp_handler;
1563     cc->debug_check_watchpoint = arm_debug_check_watchpoint;
1564
1565     cc->disas_set_info = arm_disas_set_info;
1566 }
1567
1568 static void cpu_register(const ARMCPUInfo *info)
1569 {
1570     TypeInfo type_info = {
1571         .parent = TYPE_ARM_CPU,
1572         .instance_size = sizeof(ARMCPU),
1573         .instance_init = info->initfn,
1574         .class_size = sizeof(ARMCPUClass),
1575         .class_init = info->class_init,
1576     };
1577
1578     type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
1579     type_register(&type_info);
1580     g_free((void *)type_info.name);
1581 }
1582
1583 static const TypeInfo arm_cpu_type_info = {
1584     .name = TYPE_ARM_CPU,
1585     .parent = TYPE_CPU,
1586     .instance_size = sizeof(ARMCPU),
1587     .instance_init = arm_cpu_initfn,
1588     .instance_post_init = arm_cpu_post_init,
1589     .instance_finalize = arm_cpu_finalizefn,
1590     .abstract = true,
1591     .class_size = sizeof(ARMCPUClass),
1592     .class_init = arm_cpu_class_init,
1593 };
1594
1595 static void arm_cpu_register_types(void)
1596 {
1597     const ARMCPUInfo *info = arm_cpus;
1598
1599     type_register_static(&arm_cpu_type_info);
1600
1601     while (info->name) {
1602         cpu_register(info);
1603         info++;
1604     }
1605 }
1606
1607 type_init(arm_cpu_register_types)