hw/musicpal.c

   1 /*
   2  * Marvell MV88W8618 / Freecom MusicPal emulation.
   3  *
   4  * Copyright (c) 2008 Jan Kiszka
   5  *
   6  * This code is licenced under the GNU GPL v2.
   7  */
   8
   9 #include "sysbus.h"
  10 #include "arm-misc.h"
  11 #include "devices.h"
  12 #include "net.h"
  13 #include "sysemu.h"
  14 #include "boards.h"
  15 #include "pc.h"
  16 #include "qemu-timer.h"
  17 #include "block.h"
  18 #include "flash.h"
  19 #include "console.h"
  20 #include "i2c.h"
  21
  22 #define MP_MISC_BASE            0x80002000
  23 #define MP_MISC_SIZE            0x00001000
  24
  25 #define MP_ETH_BASE             0x80008000
  26 #define MP_ETH_SIZE             0x00001000
  27
  28 #define MP_WLAN_BASE            0x8000C000
  29 #define MP_WLAN_SIZE            0x00000800
  30
  31 #define MP_UART1_BASE           0x8000C840
  32 #define MP_UART2_BASE           0x8000C940
  33
  34 #define MP_GPIO_BASE            0x8000D000
  35 #define MP_GPIO_SIZE            0x00001000
  36
  37 #define MP_FLASHCFG_BASE        0x90006000
  38 #define MP_FLASHCFG_SIZE        0x00001000
  39
  40 #define MP_AUDIO_BASE           0x90007000
  41
  42 #define MP_PIC_BASE             0x90008000
  43 #define MP_PIC_SIZE             0x00001000
  44
  45 #define MP_PIT_BASE             0x90009000
  46 #define MP_PIT_SIZE             0x00001000
  47
  48 #define MP_LCD_BASE             0x9000c000
  49 #define MP_LCD_SIZE             0x00001000
  50
  51 #define MP_SRAM_BASE            0xC0000000
  52 #define MP_SRAM_SIZE            0x00020000
  53
  54 #define MP_RAM_DEFAULT_SIZE     32*1024*1024
  55 #define MP_FLASH_SIZE_MAX       32*1024*1024
  56
  57 #define MP_TIMER1_IRQ           4
  58 #define MP_TIMER2_IRQ           5
  59 #define MP_TIMER3_IRQ           6
  60 #define MP_TIMER4_IRQ           7
  61 #define MP_EHCI_IRQ             8
  62 #define MP_ETH_IRQ              9
  63 #define MP_UART1_IRQ            11
  64 #define MP_UART2_IRQ            11
  65 #define MP_GPIO_IRQ             12
  66 #define MP_RTC_IRQ              28
  67 #define MP_AUDIO_IRQ            30
  68
  69 /* Wolfson 8750 I2C address */
  70 #define MP_WM_ADDR              0x34
  71
  72 /* Ethernet register offsets */
  73 #define MP_ETH_SMIR             0x010
  74 #define MP_ETH_PCXR             0x408
  75 #define MP_ETH_SDCMR            0x448
  76 #define MP_ETH_ICR              0x450
  77 #define MP_ETH_IMR              0x458
  78 #define MP_ETH_FRDP0            0x480
  79 #define MP_ETH_FRDP1            0x484
  80 #define MP_ETH_FRDP2            0x488
  81 #define MP_ETH_FRDP3            0x48C
  82 #define MP_ETH_CRDP0            0x4A0
  83 #define MP_ETH_CRDP1            0x4A4
  84 #define MP_ETH_CRDP2            0x4A8
  85 #define MP_ETH_CRDP3            0x4AC
  86 #define MP_ETH_CTDP0            0x4E0
  87 #define MP_ETH_CTDP1            0x4E4
  88 #define MP_ETH_CTDP2            0x4E8
  89 #define MP_ETH_CTDP3            0x4EC
  90
  91 /* MII PHY access */
  92 #define MP_ETH_SMIR_DATA        0x0000FFFF
  93 #define MP_ETH_SMIR_ADDR        0x03FF0000
  94 #define MP_ETH_SMIR_OPCODE      (1 << 26) /* Read value */
  95 #define MP_ETH_SMIR_RDVALID     (1 << 27)
  96
  97 /* PHY registers */
  98 #define MP_ETH_PHY1_BMSR        0x00210000
  99 #define MP_ETH_PHY1_PHYSID1     0x00410000
 100 #define MP_ETH_PHY1_PHYSID2     0x00610000
 101
 102 #define MP_PHY_BMSR_LINK        0x0004
 103 #define MP_PHY_BMSR_AUTONEG     0x0008
 104
 105 #define MP_PHY_88E3015          0x01410E20
 106
 107 /* TX descriptor status */
 108 #define MP_ETH_TX_OWN           (1 << 31)
 109
 110 /* RX descriptor status */
 111 #define MP_ETH_RX_OWN           (1 << 31)
 112
 113 /* Interrupt cause/mask bits */
 114 #define MP_ETH_IRQ_RX_BIT       0
 115 #define MP_ETH_IRQ_RX           (1 << MP_ETH_IRQ_RX_BIT)
 116 #define MP_ETH_IRQ_TXHI_BIT     2
 117 #define MP_ETH_IRQ_TXLO_BIT     3
 118
 119 /* Port config bits */
 120 #define MP_ETH_PCXR_2BSM_BIT    28 /* 2-byte incoming suffix */
 121
 122 /* SDMA command bits */
 123 #define MP_ETH_CMD_TXHI         (1 << 23)
 124 #define MP_ETH_CMD_TXLO         (1 << 22)
 125
 126 typedef struct mv88w8618_tx_desc {
 127     uint32_t cmdstat;
 128     uint16_t res;
 129     uint16_t bytes;
 130     uint32_t buffer;
 131     uint32_t next;
 132 } mv88w8618_tx_desc;
 133
 134 typedef struct mv88w8618_rx_desc {
 135     uint32_t cmdstat;
 136     uint16_t bytes;
 137     uint16_t buffer_size;
 138     uint32_t buffer;
 139     uint32_t next;
 140 } mv88w8618_rx_desc;
 141
 142 typedef struct mv88w8618_eth_state {
 143     SysBusDevice busdev;
 144     qemu_irq irq;
 145     uint32_t smir;
 146     uint32_t icr;
 147     uint32_t imr;
 148     int mmio_index;
 149     int vlan_header;
 150     uint32_t tx_queue[2];
 151     uint32_t rx_queue[4];
 152     uint32_t frx_queue[4];
 153     uint32_t cur_rx[4];
 154     VLANClientState *vc;
 155 } mv88w8618_eth_state;
 156
 157 static void eth_rx_desc_put(uint32_t addr, mv88w8618_rx_desc *desc)
 158 {
 159     cpu_to_le32s(&desc->cmdstat);
 160     cpu_to_le16s(&desc->bytes);
 161     cpu_to_le16s(&desc->buffer_size);
 162     cpu_to_le32s(&desc->buffer);
 163     cpu_to_le32s(&desc->next);
 164     cpu_physical_memory_write(addr, (void *)desc, sizeof(*desc));
 165 }
 166
 167 static void eth_rx_desc_get(uint32_t addr, mv88w8618_rx_desc *desc)
 168 {
 169     cpu_physical_memory_read(addr, (void *)desc, sizeof(*desc));
 170     le32_to_cpus(&desc->cmdstat);
 171     le16_to_cpus(&desc->bytes);
 172     le16_to_cpus(&desc->buffer_size);
 173     le32_to_cpus(&desc->buffer);
 174     le32_to_cpus(&desc->next);
 175 }
 176
 177 static int eth_can_receive(VLANClientState *vc)
 178 {
 179     return 1;
 180 }
 181
 182 static ssize_t eth_receive(VLANClientState *vc, const uint8_t *buf, size_t size)
 183 {
 184     mv88w8618_eth_state *s = vc->opaque;
 185     uint32_t desc_addr;
 186     mv88w8618_rx_desc desc;
 187     int i;
 188
 189     for (i = 0; i < 4; i++) {
 190         desc_addr = s->cur_rx[i];
 191         if (!desc_addr)
 192             continue;
 193         do {
 194             eth_rx_desc_get(desc_addr, &desc);
 195             if ((desc.cmdstat & MP_ETH_RX_OWN) && desc.buffer_size >= size) {
 196                 cpu_physical_memory_write(desc.buffer + s->vlan_header,
 197                                           buf, size);
 198                 desc.bytes = size + s->vlan_header;
 199                 desc.cmdstat &= ~MP_ETH_RX_OWN;
 200                 s->cur_rx[i] = desc.next;
 201
 202                 s->icr |= MP_ETH_IRQ_RX;
 203                 if (s->icr & s->imr)
 204                     qemu_irq_raise(s->irq);
 205                 eth_rx_desc_put(desc_addr, &desc);
 206                 return size;
 207             }
 208             desc_addr = desc.next;
 209         } while (desc_addr != s->rx_queue[i]);
 210     }
 211     return size;
 212 }
 213
 214 static void eth_tx_desc_put(uint32_t addr, mv88w8618_tx_desc *desc)
 215 {
 216     cpu_to_le32s(&desc->cmdstat);
 217     cpu_to_le16s(&desc->res);
 218     cpu_to_le16s(&desc->bytes);
 219     cpu_to_le32s(&desc->buffer);
 220     cpu_to_le32s(&desc->next);
 221     cpu_physical_memory_write(addr, (void *)desc, sizeof(*desc));
 222 }
 223
 224 static void eth_tx_desc_get(uint32_t addr, mv88w8618_tx_desc *desc)
 225 {
 226     cpu_physical_memory_read(addr, (void *)desc, sizeof(*desc));
 227     le32_to_cpus(&desc->cmdstat);
 228     le16_to_cpus(&desc->res);
 229     le16_to_cpus(&desc->bytes);
 230     le32_to_cpus(&desc->buffer);
 231     le32_to_cpus(&desc->next);
 232 }
 233
 234 static void eth_send(mv88w8618_eth_state *s, int queue_index)
 235 {
 236     uint32_t desc_addr = s->tx_queue[queue_index];
 237     mv88w8618_tx_desc desc;
 238     uint8_t buf[2048];
 239     int len;
 240
 241
 242     do {
 243         eth_tx_desc_get(desc_addr, &desc);
 244         if (desc.cmdstat & MP_ETH_TX_OWN) {
 245             len = desc.bytes;
 246             if (len < 2048) {
 247                 cpu_physical_memory_read(desc.buffer, buf, len);
 248                 qemu_send_packet(s->vc, buf, len);
 249             }
 250             desc.cmdstat &= ~MP_ETH_TX_OWN;
 251             s->icr |= 1 << (MP_ETH_IRQ_TXLO_BIT - queue_index);
 252             eth_tx_desc_put(desc_addr, &desc);
 253         }
 254         desc_addr = desc.next;
 255     } while (desc_addr != s->tx_queue[queue_index]);
 256 }
 257
 258 static uint32_t mv88w8618_eth_read(void *opaque, target_phys_addr_t offset)
 259 {
 260     mv88w8618_eth_state *s = opaque;
 261
 262     switch (offset) {
 263     case MP_ETH_SMIR:
 264         if (s->smir & MP_ETH_SMIR_OPCODE) {
 265             switch (s->smir & MP_ETH_SMIR_ADDR) {
 266             case MP_ETH_PHY1_BMSR:
 267                 return MP_PHY_BMSR_LINK | MP_PHY_BMSR_AUTONEG |
 268                        MP_ETH_SMIR_RDVALID;
 269             case MP_ETH_PHY1_PHYSID1:
 270                 return (MP_PHY_88E3015 >> 16) | MP_ETH_SMIR_RDVALID;
 271             case MP_ETH_PHY1_PHYSID2:
 272                 return (MP_PHY_88E3015 & 0xFFFF) | MP_ETH_SMIR_RDVALID;
 273             default:
 274                 return MP_ETH_SMIR_RDVALID;
 275             }
 276         }
 277         return 0;
 278
 279     case MP_ETH_ICR:
 280         return s->icr;
 281
 282     case MP_ETH_IMR:
 283         return s->imr;
 284
 285     case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
 286         return s->frx_queue[(offset - MP_ETH_FRDP0)/4];
 287
 288     case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
 289         return s->rx_queue[(offset - MP_ETH_CRDP0)/4];
 290
 291     case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
 292         return s->tx_queue[(offset - MP_ETH_CTDP0)/4];
 293
 294     default:
 295         return 0;
 296     }
 297 }
 298
 299 static void mv88w8618_eth_write(void *opaque, target_phys_addr_t offset,
 300                                 uint32_t value)
 301 {
 302     mv88w8618_eth_state *s = opaque;
 303
 304     switch (offset) {
 305     case MP_ETH_SMIR:
 306         s->smir = value;
 307         break;
 308
 309     case MP_ETH_PCXR:
 310         s->vlan_header = ((value >> MP_ETH_PCXR_2BSM_BIT) & 1) * 2;
 311         break;
 312
 313     case MP_ETH_SDCMR:
 314         if (value & MP_ETH_CMD_TXHI)
 315             eth_send(s, 1);
 316         if (value & MP_ETH_CMD_TXLO)
 317             eth_send(s, 0);
 318         if (value & (MP_ETH_CMD_TXHI | MP_ETH_CMD_TXLO) && s->icr & s->imr)
 319             qemu_irq_raise(s->irq);
 320         break;
 321
 322     case MP_ETH_ICR:
 323         s->icr &= value;
 324         break;
 325
 326     case MP_ETH_IMR:
 327         s->imr = value;
 328         if (s->icr & s->imr)
 329             qemu_irq_raise(s->irq);
 330         break;
 331
 332     case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
 333         s->frx_queue[(offset - MP_ETH_FRDP0)/4] = value;
 334         break;
 335
 336     case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
 337         s->rx_queue[(offset - MP_ETH_CRDP0)/4] =
 338             s->cur_rx[(offset - MP_ETH_CRDP0)/4] = value;
 339         break;
 340
 341     case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
 342         s->tx_queue[(offset - MP_ETH_CTDP0)/4] = value;
 343         break;
 344     }
 345 }
 346
 347 static CPUReadMemoryFunc * const mv88w8618_eth_readfn[] = {
 348     mv88w8618_eth_read,
 349     mv88w8618_eth_read,
 350     mv88w8618_eth_read
 351 };
 352
 353 static CPUWriteMemoryFunc * const mv88w8618_eth_writefn[] = {
 354     mv88w8618_eth_write,
 355     mv88w8618_eth_write,
 356     mv88w8618_eth_write
 357 };
 358
 359 static void eth_cleanup(VLANClientState *vc)
 360 {
 361     mv88w8618_eth_state *s = vc->opaque;
 362
 363     cpu_unregister_io_memory(s->mmio_index);
 364
 365     qemu_free(s);
 366 }
 367
 368 static void mv88w8618_eth_init(SysBusDevice *dev)
 369 {
 370     mv88w8618_eth_state *s = FROM_SYSBUS(mv88w8618_eth_state, dev);
 371
 372     sysbus_init_irq(dev, &s->irq);
 373     s->vc = qdev_get_vlan_client(&dev->qdev,
 374                                  eth_can_receive, eth_receive, NULL,
 375                                  eth_cleanup, s);
 376     s->mmio_index = cpu_register_io_memory(mv88w8618_eth_readfn,
 377                                            mv88w8618_eth_writefn, s);
 378     sysbus_init_mmio(dev, MP_ETH_SIZE, s->mmio_index);
 379 }
 380
 381 /* LCD register offsets */
 382 #define MP_LCD_IRQCTRL          0x180
 383 #define MP_LCD_IRQSTAT          0x184
 384 #define MP_LCD_SPICTRL          0x1ac
 385 #define MP_LCD_INST             0x1bc
 386 #define MP_LCD_DATA             0x1c0
 387
 388 /* Mode magics */
 389 #define MP_LCD_SPI_DATA         0x00100011
 390 #define MP_LCD_SPI_CMD          0x00104011
 391 #define MP_LCD_SPI_INVALID      0x00000000
 392
 393 /* Commmands */
 394 #define MP_LCD_INST_SETPAGE0    0xB0
 395 /* ... */
 396 #define MP_LCD_INST_SETPAGE7    0xB7
 397
 398 #define MP_LCD_TEXTCOLOR        0xe0e0ff /* RRGGBB */
 399
 400 typedef struct musicpal_lcd_state {
 401     SysBusDevice busdev;
 402     uint32_t brightness;
 403     uint32_t mode;
 404     uint32_t irqctrl;
 405     int page;
 406     int page_off;
 407     DisplayState *ds;
 408     uint8_t video_ram[128*64/8];
 409 } musicpal_lcd_state;
 410
 411 static uint8_t scale_lcd_color(musicpal_lcd_state *s, uint8_t col)
 412 {
 413     switch (s->brightness) {
 414     case 7:
 415         return col;
 416     case 0:
 417         return 0;
 418     default:
 419         return (col * s->brightness) / 7;
 420     }
 421 }
 422
 423 #define SET_LCD_PIXEL(depth, type) \
 424 static inline void glue(set_lcd_pixel, depth) \
 425         (musicpal_lcd_state *s, int x, int y, type col) \
 426 { \
 427     int dx, dy; \
 428     type *pixel = &((type *) ds_get_data(s->ds))[(y * 128 * 3 + x) * 3]; \
 429 \
 430     for (dy = 0; dy < 3; dy++, pixel += 127 * 3) \
 431         for (dx = 0; dx < 3; dx++, pixel++) \
 432             *pixel = col; \
 433 }
 434 SET_LCD_PIXEL(8, uint8_t)
 435 SET_LCD_PIXEL(16, uint16_t)
 436 SET_LCD_PIXEL(32, uint32_t)
 437
 438 #include "pixel_ops.h"
 439
 440 static void lcd_refresh(void *opaque)
 441 {
 442     musicpal_lcd_state *s = opaque;
 443     int x, y, col;
 444
 445     switch (ds_get_bits_per_pixel(s->ds)) {
 446     case 0:
 447         return;
 448 #define LCD_REFRESH(depth, func) \
 449     case depth: \
 450         col = func(scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 16) & 0xff), \
 451                    scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 8) & 0xff), \
 452                    scale_lcd_color(s, MP_LCD_TEXTCOLOR & 0xff)); \
 453         for (x = 0; x < 128; x++) \
 454             for (y = 0; y < 64; y++) \
 455                 if (s->video_ram[x + (y/8)*128] & (1 << (y % 8))) \
 456                     glue(set_lcd_pixel, depth)(s, x, y, col); \
 457                 else \
 458                     glue(set_lcd_pixel, depth)(s, x, y, 0); \
 459         break;
 460     LCD_REFRESH(8, rgb_to_pixel8)
 461     LCD_REFRESH(16, rgb_to_pixel16)
 462     LCD_REFRESH(32, (is_surface_bgr(s->ds->surface) ?
 463                      rgb_to_pixel32bgr : rgb_to_pixel32))
 464     default:
 465         hw_error("unsupported colour depth %i\n",
 466                   ds_get_bits_per_pixel(s->ds));
 467     }
 468
 469     dpy_update(s->ds, 0, 0, 128*3, 64*3);
 470 }
 471
 472 static void lcd_invalidate(void *opaque)
 473 {
 474 }
 475
 476 static void musicpal_lcd_gpio_brigthness_in(void *opaque, int irq, int level)
 477 {
 478     musicpal_lcd_state *s = (musicpal_lcd_state *) opaque;
 479     s->brightness &= ~(1 << irq);
 480     s->brightness |= level << irq;
 481 }
 482
 483 static uint32_t musicpal_lcd_read(void *opaque, target_phys_addr_t offset)
 484 {
 485     musicpal_lcd_state *s = opaque;
 486
 487     switch (offset) {
 488     case MP_LCD_IRQCTRL:
 489         return s->irqctrl;
 490
 491     default:
 492         return 0;
 493     }
 494 }
 495
 496 static void musicpal_lcd_write(void *opaque, target_phys_addr_t offset,
 497                                uint32_t value)
 498 {
 499     musicpal_lcd_state *s = opaque;
 500
 501     switch (offset) {
 502     case MP_LCD_IRQCTRL:
 503         s->irqctrl = value;
 504         break;
 505
 506     case MP_LCD_SPICTRL:
 507         if (value == MP_LCD_SPI_DATA || value == MP_LCD_SPI_CMD)
 508             s->mode = value;
 509         else
 510             s->mode = MP_LCD_SPI_INVALID;
 511         break;
 512
 513     case MP_LCD_INST:
 514         if (value >= MP_LCD_INST_SETPAGE0 && value <= MP_LCD_INST_SETPAGE7) {
 515             s->page = value - MP_LCD_INST_SETPAGE0;
 516             s->page_off = 0;
 517         }
 518         break;
 519
 520     case MP_LCD_DATA:
 521         if (s->mode == MP_LCD_SPI_CMD) {
 522             if (value >= MP_LCD_INST_SETPAGE0 &&
 523                 value <= MP_LCD_INST_SETPAGE7) {
 524                 s->page = value - MP_LCD_INST_SETPAGE0;
 525                 s->page_off = 0;
 526             }
 527         } else if (s->mode == MP_LCD_SPI_DATA) {
 528             s->video_ram[s->page*128 + s->page_off] = value;
 529             s->page_off = (s->page_off + 1) & 127;
 530         }
 531         break;
 532     }
 533 }
 534
 535 static CPUReadMemoryFunc * const musicpal_lcd_readfn[] = {
 536     musicpal_lcd_read,
 537     musicpal_lcd_read,
 538     musicpal_lcd_read
 539 };
 540
 541 static CPUWriteMemoryFunc * const musicpal_lcd_writefn[] = {
 542     musicpal_lcd_write,
 543     musicpal_lcd_write,
 544     musicpal_lcd_write
 545 };
 546
 547 static void musicpal_lcd_init(SysBusDevice *dev)
 548 {
 549     musicpal_lcd_state *s = FROM_SYSBUS(musicpal_lcd_state, dev);
 550     int iomemtype;
 551
 552     s->brightness = 7;
 553
 554     iomemtype = cpu_register_io_memory(musicpal_lcd_readfn,
 555                                        musicpal_lcd_writefn, s);
 556     sysbus_init_mmio(dev, MP_LCD_SIZE, iomemtype);
 557
 558     s->ds = graphic_console_init(lcd_refresh, lcd_invalidate,
 559                                  NULL, NULL, s);
 560     qemu_console_resize(s->ds, 128*3, 64*3);
 561
 562     qdev_init_gpio_in(&dev->qdev, musicpal_lcd_gpio_brigthness_in, 3);
 563 }
 564
 565 /* PIC register offsets */
 566 #define MP_PIC_STATUS           0x00
 567 #define MP_PIC_ENABLE_SET       0x08
 568 #define MP_PIC_ENABLE_CLR       0x0C
 569
 570 typedef struct mv88w8618_pic_state
 571 {
 572     SysBusDevice busdev;
 573     uint32_t level;
 574     uint32_t enabled;
 575     qemu_irq parent_irq;
 576 } mv88w8618_pic_state;
 577
 578 static void mv88w8618_pic_update(mv88w8618_pic_state *s)
 579 {
 580     qemu_set_irq(s->parent_irq, (s->level & s->enabled));
 581 }
 582
 583 static void mv88w8618_pic_set_irq(void *opaque, int irq, int level)
 584 {
 585     mv88w8618_pic_state *s = opaque;
 586
 587     if (level)
 588         s->level |= 1 << irq;
 589     else
 590         s->level &= ~(1 << irq);
 591     mv88w8618_pic_update(s);
 592 }
 593
 594 static uint32_t mv88w8618_pic_read(void *opaque, target_phys_addr_t offset)
 595 {
 596     mv88w8618_pic_state *s = opaque;
 597
 598     switch (offset) {
 599     case MP_PIC_STATUS:
 600         return s->level & s->enabled;
 601
 602     default:
 603         return 0;
 604     }
 605 }
 606
 607 static void mv88w8618_pic_write(void *opaque, target_phys_addr_t offset,
 608                                 uint32_t value)
 609 {
 610     mv88w8618_pic_state *s = opaque;
 611
 612     switch (offset) {
 613     case MP_PIC_ENABLE_SET:
 614         s->enabled |= value;
 615         break;
 616
 617     case MP_PIC_ENABLE_CLR:
 618         s->enabled &= ~value;
 619         s->level &= ~value;
 620         break;
 621     }
 622     mv88w8618_pic_update(s);
 623 }
 624
 625 static void mv88w8618_pic_reset(void *opaque)
 626 {
 627     mv88w8618_pic_state *s = opaque;
 628
 629     s->level = 0;
 630     s->enabled = 0;
 631 }
 632
 633 static CPUReadMemoryFunc * const mv88w8618_pic_readfn[] = {
 634     mv88w8618_pic_read,
 635     mv88w8618_pic_read,
 636     mv88w8618_pic_read
 637 };
 638
 639 static CPUWriteMemoryFunc * const mv88w8618_pic_writefn[] = {
 640     mv88w8618_pic_write,
 641     mv88w8618_pic_write,
 642     mv88w8618_pic_write
 643 };
 644
 645 static void mv88w8618_pic_init(SysBusDevice *dev)
 646 {
 647     mv88w8618_pic_state *s = FROM_SYSBUS(mv88w8618_pic_state, dev);
 648     int iomemtype;
 649
 650     qdev_init_gpio_in(&dev->qdev, mv88w8618_pic_set_irq, 32);
 651     sysbus_init_irq(dev, &s->parent_irq);
 652     iomemtype = cpu_register_io_memory(mv88w8618_pic_readfn,
 653                                        mv88w8618_pic_writefn, s);
 654     sysbus_init_mmio(dev, MP_PIC_SIZE, iomemtype);
 655
 656     qemu_register_reset(mv88w8618_pic_reset, s);
 657 }
 658
 659 /* PIT register offsets */
 660 #define MP_PIT_TIMER1_LENGTH    0x00
 661 /* ... */
 662 #define MP_PIT_TIMER4_LENGTH    0x0C
 663 #define MP_PIT_CONTROL          0x10
 664 #define MP_PIT_TIMER1_VALUE     0x14
 665 /* ... */
 666 #define MP_PIT_TIMER4_VALUE     0x20
 667 #define MP_BOARD_RESET          0x34
 668
 669 /* Magic board reset value (probably some watchdog behind it) */
 670 #define MP_BOARD_RESET_MAGIC    0x10000
 671
 672 typedef struct mv88w8618_timer_state {
 673     ptimer_state *ptimer;
 674     uint32_t limit;
 675     int freq;
 676     qemu_irq irq;
 677 } mv88w8618_timer_state;
 678
 679 typedef struct mv88w8618_pit_state {
 680     SysBusDevice busdev;
 681     mv88w8618_timer_state timer[4];
 682     uint32_t control;
 683 } mv88w8618_pit_state;
 684
 685 static void mv88w8618_timer_tick(void *opaque)
 686 {
 687     mv88w8618_timer_state *s = opaque;
 688
 689     qemu_irq_raise(s->irq);
 690 }
 691
 692 static void mv88w8618_timer_init(SysBusDevice *dev, mv88w8618_timer_state *s,
 693                                  uint32_t freq)
 694 {
 695     QEMUBH *bh;
 696
 697     sysbus_init_irq(dev, &s->irq);
 698     s->freq = freq;
 699
 700     bh = qemu_bh_new(mv88w8618_timer_tick, s);
 701     s->ptimer = ptimer_init(bh);
 702 }
 703
 704 static uint32_t mv88w8618_pit_read(void *opaque, target_phys_addr_t offset)
 705 {
 706     mv88w8618_pit_state *s = opaque;
 707     mv88w8618_timer_state *t;
 708
 709     switch (offset) {
 710     case MP_PIT_TIMER1_VALUE ... MP_PIT_TIMER4_VALUE:
 711         t = &s->timer[(offset-MP_PIT_TIMER1_VALUE) >> 2];
 712         return ptimer_get_count(t->ptimer);
 713
 714     default:
 715         return 0;
 716     }
 717 }
 718
 719 static void mv88w8618_pit_write(void *opaque, target_phys_addr_t offset,
 720                                 uint32_t value)
 721 {
 722     mv88w8618_pit_state *s = opaque;
 723     mv88w8618_timer_state *t;
 724     int i;
 725
 726     switch (offset) {
 727     case MP_PIT_TIMER1_LENGTH ... MP_PIT_TIMER4_LENGTH:
 728         t = &s->timer[offset >> 2];
 729         t->limit = value;
 730         ptimer_set_limit(t->ptimer, t->limit, 1);
 731         break;
 732
 733     case MP_PIT_CONTROL:
 734         for (i = 0; i < 4; i++) {
 735             if (value & 0xf) {
 736                 t = &s->timer[i];
 737                 ptimer_set_limit(t->ptimer, t->limit, 0);
 738                 ptimer_set_freq(t->ptimer, t->freq);
 739                 ptimer_run(t->ptimer, 0);
 740             }
 741             value >>= 4;
 742         }
 743         break;
 744
 745     case MP_BOARD_RESET:
 746         if (value == MP_BOARD_RESET_MAGIC)
 747             qemu_system_reset_request();
 748         break;
 749     }
 750 }
 751
 752 static CPUReadMemoryFunc * const mv88w8618_pit_readfn[] = {
 753     mv88w8618_pit_read,
 754     mv88w8618_pit_read,
 755     mv88w8618_pit_read
 756 };
 757
 758 static CPUWriteMemoryFunc * const mv88w8618_pit_writefn[] = {
 759     mv88w8618_pit_write,
 760     mv88w8618_pit_write,
 761     mv88w8618_pit_write
 762 };
 763
 764 static void mv88w8618_pit_init(SysBusDevice *dev)
 765 {
 766     int iomemtype;
 767     mv88w8618_pit_state *s = FROM_SYSBUS(mv88w8618_pit_state, dev);
 768     int i;
 769
 770     /* Letting them all run at 1 MHz is likely just a pragmatic
 771      * simplification. */
 772     for (i = 0; i < 4; i++) {
 773         mv88w8618_timer_init(dev, &s->timer[i], 1000000);
 774     }
 775
 776     iomemtype = cpu_register_io_memory(mv88w8618_pit_readfn,
 777                                        mv88w8618_pit_writefn, s);
 778     sysbus_init_mmio(dev, MP_PIT_SIZE, iomemtype);
 779 }
 780
 781 /* Flash config register offsets */
 782 #define MP_FLASHCFG_CFGR0    0x04
 783
 784 typedef struct mv88w8618_flashcfg_state {
 785     SysBusDevice busdev;
 786     uint32_t cfgr0;
 787 } mv88w8618_flashcfg_state;
 788
 789 static uint32_t mv88w8618_flashcfg_read(void *opaque,
 790                                         target_phys_addr_t offset)
 791 {
 792     mv88w8618_flashcfg_state *s = opaque;
 793
 794     switch (offset) {
 795     case MP_FLASHCFG_CFGR0:
 796         return s->cfgr0;
 797
 798     default:
 799         return 0;
 800     }
 801 }
 802
 803 static void mv88w8618_flashcfg_write(void *opaque, target_phys_addr_t offset,
 804                                      uint32_t value)
 805 {
 806     mv88w8618_flashcfg_state *s = opaque;
 807
 808     switch (offset) {
 809     case MP_FLASHCFG_CFGR0:
 810         s->cfgr0 = value;
 811         break;
 812     }
 813 }
 814
 815 static CPUReadMemoryFunc * const mv88w8618_flashcfg_readfn[] = {
 816     mv88w8618_flashcfg_read,
 817     mv88w8618_flashcfg_read,
 818     mv88w8618_flashcfg_read
 819 };
 820
 821 static CPUWriteMemoryFunc * const mv88w8618_flashcfg_writefn[] = {
 822     mv88w8618_flashcfg_write,
 823     mv88w8618_flashcfg_write,
 824     mv88w8618_flashcfg_write
 825 };
 826
 827 static void mv88w8618_flashcfg_init(SysBusDevice *dev)
 828 {
 829     int iomemtype;
 830     mv88w8618_flashcfg_state *s = FROM_SYSBUS(mv88w8618_flashcfg_state, dev);
 831
 832     s->cfgr0 = 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */
 833     iomemtype = cpu_register_io_memory(mv88w8618_flashcfg_readfn,
 834                        mv88w8618_flashcfg_writefn, s);
 835     sysbus_init_mmio(dev, MP_FLASHCFG_SIZE, iomemtype);
 836 }
 837
 838 /* Misc register offsets */
 839 #define MP_MISC_BOARD_REVISION  0x18
 840
 841 #define MP_BOARD_REVISION       0x31
 842
 843 static uint32_t musicpal_misc_read(void *opaque, target_phys_addr_t offset)
 844 {
 845     switch (offset) {
 846     case MP_MISC_BOARD_REVISION:
 847         return MP_BOARD_REVISION;
 848
 849     default:
 850         return 0;
 851     }
 852 }
 853
 854 static void musicpal_misc_write(void *opaque, target_phys_addr_t offset,
 855                                 uint32_t value)
 856 {
 857 }
 858
 859 static CPUReadMemoryFunc * const musicpal_misc_readfn[] = {
 860     musicpal_misc_read,
 861     musicpal_misc_read,
 862     musicpal_misc_read,
 863 };
 864
 865 static CPUWriteMemoryFunc * const musicpal_misc_writefn[] = {
 866     musicpal_misc_write,
 867     musicpal_misc_write,
 868     musicpal_misc_write,
 869 };
 870
 871 static void musicpal_misc_init(void)
 872 {
 873     int iomemtype;
 874
 875     iomemtype = cpu_register_io_memory(musicpal_misc_readfn,
 876                                        musicpal_misc_writefn, NULL);
 877     cpu_register_physical_memory(MP_MISC_BASE, MP_MISC_SIZE, iomemtype);
 878 }
 879
 880 /* WLAN register offsets */
 881 #define MP_WLAN_MAGIC1          0x11c
 882 #define MP_WLAN_MAGIC2          0x124
 883
 884 static uint32_t mv88w8618_wlan_read(void *opaque, target_phys_addr_t offset)
 885 {
 886     switch (offset) {
 887     /* Workaround to allow loading the binary-only wlandrv.ko crap
 888      * from the original Freecom firmware. */
 889     case MP_WLAN_MAGIC1:
 890         return ~3;
 891     case MP_WLAN_MAGIC2:
 892         return -1;
 893
 894     default:
 895         return 0;
 896     }
 897 }
 898
 899 static void mv88w8618_wlan_write(void *opaque, target_phys_addr_t offset,
 900                                  uint32_t value)
 901 {
 902 }
 903
 904 static CPUReadMemoryFunc * const mv88w8618_wlan_readfn[] = {
 905     mv88w8618_wlan_read,
 906     mv88w8618_wlan_read,
 907     mv88w8618_wlan_read,
 908 };
 909
 910 static CPUWriteMemoryFunc * const mv88w8618_wlan_writefn[] = {
 911     mv88w8618_wlan_write,
 912     mv88w8618_wlan_write,
 913     mv88w8618_wlan_write,
 914 };
 915
 916 static void mv88w8618_wlan_init(SysBusDevice *dev)
 917 {
 918     int iomemtype;
 919
 920     iomemtype = cpu_register_io_memory(mv88w8618_wlan_readfn,
 921                                        mv88w8618_wlan_writefn, NULL);
 922     sysbus_init_mmio(dev, MP_WLAN_SIZE, iomemtype);
 923 }
 924
 925 /* GPIO register offsets */
 926 #define MP_GPIO_OE_LO           0x008
 927 #define MP_GPIO_OUT_LO          0x00c
 928 #define MP_GPIO_IN_LO           0x010
 929 #define MP_GPIO_ISR_LO          0x020
 930 #define MP_GPIO_OE_HI           0x508
 931 #define MP_GPIO_OUT_HI          0x50c
 932 #define MP_GPIO_IN_HI           0x510
 933 #define MP_GPIO_ISR_HI          0x520
 934
 935 /* GPIO bits & masks */
 936 #define MP_GPIO_LCD_BRIGHTNESS  0x00070000
 937 #define MP_GPIO_I2C_DATA_BIT    29
 938 #define MP_GPIO_I2C_DATA        (1 << MP_GPIO_I2C_DATA_BIT)
 939 #define MP_GPIO_I2C_CLOCK_BIT   30
 940
 941 /* LCD brightness bits in GPIO_OE_HI */
 942 #define MP_OE_LCD_BRIGHTNESS    0x0007
 943
 944 typedef struct musicpal_gpio_state {
 945     SysBusDevice busdev;
 946     uint32_t lcd_brightness;
 947     uint32_t out_state;
 948     uint32_t in_state;
 949     uint32_t isr;
 950     uint32_t i2c_read_data;
 951     uint32_t key_released;
 952     uint32_t keys_event;    /* store the received key event */
 953     qemu_irq irq;
 954     qemu_irq out[5];
 955 } musicpal_gpio_state;
 956
 957 static void musicpal_gpio_brightness_update(musicpal_gpio_state *s) {
 958     int i;
 959     uint32_t brightness;
 960
 961     /* compute brightness ratio */
 962     switch (s->lcd_brightness) {
 963     case 0x00000007:
 964         brightness = 0;
 965         break;
 966
 967     case 0x00020000:
 968         brightness = 1;
 969         break;
 970
 971     case 0x00020001:
 972         brightness = 2;
 973         break;
 974
 975     case 0x00040000:
 976         brightness = 3;
 977         break;
 978
 979     case 0x00010006:
 980         brightness = 4;
 981         break;
 982
 983     case 0x00020005:
 984         brightness = 5;
 985         break;
 986
 987     case 0x00040003:
 988         brightness = 6;
 989         break;
 990
 991     case 0x00030004:
 992     default:
 993         brightness = 7;
 994     }
 995
 996     /* set lcd brightness GPIOs  */
 997     for (i = 0; i <= 2; i++)
 998         qemu_set_irq(s->out[i], (brightness >> i) & 1);
 999 }
1000
1001 static void musicpal_gpio_keys_update(musicpal_gpio_state *s)
1002 {
1003         int gpio_mask = 0;
1004
1005         /* transform the key state for GPIO usage */
1006         gpio_mask |= (s->keys_event & 15) << 8;
1007         gpio_mask |= ((s->keys_event >> 4) & 15) << 19;
1008
1009         /* update GPIO state */
1010         if (s->key_released) {
1011             s->in_state |= gpio_mask;
1012         } else {
1013             s->in_state &= ~gpio_mask;
1014             s->isr = gpio_mask;
1015             qemu_irq_raise(s->irq);
1016         }
1017 }
1018
1019 static void musicpal_gpio_irq(void *opaque, int irq, int level)
1020 {
1021     musicpal_gpio_state *s = (musicpal_gpio_state *) opaque;
1022
1023     if (irq == 10) {
1024         s->i2c_read_data = level;
1025     }
1026
1027     /* receives keys bits */
1028     if (irq <= 7) {
1029         s->keys_event &= ~(1 << irq);
1030         s->keys_event |= level << irq;
1031         return;
1032     }
1033
1034     /* receives key press/release */
1035     if (irq == 8) {
1036         s->key_released = level;
1037         return;
1038     }
1039
1040     /* a key has been transmited */
1041     if (irq == 9 && level == 1)
1042         musicpal_gpio_keys_update(s);
1043 }
1044
1045 static uint32_t musicpal_gpio_read(void *opaque, target_phys_addr_t offset)
1046 {
1047     musicpal_gpio_state *s = (musicpal_gpio_state *) opaque;
1048
1049     switch (offset) {
1050     case MP_GPIO_OE_HI: /* used for LCD brightness control */
1051         return s->lcd_brightness & MP_OE_LCD_BRIGHTNESS;
1052
1053     case MP_GPIO_OUT_LO:
1054         return s->out_state & 0xFFFF;
1055     case MP_GPIO_OUT_HI:
1056         return s->out_state >> 16;
1057
1058     case MP_GPIO_IN_LO:
1059         return s->in_state & 0xFFFF;
1060     case MP_GPIO_IN_HI:
1061         /* Update received I2C data */
1062         s->in_state = (s->in_state & ~MP_GPIO_I2C_DATA) |
1063                         (s->i2c_read_data << MP_GPIO_I2C_DATA_BIT);
1064         return s->in_state >> 16;
1065
1066     case MP_GPIO_ISR_LO:
1067         return s->isr & 0xFFFF;
1068     case MP_GPIO_ISR_HI:
1069         return s->isr >> 16;
1070
1071     default:
1072         return 0;
1073     }
1074 }
1075
1076 static void musicpal_gpio_write(void *opaque, target_phys_addr_t offset,
1077                                 uint32_t value)
1078 {
1079     musicpal_gpio_state *s = (musicpal_gpio_state *) opaque;
1080     switch (offset) {
1081     case MP_GPIO_OE_HI: /* used for LCD brightness control */
1082         s->lcd_brightness = (s->lcd_brightness & MP_GPIO_LCD_BRIGHTNESS) |
1083                          (value & MP_OE_LCD_BRIGHTNESS);
1084         musicpal_gpio_brightness_update(s);
1085         break;
1086
1087     case MP_GPIO_OUT_LO:
1088         s->out_state = (s->out_state & 0xFFFF0000) | (value & 0xFFFF);
1089         break;
1090     case MP_GPIO_OUT_HI:
1091         s->out_state = (s->out_state & 0xFFFF) | (value << 16);
1092         s->lcd_brightness = (s->lcd_brightness & 0xFFFF) |
1093                             (s->out_state & MP_GPIO_LCD_BRIGHTNESS);
1094         musicpal_gpio_brightness_update(s);
1095         qemu_set_irq(s->out[3], (s->out_state >> MP_GPIO_I2C_DATA_BIT) & 1);
1096         qemu_set_irq(s->out[4], (s->out_state >> MP_GPIO_I2C_CLOCK_BIT) & 1);
1097         break;
1098
1099     }
1100 }
1101
1102 static CPUReadMemoryFunc * const musicpal_gpio_readfn[] = {
1103     musicpal_gpio_read,
1104     musicpal_gpio_read,
1105     musicpal_gpio_read,
1106 };
1107
1108 static CPUWriteMemoryFunc * const musicpal_gpio_writefn[] = {
1109     musicpal_gpio_write,
1110     musicpal_gpio_write,
1111     musicpal_gpio_write,
1112 };
1113
1114 static void musicpal_gpio_reset(musicpal_gpio_state *s)
1115 {
1116     s->in_state = 0xffffffff;
1117     s->i2c_read_data = 1;
1118     s->key_released = 0;
1119     s->keys_event = 0;
1120     s->isr = 0;
1121 }
1122
1123 static void musicpal_gpio_init(SysBusDevice *dev)
1124 {
1125     musicpal_gpio_state *s = FROM_SYSBUS(musicpal_gpio_state, dev);
1126     int iomemtype;
1127
1128     sysbus_init_irq(dev, &s->irq);
1129
1130     iomemtype = cpu_register_io_memory(musicpal_gpio_readfn,
1131                                        musicpal_gpio_writefn, s);
1132     sysbus_init_mmio(dev, MP_GPIO_SIZE, iomemtype);
1133
1134     musicpal_gpio_reset(s);
1135
1136     /* 3 brightness out + 2 lcd (data and clock ) */
1137     qdev_init_gpio_out(&dev->qdev, s->out, 5);
1138     /* 10 gpio button input + 1 I2C data input */
1139     qdev_init_gpio_in(&dev->qdev, musicpal_gpio_irq, 11);
1140 }
1141
1142 /* Keyboard codes & masks */
1143 #define KEY_RELEASED            0x80
1144 #define KEY_CODE                0x7f
1145
1146 #define KEYCODE_TAB             0x0f
1147 #define KEYCODE_ENTER           0x1c
1148 #define KEYCODE_F               0x21
1149 #define KEYCODE_M               0x32
1150
1151 #define KEYCODE_EXTENDED        0xe0
1152 #define KEYCODE_UP              0x48
1153 #define KEYCODE_DOWN            0x50
1154 #define KEYCODE_LEFT            0x4b
1155 #define KEYCODE_RIGHT           0x4d
1156
1157 #define MP_KEY_WHEEL_VOL       (1)
1158 #define MP_KEY_WHEEL_VOL_INV   (1 << 1)
1159 #define MP_KEY_WHEEL_NAV       (1 << 2)
1160 #define MP_KEY_WHEEL_NAV_INV   (1 << 3)
1161 #define MP_KEY_BTN_FAVORITS    (1 << 4)
1162 #define MP_KEY_BTN_MENU        (1 << 5)
1163 #define MP_KEY_BTN_VOLUME      (1 << 6)
1164 #define MP_KEY_BTN_NAVIGATION  (1 << 7)
1165
1166 typedef struct musicpal_key_state {
1167     SysBusDevice busdev;
1168     uint32_t kbd_extended;
1169     uint32_t keys_state;
1170     qemu_irq out[10];
1171 } musicpal_key_state;
1172
1173 static void musicpal_key_event(void *opaque, int keycode)
1174 {
1175     musicpal_key_state *s = (musicpal_key_state *) opaque;
1176     uint32_t event = 0;
1177     int i;
1178
1179     if (keycode == KEYCODE_EXTENDED) {
1180         s->kbd_extended = 1;
1181         return;
1182     }
1183
1184     if (s->kbd_extended)
1185         switch (keycode & KEY_CODE) {
1186         case KEYCODE_UP:
1187             event = MP_KEY_WHEEL_NAV | MP_KEY_WHEEL_NAV_INV;
1188             break;
1189
1190         case KEYCODE_DOWN:
1191             event = MP_KEY_WHEEL_NAV;
1192             break;
1193
1194         case KEYCODE_LEFT:
1195             event = MP_KEY_WHEEL_VOL | MP_KEY_WHEEL_VOL_INV;
1196             break;
1197
1198         case KEYCODE_RIGHT:
1199             event = MP_KEY_WHEEL_VOL;
1200             break;
1201         }
1202     else {
1203         switch (keycode & KEY_CODE) {
1204         case KEYCODE_F:
1205             event = MP_KEY_BTN_FAVORITS;
1206             break;
1207
1208         case KEYCODE_TAB:
1209             event = MP_KEY_BTN_VOLUME;
1210             break;
1211
1212         case KEYCODE_ENTER:
1213             event = MP_KEY_BTN_NAVIGATION;
1214             break;
1215
1216         case KEYCODE_M:
1217             event = MP_KEY_BTN_MENU;
1218             break;
1219         }
1220         /* Do not repeat already pressed buttons */
1221         if (!(keycode & KEY_RELEASED) && !(s->keys_state & event))
1222             event = 0;
1223     }
1224
1225     if (event) {
1226
1227         /* transmit key event on GPIOS */
1228         for (i = 0; i <= 7; i++)
1229             qemu_set_irq(s->out[i], (event >> i) & 1);
1230
1231         /* handle key press/release */
1232         if (keycode & KEY_RELEASED) {
1233             s->keys_state |= event;
1234             qemu_irq_raise(s->out[8]);
1235         } else {
1236             s->keys_state &= ~event;
1237             qemu_irq_lower(s->out[8]);
1238         }
1239
1240         /* signal that a key event occured */
1241         qemu_irq_pulse(s->out[9]);
1242     }
1243
1244     s->kbd_extended = 0;
1245 }
1246
1247 static void musicpal_key_init(SysBusDevice *dev)
1248 {
1249     musicpal_key_state *s = FROM_SYSBUS(musicpal_key_state, dev);
1250
1251     sysbus_init_mmio(dev, 0x0, 0);
1252
1253     s->kbd_extended = 0;
1254     s->keys_state = 0;
1255
1256     /* 8 key event GPIO + 1 key press/release + 1 strobe */
1257     qdev_init_gpio_out(&dev->qdev, s->out, 10);
1258
1259     qemu_add_kbd_event_handler(musicpal_key_event, s);
1260 }
1261
1262 static struct arm_boot_info musicpal_binfo = {
1263     .loader_start = 0x0,
1264     .board_id = 0x20e,
1265 };
1266
1267 static void musicpal_init(ram_addr_t ram_size,
1268                const char *boot_device,
1269                const char *kernel_filename, const char *kernel_cmdline,
1270                const char *initrd_filename, const char *cpu_model)
1271 {
1272     CPUState *env;
1273     qemu_irq *cpu_pic;
1274     qemu_irq pic[32];
1275     DeviceState *dev;
1276     DeviceState *i2c_dev;
1277     DeviceState *lcd_dev;
1278     DeviceState *key_dev;
1279 #ifdef HAS_AUDIO
1280     DeviceState *wm8750_dev;
1281     SysBusDevice *s;
1282 #endif
1283     i2c_bus *i2c;
1284     int i;
1285     unsigned long flash_size;
1286     DriveInfo *dinfo;
1287     ram_addr_t sram_off;
1288
1289     if (!cpu_model)
1290         cpu_model = "arm926";
1291
1292     env = cpu_init(cpu_model);
1293     if (!env) {
1294         fprintf(stderr, "Unable to find CPU definition\n");
1295         exit(1);
1296     }
1297     cpu_pic = arm_pic_init_cpu(env);
1298
1299     /* For now we use a fixed - the original - RAM size */
1300     cpu_register_physical_memory(0, MP_RAM_DEFAULT_SIZE,
1301                                  qemu_ram_alloc(MP_RAM_DEFAULT_SIZE));
1302
1303     sram_off = qemu_ram_alloc(MP_SRAM_SIZE);
1304     cpu_register_physical_memory(MP_SRAM_BASE, MP_SRAM_SIZE, sram_off);
1305
1306     dev = sysbus_create_simple("mv88w8618_pic", MP_PIC_BASE,
1307                                cpu_pic[ARM_PIC_CPU_IRQ]);
1308     for (i = 0; i < 32; i++) {
1309         pic[i] = qdev_get_gpio_in(dev, i);
1310     }
1311     sysbus_create_varargs("mv88w8618_pit", MP_PIT_BASE, pic[MP_TIMER1_IRQ],
1312                           pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ],
1313                           pic[MP_TIMER4_IRQ], NULL);
1314
1315     if (serial_hds[0])
1316         serial_mm_init(MP_UART1_BASE, 2, pic[MP_UART1_IRQ], 1825000,
1317                    serial_hds[0], 1);
1318     if (serial_hds[1])
1319         serial_mm_init(MP_UART2_BASE, 2, pic[MP_UART2_IRQ], 1825000,
1320                    serial_hds[1], 1);
1321
1322     /* Register flash */
1323     dinfo = drive_get(IF_PFLASH, 0, 0);
1324     if (dinfo) {
1325         flash_size = bdrv_getlength(dinfo->bdrv);
1326         if (flash_size != 8*1024*1024 && flash_size != 16*1024*1024 &&
1327             flash_size != 32*1024*1024) {
1328             fprintf(stderr, "Invalid flash image size\n");
1329             exit(1);
1330         }
1331
1332         /*
1333          * The original U-Boot accesses the flash at 0xFE000000 instead of
1334          * 0xFF800000 (if there is 8 MB flash). So remap flash access if the
1335          * image is smaller than 32 MB.
1336          */
1337         pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, qemu_ram_alloc(flash_size),
1338                               dinfo->bdrv, 0x10000,
1339                               (flash_size + 0xffff) >> 16,
1340                               MP_FLASH_SIZE_MAX / flash_size,
1341                               2, 0x00BF, 0x236D, 0x0000, 0x0000,
1342                               0x5555, 0x2AAA);
1343     }
1344     sysbus_create_simple("mv88w8618_flashcfg", MP_FLASHCFG_BASE, NULL);
1345
1346     qemu_check_nic_model(&nd_table[0], "mv88w8618");
1347     dev = qdev_create(NULL, "mv88w8618_eth");
1348     dev->nd = &nd_table[0];
1349     qdev_init(dev);
1350     sysbus_mmio_map(sysbus_from_qdev(dev), 0, MP_ETH_BASE);
1351     sysbus_connect_irq(sysbus_from_qdev(dev), 0, pic[MP_ETH_IRQ]);
1352
1353     sysbus_create_simple("mv88w8618_wlan", MP_WLAN_BASE, NULL);
1354
1355     musicpal_misc_init();
1356
1357     dev = sysbus_create_simple("musicpal_gpio", MP_GPIO_BASE, pic[MP_GPIO_IRQ]);
1358     i2c_dev = sysbus_create_simple("bitbang_i2c", 0, NULL);
1359     i2c = (i2c_bus *)qdev_get_child_bus(i2c_dev, "i2c");
1360
1361     lcd_dev = sysbus_create_simple("musicpal_lcd", MP_LCD_BASE, NULL);
1362     key_dev = sysbus_create_simple("musicpal_key", 0, NULL);
1363
1364     /* I2C read data */
1365     qdev_connect_gpio_out(i2c_dev, 0, qdev_get_gpio_in(dev, 10));
1366     /* I2C data */
1367     qdev_connect_gpio_out(dev, 3, qdev_get_gpio_in(i2c_dev, 0));
1368     /* I2C clock */
1369     qdev_connect_gpio_out(dev, 4, qdev_get_gpio_in(i2c_dev, 1));
1370
1371     for (i = 0; i < 3; i++)
1372         qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(lcd_dev, i));
1373
1374     for (i = 0; i < 10; i++)
1375         qdev_connect_gpio_out(key_dev, i, qdev_get_gpio_in(dev, i));
1376
1377 #ifdef HAS_AUDIO
1378     wm8750_dev = i2c_create_slave(i2c, "wm8750", MP_WM_ADDR);
1379     dev = qdev_create(NULL, "mv88w8618_audio");
1380     s = sysbus_from_qdev(dev);
1381     qdev_prop_set_ptr(dev, "wm8750", wm8750_dev);
1382     qdev_init(dev);
1383     sysbus_mmio_map(s, 0, MP_AUDIO_BASE);
1384     sysbus_connect_irq(s, 0, pic[MP_AUDIO_IRQ]);
1385 #endif
1386
1387     musicpal_binfo.ram_size = MP_RAM_DEFAULT_SIZE;
1388     musicpal_binfo.kernel_filename = kernel_filename;
1389     musicpal_binfo.kernel_cmdline = kernel_cmdline;
1390     musicpal_binfo.initrd_filename = initrd_filename;
1391     arm_load_kernel(env, &musicpal_binfo);
1392 }
1393
1394 static QEMUMachine musicpal_machine = {
1395     .name = "musicpal",
1396     .desc = "Marvell 88w8618 / MusicPal (ARM926EJ-S)",
1397     .init = musicpal_init,
1398 };
1399
1400 static void musicpal_machine_init(void)
1401 {
1402     qemu_register_machine(&musicpal_machine);
1403 }
1404
1405 machine_init(musicpal_machine_init);
1406
1407 static void musicpal_register_devices(void)
1408 {
1409     sysbus_register_dev("mv88w8618_pic", sizeof(mv88w8618_pic_state),
1410                         mv88w8618_pic_init);
1411     sysbus_register_dev("mv88w8618_pit", sizeof(mv88w8618_pit_state),
1412                         mv88w8618_pit_init);
1413     sysbus_register_dev("mv88w8618_flashcfg", sizeof(mv88w8618_flashcfg_state),
1414                         mv88w8618_flashcfg_init);
1415     sysbus_register_dev("mv88w8618_eth", sizeof(mv88w8618_eth_state),
1416                         mv88w8618_eth_init);
1417     sysbus_register_dev("mv88w8618_wlan", sizeof(SysBusDevice),
1418                         mv88w8618_wlan_init);
1419     sysbus_register_dev("musicpal_lcd", sizeof(musicpal_lcd_state),
1420                         musicpal_lcd_init);
1421     sysbus_register_dev("musicpal_gpio", sizeof(musicpal_gpio_state),
1422                         musicpal_gpio_init);
1423     sysbus_register_dev("musicpal_key", sizeof(musicpal_key_state),
1424                         musicpal_key_init);
1425 }
1426
1427 device_init(musicpal_register_devices)