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e1000: bounds packet size against buffer size
[qemu.git] / hw / qxl.c
blob41500e9ea4328d8b8b7ab691ae648c84913400c9
1 /*
2 * Copyright (C) 2010 Red Hat, Inc.
3 *
4 * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann
5 * maintained by Gerd Hoffmann <kraxel@redhat.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu-common.h"
22 #include "qemu-timer.h"
23 #include "qemu-queue.h"
24 #include "monitor.h"
25 #include "sysemu.h"
26
27 #include "qxl.h"
28
29 #undef SPICE_RING_PROD_ITEM
30 #define SPICE_RING_PROD_ITEM(r, ret) { \
31 typeof(r) start = r; \
32 typeof(r) end = r + 1; \
33 uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r); \
34 typeof(&(r)->items[prod]) m_item = &(r)->items[prod]; \
35 if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \
36 abort(); \
37 } \
38 ret = &m_item->el; \
39 }
40
41 #undef SPICE_RING_CONS_ITEM
42 #define SPICE_RING_CONS_ITEM(r, ret) { \
43 typeof(r) start = r; \
44 typeof(r) end = r + 1; \
45 uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \
46 typeof(&(r)->items[cons]) m_item = &(r)->items[cons]; \
47 if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \
48 abort(); \
49 } \
50 ret = &m_item->el; \
51 }
52
53 #undef ALIGN
54 #define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1))
55
56 #define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9"
57
58 #define QXL_MODE(_x, _y, _b, _o) \
59 { .x_res = _x, \
60 .y_res = _y, \
61 .bits = _b, \
62 .stride = (_x) * (_b) / 8, \
63 .x_mili = PIXEL_SIZE * (_x), \
64 .y_mili = PIXEL_SIZE * (_y), \
65 .orientation = _o, \
66 }
67
68 #define QXL_MODE_16_32(x_res, y_res, orientation) \
69 QXL_MODE(x_res, y_res, 16, orientation), \
70 QXL_MODE(x_res, y_res, 32, orientation)
71
72 #define QXL_MODE_EX(x_res, y_res) \
73 QXL_MODE_16_32(x_res, y_res, 0), \
74 QXL_MODE_16_32(y_res, x_res, 1), \
75 QXL_MODE_16_32(x_res, y_res, 2), \
76 QXL_MODE_16_32(y_res, x_res, 3)
77
78 static QXLMode qxl_modes[] = {
79 QXL_MODE_EX(640, 480),
80 QXL_MODE_EX(800, 480),
81 QXL_MODE_EX(800, 600),
82 QXL_MODE_EX(832, 624),
83 QXL_MODE_EX(960, 640),
84 QXL_MODE_EX(1024, 600),
85 QXL_MODE_EX(1024, 768),
86 QXL_MODE_EX(1152, 864),
87 QXL_MODE_EX(1152, 870),
88 QXL_MODE_EX(1280, 720),
89 QXL_MODE_EX(1280, 760),
90 QXL_MODE_EX(1280, 768),
91 QXL_MODE_EX(1280, 800),
92 QXL_MODE_EX(1280, 960),
93 QXL_MODE_EX(1280, 1024),
94 QXL_MODE_EX(1360, 768),
95 QXL_MODE_EX(1366, 768),
96 QXL_MODE_EX(1400, 1050),
97 QXL_MODE_EX(1440, 900),
98 QXL_MODE_EX(1600, 900),
99 QXL_MODE_EX(1600, 1200),
100 QXL_MODE_EX(1680, 1050),
101 QXL_MODE_EX(1920, 1080),
102 #if VGA_RAM_SIZE >= (16 * 1024 * 1024)
103 /* these modes need more than 8 MB video memory */
104 QXL_MODE_EX(1920, 1200),
105 QXL_MODE_EX(1920, 1440),
106 QXL_MODE_EX(2048, 1536),
107 QXL_MODE_EX(2560, 1440),
108 QXL_MODE_EX(2560, 1600),
109 #endif
110 #if VGA_RAM_SIZE >= (32 * 1024 * 1024)
111 /* these modes need more than 16 MB video memory */
112 QXL_MODE_EX(2560, 2048),
113 QXL_MODE_EX(2800, 2100),
114 QXL_MODE_EX(3200, 2400),
115 #endif
116 };
117
118 static PCIQXLDevice *qxl0;
119
120 static void qxl_send_events(PCIQXLDevice *d, uint32_t events);
121 static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async);
122 static void qxl_reset_memslots(PCIQXLDevice *d);
123 static void qxl_reset_surfaces(PCIQXLDevice *d);
124 static void qxl_ring_set_dirty(PCIQXLDevice *qxl);
125
126 void qxl_guest_bug(PCIQXLDevice *qxl, const char *msg, ...)
127 {
128 #if SPICE_INTERFACE_QXL_MINOR >= 1
129 qxl_send_events(qxl, QXL_INTERRUPT_ERROR);
130 #endif
131 if (qxl->guestdebug) {
132 va_list ap;
133 va_start(ap, msg);
134 fprintf(stderr, "qxl-%d: guest bug: ", qxl->id);
135 vfprintf(stderr, msg, ap);
136 fprintf(stderr, "\n");
137 va_end(ap);
138 }
139 }
140
141
142 void qxl_spice_update_area(PCIQXLDevice *qxl, uint32_t surface_id,
143 struct QXLRect *area, struct QXLRect *dirty_rects,
144 uint32_t num_dirty_rects,
145 uint32_t clear_dirty_region,
146 qxl_async_io async)
147 {
148 if (async == QXL_SYNC) {
149 qxl->ssd.worker->update_area(qxl->ssd.worker, surface_id, area,
150 dirty_rects, num_dirty_rects, clear_dirty_region);
151 } else {
152 #if SPICE_INTERFACE_QXL_MINOR >= 1
153 spice_qxl_update_area_async(&qxl->ssd.qxl, surface_id, area,
154 clear_dirty_region, 0);
155 #else
156 abort();
157 #endif
158 }
159 }
160
161 static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice *qxl,
162 uint32_t id)
163 {
164 qemu_mutex_lock(&qxl->track_lock);
165 qxl->guest_surfaces.cmds[id] = 0;
166 qxl->guest_surfaces.count--;
167 qemu_mutex_unlock(&qxl->track_lock);
168 }
169
170 static void qxl_spice_destroy_surface_wait(PCIQXLDevice *qxl, uint32_t id,
171 qxl_async_io async)
172 {
173 if (async) {
174 #if SPICE_INTERFACE_QXL_MINOR < 1
175 abort();
176 #else
177 spice_qxl_destroy_surface_async(&qxl->ssd.qxl, id,
178 (uint64_t)id);
179 #endif
180 } else {
181 qxl->ssd.worker->destroy_surface_wait(qxl->ssd.worker, id);
182 qxl_spice_destroy_surface_wait_complete(qxl, id);
183 }
184 }
185
186 #if SPICE_INTERFACE_QXL_MINOR >= 1
187 static void qxl_spice_flush_surfaces_async(PCIQXLDevice *qxl)
188 {
189 spice_qxl_flush_surfaces_async(&qxl->ssd.qxl, 0);
190 }
191 #endif
192
193 void qxl_spice_loadvm_commands(PCIQXLDevice *qxl, struct QXLCommandExt *ext,
194 uint32_t count)
195 {
196 qxl->ssd.worker->loadvm_commands(qxl->ssd.worker, ext, count);
197 }
198
199 void qxl_spice_oom(PCIQXLDevice *qxl)
200 {
201 qxl->ssd.worker->oom(qxl->ssd.worker);
202 }
203
204 void qxl_spice_reset_memslots(PCIQXLDevice *qxl)
205 {
206 qxl->ssd.worker->reset_memslots(qxl->ssd.worker);
207 }
208
209 static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice *qxl)
210 {
211 qemu_mutex_lock(&qxl->track_lock);
212 memset(&qxl->guest_surfaces.cmds, 0, sizeof(qxl->guest_surfaces.cmds));
213 qxl->guest_surfaces.count = 0;
214 qemu_mutex_unlock(&qxl->track_lock);
215 }
216
217 static void qxl_spice_destroy_surfaces(PCIQXLDevice *qxl, qxl_async_io async)
218 {
219 if (async) {
220 #if SPICE_INTERFACE_QXL_MINOR < 1
221 abort();
222 #else
223 spice_qxl_destroy_surfaces_async(&qxl->ssd.qxl, 0);
224 #endif
225 } else {
226 qxl->ssd.worker->destroy_surfaces(qxl->ssd.worker);
227 qxl_spice_destroy_surfaces_complete(qxl);
228 }
229 }
230
231 void qxl_spice_reset_image_cache(PCIQXLDevice *qxl)
232 {
233 qxl->ssd.worker->reset_image_cache(qxl->ssd.worker);
234 }
235
236 void qxl_spice_reset_cursor(PCIQXLDevice *qxl)
237 {
238 qxl->ssd.worker->reset_cursor(qxl->ssd.worker);
239 qemu_mutex_lock(&qxl->track_lock);
240 qxl->guest_cursor = 0;
241 qemu_mutex_unlock(&qxl->track_lock);
242 }
243
244
245 static inline uint32_t msb_mask(uint32_t val)
246 {
247 uint32_t mask;
248
249 do {
250 mask = ~(val - 1) & val;
251 val &= ~mask;
252 } while (mask < val);
253
254 return mask;
255 }
256
257 static ram_addr_t qxl_rom_size(void)
258 {
259 uint32_t rom_size = sizeof(QXLRom) + sizeof(QXLModes) + sizeof(qxl_modes);
260 rom_size = MAX(rom_size, TARGET_PAGE_SIZE);
261 rom_size = msb_mask(rom_size * 2 - 1);
262 return rom_size;
263 }
264
265 static void init_qxl_rom(PCIQXLDevice *d)
266 {
267 QXLRom *rom = memory_region_get_ram_ptr(&d->rom_bar);
268 QXLModes *modes = (QXLModes *)(rom + 1);
269 uint32_t ram_header_size;
270 uint32_t surface0_area_size;
271 uint32_t num_pages;
272 uint32_t fb, maxfb = 0;
273 int i;
274
275 memset(rom, 0, d->rom_size);
276
277 rom->magic = cpu_to_le32(QXL_ROM_MAGIC);
278 rom->id = cpu_to_le32(d->id);
279 rom->log_level = cpu_to_le32(d->guestdebug);
280 rom->modes_offset = cpu_to_le32(sizeof(QXLRom));
281
282 rom->slot_gen_bits = MEMSLOT_GENERATION_BITS;
283 rom->slot_id_bits = MEMSLOT_SLOT_BITS;
284 rom->slots_start = 1;
285 rom->slots_end = NUM_MEMSLOTS - 1;
286 rom->n_surfaces = cpu_to_le32(NUM_SURFACES);
287
288 modes->n_modes = cpu_to_le32(ARRAY_SIZE(qxl_modes));
289 for (i = 0; i < modes->n_modes; i++) {
290 fb = qxl_modes[i].y_res * qxl_modes[i].stride;
291 if (maxfb < fb) {
292 maxfb = fb;
293 }
294 modes->modes[i].id = cpu_to_le32(i);
295 modes->modes[i].x_res = cpu_to_le32(qxl_modes[i].x_res);
296 modes->modes[i].y_res = cpu_to_le32(qxl_modes[i].y_res);
297 modes->modes[i].bits = cpu_to_le32(qxl_modes[i].bits);
298 modes->modes[i].stride = cpu_to_le32(qxl_modes[i].stride);
299 modes->modes[i].x_mili = cpu_to_le32(qxl_modes[i].x_mili);
300 modes->modes[i].y_mili = cpu_to_le32(qxl_modes[i].y_mili);
301 modes->modes[i].orientation = cpu_to_le32(qxl_modes[i].orientation);
302 }
303 if (maxfb < VGA_RAM_SIZE && d->id == 0)
304 maxfb = VGA_RAM_SIZE;
305
306 ram_header_size = ALIGN(sizeof(QXLRam), 4096);
307 surface0_area_size = ALIGN(maxfb, 4096);
308 num_pages = d->vga.vram_size;
309 num_pages -= ram_header_size;
310 num_pages -= surface0_area_size;
311 num_pages = num_pages / TARGET_PAGE_SIZE;
312
313 rom->draw_area_offset = cpu_to_le32(0);
314 rom->surface0_area_size = cpu_to_le32(surface0_area_size);
315 rom->pages_offset = cpu_to_le32(surface0_area_size);
316 rom->num_pages = cpu_to_le32(num_pages);
317 rom->ram_header_offset = cpu_to_le32(d->vga.vram_size - ram_header_size);
318
319 d->shadow_rom = *rom;
320 d->rom = rom;
321 d->modes = modes;
322 }
323
324 static void init_qxl_ram(PCIQXLDevice *d)
325 {
326 uint8_t *buf;
327 uint64_t *item;
328
329 buf = d->vga.vram_ptr;
330 d->ram = (QXLRam *)(buf + le32_to_cpu(d->shadow_rom.ram_header_offset));
331 d->ram->magic = cpu_to_le32(QXL_RAM_MAGIC);
332 d->ram->int_pending = cpu_to_le32(0);
333 d->ram->int_mask = cpu_to_le32(0);
334 d->ram->update_surface = 0;
335 SPICE_RING_INIT(&d->ram->cmd_ring);
336 SPICE_RING_INIT(&d->ram->cursor_ring);
337 SPICE_RING_INIT(&d->ram->release_ring);
338 SPICE_RING_PROD_ITEM(&d->ram->release_ring, item);
339 *item = 0;
340 qxl_ring_set_dirty(d);
341 }
342
343 /* can be called from spice server thread context */
344 static void qxl_set_dirty(MemoryRegion *mr, ram_addr_t addr, ram_addr_t end)
345 {
346 while (addr < end) {
347 memory_region_set_dirty(mr, addr);
348 addr += TARGET_PAGE_SIZE;
349 }
350 }
351
352 static void qxl_rom_set_dirty(PCIQXLDevice *qxl)
353 {
354 qxl_set_dirty(&qxl->rom_bar, 0, qxl->rom_size);
355 }
356
357 /* called from spice server thread context only */
358 static void qxl_ram_set_dirty(PCIQXLDevice *qxl, void *ptr)
359 {
360 void *base = qxl->vga.vram_ptr;
361 intptr_t offset;
362
363 offset = ptr - base;
364 offset &= ~(TARGET_PAGE_SIZE-1);
365 assert(offset < qxl->vga.vram_size);
366 qxl_set_dirty(&qxl->vga.vram, offset, offset + TARGET_PAGE_SIZE);
367 }
368
369 /* can be called from spice server thread context */
370 static void qxl_ring_set_dirty(PCIQXLDevice *qxl)
371 {
372 ram_addr_t addr = qxl->shadow_rom.ram_header_offset;
373 ram_addr_t end = qxl->vga.vram_size;
374 qxl_set_dirty(&qxl->vga.vram, addr, end);
375 }
376
377 /*
378 * keep track of some command state, for savevm/loadvm.
379 * called from spice server thread context only
380 */
381 static void qxl_track_command(PCIQXLDevice *qxl, struct QXLCommandExt *ext)
382 {
383 switch (le32_to_cpu(ext->cmd.type)) {
384 case QXL_CMD_SURFACE:
385 {
386 QXLSurfaceCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
387 uint32_t id = le32_to_cpu(cmd->surface_id);
388 PANIC_ON(id >= NUM_SURFACES);
389 qemu_mutex_lock(&qxl->track_lock);
390 if (cmd->type == QXL_SURFACE_CMD_CREATE) {
391 qxl->guest_surfaces.cmds[id] = ext->cmd.data;
392 qxl->guest_surfaces.count++;
393 if (qxl->guest_surfaces.max < qxl->guest_surfaces.count)
394 qxl->guest_surfaces.max = qxl->guest_surfaces.count;
395 }
396 if (cmd->type == QXL_SURFACE_CMD_DESTROY) {
397 qxl->guest_surfaces.cmds[id] = 0;
398 qxl->guest_surfaces.count--;
399 }
400 qemu_mutex_unlock(&qxl->track_lock);
401 break;
402 }
403 case QXL_CMD_CURSOR:
404 {
405 QXLCursorCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
406 if (cmd->type == QXL_CURSOR_SET) {
407 qemu_mutex_lock(&qxl->track_lock);
408 qxl->guest_cursor = ext->cmd.data;
409 qemu_mutex_unlock(&qxl->track_lock);
410 }
411 break;
412 }
413 }
414 }
415
416 /* spice display interface callbacks */
417
418 static void interface_attach_worker(QXLInstance *sin, QXLWorker *qxl_worker)
419 {
420 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
421
422 dprint(qxl, 1, "%s:\n", __FUNCTION__);
423 qxl->ssd.worker = qxl_worker;
424 }
425
426 static void interface_set_compression_level(QXLInstance *sin, int level)
427 {
428 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
429
430 dprint(qxl, 1, "%s: %d\n", __FUNCTION__, level);
431 qxl->shadow_rom.compression_level = cpu_to_le32(level);
432 qxl->rom->compression_level = cpu_to_le32(level);
433 qxl_rom_set_dirty(qxl);
434 }
435
436 static void interface_set_mm_time(QXLInstance *sin, uint32_t mm_time)
437 {
438 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
439
440 qxl->shadow_rom.mm_clock = cpu_to_le32(mm_time);
441 qxl->rom->mm_clock = cpu_to_le32(mm_time);
442 qxl_rom_set_dirty(qxl);
443 }
444
445 static void interface_get_init_info(QXLInstance *sin, QXLDevInitInfo *info)
446 {
447 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
448
449 dprint(qxl, 1, "%s:\n", __FUNCTION__);
450 info->memslot_gen_bits = MEMSLOT_GENERATION_BITS;
451 info->memslot_id_bits = MEMSLOT_SLOT_BITS;
452 info->num_memslots = NUM_MEMSLOTS;
453 info->num_memslots_groups = NUM_MEMSLOTS_GROUPS;
454 info->internal_groupslot_id = 0;
455 info->qxl_ram_size = le32_to_cpu(qxl->shadow_rom.num_pages) << TARGET_PAGE_BITS;
456 info->n_surfaces = NUM_SURFACES;
457 }
458
459 static const char *qxl_mode_to_string(int mode)
460 {
461 switch (mode) {
462 case QXL_MODE_COMPAT:
463 return "compat";
464 case QXL_MODE_NATIVE:
465 return "native";
466 case QXL_MODE_UNDEFINED:
467 return "undefined";
468 case QXL_MODE_VGA:
469 return "vga";
470 }
471 return "INVALID";
472 }
473
474 static const char *io_port_to_string(uint32_t io_port)
475 {
476 if (io_port >= QXL_IO_RANGE_SIZE) {
477 return "out of range";
478 }
479 static const char *io_port_to_string[QXL_IO_RANGE_SIZE + 1] = {
480 [QXL_IO_NOTIFY_CMD] = "QXL_IO_NOTIFY_CMD",
481 [QXL_IO_NOTIFY_CURSOR] = "QXL_IO_NOTIFY_CURSOR",
482 [QXL_IO_UPDATE_AREA] = "QXL_IO_UPDATE_AREA",
483 [QXL_IO_UPDATE_IRQ] = "QXL_IO_UPDATE_IRQ",
484 [QXL_IO_NOTIFY_OOM] = "QXL_IO_NOTIFY_OOM",
485 [QXL_IO_RESET] = "QXL_IO_RESET",
486 [QXL_IO_SET_MODE] = "QXL_IO_SET_MODE",
487 [QXL_IO_LOG] = "QXL_IO_LOG",
488 [QXL_IO_MEMSLOT_ADD] = "QXL_IO_MEMSLOT_ADD",
489 [QXL_IO_MEMSLOT_DEL] = "QXL_IO_MEMSLOT_DEL",
490 [QXL_IO_DETACH_PRIMARY] = "QXL_IO_DETACH_PRIMARY",
491 [QXL_IO_ATTACH_PRIMARY] = "QXL_IO_ATTACH_PRIMARY",
492 [QXL_IO_CREATE_PRIMARY] = "QXL_IO_CREATE_PRIMARY",
493 [QXL_IO_DESTROY_PRIMARY] = "QXL_IO_DESTROY_PRIMARY",
494 [QXL_IO_DESTROY_SURFACE_WAIT] = "QXL_IO_DESTROY_SURFACE_WAIT",
495 [QXL_IO_DESTROY_ALL_SURFACES] = "QXL_IO_DESTROY_ALL_SURFACES",
496 #if SPICE_INTERFACE_QXL_MINOR >= 1
497 [QXL_IO_UPDATE_AREA_ASYNC] = "QXL_IO_UPDATE_AREA_ASYNC",
498 [QXL_IO_MEMSLOT_ADD_ASYNC] = "QXL_IO_MEMSLOT_ADD_ASYNC",
499 [QXL_IO_CREATE_PRIMARY_ASYNC] = "QXL_IO_CREATE_PRIMARY_ASYNC",
500 [QXL_IO_DESTROY_PRIMARY_ASYNC] = "QXL_IO_DESTROY_PRIMARY_ASYNC",
501 [QXL_IO_DESTROY_SURFACE_ASYNC] = "QXL_IO_DESTROY_SURFACE_ASYNC",
502 [QXL_IO_DESTROY_ALL_SURFACES_ASYNC]
503 = "QXL_IO_DESTROY_ALL_SURFACES_ASYNC",
504 [QXL_IO_FLUSH_SURFACES_ASYNC] = "QXL_IO_FLUSH_SURFACES_ASYNC",
505 [QXL_IO_FLUSH_RELEASE] = "QXL_IO_FLUSH_RELEASE",
506 #endif
507 };
508 return io_port_to_string[io_port];
509 }
510
511 /* called from spice server thread context only */
512 static int interface_get_command(QXLInstance *sin, struct QXLCommandExt *ext)
513 {
514 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
515 SimpleSpiceUpdate *update;
516 QXLCommandRing *ring;
517 QXLCommand *cmd;
518 int notify, ret;
519
520 switch (qxl->mode) {
521 case QXL_MODE_VGA:
522 dprint(qxl, 2, "%s: vga\n", __FUNCTION__);
523 ret = false;
524 qemu_mutex_lock(&qxl->ssd.lock);
525 if (qxl->ssd.update != NULL) {
526 update = qxl->ssd.update;
527 qxl->ssd.update = NULL;
528 *ext = update->ext;
529 ret = true;
530 }
531 qemu_mutex_unlock(&qxl->ssd.lock);
532 if (ret) {
533 dprint(qxl, 2, "%s %s\n", __FUNCTION__, qxl_mode_to_string(qxl->mode));
534 qxl_log_command(qxl, "vga", ext);
535 }
536 return ret;
537 case QXL_MODE_COMPAT:
538 case QXL_MODE_NATIVE:
539 case QXL_MODE_UNDEFINED:
540 dprint(qxl, 4, "%s: %s\n", __FUNCTION__, qxl_mode_to_string(qxl->mode));
541 ring = &qxl->ram->cmd_ring;
542 if (SPICE_RING_IS_EMPTY(ring)) {
543 return false;
544 }
545 dprint(qxl, 2, "%s: %s\n", __FUNCTION__, qxl_mode_to_string(qxl->mode));
546 SPICE_RING_CONS_ITEM(ring, cmd);
547 ext->cmd = *cmd;
548 ext->group_id = MEMSLOT_GROUP_GUEST;
549 ext->flags = qxl->cmdflags;
550 SPICE_RING_POP(ring, notify);
551 qxl_ring_set_dirty(qxl);
552 if (notify) {
553 qxl_send_events(qxl, QXL_INTERRUPT_DISPLAY);
554 }
555 qxl->guest_primary.commands++;
556 qxl_track_command(qxl, ext);
557 qxl_log_command(qxl, "cmd", ext);
558 return true;
559 default:
560 return false;
561 }
562 }
563
564 /* called from spice server thread context only */
565 static int interface_req_cmd_notification(QXLInstance *sin)
566 {
567 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
568 int wait = 1;
569
570 switch (qxl->mode) {
571 case QXL_MODE_COMPAT:
572 case QXL_MODE_NATIVE:
573 case QXL_MODE_UNDEFINED:
574 SPICE_RING_CONS_WAIT(&qxl->ram->cmd_ring, wait);
575 qxl_ring_set_dirty(qxl);
576 break;
577 default:
578 /* nothing */
579 break;
580 }
581 return wait;
582 }
583
584 /* called from spice server thread context only */
585 static inline void qxl_push_free_res(PCIQXLDevice *d, int flush)
586 {
587 QXLReleaseRing *ring = &d->ram->release_ring;
588 uint64_t *item;
589 int notify;
590
591 #define QXL_FREE_BUNCH_SIZE 32
592
593 if (ring->prod - ring->cons + 1 == ring->num_items) {
594 /* ring full -- can't push */
595 return;
596 }
597 if (!flush && d->oom_running) {
598 /* collect everything from oom handler before pushing */
599 return;
600 }
601 if (!flush && d->num_free_res < QXL_FREE_BUNCH_SIZE) {
602 /* collect a bit more before pushing */
603 return;
604 }
605
606 SPICE_RING_PUSH(ring, notify);
607 dprint(d, 2, "free: push %d items, notify %s, ring %d/%d [%d,%d]\n",
608 d->num_free_res, notify ? "yes" : "no",
609 ring->prod - ring->cons, ring->num_items,
610 ring->prod, ring->cons);
611 if (notify) {
612 qxl_send_events(d, QXL_INTERRUPT_DISPLAY);
613 }
614 SPICE_RING_PROD_ITEM(ring, item);
615 *item = 0;
616 d->num_free_res = 0;
617 d->last_release = NULL;
618 qxl_ring_set_dirty(d);
619 }
620
621 /* called from spice server thread context only */
622 static void interface_release_resource(QXLInstance *sin,
623 struct QXLReleaseInfoExt ext)
624 {
625 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
626 QXLReleaseRing *ring;
627 uint64_t *item, id;
628
629 if (ext.group_id == MEMSLOT_GROUP_HOST) {
630 /* host group -> vga mode update request */
631 qemu_spice_destroy_update(&qxl->ssd, (void*)ext.info->id);
632 return;
633 }
634
635 /*
636 * ext->info points into guest-visible memory
637 * pci bar 0, $command.release_info
638 */
639 ring = &qxl->ram->release_ring;
640 SPICE_RING_PROD_ITEM(ring, item);
641 if (*item == 0) {
642 /* stick head into the ring */
643 id = ext.info->id;
644 ext.info->next = 0;
645 qxl_ram_set_dirty(qxl, &ext.info->next);
646 *item = id;
647 qxl_ring_set_dirty(qxl);
648 } else {
649 /* append item to the list */
650 qxl->last_release->next = ext.info->id;
651 qxl_ram_set_dirty(qxl, &qxl->last_release->next);
652 ext.info->next = 0;
653 qxl_ram_set_dirty(qxl, &ext.info->next);
654 }
655 qxl->last_release = ext.info;
656 qxl->num_free_res++;
657 dprint(qxl, 3, "%4d\r", qxl->num_free_res);
658 qxl_push_free_res(qxl, 0);
659 }
660
661 /* called from spice server thread context only */
662 static int interface_get_cursor_command(QXLInstance *sin, struct QXLCommandExt *ext)
663 {
664 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
665 QXLCursorRing *ring;
666 QXLCommand *cmd;
667 int notify;
668
669 switch (qxl->mode) {
670 case QXL_MODE_COMPAT:
671 case QXL_MODE_NATIVE:
672 case QXL_MODE_UNDEFINED:
673 ring = &qxl->ram->cursor_ring;
674 if (SPICE_RING_IS_EMPTY(ring)) {
675 return false;
676 }
677 SPICE_RING_CONS_ITEM(ring, cmd);
678 ext->cmd = *cmd;
679 ext->group_id = MEMSLOT_GROUP_GUEST;
680 ext->flags = qxl->cmdflags;
681 SPICE_RING_POP(ring, notify);
682 qxl_ring_set_dirty(qxl);
683 if (notify) {
684 qxl_send_events(qxl, QXL_INTERRUPT_CURSOR);
685 }
686 qxl->guest_primary.commands++;
687 qxl_track_command(qxl, ext);
688 qxl_log_command(qxl, "csr", ext);
689 if (qxl->id == 0) {
690 qxl_render_cursor(qxl, ext);
691 }
692 return true;
693 default:
694 return false;
695 }
696 }
697
698 /* called from spice server thread context only */
699 static int interface_req_cursor_notification(QXLInstance *sin)
700 {
701 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
702 int wait = 1;
703
704 switch (qxl->mode) {
705 case QXL_MODE_COMPAT:
706 case QXL_MODE_NATIVE:
707 case QXL_MODE_UNDEFINED:
708 SPICE_RING_CONS_WAIT(&qxl->ram->cursor_ring, wait);
709 qxl_ring_set_dirty(qxl);
710 break;
711 default:
712 /* nothing */
713 break;
714 }
715 return wait;
716 }
717
718 /* called from spice server thread context */
719 static void interface_notify_update(QXLInstance *sin, uint32_t update_id)
720 {
721 fprintf(stderr, "%s: abort()\n", __FUNCTION__);
722 abort();
723 }
724
725 /* called from spice server thread context only */
726 static int interface_flush_resources(QXLInstance *sin)
727 {
728 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
729 int ret;
730
731 dprint(qxl, 1, "free: guest flush (have %d)\n", qxl->num_free_res);
732 ret = qxl->num_free_res;
733 if (ret) {
734 qxl_push_free_res(qxl, 1);
735 }
736 return ret;
737 }
738
739 static void qxl_create_guest_primary_complete(PCIQXLDevice *d);
740
741 #if SPICE_INTERFACE_QXL_MINOR >= 1
742
743 /* called from spice server thread context only */
744 static void interface_async_complete(QXLInstance *sin, uint64_t cookie)
745 {
746 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
747 uint32_t current_async;
748
749 qemu_mutex_lock(&qxl->async_lock);
750 current_async = qxl->current_async;
751 qxl->current_async = QXL_UNDEFINED_IO;
752 qemu_mutex_unlock(&qxl->async_lock);
753
754 dprint(qxl, 2, "async_complete: %d (%ld) done\n", current_async, cookie);
755 switch (current_async) {
756 case QXL_IO_CREATE_PRIMARY_ASYNC:
757 qxl_create_guest_primary_complete(qxl);
758 break;
759 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
760 qxl_spice_destroy_surfaces_complete(qxl);
761 break;
762 case QXL_IO_DESTROY_SURFACE_ASYNC:
763 qxl_spice_destroy_surface_wait_complete(qxl, (uint32_t)cookie);
764 break;
765 }
766 qxl_send_events(qxl, QXL_INTERRUPT_IO_CMD);
767 }
768
769 #endif
770
771 static const QXLInterface qxl_interface = {
772 .base.type = SPICE_INTERFACE_QXL,
773 .base.description = "qxl gpu",
774 .base.major_version = SPICE_INTERFACE_QXL_MAJOR,
775 .base.minor_version = SPICE_INTERFACE_QXL_MINOR,
776
777 .attache_worker = interface_attach_worker,
778 .set_compression_level = interface_set_compression_level,
779 .set_mm_time = interface_set_mm_time,
780 .get_init_info = interface_get_init_info,
781
782 /* the callbacks below are called from spice server thread context */
783 .get_command = interface_get_command,
784 .req_cmd_notification = interface_req_cmd_notification,
785 .release_resource = interface_release_resource,
786 .get_cursor_command = interface_get_cursor_command,
787 .req_cursor_notification = interface_req_cursor_notification,
788 .notify_update = interface_notify_update,
789 .flush_resources = interface_flush_resources,
790 #if SPICE_INTERFACE_QXL_MINOR >= 1
791 .async_complete = interface_async_complete,
792 #endif
793 };
794
795 static void qxl_enter_vga_mode(PCIQXLDevice *d)
796 {
797 if (d->mode == QXL_MODE_VGA) {
798 return;
799 }
800 dprint(d, 1, "%s\n", __FUNCTION__);
801 qemu_spice_create_host_primary(&d->ssd);
802 d->mode = QXL_MODE_VGA;
803 memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty));
804 }
805
806 static void qxl_exit_vga_mode(PCIQXLDevice *d)
807 {
808 if (d->mode != QXL_MODE_VGA) {
809 return;
810 }
811 dprint(d, 1, "%s\n", __FUNCTION__);
812 qxl_destroy_primary(d, QXL_SYNC);
813 }
814
815 static void qxl_update_irq(PCIQXLDevice *d)
816 {
817 uint32_t pending = le32_to_cpu(d->ram->int_pending);
818 uint32_t mask = le32_to_cpu(d->ram->int_mask);
819 int level = !!(pending & mask);
820 qemu_set_irq(d->pci.irq[0], level);
821 qxl_ring_set_dirty(d);
822 }
823
824 static void qxl_check_state(PCIQXLDevice *d)
825 {
826 QXLRam *ram = d->ram;
827
828 assert(!d->ssd.running || SPICE_RING_IS_EMPTY(&ram->cmd_ring));
829 assert(!d->ssd.running || SPICE_RING_IS_EMPTY(&ram->cursor_ring));
830 }
831
832 static void qxl_reset_state(PCIQXLDevice *d)
833 {
834 QXLRom *rom = d->rom;
835
836 qxl_check_state(d);
837 d->shadow_rom.update_id = cpu_to_le32(0);
838 *rom = d->shadow_rom;
839 qxl_rom_set_dirty(d);
840 init_qxl_ram(d);
841 d->num_free_res = 0;
842 d->last_release = NULL;
843 memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty));
844 }
845
846 static void qxl_soft_reset(PCIQXLDevice *d)
847 {
848 dprint(d, 1, "%s:\n", __FUNCTION__);
849 qxl_check_state(d);
850
851 if (d->id == 0) {
852 qxl_enter_vga_mode(d);
853 } else {
854 d->mode = QXL_MODE_UNDEFINED;
855 }
856 }
857
858 static void qxl_hard_reset(PCIQXLDevice *d, int loadvm)
859 {
860 dprint(d, 1, "%s: start%s\n", __FUNCTION__,
861 loadvm ? " (loadvm)" : "");
862
863 qxl_spice_reset_cursor(d);
864 qxl_spice_reset_image_cache(d);
865 qxl_reset_surfaces(d);
866 qxl_reset_memslots(d);
867
868 /* pre loadvm reset must not touch QXLRam. This lives in
869 * device memory, is migrated together with RAM and thus
870 * already loaded at this point */
871 if (!loadvm) {
872 qxl_reset_state(d);
873 }
874 qemu_spice_create_host_memslot(&d->ssd);
875 qxl_soft_reset(d);
876
877 dprint(d, 1, "%s: done\n", __FUNCTION__);
878 }
879
880 static void qxl_reset_handler(DeviceState *dev)
881 {
882 PCIQXLDevice *d = DO_UPCAST(PCIQXLDevice, pci.qdev, dev);
883 qxl_hard_reset(d, 0);
884 }
885
886 static void qxl_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
887 {
888 VGACommonState *vga = opaque;
889 PCIQXLDevice *qxl = container_of(vga, PCIQXLDevice, vga);
890
891 if (qxl->mode != QXL_MODE_VGA) {
892 dprint(qxl, 1, "%s\n", __FUNCTION__);
893 qxl_destroy_primary(qxl, QXL_SYNC);
894 qxl_soft_reset(qxl);
895 }
896 vga_ioport_write(opaque, addr, val);
897 }
898
899 static const MemoryRegionPortio qxl_vga_portio_list[] = {
900 { 0x04, 2, 1, .read = vga_ioport_read,
901 .write = qxl_vga_ioport_write }, /* 3b4 */
902 { 0x0a, 1, 1, .read = vga_ioport_read,
903 .write = qxl_vga_ioport_write }, /* 3ba */
904 { 0x10, 16, 1, .read = vga_ioport_read,
905 .write = qxl_vga_ioport_write }, /* 3c0 */
906 { 0x24, 2, 1, .read = vga_ioport_read,
907 .write = qxl_vga_ioport_write }, /* 3d4 */
908 { 0x2a, 1, 1, .read = vga_ioport_read,
909 .write = qxl_vga_ioport_write }, /* 3da */
910 PORTIO_END_OF_LIST(),
911 };
912
913 static void qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta,
914 qxl_async_io async)
915 {
916 static const int regions[] = {
917 QXL_RAM_RANGE_INDEX,
918 QXL_VRAM_RANGE_INDEX,
919 };
920 uint64_t guest_start;
921 uint64_t guest_end;
922 int pci_region;
923 pcibus_t pci_start;
924 pcibus_t pci_end;
925 intptr_t virt_start;
926 QXLDevMemSlot memslot;
927 int i;
928
929 guest_start = le64_to_cpu(d->guest_slots[slot_id].slot.mem_start);
930 guest_end = le64_to_cpu(d->guest_slots[slot_id].slot.mem_end);
931
932 dprint(d, 1, "%s: slot %d: guest phys 0x%" PRIx64 " - 0x%" PRIx64 "\n",
933 __FUNCTION__, slot_id,
934 guest_start, guest_end);
935
936 PANIC_ON(slot_id >= NUM_MEMSLOTS);
937 PANIC_ON(guest_start > guest_end);
938
939 for (i = 0; i < ARRAY_SIZE(regions); i++) {
940 pci_region = regions[i];
941 pci_start = d->pci.io_regions[pci_region].addr;
942 pci_end = pci_start + d->pci.io_regions[pci_region].size;
943 /* mapped? */
944 if (pci_start == -1) {
945 continue;
946 }
947 /* start address in range ? */
948 if (guest_start < pci_start || guest_start > pci_end) {
949 continue;
950 }
951 /* end address in range ? */
952 if (guest_end > pci_end) {
953 continue;
954 }
955 /* passed */
956 break;
957 }
958 PANIC_ON(i == ARRAY_SIZE(regions)); /* finished loop without match */
959
960 switch (pci_region) {
961 case QXL_RAM_RANGE_INDEX:
962 virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vga.vram);
963 break;
964 case QXL_VRAM_RANGE_INDEX:
965 virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vram_bar);
966 break;
967 default:
968 /* should not happen */
969 abort();
970 }
971
972 memslot.slot_id = slot_id;
973 memslot.slot_group_id = MEMSLOT_GROUP_GUEST; /* guest group */
974 memslot.virt_start = virt_start + (guest_start - pci_start);
975 memslot.virt_end = virt_start + (guest_end - pci_start);
976 memslot.addr_delta = memslot.virt_start - delta;
977 memslot.generation = d->rom->slot_generation = 0;
978 qxl_rom_set_dirty(d);
979
980 dprint(d, 1, "%s: slot %d: host virt 0x%lx - 0x%lx\n",
981 __FUNCTION__, memslot.slot_id,
982 memslot.virt_start, memslot.virt_end);
983
984 qemu_spice_add_memslot(&d->ssd, &memslot, async);
985 d->guest_slots[slot_id].ptr = (void*)memslot.virt_start;
986 d->guest_slots[slot_id].size = memslot.virt_end - memslot.virt_start;
987 d->guest_slots[slot_id].delta = delta;
988 d->guest_slots[slot_id].active = 1;
989 }
990
991 static void qxl_del_memslot(PCIQXLDevice *d, uint32_t slot_id)
992 {
993 dprint(d, 1, "%s: slot %d\n", __FUNCTION__, slot_id);
994 qemu_spice_del_memslot(&d->ssd, MEMSLOT_GROUP_HOST, slot_id);
995 d->guest_slots[slot_id].active = 0;
996 }
997
998 static void qxl_reset_memslots(PCIQXLDevice *d)
999 {
1000 dprint(d, 1, "%s:\n", __FUNCTION__);
1001 qxl_spice_reset_memslots(d);
1002 memset(&d->guest_slots, 0, sizeof(d->guest_slots));
1003 }
1004
1005 static void qxl_reset_surfaces(PCIQXLDevice *d)
1006 {
1007 dprint(d, 1, "%s:\n", __FUNCTION__);
1008 d->mode = QXL_MODE_UNDEFINED;
1009 qxl_spice_destroy_surfaces(d, QXL_SYNC);
1010 }
1011
1012 /* called from spice server thread context only */
1013 void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, int group_id)
1014 {
1015 uint64_t phys = le64_to_cpu(pqxl);
1016 uint32_t slot = (phys >> (64 - 8)) & 0xff;
1017 uint64_t offset = phys & 0xffffffffffff;
1018
1019 switch (group_id) {
1020 case MEMSLOT_GROUP_HOST:
1021 return (void*)offset;
1022 case MEMSLOT_GROUP_GUEST:
1023 PANIC_ON(slot > NUM_MEMSLOTS);
1024 PANIC_ON(!qxl->guest_slots[slot].active);
1025 PANIC_ON(offset < qxl->guest_slots[slot].delta);
1026 offset -= qxl->guest_slots[slot].delta;
1027 PANIC_ON(offset > qxl->guest_slots[slot].size)
1028 return qxl->guest_slots[slot].ptr + offset;
1029 default:
1030 PANIC_ON(1);
1031 }
1032 }
1033
1034 static void qxl_create_guest_primary_complete(PCIQXLDevice *qxl)
1035 {
1036 /* for local rendering */
1037 qxl_render_resize(qxl);
1038 }
1039
1040 static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm,
1041 qxl_async_io async)
1042 {
1043 QXLDevSurfaceCreate surface;
1044 QXLSurfaceCreate *sc = &qxl->guest_primary.surface;
1045
1046 assert(qxl->mode != QXL_MODE_NATIVE);
1047 qxl_exit_vga_mode(qxl);
1048
1049 dprint(qxl, 1, "%s: %dx%d\n", __FUNCTION__,
1050 le32_to_cpu(sc->width), le32_to_cpu(sc->height));
1051
1052 surface.format = le32_to_cpu(sc->format);
1053 surface.height = le32_to_cpu(sc->height);
1054 surface.mem = le64_to_cpu(sc->mem);
1055 surface.position = le32_to_cpu(sc->position);
1056 surface.stride = le32_to_cpu(sc->stride);
1057 surface.width = le32_to_cpu(sc->width);
1058 surface.type = le32_to_cpu(sc->type);
1059 surface.flags = le32_to_cpu(sc->flags);
1060
1061 surface.mouse_mode = true;
1062 surface.group_id = MEMSLOT_GROUP_GUEST;
1063 if (loadvm) {
1064 surface.flags |= QXL_SURF_FLAG_KEEP_DATA;
1065 }
1066
1067 qxl->mode = QXL_MODE_NATIVE;
1068 qxl->cmdflags = 0;
1069 qemu_spice_create_primary_surface(&qxl->ssd, 0, &surface, async);
1070
1071 if (async == QXL_SYNC) {
1072 qxl_create_guest_primary_complete(qxl);
1073 }
1074 }
1075
1076 /* return 1 if surface destoy was initiated (in QXL_ASYNC case) or
1077 * done (in QXL_SYNC case), 0 otherwise. */
1078 static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async)
1079 {
1080 if (d->mode == QXL_MODE_UNDEFINED) {
1081 return 0;
1082 }
1083
1084 dprint(d, 1, "%s\n", __FUNCTION__);
1085
1086 d->mode = QXL_MODE_UNDEFINED;
1087 qemu_spice_destroy_primary_surface(&d->ssd, 0, async);
1088 qxl_spice_reset_cursor(d);
1089 return 1;
1090 }
1091
1092 static void qxl_set_mode(PCIQXLDevice *d, int modenr, int loadvm)
1093 {
1094 pcibus_t start = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1095 pcibus_t end = d->pci.io_regions[QXL_RAM_RANGE_INDEX].size + start;
1096 QXLMode *mode = d->modes->modes + modenr;
1097 uint64_t devmem = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1098 QXLMemSlot slot = {
1099 .mem_start = start,
1100 .mem_end = end
1101 };
1102 QXLSurfaceCreate surface = {
1103 .width = mode->x_res,
1104 .height = mode->y_res,
1105 .stride = -mode->x_res * 4,
1106 .format = SPICE_SURFACE_FMT_32_xRGB,
1107 .flags = loadvm ? QXL_SURF_FLAG_KEEP_DATA : 0,
1108 .mouse_mode = true,
1109 .mem = devmem + d->shadow_rom.draw_area_offset,
1110 };
1111
1112 dprint(d, 1, "%s: mode %d [ %d x %d @ %d bpp devmem 0x%" PRIx64 " ]\n",
1113 __func__, modenr, mode->x_res, mode->y_res, mode->bits, devmem);
1114 if (!loadvm) {
1115 qxl_hard_reset(d, 0);
1116 }
1117
1118 d->guest_slots[0].slot = slot;
1119 qxl_add_memslot(d, 0, devmem, QXL_SYNC);
1120
1121 d->guest_primary.surface = surface;
1122 qxl_create_guest_primary(d, 0, QXL_SYNC);
1123
1124 d->mode = QXL_MODE_COMPAT;
1125 d->cmdflags = QXL_COMMAND_FLAG_COMPAT;
1126 #ifdef QXL_COMMAND_FLAG_COMPAT_16BPP /* new in spice 0.6.1 */
1127 if (mode->bits == 16) {
1128 d->cmdflags |= QXL_COMMAND_FLAG_COMPAT_16BPP;
1129 }
1130 #endif
1131 d->shadow_rom.mode = cpu_to_le32(modenr);
1132 d->rom->mode = cpu_to_le32(modenr);
1133 qxl_rom_set_dirty(d);
1134 }
1135
1136 static void ioport_write(void *opaque, target_phys_addr_t addr,
1137 uint64_t val, unsigned size)
1138 {
1139 PCIQXLDevice *d = opaque;
1140 uint32_t io_port = addr;
1141 qxl_async_io async = QXL_SYNC;
1142 #if SPICE_INTERFACE_QXL_MINOR >= 1
1143 uint32_t orig_io_port = io_port;
1144 #endif
1145
1146 switch (io_port) {
1147 case QXL_IO_RESET:
1148 case QXL_IO_SET_MODE:
1149 case QXL_IO_MEMSLOT_ADD:
1150 case QXL_IO_MEMSLOT_DEL:
1151 case QXL_IO_CREATE_PRIMARY:
1152 case QXL_IO_UPDATE_IRQ:
1153 case QXL_IO_LOG:
1154 #if SPICE_INTERFACE_QXL_MINOR >= 1
1155 case QXL_IO_MEMSLOT_ADD_ASYNC:
1156 case QXL_IO_CREATE_PRIMARY_ASYNC:
1157 #endif
1158 break;
1159 default:
1160 if (d->mode != QXL_MODE_VGA) {
1161 break;
1162 }
1163 dprint(d, 1, "%s: unexpected port 0x%x (%s) in vga mode\n",
1164 __func__, io_port, io_port_to_string(io_port));
1165 #if SPICE_INTERFACE_QXL_MINOR >= 1
1166 /* be nice to buggy guest drivers */
1167 if (io_port >= QXL_IO_UPDATE_AREA_ASYNC &&
1168 io_port <= QXL_IO_DESTROY_ALL_SURFACES_ASYNC) {
1169 qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1170 }
1171 #endif
1172 return;
1173 }
1174
1175 #if SPICE_INTERFACE_QXL_MINOR >= 1
1176 /* we change the io_port to avoid ifdeffery in the main switch */
1177 orig_io_port = io_port;
1178 switch (io_port) {
1179 case QXL_IO_UPDATE_AREA_ASYNC:
1180 io_port = QXL_IO_UPDATE_AREA;
1181 goto async_common;
1182 case QXL_IO_MEMSLOT_ADD_ASYNC:
1183 io_port = QXL_IO_MEMSLOT_ADD;
1184 goto async_common;
1185 case QXL_IO_CREATE_PRIMARY_ASYNC:
1186 io_port = QXL_IO_CREATE_PRIMARY;
1187 goto async_common;
1188 case QXL_IO_DESTROY_PRIMARY_ASYNC:
1189 io_port = QXL_IO_DESTROY_PRIMARY;
1190 goto async_common;
1191 case QXL_IO_DESTROY_SURFACE_ASYNC:
1192 io_port = QXL_IO_DESTROY_SURFACE_WAIT;
1193 goto async_common;
1194 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
1195 io_port = QXL_IO_DESTROY_ALL_SURFACES;
1196 goto async_common;
1197 case QXL_IO_FLUSH_SURFACES_ASYNC:
1198 async_common:
1199 async = QXL_ASYNC;
1200 qemu_mutex_lock(&d->async_lock);
1201 if (d->current_async != QXL_UNDEFINED_IO) {
1202 qxl_guest_bug(d, "%d async started before last (%d) complete",
1203 io_port, d->current_async);
1204 qemu_mutex_unlock(&d->async_lock);
1205 return;
1206 }
1207 d->current_async = orig_io_port;
1208 qemu_mutex_unlock(&d->async_lock);
1209 dprint(d, 2, "start async %d (%"PRId64")\n", io_port, val);
1210 break;
1211 default:
1212 break;
1213 }
1214 #endif
1215
1216 switch (io_port) {
1217 case QXL_IO_UPDATE_AREA:
1218 {
1219 QXLRect update = d->ram->update_area;
1220 qxl_spice_update_area(d, d->ram->update_surface,
1221 &update, NULL, 0, 0, async);
1222 break;
1223 }
1224 case QXL_IO_NOTIFY_CMD:
1225 qemu_spice_wakeup(&d->ssd);
1226 break;
1227 case QXL_IO_NOTIFY_CURSOR:
1228 qemu_spice_wakeup(&d->ssd);
1229 break;
1230 case QXL_IO_UPDATE_IRQ:
1231 qxl_update_irq(d);
1232 break;
1233 case QXL_IO_NOTIFY_OOM:
1234 if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) {
1235 break;
1236 }
1237 d->oom_running = 1;
1238 qxl_spice_oom(d);
1239 d->oom_running = 0;
1240 break;
1241 case QXL_IO_SET_MODE:
1242 dprint(d, 1, "QXL_SET_MODE %d\n", (int)val);
1243 qxl_set_mode(d, val, 0);
1244 break;
1245 case QXL_IO_LOG:
1246 if (d->guestdebug) {
1247 fprintf(stderr, "qxl/guest-%d: %" PRId64 ": %s", d->id,
1248 qemu_get_clock_ns(vm_clock), d->ram->log_buf);
1249 }
1250 break;
1251 case QXL_IO_RESET:
1252 dprint(d, 1, "QXL_IO_RESET\n");
1253 qxl_hard_reset(d, 0);
1254 break;
1255 case QXL_IO_MEMSLOT_ADD:
1256 if (val >= NUM_MEMSLOTS) {
1257 qxl_guest_bug(d, "QXL_IO_MEMSLOT_ADD: val out of range");
1258 break;
1259 }
1260 if (d->guest_slots[val].active) {
1261 qxl_guest_bug(d, "QXL_IO_MEMSLOT_ADD: memory slot already active");
1262 break;
1263 }
1264 d->guest_slots[val].slot = d->ram->mem_slot;
1265 qxl_add_memslot(d, val, 0, async);
1266 break;
1267 case QXL_IO_MEMSLOT_DEL:
1268 if (val >= NUM_MEMSLOTS) {
1269 qxl_guest_bug(d, "QXL_IO_MEMSLOT_DEL: val out of range");
1270 break;
1271 }
1272 qxl_del_memslot(d, val);
1273 break;
1274 case QXL_IO_CREATE_PRIMARY:
1275 if (val != 0) {
1276 qxl_guest_bug(d, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0",
1277 async);
1278 goto cancel_async;
1279 }
1280 dprint(d, 1, "QXL_IO_CREATE_PRIMARY async=%d\n", async);
1281 d->guest_primary.surface = d->ram->create_surface;
1282 qxl_create_guest_primary(d, 0, async);
1283 break;
1284 case QXL_IO_DESTROY_PRIMARY:
1285 if (val != 0) {
1286 qxl_guest_bug(d, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0",
1287 async);
1288 goto cancel_async;
1289 }
1290 dprint(d, 1, "QXL_IO_DESTROY_PRIMARY (async=%d) (%s)\n", async,
1291 qxl_mode_to_string(d->mode));
1292 if (!qxl_destroy_primary(d, async)) {
1293 dprint(d, 1, "QXL_IO_DESTROY_PRIMARY_ASYNC in %s, ignored\n",
1294 qxl_mode_to_string(d->mode));
1295 goto cancel_async;
1296 }
1297 break;
1298 case QXL_IO_DESTROY_SURFACE_WAIT:
1299 if (val >= NUM_SURFACES) {
1300 qxl_guest_bug(d, "QXL_IO_DESTROY_SURFACE (async=%d):"
1301 "%d >= NUM_SURFACES", async, val);
1302 goto cancel_async;
1303 }
1304 qxl_spice_destroy_surface_wait(d, val, async);
1305 break;
1306 #if SPICE_INTERFACE_QXL_MINOR >= 1
1307 case QXL_IO_FLUSH_RELEASE: {
1308 QXLReleaseRing *ring = &d->ram->release_ring;
1309 if (ring->prod - ring->cons + 1 == ring->num_items) {
1310 fprintf(stderr,
1311 "ERROR: no flush, full release ring [p%d,%dc]\n",
1312 ring->prod, ring->cons);
1313 }
1314 qxl_push_free_res(d, 1 /* flush */);
1315 dprint(d, 1, "QXL_IO_FLUSH_RELEASE exit (%s, s#=%d, res#=%d,%p)\n",
1316 qxl_mode_to_string(d->mode), d->guest_surfaces.count,
1317 d->num_free_res, d->last_release);
1318 break;
1319 }
1320 case QXL_IO_FLUSH_SURFACES_ASYNC:
1321 dprint(d, 1, "QXL_IO_FLUSH_SURFACES_ASYNC"
1322 " (%"PRId64") (%s, s#=%d, res#=%d)\n",
1323 val, qxl_mode_to_string(d->mode), d->guest_surfaces.count,
1324 d->num_free_res);
1325 qxl_spice_flush_surfaces_async(d);
1326 break;
1327 #endif
1328 case QXL_IO_DESTROY_ALL_SURFACES:
1329 d->mode = QXL_MODE_UNDEFINED;
1330 qxl_spice_destroy_surfaces(d, async);
1331 break;
1332 default:
1333 fprintf(stderr, "%s: ioport=0x%x, abort()\n", __FUNCTION__, io_port);
1334 abort();
1335 }
1336 return;
1337 cancel_async:
1338 #if SPICE_INTERFACE_QXL_MINOR >= 1
1339 if (async) {
1340 qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1341 qemu_mutex_lock(&d->async_lock);
1342 d->current_async = QXL_UNDEFINED_IO;
1343 qemu_mutex_unlock(&d->async_lock);
1344 }
1345 #else
1346 return;
1347 #endif
1348 }
1349
1350 static uint64_t ioport_read(void *opaque, target_phys_addr_t addr,
1351 unsigned size)
1352 {
1353 PCIQXLDevice *d = opaque;
1354
1355 dprint(d, 1, "%s: unexpected\n", __FUNCTION__);
1356 return 0xff;
1357 }
1358
1359 static const MemoryRegionOps qxl_io_ops = {
1360 .read = ioport_read,
1361 .write = ioport_write,
1362 .valid = {
1363 .min_access_size = 1,
1364 .max_access_size = 1,
1365 },
1366 };
1367
1368 static void pipe_read(void *opaque)
1369 {
1370 PCIQXLDevice *d = opaque;
1371 char dummy;
1372 int len;
1373
1374 do {
1375 len = read(d->pipe[0], &dummy, sizeof(dummy));
1376 } while (len == sizeof(dummy));
1377 qxl_update_irq(d);
1378 }
1379
1380 static void qxl_send_events(PCIQXLDevice *d, uint32_t events)
1381 {
1382 uint32_t old_pending;
1383 uint32_t le_events = cpu_to_le32(events);
1384
1385 assert(d->ssd.running);
1386 old_pending = __sync_fetch_and_or(&d->ram->int_pending, le_events);
1387 if ((old_pending & le_events) == le_events) {
1388 return;
1389 }
1390 if (qemu_thread_is_self(&d->main)) {
1391 qxl_update_irq(d);
1392 } else {
1393 if (write(d->pipe[1], d, 1) != 1) {
1394 dprint(d, 1, "%s: write to pipe failed\n", __FUNCTION__);
1395 }
1396 }
1397 }
1398
1399 static void init_pipe_signaling(PCIQXLDevice *d)
1400 {
1401 if (pipe(d->pipe) < 0) {
1402 dprint(d, 1, "%s: pipe creation failed\n", __FUNCTION__);
1403 return;
1404 }
1405 fcntl(d->pipe[0], F_SETFL, O_NONBLOCK);
1406 fcntl(d->pipe[1], F_SETFL, O_NONBLOCK);
1407 fcntl(d->pipe[0], F_SETOWN, getpid());
1408
1409 qemu_thread_get_self(&d->main);
1410 qemu_set_fd_handler(d->pipe[0], pipe_read, NULL, d);
1411 }
1412
1413 /* graphics console */
1414
1415 static void qxl_hw_update(void *opaque)
1416 {
1417 PCIQXLDevice *qxl = opaque;
1418 VGACommonState *vga = &qxl->vga;
1419
1420 switch (qxl->mode) {
1421 case QXL_MODE_VGA:
1422 vga->update(vga);
1423 break;
1424 case QXL_MODE_COMPAT:
1425 case QXL_MODE_NATIVE:
1426 qxl_render_update(qxl);
1427 break;
1428 default:
1429 break;
1430 }
1431 }
1432
1433 static void qxl_hw_invalidate(void *opaque)
1434 {
1435 PCIQXLDevice *qxl = opaque;
1436 VGACommonState *vga = &qxl->vga;
1437
1438 vga->invalidate(vga);
1439 }
1440
1441 static void qxl_hw_screen_dump(void *opaque, const char *filename)
1442 {
1443 PCIQXLDevice *qxl = opaque;
1444 VGACommonState *vga = &qxl->vga;
1445
1446 switch (qxl->mode) {
1447 case QXL_MODE_COMPAT:
1448 case QXL_MODE_NATIVE:
1449 qxl_render_update(qxl);
1450 ppm_save(filename, qxl->ssd.ds->surface);
1451 break;
1452 case QXL_MODE_VGA:
1453 vga->screen_dump(vga, filename);
1454 break;
1455 default:
1456 break;
1457 }
1458 }
1459
1460 static void qxl_hw_text_update(void *opaque, console_ch_t *chardata)
1461 {
1462 PCIQXLDevice *qxl = opaque;
1463 VGACommonState *vga = &qxl->vga;
1464
1465 if (qxl->mode == QXL_MODE_VGA) {
1466 vga->text_update(vga, chardata);
1467 return;
1468 }
1469 }
1470
1471 static void qxl_vm_change_state_handler(void *opaque, int running,
1472 RunState state)
1473 {
1474 PCIQXLDevice *qxl = opaque;
1475 qemu_spice_vm_change_state_handler(&qxl->ssd, running, state);
1476
1477 if (running) {
1478 /*
1479 * if qxl_send_events was called from spice server context before
1480 * migration ended, qxl_update_irq for these events might not have been
1481 * called
1482 */
1483 qxl_update_irq(qxl);
1484 } else if (qxl->mode == QXL_MODE_NATIVE) {
1485 /* dirty all vram (which holds surfaces) and devram (primary surface)
1486 * to make sure they are saved */
1487 /* FIXME #1: should go out during "live" stage */
1488 /* FIXME #2: we only need to save the areas which are actually used */
1489 qxl_set_dirty(&qxl->vram_bar, 0, qxl->vram_size);
1490 qxl_set_dirty(&qxl->vga.vram, qxl->shadow_rom.draw_area_offset,
1491 qxl->shadow_rom.surface0_area_size);
1492 }
1493 }
1494
1495 /* display change listener */
1496
1497 static void display_update(struct DisplayState *ds, int x, int y, int w, int h)
1498 {
1499 if (qxl0->mode == QXL_MODE_VGA) {
1500 qemu_spice_display_update(&qxl0->ssd, x, y, w, h);
1501 }
1502 }
1503
1504 static void display_resize(struct DisplayState *ds)
1505 {
1506 if (qxl0->mode == QXL_MODE_VGA) {
1507 qemu_spice_display_resize(&qxl0->ssd);
1508 }
1509 }
1510
1511 static void display_refresh(struct DisplayState *ds)
1512 {
1513 if (qxl0->mode == QXL_MODE_VGA) {
1514 qemu_spice_display_refresh(&qxl0->ssd);
1515 }
1516 }
1517
1518 static DisplayChangeListener display_listener = {
1519 .dpy_update = display_update,
1520 .dpy_resize = display_resize,
1521 .dpy_refresh = display_refresh,
1522 };
1523
1524 static int qxl_init_common(PCIQXLDevice *qxl)
1525 {
1526 uint8_t* config = qxl->pci.config;
1527 uint32_t pci_device_rev;
1528 uint32_t io_size;
1529
1530 qxl->mode = QXL_MODE_UNDEFINED;
1531 qxl->generation = 1;
1532 qxl->num_memslots = NUM_MEMSLOTS;
1533 qxl->num_surfaces = NUM_SURFACES;
1534 qemu_mutex_init(&qxl->track_lock);
1535 qemu_mutex_init(&qxl->async_lock);
1536 qxl->current_async = QXL_UNDEFINED_IO;
1537
1538 switch (qxl->revision) {
1539 case 1: /* spice 0.4 -- qxl-1 */
1540 pci_device_rev = QXL_REVISION_STABLE_V04;
1541 break;
1542 case 2: /* spice 0.6 -- qxl-2 */
1543 pci_device_rev = QXL_REVISION_STABLE_V06;
1544 break;
1545 #if SPICE_INTERFACE_QXL_MINOR >= 1
1546 case 3: /* qxl-3 */
1547 #endif
1548 default:
1549 pci_device_rev = QXL_DEFAULT_REVISION;
1550 break;
1551 }
1552
1553 pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev);
1554 pci_set_byte(&config[PCI_INTERRUPT_PIN], 1);
1555
1556 qxl->rom_size = qxl_rom_size();
1557 memory_region_init_ram(&qxl->rom_bar, &qxl->pci.qdev, "qxl.vrom",
1558 qxl->rom_size);
1559 init_qxl_rom(qxl);
1560 init_qxl_ram(qxl);
1561
1562 if (qxl->vram_size < 16 * 1024 * 1024) {
1563 qxl->vram_size = 16 * 1024 * 1024;
1564 }
1565 if (qxl->revision == 1) {
1566 qxl->vram_size = 4096;
1567 }
1568 qxl->vram_size = msb_mask(qxl->vram_size * 2 - 1);
1569 memory_region_init_ram(&qxl->vram_bar, &qxl->pci.qdev, "qxl.vram",
1570 qxl->vram_size);
1571
1572 io_size = msb_mask(QXL_IO_RANGE_SIZE * 2 - 1);
1573 if (qxl->revision == 1) {
1574 io_size = 8;
1575 }
1576
1577 memory_region_init_io(&qxl->io_bar, &qxl_io_ops, qxl,
1578 "qxl-ioports", io_size);
1579 if (qxl->id == 0) {
1580 vga_dirty_log_start(&qxl->vga);
1581 }
1582
1583
1584 pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX,
1585 PCI_BASE_ADDRESS_SPACE_IO, &qxl->io_bar);
1586
1587 pci_register_bar(&qxl->pci, QXL_ROM_RANGE_INDEX,
1588 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->rom_bar);
1589
1590 pci_register_bar(&qxl->pci, QXL_RAM_RANGE_INDEX,
1591 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vga.vram);
1592
1593 pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX,
1594 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vram_bar);
1595
1596 qxl->ssd.qxl.base.sif = &qxl_interface.base;
1597 qxl->ssd.qxl.id = qxl->id;
1598 qemu_spice_add_interface(&qxl->ssd.qxl.base);
1599 qemu_add_vm_change_state_handler(qxl_vm_change_state_handler, qxl);
1600
1601 init_pipe_signaling(qxl);
1602 qxl_reset_state(qxl);
1603
1604 return 0;
1605 }
1606
1607 static int qxl_init_primary(PCIDevice *dev)
1608 {
1609 PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev);
1610 VGACommonState *vga = &qxl->vga;
1611 ram_addr_t ram_size = msb_mask(qxl->vga.vram_size * 2 - 1);
1612 PortioList *qxl_vga_port_list = g_new(PortioList, 1);
1613
1614 qxl->id = 0;
1615
1616 if (ram_size < 32 * 1024 * 1024) {
1617 ram_size = 32 * 1024 * 1024;
1618 }
1619 vga_common_init(vga, ram_size);
1620 vga_init(vga, pci_address_space(dev), pci_address_space_io(dev), false);
1621 portio_list_init(qxl_vga_port_list, qxl_vga_portio_list, vga, "vga");
1622 portio_list_add(qxl_vga_port_list, pci_address_space_io(dev), 0x3b0);
1623
1624 vga->ds = graphic_console_init(qxl_hw_update, qxl_hw_invalidate,
1625 qxl_hw_screen_dump, qxl_hw_text_update, qxl);
1626 qemu_spice_display_init_common(&qxl->ssd, vga->ds);
1627
1628 qxl0 = qxl;
1629 register_displaychangelistener(vga->ds, &display_listener);
1630
1631 return qxl_init_common(qxl);
1632 }
1633
1634 static int qxl_init_secondary(PCIDevice *dev)
1635 {
1636 static int device_id = 1;
1637 PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev);
1638 ram_addr_t ram_size = msb_mask(qxl->vga.vram_size * 2 - 1);
1639
1640 qxl->id = device_id++;
1641
1642 if (ram_size < 16 * 1024 * 1024) {
1643 ram_size = 16 * 1024 * 1024;
1644 }
1645 qxl->vga.vram_size = ram_size;
1646 memory_region_init_ram(&qxl->vga.vram, &qxl->pci.qdev, "qxl.vgavram",
1647 qxl->vga.vram_size);
1648 qxl->vga.vram_ptr = memory_region_get_ram_ptr(&qxl->vga.vram);
1649
1650 return qxl_init_common(qxl);
1651 }
1652
1653 static void qxl_pre_save(void *opaque)
1654 {
1655 PCIQXLDevice* d = opaque;
1656 uint8_t *ram_start = d->vga.vram_ptr;
1657
1658 dprint(d, 1, "%s:\n", __FUNCTION__);
1659 if (d->last_release == NULL) {
1660 d->last_release_offset = 0;
1661 } else {
1662 d->last_release_offset = (uint8_t *)d->last_release - ram_start;
1663 }
1664 assert(d->last_release_offset < d->vga.vram_size);
1665 }
1666
1667 static int qxl_pre_load(void *opaque)
1668 {
1669 PCIQXLDevice* d = opaque;
1670
1671 dprint(d, 1, "%s: start\n", __FUNCTION__);
1672 qxl_hard_reset(d, 1);
1673 qxl_exit_vga_mode(d);
1674 dprint(d, 1, "%s: done\n", __FUNCTION__);
1675 return 0;
1676 }
1677
1678 static void qxl_create_memslots(PCIQXLDevice *d)
1679 {
1680 int i;
1681
1682 for (i = 0; i < NUM_MEMSLOTS; i++) {
1683 if (!d->guest_slots[i].active) {
1684 continue;
1685 }
1686 dprint(d, 1, "%s: restoring guest slot %d\n", __func__, i);
1687 qxl_add_memslot(d, i, 0, QXL_SYNC);
1688 }
1689 }
1690
1691 static int qxl_post_load(void *opaque, int version)
1692 {
1693 PCIQXLDevice* d = opaque;
1694 uint8_t *ram_start = d->vga.vram_ptr;
1695 QXLCommandExt *cmds;
1696 int in, out, newmode;
1697
1698 dprint(d, 1, "%s: start\n", __FUNCTION__);
1699
1700 assert(d->last_release_offset < d->vga.vram_size);
1701 if (d->last_release_offset == 0) {
1702 d->last_release = NULL;
1703 } else {
1704 d->last_release = (QXLReleaseInfo *)(ram_start + d->last_release_offset);
1705 }
1706
1707 d->modes = (QXLModes*)((uint8_t*)d->rom + d->rom->modes_offset);
1708
1709 dprint(d, 1, "%s: restore mode (%s)\n", __FUNCTION__,
1710 qxl_mode_to_string(d->mode));
1711 newmode = d->mode;
1712 d->mode = QXL_MODE_UNDEFINED;
1713
1714 switch (newmode) {
1715 case QXL_MODE_UNDEFINED:
1716 break;
1717 case QXL_MODE_VGA:
1718 qxl_create_memslots(d);
1719 qxl_enter_vga_mode(d);
1720 break;
1721 case QXL_MODE_NATIVE:
1722 qxl_create_memslots(d);
1723 qxl_create_guest_primary(d, 1, QXL_SYNC);
1724
1725 /* replay surface-create and cursor-set commands */
1726 cmds = g_malloc0(sizeof(QXLCommandExt) * (NUM_SURFACES + 1));
1727 for (in = 0, out = 0; in < NUM_SURFACES; in++) {
1728 if (d->guest_surfaces.cmds[in] == 0) {
1729 continue;
1730 }
1731 cmds[out].cmd.data = d->guest_surfaces.cmds[in];
1732 cmds[out].cmd.type = QXL_CMD_SURFACE;
1733 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
1734 out++;
1735 }
1736 if (d->guest_cursor) {
1737 cmds[out].cmd.data = d->guest_cursor;
1738 cmds[out].cmd.type = QXL_CMD_CURSOR;
1739 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
1740 out++;
1741 }
1742 qxl_spice_loadvm_commands(d, cmds, out);
1743 g_free(cmds);
1744
1745 break;
1746 case QXL_MODE_COMPAT:
1747 /* note: no need to call qxl_create_memslots, qxl_set_mode
1748 * creates the mem slot. */
1749 qxl_set_mode(d, d->shadow_rom.mode, 1);
1750 break;
1751 }
1752 dprint(d, 1, "%s: done\n", __FUNCTION__);
1753
1754 return 0;
1755 }
1756
1757 #define QXL_SAVE_VERSION 21
1758
1759 static VMStateDescription qxl_memslot = {
1760 .name = "qxl-memslot",
1761 .version_id = QXL_SAVE_VERSION,
1762 .minimum_version_id = QXL_SAVE_VERSION,
1763 .fields = (VMStateField[]) {
1764 VMSTATE_UINT64(slot.mem_start, struct guest_slots),
1765 VMSTATE_UINT64(slot.mem_end, struct guest_slots),
1766 VMSTATE_UINT32(active, struct guest_slots),
1767 VMSTATE_END_OF_LIST()
1768 }
1769 };
1770
1771 static VMStateDescription qxl_surface = {
1772 .name = "qxl-surface",
1773 .version_id = QXL_SAVE_VERSION,
1774 .minimum_version_id = QXL_SAVE_VERSION,
1775 .fields = (VMStateField[]) {
1776 VMSTATE_UINT32(width, QXLSurfaceCreate),
1777 VMSTATE_UINT32(height, QXLSurfaceCreate),
1778 VMSTATE_INT32(stride, QXLSurfaceCreate),
1779 VMSTATE_UINT32(format, QXLSurfaceCreate),
1780 VMSTATE_UINT32(position, QXLSurfaceCreate),
1781 VMSTATE_UINT32(mouse_mode, QXLSurfaceCreate),
1782 VMSTATE_UINT32(flags, QXLSurfaceCreate),
1783 VMSTATE_UINT32(type, QXLSurfaceCreate),
1784 VMSTATE_UINT64(mem, QXLSurfaceCreate),
1785 VMSTATE_END_OF_LIST()
1786 }
1787 };
1788
1789 static VMStateDescription qxl_vmstate = {
1790 .name = "qxl",
1791 .version_id = QXL_SAVE_VERSION,
1792 .minimum_version_id = QXL_SAVE_VERSION,
1793 .pre_save = qxl_pre_save,
1794 .pre_load = qxl_pre_load,
1795 .post_load = qxl_post_load,
1796 .fields = (VMStateField []) {
1797 VMSTATE_PCI_DEVICE(pci, PCIQXLDevice),
1798 VMSTATE_STRUCT(vga, PCIQXLDevice, 0, vmstate_vga_common, VGACommonState),
1799 VMSTATE_UINT32(shadow_rom.mode, PCIQXLDevice),
1800 VMSTATE_UINT32(num_free_res, PCIQXLDevice),
1801 VMSTATE_UINT32(last_release_offset, PCIQXLDevice),
1802 VMSTATE_UINT32(mode, PCIQXLDevice),
1803 VMSTATE_UINT32(ssd.unique, PCIQXLDevice),
1804 VMSTATE_INT32_EQUAL(num_memslots, PCIQXLDevice),
1805 VMSTATE_STRUCT_ARRAY(guest_slots, PCIQXLDevice, NUM_MEMSLOTS, 0,
1806 qxl_memslot, struct guest_slots),
1807 VMSTATE_STRUCT(guest_primary.surface, PCIQXLDevice, 0,
1808 qxl_surface, QXLSurfaceCreate),
1809 VMSTATE_INT32_EQUAL(num_surfaces, PCIQXLDevice),
1810 VMSTATE_ARRAY(guest_surfaces.cmds, PCIQXLDevice, NUM_SURFACES, 0,
1811 vmstate_info_uint64, uint64_t),
1812 VMSTATE_UINT64(guest_cursor, PCIQXLDevice),
1813 VMSTATE_END_OF_LIST()
1814 },
1815 };
1816
1817 static Property qxl_properties[] = {
1818 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size,
1819 64 * 1024 * 1024),
1820 DEFINE_PROP_UINT32("vram_size", PCIQXLDevice, vram_size,
1821 64 * 1024 * 1024),
1822 DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision,
1823 QXL_DEFAULT_REVISION),
1824 DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0),
1825 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0),
1826 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0),
1827 DEFINE_PROP_END_OF_LIST(),
1828 };
1829
1830 static PCIDeviceInfo qxl_info_primary = {
1831 .qdev.name = "qxl-vga",
1832 .qdev.desc = "Spice QXL GPU (primary, vga compatible)",
1833 .qdev.size = sizeof(PCIQXLDevice),
1834 .qdev.reset = qxl_reset_handler,
1835 .qdev.vmsd = &qxl_vmstate,
1836 .no_hotplug = 1,
1837 .init = qxl_init_primary,
1838 .romfile = "vgabios-qxl.bin",
1839 .vendor_id = REDHAT_PCI_VENDOR_ID,
1840 .device_id = QXL_DEVICE_ID_STABLE,
1841 .class_id = PCI_CLASS_DISPLAY_VGA,
1842 .qdev.props = qxl_properties,
1843 };
1844
1845 static PCIDeviceInfo qxl_info_secondary = {
1846 .qdev.name = "qxl",
1847 .qdev.desc = "Spice QXL GPU (secondary)",
1848 .qdev.size = sizeof(PCIQXLDevice),
1849 .qdev.reset = qxl_reset_handler,
1850 .qdev.vmsd = &qxl_vmstate,
1851 .init = qxl_init_secondary,
1852 .vendor_id = REDHAT_PCI_VENDOR_ID,
1853 .device_id = QXL_DEVICE_ID_STABLE,
1854 .class_id = PCI_CLASS_DISPLAY_OTHER,
1855 .qdev.props = qxl_properties,
1856 };
1857
1858 static void qxl_register(void)
1859 {
1860 pci_qdev_register(&qxl_info_primary);
1861 pci_qdev_register(&qxl_info_secondary);
1862 }
1863
1864 device_init(qxl_register);
QEmu