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e1000: bounds packet size against buffer size
[qemu.git] / hw / eepro100.c
blob29ec5b44f8d16b97fc07a7095733a84d63344ff1
1 /*
2 * QEMU i8255x (PRO100) emulation
3 *
4 * Copyright (C) 2006-2011 Stefan Weil
5 *
6 * Portions of the code are copies from grub / etherboot eepro100.c
7 * and linux e100.c.
8 *
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation, either version 2 of the License, or
12 * (at your option) version 3 or any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 *
22 * Tested features (i82559):
23 * PXE boot (i386 guest, i386 / mips / mipsel / ppc host) ok
24 * Linux networking (i386) ok
25 *
26 * Untested:
27 * Windows networking
28 *
29 * References:
30 *
31 * Intel 8255x 10/100 Mbps Ethernet Controller Family
32 * Open Source Software Developer Manual
33 *
34 * TODO:
35 * * PHY emulation should be separated from nic emulation.
36 * Most nic emulations could share the same phy code.
37 * * i82550 is untested. It is programmed like the i82559.
38 * * i82562 is untested. It is programmed like the i82559.
39 * * Power management (i82558 and later) is not implemented.
40 * * Wake-on-LAN is not implemented.
41 */
42
43 #include <stddef.h> /* offsetof */
44 #include "hw.h"
45 #include "pci.h"
46 #include "net.h"
47 #include "eeprom93xx.h"
48 #include "sysemu.h"
49 #include "dma.h"
50
51 /* QEMU sends frames smaller than 60 bytes to ethernet nics.
52 * Such frames are rejected by real nics and their emulations.
53 * To avoid this behaviour, other nic emulations pad received
54 * frames. The following definition enables this padding for
55 * eepro100, too. We keep the define around in case it might
56 * become useful the future if the core networking is ever
57 * changed to pad short packets itself. */
58 #define CONFIG_PAD_RECEIVED_FRAMES
59
60 #define KiB 1024
61
62 /* Debug EEPRO100 card. */
63 #if 0
64 # define DEBUG_EEPRO100
65 #endif
66
67 #ifdef DEBUG_EEPRO100
68 #define logout(fmt, ...) fprintf(stderr, "EE100\t%-24s" fmt, __func__, ## __VA_ARGS__)
69 #else
70 #define logout(fmt, ...) ((void)0)
71 #endif
72
73 /* Set flags to 0 to disable debug output. */
74 #define INT 1 /* interrupt related actions */
75 #define MDI 1 /* mdi related actions */
76 #define OTHER 1
77 #define RXTX 1
78 #define EEPROM 1 /* eeprom related actions */
79
80 #define TRACE(flag, command) ((flag) ? (command) : (void)0)
81
82 #define missing(text) fprintf(stderr, "eepro100: feature is missing in this emulation: " text "\n")
83
84 #define MAX_ETH_FRAME_SIZE 1514
85
86 /* This driver supports several different devices which are declared here. */
87 #define i82550 0x82550
88 #define i82551 0x82551
89 #define i82557A 0x82557a
90 #define i82557B 0x82557b
91 #define i82557C 0x82557c
92 #define i82558A 0x82558a
93 #define i82558B 0x82558b
94 #define i82559A 0x82559a
95 #define i82559B 0x82559b
96 #define i82559C 0x82559c
97 #define i82559ER 0x82559e
98 #define i82562 0x82562
99 #define i82801 0x82801
100
101 /* Use 64 word EEPROM. TODO: could be a runtime option. */
102 #define EEPROM_SIZE 64
103
104 #define PCI_MEM_SIZE (4 * KiB)
105 #define PCI_IO_SIZE 64
106 #define PCI_FLASH_SIZE (128 * KiB)
107
108 #define BIT(n) (1 << (n))
109 #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
110
111 /* The SCB accepts the following controls for the Tx and Rx units: */
112 #define CU_NOP 0x0000 /* No operation. */
113 #define CU_START 0x0010 /* CU start. */
114 #define CU_RESUME 0x0020 /* CU resume. */
115 #define CU_STATSADDR 0x0040 /* Load dump counters address. */
116 #define CU_SHOWSTATS 0x0050 /* Dump statistical counters. */
117 #define CU_CMD_BASE 0x0060 /* Load CU base address. */
118 #define CU_DUMPSTATS 0x0070 /* Dump and reset statistical counters. */
119 #define CU_SRESUME 0x00a0 /* CU static resume. */
120
121 #define RU_NOP 0x0000
122 #define RX_START 0x0001
123 #define RX_RESUME 0x0002
124 #define RU_ABORT 0x0004
125 #define RX_ADDR_LOAD 0x0006
126 #define RX_RESUMENR 0x0007
127 #define INT_MASK 0x0100
128 #define DRVR_INT 0x0200 /* Driver generated interrupt. */
129
130 typedef struct {
131 PCIDeviceInfo pci;
132 uint32_t device;
133 uint8_t stats_size;
134 bool has_extended_tcb_support;
135 bool power_management;
136 } E100PCIDeviceInfo;
137
138 /* Offsets to the various registers.
139 All accesses need not be longword aligned. */
140 typedef enum {
141 SCBStatus = 0, /* Status Word. */
142 SCBAck = 1,
143 SCBCmd = 2, /* Rx/Command Unit command and status. */
144 SCBIntmask = 3,
145 SCBPointer = 4, /* General purpose pointer. */
146 SCBPort = 8, /* Misc. commands and operands. */
147 SCBflash = 12, /* Flash memory control. */
148 SCBeeprom = 14, /* EEPROM control. */
149 SCBCtrlMDI = 16, /* MDI interface control. */
150 SCBEarlyRx = 20, /* Early receive byte count. */
151 SCBFlow = 24, /* Flow Control. */
152 SCBpmdr = 27, /* Power Management Driver. */
153 SCBgctrl = 28, /* General Control. */
154 SCBgstat = 29, /* General Status. */
155 } E100RegisterOffset;
156
157 /* A speedo3 transmit buffer descriptor with two buffers... */
158 typedef struct {
159 uint16_t status;
160 uint16_t command;
161 uint32_t link; /* void * */
162 uint32_t tbd_array_addr; /* transmit buffer descriptor array address. */
163 uint16_t tcb_bytes; /* transmit command block byte count (in lower 14 bits */
164 uint8_t tx_threshold; /* transmit threshold */
165 uint8_t tbd_count; /* TBD number */
166 #if 0
167 /* This constitutes two "TBD" entries: hdr and data */
168 uint32_t tx_buf_addr0; /* void *, header of frame to be transmitted. */
169 int32_t tx_buf_size0; /* Length of Tx hdr. */
170 uint32_t tx_buf_addr1; /* void *, data to be transmitted. */
171 int32_t tx_buf_size1; /* Length of Tx data. */
172 #endif
173 } eepro100_tx_t;
174
175 /* Receive frame descriptor. */
176 typedef struct {
177 int16_t status;
178 uint16_t command;
179 uint32_t link; /* struct RxFD * */
180 uint32_t rx_buf_addr; /* void * */
181 uint16_t count;
182 uint16_t size;
183 /* Ethernet frame data follows. */
184 } eepro100_rx_t;
185
186 typedef enum {
187 COMMAND_EL = BIT(15),
188 COMMAND_S = BIT(14),
189 COMMAND_I = BIT(13),
190 COMMAND_NC = BIT(4),
191 COMMAND_SF = BIT(3),
192 COMMAND_CMD = BITS(2, 0),
193 } scb_command_bit;
194
195 typedef enum {
196 STATUS_C = BIT(15),
197 STATUS_OK = BIT(13),
198 } scb_status_bit;
199
200 typedef struct {
201 uint32_t tx_good_frames, tx_max_collisions, tx_late_collisions,
202 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
203 tx_multiple_collisions, tx_total_collisions;
204 uint32_t rx_good_frames, rx_crc_errors, rx_alignment_errors,
205 rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
206 rx_short_frame_errors;
207 uint32_t fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
208 uint16_t xmt_tco_frames, rcv_tco_frames;
209 /* TODO: i82559 has six reserved statistics but a total of 24 dwords. */
210 uint32_t reserved[4];
211 } eepro100_stats_t;
212
213 typedef enum {
214 cu_idle = 0,
215 cu_suspended = 1,
216 cu_active = 2,
217 cu_lpq_active = 2,
218 cu_hqp_active = 3
219 } cu_state_t;
220
221 typedef enum {
222 ru_idle = 0,
223 ru_suspended = 1,
224 ru_no_resources = 2,
225 ru_ready = 4
226 } ru_state_t;
227
228 typedef struct {
229 PCIDevice dev;
230 /* Hash register (multicast mask array, multiple individual addresses). */
231 uint8_t mult[8];
232 MemoryRegion mmio_bar;
233 MemoryRegion io_bar;
234 MemoryRegion flash_bar;
235 NICState *nic;
236 NICConf conf;
237 uint8_t scb_stat; /* SCB stat/ack byte */
238 uint8_t int_stat; /* PCI interrupt status */
239 /* region must not be saved by nic_save. */
240 uint16_t mdimem[32];
241 eeprom_t *eeprom;
242 uint32_t device; /* device variant */
243 /* (cu_base + cu_offset) address the next command block in the command block list. */
244 uint32_t cu_base; /* CU base address */
245 uint32_t cu_offset; /* CU address offset */
246 /* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */
247 uint32_t ru_base; /* RU base address */
248 uint32_t ru_offset; /* RU address offset */
249 uint32_t statsaddr; /* pointer to eepro100_stats_t */
250
251 /* Temporary status information (no need to save these values),
252 * used while processing CU commands. */
253 eepro100_tx_t tx; /* transmit buffer descriptor */
254 uint32_t cb_address; /* = cu_base + cu_offset */
255
256 /* Statistical counters. Also used for wake-up packet (i82559). */
257 eepro100_stats_t statistics;
258
259 /* Data in mem is always in the byte order of the controller (le).
260 * It must be dword aligned to allow direct access to 32 bit values. */
261 uint8_t mem[PCI_MEM_SIZE] __attribute__((aligned(8)));;
262
263 /* Configuration bytes. */
264 uint8_t configuration[22];
265
266 /* vmstate for each particular nic */
267 VMStateDescription *vmstate;
268
269 /* Quasi static device properties (no need to save them). */
270 uint16_t stats_size;
271 bool has_extended_tcb_support;
272 } EEPRO100State;
273
274 /* Word indices in EEPROM. */
275 typedef enum {
276 EEPROM_CNFG_MDIX = 0x03,
277 EEPROM_ID = 0x05,
278 EEPROM_PHY_ID = 0x06,
279 EEPROM_VENDOR_ID = 0x0c,
280 EEPROM_CONFIG_ASF = 0x0d,
281 EEPROM_DEVICE_ID = 0x23,
282 EEPROM_SMBUS_ADDR = 0x90,
283 } EEPROMOffset;
284
285 /* Bit values for EEPROM ID word. */
286 typedef enum {
287 EEPROM_ID_MDM = BIT(0), /* Modem */
288 EEPROM_ID_STB = BIT(1), /* Standby Enable */
289 EEPROM_ID_WMR = BIT(2), /* ??? */
290 EEPROM_ID_WOL = BIT(5), /* Wake on LAN */
291 EEPROM_ID_DPD = BIT(6), /* Deep Power Down */
292 EEPROM_ID_ALT = BIT(7), /* */
293 /* BITS(10, 8) device revision */
294 EEPROM_ID_BD = BIT(11), /* boot disable */
295 EEPROM_ID_ID = BIT(13), /* id bit */
296 /* BITS(15, 14) signature */
297 EEPROM_ID_VALID = BIT(14), /* signature for valid eeprom */
298 } eeprom_id_bit;
299
300 /* Default values for MDI (PHY) registers */
301 static const uint16_t eepro100_mdi_default[] = {
302 /* MDI Registers 0 - 6, 7 */
303 0x3000, 0x780d, 0x02a8, 0x0154, 0x05e1, 0x0000, 0x0000, 0x0000,
304 /* MDI Registers 8 - 15 */
305 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
306 /* MDI Registers 16 - 31 */
307 0x0003, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
308 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
309 };
310
311 /* Readonly mask for MDI (PHY) registers */
312 static const uint16_t eepro100_mdi_mask[] = {
313 0x0000, 0xffff, 0xffff, 0xffff, 0xc01f, 0xffff, 0xffff, 0x0000,
314 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
315 0x0fff, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
316 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
317 };
318
319 #define POLYNOMIAL 0x04c11db6
320
321 /* From FreeBSD */
322 /* XXX: optimize */
323 static unsigned compute_mcast_idx(const uint8_t * ep)
324 {
325 uint32_t crc;
326 int carry, i, j;
327 uint8_t b;
328
329 crc = 0xffffffff;
330 for (i = 0; i < 6; i++) {
331 b = *ep++;
332 for (j = 0; j < 8; j++) {
333 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
334 crc <<= 1;
335 b >>= 1;
336 if (carry) {
337 crc = ((crc ^ POLYNOMIAL) | carry);
338 }
339 }
340 }
341 return (crc & BITS(7, 2)) >> 2;
342 }
343
344 /* Read a 16 bit control/status (CSR) register. */
345 static uint16_t e100_read_reg2(EEPRO100State *s, E100RegisterOffset addr)
346 {
347 assert(!((uintptr_t)&s->mem[addr] & 1));
348 return le16_to_cpup((uint16_t *)&s->mem[addr]);
349 }
350
351 /* Read a 32 bit control/status (CSR) register. */
352 static uint32_t e100_read_reg4(EEPRO100State *s, E100RegisterOffset addr)
353 {
354 assert(!((uintptr_t)&s->mem[addr] & 3));
355 return le32_to_cpup((uint32_t *)&s->mem[addr]);
356 }
357
358 /* Write a 16 bit control/status (CSR) register. */
359 static void e100_write_reg2(EEPRO100State *s, E100RegisterOffset addr,
360 uint16_t val)
361 {
362 assert(!((uintptr_t)&s->mem[addr] & 1));
363 cpu_to_le16w((uint16_t *)&s->mem[addr], val);
364 }
365
366 /* Read a 32 bit control/status (CSR) register. */
367 static void e100_write_reg4(EEPRO100State *s, E100RegisterOffset addr,
368 uint32_t val)
369 {
370 assert(!((uintptr_t)&s->mem[addr] & 3));
371 cpu_to_le32w((uint32_t *)&s->mem[addr], val);
372 }
373
374 #if defined(DEBUG_EEPRO100)
375 static const char *nic_dump(const uint8_t * buf, unsigned size)
376 {
377 static char dump[3 * 16 + 1];
378 char *p = &dump[0];
379 if (size > 16) {
380 size = 16;
381 }
382 while (size-- > 0) {
383 p += sprintf(p, " %02x", *buf++);
384 }
385 return dump;
386 }
387 #endif /* DEBUG_EEPRO100 */
388
389 enum scb_stat_ack {
390 stat_ack_not_ours = 0x00,
391 stat_ack_sw_gen = 0x04,
392 stat_ack_rnr = 0x10,
393 stat_ack_cu_idle = 0x20,
394 stat_ack_frame_rx = 0x40,
395 stat_ack_cu_cmd_done = 0x80,
396 stat_ack_not_present = 0xFF,
397 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
398 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
399 };
400
401 static void disable_interrupt(EEPRO100State * s)
402 {
403 if (s->int_stat) {
404 TRACE(INT, logout("interrupt disabled\n"));
405 qemu_irq_lower(s->dev.irq[0]);
406 s->int_stat = 0;
407 }
408 }
409
410 static void enable_interrupt(EEPRO100State * s)
411 {
412 if (!s->int_stat) {
413 TRACE(INT, logout("interrupt enabled\n"));
414 qemu_irq_raise(s->dev.irq[0]);
415 s->int_stat = 1;
416 }
417 }
418
419 static void eepro100_acknowledge(EEPRO100State * s)
420 {
421 s->scb_stat &= ~s->mem[SCBAck];
422 s->mem[SCBAck] = s->scb_stat;
423 if (s->scb_stat == 0) {
424 disable_interrupt(s);
425 }
426 }
427
428 static void eepro100_interrupt(EEPRO100State * s, uint8_t status)
429 {
430 uint8_t mask = ~s->mem[SCBIntmask];
431 s->mem[SCBAck] |= status;
432 status = s->scb_stat = s->mem[SCBAck];
433 status &= (mask | 0x0f);
434 #if 0
435 status &= (~s->mem[SCBIntmask] | 0x0xf);
436 #endif
437 if (status && (mask & 0x01)) {
438 /* SCB mask and SCB Bit M do not disable interrupt. */
439 enable_interrupt(s);
440 } else if (s->int_stat) {
441 disable_interrupt(s);
442 }
443 }
444
445 static void eepro100_cx_interrupt(EEPRO100State * s)
446 {
447 /* CU completed action command. */
448 /* Transmit not ok (82557 only, not in emulation). */
449 eepro100_interrupt(s, 0x80);
450 }
451
452 static void eepro100_cna_interrupt(EEPRO100State * s)
453 {
454 /* CU left the active state. */
455 eepro100_interrupt(s, 0x20);
456 }
457
458 static void eepro100_fr_interrupt(EEPRO100State * s)
459 {
460 /* RU received a complete frame. */
461 eepro100_interrupt(s, 0x40);
462 }
463
464 static void eepro100_rnr_interrupt(EEPRO100State * s)
465 {
466 /* RU is not ready. */
467 eepro100_interrupt(s, 0x10);
468 }
469
470 static void eepro100_mdi_interrupt(EEPRO100State * s)
471 {
472 /* MDI completed read or write cycle. */
473 eepro100_interrupt(s, 0x08);
474 }
475
476 static void eepro100_swi_interrupt(EEPRO100State * s)
477 {
478 /* Software has requested an interrupt. */
479 eepro100_interrupt(s, 0x04);
480 }
481
482 #if 0
483 static void eepro100_fcp_interrupt(EEPRO100State * s)
484 {
485 /* Flow control pause interrupt (82558 and later). */
486 eepro100_interrupt(s, 0x01);
487 }
488 #endif
489
490 static void e100_pci_reset(EEPRO100State * s, E100PCIDeviceInfo *e100_device)
491 {
492 uint32_t device = s->device;
493 uint8_t *pci_conf = s->dev.config;
494
495 TRACE(OTHER, logout("%p\n", s));
496
497 /* PCI Status */
498 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
499 PCI_STATUS_FAST_BACK);
500 /* PCI Latency Timer */
501 pci_set_byte(pci_conf + PCI_LATENCY_TIMER, 0x20); /* latency timer = 32 clocks */
502 /* Capability Pointer is set by PCI framework. */
503 /* Interrupt Line */
504 /* Interrupt Pin */
505 pci_set_byte(pci_conf + PCI_INTERRUPT_PIN, 1); /* interrupt pin A */
506 /* Minimum Grant */
507 pci_set_byte(pci_conf + PCI_MIN_GNT, 0x08);
508 /* Maximum Latency */
509 pci_set_byte(pci_conf + PCI_MAX_LAT, 0x18);
510
511 s->stats_size = e100_device->stats_size;
512 s->has_extended_tcb_support = e100_device->has_extended_tcb_support;
513
514 switch (device) {
515 case i82550:
516 case i82551:
517 case i82557A:
518 case i82557B:
519 case i82557C:
520 case i82558A:
521 case i82558B:
522 case i82559A:
523 case i82559B:
524 case i82559ER:
525 case i82562:
526 case i82801:
527 case i82559C:
528 break;
529 default:
530 logout("Device %X is undefined!\n", device);
531 }
532
533 /* Standard TxCB. */
534 s->configuration[6] |= BIT(4);
535
536 /* Standard statistical counters. */
537 s->configuration[6] |= BIT(5);
538
539 if (s->stats_size == 80) {
540 /* TODO: check TCO Statistical Counters bit. Documentation not clear. */
541 if (s->configuration[6] & BIT(2)) {
542 /* TCO statistical counters. */
543 assert(s->configuration[6] & BIT(5));
544 } else {
545 if (s->configuration[6] & BIT(5)) {
546 /* No extended statistical counters, i82557 compatible. */
547 s->stats_size = 64;
548 } else {
549 /* i82558 compatible. */
550 s->stats_size = 76;
551 }
552 }
553 } else {
554 if (s->configuration[6] & BIT(5)) {
555 /* No extended statistical counters. */
556 s->stats_size = 64;
557 }
558 }
559 assert(s->stats_size > 0 && s->stats_size <= sizeof(s->statistics));
560
561 if (e100_device->power_management) {
562 /* Power Management Capabilities */
563 int cfg_offset = 0xdc;
564 int r = pci_add_capability(&s->dev, PCI_CAP_ID_PM,
565 cfg_offset, PCI_PM_SIZEOF);
566 assert(r >= 0);
567 pci_set_word(pci_conf + cfg_offset + PCI_PM_PMC, 0x7e21);
568 #if 0 /* TODO: replace dummy code for power management emulation. */
569 /* TODO: Power Management Control / Status. */
570 pci_set_word(pci_conf + cfg_offset + PCI_PM_CTRL, 0x0000);
571 /* TODO: Ethernet Power Consumption Registers (i82559 and later). */
572 pci_set_byte(pci_conf + cfg_offset + PCI_PM_PPB_EXTENSIONS, 0x0000);
573 #endif
574 }
575
576 #if EEPROM_SIZE > 0
577 if (device == i82557C || device == i82558B || device == i82559C) {
578 /*
579 TODO: get vendor id from EEPROM for i82557C or later.
580 TODO: get device id from EEPROM for i82557C or later.
581 TODO: status bit 4 can be disabled by EEPROM for i82558, i82559.
582 TODO: header type is determined by EEPROM for i82559.
583 TODO: get subsystem id from EEPROM for i82557C or later.
584 TODO: get subsystem vendor id from EEPROM for i82557C or later.
585 TODO: exp. rom baddr depends on a bit in EEPROM for i82558 or later.
586 TODO: capability pointer depends on EEPROM for i82558.
587 */
588 logout("Get device id and revision from EEPROM!!!\n");
589 }
590 #endif /* EEPROM_SIZE > 0 */
591 }
592
593 static void nic_selective_reset(EEPRO100State * s)
594 {
595 size_t i;
596 uint16_t *eeprom_contents = eeprom93xx_data(s->eeprom);
597 #if 0
598 eeprom93xx_reset(s->eeprom);
599 #endif
600 memcpy(eeprom_contents, s->conf.macaddr.a, 6);
601 eeprom_contents[EEPROM_ID] = EEPROM_ID_VALID;
602 if (s->device == i82557B || s->device == i82557C)
603 eeprom_contents[5] = 0x0100;
604 eeprom_contents[EEPROM_PHY_ID] = 1;
605 uint16_t sum = 0;
606 for (i = 0; i < EEPROM_SIZE - 1; i++) {
607 sum += eeprom_contents[i];
608 }
609 eeprom_contents[EEPROM_SIZE - 1] = 0xbaba - sum;
610 TRACE(EEPROM, logout("checksum=0x%04x\n", eeprom_contents[EEPROM_SIZE - 1]));
611
612 memset(s->mem, 0, sizeof(s->mem));
613 e100_write_reg4(s, SCBCtrlMDI, BIT(21));
614
615 assert(sizeof(s->mdimem) == sizeof(eepro100_mdi_default));
616 memcpy(&s->mdimem[0], &eepro100_mdi_default[0], sizeof(s->mdimem));
617 }
618
619 static void nic_reset(void *opaque)
620 {
621 EEPRO100State *s = opaque;
622 TRACE(OTHER, logout("%p\n", s));
623 /* TODO: Clearing of hash register for selective reset, too? */
624 memset(&s->mult[0], 0, sizeof(s->mult));
625 nic_selective_reset(s);
626 }
627
628 #if defined(DEBUG_EEPRO100)
629 static const char * const e100_reg[PCI_IO_SIZE / 4] = {
630 "Command/Status",
631 "General Pointer",
632 "Port",
633 "EEPROM/Flash Control",
634 "MDI Control",
635 "Receive DMA Byte Count",
636 "Flow Control",
637 "General Status/Control"
638 };
639
640 static char *regname(uint32_t addr)
641 {
642 static char buf[32];
643 if (addr < PCI_IO_SIZE) {
644 const char *r = e100_reg[addr / 4];
645 if (r != 0) {
646 snprintf(buf, sizeof(buf), "%s+%u", r, addr % 4);
647 } else {
648 snprintf(buf, sizeof(buf), "0x%02x", addr);
649 }
650 } else {
651 snprintf(buf, sizeof(buf), "??? 0x%08x", addr);
652 }
653 return buf;
654 }
655 #endif /* DEBUG_EEPRO100 */
656
657 /*****************************************************************************
658 *
659 * Command emulation.
660 *
661 ****************************************************************************/
662
663 #if 0
664 static uint16_t eepro100_read_command(EEPRO100State * s)
665 {
666 uint16_t val = 0xffff;
667 TRACE(OTHER, logout("val=0x%04x\n", val));
668 return val;
669 }
670 #endif
671
672 /* Commands that can be put in a command list entry. */
673 enum commands {
674 CmdNOp = 0,
675 CmdIASetup = 1,
676 CmdConfigure = 2,
677 CmdMulticastList = 3,
678 CmdTx = 4,
679 CmdTDR = 5, /* load microcode */
680 CmdDump = 6,
681 CmdDiagnose = 7,
682
683 /* And some extra flags: */
684 CmdSuspend = 0x4000, /* Suspend after completion. */
685 CmdIntr = 0x2000, /* Interrupt after completion. */
686 CmdTxFlex = 0x0008, /* Use "Flexible mode" for CmdTx command. */
687 };
688
689 static cu_state_t get_cu_state(EEPRO100State * s)
690 {
691 return ((s->mem[SCBStatus] & BITS(7, 6)) >> 6);
692 }
693
694 static void set_cu_state(EEPRO100State * s, cu_state_t state)
695 {
696 s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(7, 6)) + (state << 6);
697 }
698
699 static ru_state_t get_ru_state(EEPRO100State * s)
700 {
701 return ((s->mem[SCBStatus] & BITS(5, 2)) >> 2);
702 }
703
704 static void set_ru_state(EEPRO100State * s, ru_state_t state)
705 {
706 s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(5, 2)) + (state << 2);
707 }
708
709 static void dump_statistics(EEPRO100State * s)
710 {
711 /* Dump statistical data. Most data is never changed by the emulation
712 * and always 0, so we first just copy the whole block and then those
713 * values which really matter.
714 * Number of data should check configuration!!!
715 */
716 pci_dma_write(&s->dev, s->statsaddr,
717 (uint8_t *) &s->statistics, s->stats_size);
718 stl_le_pci_dma(&s->dev, s->statsaddr + 0,
719 s->statistics.tx_good_frames);
720 stl_le_pci_dma(&s->dev, s->statsaddr + 36,
721 s->statistics.rx_good_frames);
722 stl_le_pci_dma(&s->dev, s->statsaddr + 48,
723 s->statistics.rx_resource_errors);
724 stl_le_pci_dma(&s->dev, s->statsaddr + 60,
725 s->statistics.rx_short_frame_errors);
726 #if 0
727 stw_le_pci_dma(&s->dev, s->statsaddr + 76, s->statistics.xmt_tco_frames);
728 stw_le_pci_dma(&s->dev, s->statsaddr + 78, s->statistics.rcv_tco_frames);
729 missing("CU dump statistical counters");
730 #endif
731 }
732
733 static void read_cb(EEPRO100State *s)
734 {
735 pci_dma_read(&s->dev, s->cb_address, (uint8_t *) &s->tx, sizeof(s->tx));
736 s->tx.status = le16_to_cpu(s->tx.status);
737 s->tx.command = le16_to_cpu(s->tx.command);
738 s->tx.link = le32_to_cpu(s->tx.link);
739 s->tx.tbd_array_addr = le32_to_cpu(s->tx.tbd_array_addr);
740 s->tx.tcb_bytes = le16_to_cpu(s->tx.tcb_bytes);
741 }
742
743 static void tx_command(EEPRO100State *s)
744 {
745 uint32_t tbd_array = le32_to_cpu(s->tx.tbd_array_addr);
746 uint16_t tcb_bytes = (le16_to_cpu(s->tx.tcb_bytes) & 0x3fff);
747 /* Sends larger than MAX_ETH_FRAME_SIZE are allowed, up to 2600 bytes. */
748 uint8_t buf[2600];
749 uint16_t size = 0;
750 uint32_t tbd_address = s->cb_address + 0x10;
751 TRACE(RXTX, logout
752 ("transmit, TBD array address 0x%08x, TCB byte count 0x%04x, TBD count %u\n",
753 tbd_array, tcb_bytes, s->tx.tbd_count));
754
755 if (tcb_bytes > 2600) {
756 logout("TCB byte count too large, using 2600\n");
757 tcb_bytes = 2600;
758 }
759 if (!((tcb_bytes > 0) || (tbd_array != 0xffffffff))) {
760 logout
761 ("illegal values of TBD array address and TCB byte count!\n");
762 }
763 assert(tcb_bytes <= sizeof(buf));
764 while (size < tcb_bytes) {
765 uint32_t tx_buffer_address = ldl_le_pci_dma(&s->dev, tbd_address);
766 uint16_t tx_buffer_size = lduw_le_pci_dma(&s->dev, tbd_address + 4);
767 #if 0
768 uint16_t tx_buffer_el = lduw_le_pci_dma(&s->dev, tbd_address + 6);
769 #endif
770 tbd_address += 8;
771 TRACE(RXTX, logout
772 ("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n",
773 tx_buffer_address, tx_buffer_size));
774 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
775 pci_dma_read(&s->dev, tx_buffer_address, &buf[size], tx_buffer_size);
776 size += tx_buffer_size;
777 }
778 if (tbd_array == 0xffffffff) {
779 /* Simplified mode. Was already handled by code above. */
780 } else {
781 /* Flexible mode. */
782 uint8_t tbd_count = 0;
783 if (s->has_extended_tcb_support && !(s->configuration[6] & BIT(4))) {
784 /* Extended Flexible TCB. */
785 for (; tbd_count < 2; tbd_count++) {
786 uint32_t tx_buffer_address = ldl_le_pci_dma(&s->dev,
787 tbd_address);
788 uint16_t tx_buffer_size = lduw_le_pci_dma(&s->dev,
789 tbd_address + 4);
790 uint16_t tx_buffer_el = lduw_le_pci_dma(&s->dev,
791 tbd_address + 6);
792 tbd_address += 8;
793 TRACE(RXTX, logout
794 ("TBD (extended flexible mode): buffer address 0x%08x, size 0x%04x\n",
795 tx_buffer_address, tx_buffer_size));
796 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
797 pci_dma_read(&s->dev, tx_buffer_address,
798 &buf[size], tx_buffer_size);
799 size += tx_buffer_size;
800 if (tx_buffer_el & 1) {
801 break;
802 }
803 }
804 }
805 tbd_address = tbd_array;
806 for (; tbd_count < s->tx.tbd_count; tbd_count++) {
807 uint32_t tx_buffer_address = ldl_le_pci_dma(&s->dev, tbd_address);
808 uint16_t tx_buffer_size = lduw_le_pci_dma(&s->dev, tbd_address + 4);
809 uint16_t tx_buffer_el = lduw_le_pci_dma(&s->dev, tbd_address + 6);
810 tbd_address += 8;
811 TRACE(RXTX, logout
812 ("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n",
813 tx_buffer_address, tx_buffer_size));
814 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
815 pci_dma_read(&s->dev, tx_buffer_address,
816 &buf[size], tx_buffer_size);
817 size += tx_buffer_size;
818 if (tx_buffer_el & 1) {
819 break;
820 }
821 }
822 }
823 TRACE(RXTX, logout("%p sending frame, len=%d,%s\n", s, size, nic_dump(buf, size)));
824 qemu_send_packet(&s->nic->nc, buf, size);
825 s->statistics.tx_good_frames++;
826 /* Transmit with bad status would raise an CX/TNO interrupt.
827 * (82557 only). Emulation never has bad status. */
828 #if 0
829 eepro100_cx_interrupt(s);
830 #endif
831 }
832
833 static void set_multicast_list(EEPRO100State *s)
834 {
835 uint16_t multicast_count = s->tx.tbd_array_addr & BITS(13, 0);
836 uint16_t i;
837 memset(&s->mult[0], 0, sizeof(s->mult));
838 TRACE(OTHER, logout("multicast list, multicast count = %u\n", multicast_count));
839 for (i = 0; i < multicast_count; i += 6) {
840 uint8_t multicast_addr[6];
841 pci_dma_read(&s->dev, s->cb_address + 10 + i, multicast_addr, 6);
842 TRACE(OTHER, logout("multicast entry %s\n", nic_dump(multicast_addr, 6)));
843 unsigned mcast_idx = compute_mcast_idx(multicast_addr);
844 assert(mcast_idx < 64);
845 s->mult[mcast_idx >> 3] |= (1 << (mcast_idx & 7));
846 }
847 }
848
849 static void action_command(EEPRO100State *s)
850 {
851 for (;;) {
852 bool bit_el;
853 bool bit_s;
854 bool bit_i;
855 bool bit_nc;
856 uint16_t ok_status = STATUS_OK;
857 s->cb_address = s->cu_base + s->cu_offset;
858 read_cb(s);
859 bit_el = ((s->tx.command & COMMAND_EL) != 0);
860 bit_s = ((s->tx.command & COMMAND_S) != 0);
861 bit_i = ((s->tx.command & COMMAND_I) != 0);
862 bit_nc = ((s->tx.command & COMMAND_NC) != 0);
863 #if 0
864 bool bit_sf = ((s->tx.command & COMMAND_SF) != 0);
865 #endif
866 s->cu_offset = s->tx.link;
867 TRACE(OTHER,
868 logout("val=(cu start), status=0x%04x, command=0x%04x, link=0x%08x\n",
869 s->tx.status, s->tx.command, s->tx.link));
870 switch (s->tx.command & COMMAND_CMD) {
871 case CmdNOp:
872 /* Do nothing. */
873 break;
874 case CmdIASetup:
875 pci_dma_read(&s->dev, s->cb_address + 8, &s->conf.macaddr.a[0], 6);
876 TRACE(OTHER, logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6)));
877 break;
878 case CmdConfigure:
879 pci_dma_read(&s->dev, s->cb_address + 8,
880 &s->configuration[0], sizeof(s->configuration));
881 TRACE(OTHER, logout("configuration: %s\n",
882 nic_dump(&s->configuration[0], 16)));
883 TRACE(OTHER, logout("configuration: %s\n",
884 nic_dump(&s->configuration[16],
885 ARRAY_SIZE(s->configuration) - 16)));
886 if (s->configuration[20] & BIT(6)) {
887 TRACE(OTHER, logout("Multiple IA bit\n"));
888 }
889 break;
890 case CmdMulticastList:
891 set_multicast_list(s);
892 break;
893 case CmdTx:
894 if (bit_nc) {
895 missing("CmdTx: NC = 0");
896 ok_status = 0;
897 break;
898 }
899 tx_command(s);
900 break;
901 case CmdTDR:
902 TRACE(OTHER, logout("load microcode\n"));
903 /* Starting with offset 8, the command contains
904 * 64 dwords microcode which we just ignore here. */
905 break;
906 case CmdDiagnose:
907 TRACE(OTHER, logout("diagnose\n"));
908 /* Make sure error flag is not set. */
909 s->tx.status = 0;
910 break;
911 default:
912 missing("undefined command");
913 ok_status = 0;
914 break;
915 }
916 /* Write new status. */
917 stw_le_pci_dma(&s->dev, s->cb_address,
918 s->tx.status | ok_status | STATUS_C);
919 if (bit_i) {
920 /* CU completed action. */
921 eepro100_cx_interrupt(s);
922 }
923 if (bit_el) {
924 /* CU becomes idle. Terminate command loop. */
925 set_cu_state(s, cu_idle);
926 eepro100_cna_interrupt(s);
927 break;
928 } else if (bit_s) {
929 /* CU becomes suspended. Terminate command loop. */
930 set_cu_state(s, cu_suspended);
931 eepro100_cna_interrupt(s);
932 break;
933 } else {
934 /* More entries in list. */
935 TRACE(OTHER, logout("CU list with at least one more entry\n"));
936 }
937 }
938 TRACE(OTHER, logout("CU list empty\n"));
939 /* List is empty. Now CU is idle or suspended. */
940 }
941
942 static void eepro100_cu_command(EEPRO100State * s, uint8_t val)
943 {
944 cu_state_t cu_state;
945 switch (val) {
946 case CU_NOP:
947 /* No operation. */
948 break;
949 case CU_START:
950 cu_state = get_cu_state(s);
951 if (cu_state != cu_idle && cu_state != cu_suspended) {
952 /* Intel documentation says that CU must be idle or suspended
953 * for the CU start command. */
954 logout("unexpected CU state is %u\n", cu_state);
955 }
956 set_cu_state(s, cu_active);
957 s->cu_offset = e100_read_reg4(s, SCBPointer);
958 action_command(s);
959 break;
960 case CU_RESUME:
961 if (get_cu_state(s) != cu_suspended) {
962 logout("bad CU resume from CU state %u\n", get_cu_state(s));
963 /* Workaround for bad Linux eepro100 driver which resumes
964 * from idle state. */
965 #if 0
966 missing("cu resume");
967 #endif
968 set_cu_state(s, cu_suspended);
969 }
970 if (get_cu_state(s) == cu_suspended) {
971 TRACE(OTHER, logout("CU resuming\n"));
972 set_cu_state(s, cu_active);
973 action_command(s);
974 }
975 break;
976 case CU_STATSADDR:
977 /* Load dump counters address. */
978 s->statsaddr = e100_read_reg4(s, SCBPointer);
979 TRACE(OTHER, logout("val=0x%02x (dump counters address)\n", val));
980 if (s->statsaddr & 3) {
981 /* Memory must be Dword aligned. */
982 logout("unaligned dump counters address\n");
983 /* Handling of misaligned addresses is undefined.
984 * Here we align the address by ignoring the lower bits. */
985 /* TODO: Test unaligned dump counter address on real hardware. */
986 s->statsaddr &= ~3;
987 }
988 break;
989 case CU_SHOWSTATS:
990 /* Dump statistical counters. */
991 TRACE(OTHER, logout("val=0x%02x (dump stats)\n", val));
992 dump_statistics(s);
993 stl_le_pci_dma(&s->dev, s->statsaddr + s->stats_size, 0xa005);
994 break;
995 case CU_CMD_BASE:
996 /* Load CU base. */
997 TRACE(OTHER, logout("val=0x%02x (CU base address)\n", val));
998 s->cu_base = e100_read_reg4(s, SCBPointer);
999 break;
1000 case CU_DUMPSTATS:
1001 /* Dump and reset statistical counters. */
1002 TRACE(OTHER, logout("val=0x%02x (dump stats and reset)\n", val));
1003 dump_statistics(s);
1004 stl_le_pci_dma(&s->dev, s->statsaddr + s->stats_size, 0xa007);
1005 memset(&s->statistics, 0, sizeof(s->statistics));
1006 break;
1007 case CU_SRESUME:
1008 /* CU static resume. */
1009 missing("CU static resume");
1010 break;
1011 default:
1012 missing("Undefined CU command");
1013 }
1014 }
1015
1016 static void eepro100_ru_command(EEPRO100State * s, uint8_t val)
1017 {
1018 switch (val) {
1019 case RU_NOP:
1020 /* No operation. */
1021 break;
1022 case RX_START:
1023 /* RU start. */
1024 if (get_ru_state(s) != ru_idle) {
1025 logout("RU state is %u, should be %u\n", get_ru_state(s), ru_idle);
1026 #if 0
1027 assert(!"wrong RU state");
1028 #endif
1029 }
1030 set_ru_state(s, ru_ready);
1031 s->ru_offset = e100_read_reg4(s, SCBPointer);
1032 TRACE(OTHER, logout("val=0x%02x (rx start)\n", val));
1033 break;
1034 case RX_RESUME:
1035 /* Restart RU. */
1036 if (get_ru_state(s) != ru_suspended) {
1037 logout("RU state is %u, should be %u\n", get_ru_state(s),
1038 ru_suspended);
1039 #if 0
1040 assert(!"wrong RU state");
1041 #endif
1042 }
1043 set_ru_state(s, ru_ready);
1044 break;
1045 case RU_ABORT:
1046 /* RU abort. */
1047 if (get_ru_state(s) == ru_ready) {
1048 eepro100_rnr_interrupt(s);
1049 }
1050 set_ru_state(s, ru_idle);
1051 break;
1052 case RX_ADDR_LOAD:
1053 /* Load RU base. */
1054 TRACE(OTHER, logout("val=0x%02x (RU base address)\n", val));
1055 s->ru_base = e100_read_reg4(s, SCBPointer);
1056 break;
1057 default:
1058 logout("val=0x%02x (undefined RU command)\n", val);
1059 missing("Undefined SU command");
1060 }
1061 }
1062
1063 static void eepro100_write_command(EEPRO100State * s, uint8_t val)
1064 {
1065 eepro100_ru_command(s, val & 0x0f);
1066 eepro100_cu_command(s, val & 0xf0);
1067 if ((val) == 0) {
1068 TRACE(OTHER, logout("val=0x%02x\n", val));
1069 }
1070 /* Clear command byte after command was accepted. */
1071 s->mem[SCBCmd] = 0;
1072 }
1073
1074 /*****************************************************************************
1075 *
1076 * EEPROM emulation.
1077 *
1078 ****************************************************************************/
1079
1080 #define EEPROM_CS 0x02
1081 #define EEPROM_SK 0x01
1082 #define EEPROM_DI 0x04
1083 #define EEPROM_DO 0x08
1084
1085 static uint16_t eepro100_read_eeprom(EEPRO100State * s)
1086 {
1087 uint16_t val = e100_read_reg2(s, SCBeeprom);
1088 if (eeprom93xx_read(s->eeprom)) {
1089 val |= EEPROM_DO;
1090 } else {
1091 val &= ~EEPROM_DO;
1092 }
1093 TRACE(EEPROM, logout("val=0x%04x\n", val));
1094 return val;
1095 }
1096
1097 static void eepro100_write_eeprom(eeprom_t * eeprom, uint8_t val)
1098 {
1099 TRACE(EEPROM, logout("val=0x%02x\n", val));
1100
1101 /* mask unwritable bits */
1102 #if 0
1103 val = SET_MASKED(val, 0x31, eeprom->value);
1104 #endif
1105
1106 int eecs = ((val & EEPROM_CS) != 0);
1107 int eesk = ((val & EEPROM_SK) != 0);
1108 int eedi = ((val & EEPROM_DI) != 0);
1109 eeprom93xx_write(eeprom, eecs, eesk, eedi);
1110 }
1111
1112 /*****************************************************************************
1113 *
1114 * MDI emulation.
1115 *
1116 ****************************************************************************/
1117
1118 #if defined(DEBUG_EEPRO100)
1119 static const char * const mdi_op_name[] = {
1120 "opcode 0",
1121 "write",
1122 "read",
1123 "opcode 3"
1124 };
1125
1126 static const char * const mdi_reg_name[] = {
1127 "Control",
1128 "Status",
1129 "PHY Identification (Word 1)",
1130 "PHY Identification (Word 2)",
1131 "Auto-Negotiation Advertisement",
1132 "Auto-Negotiation Link Partner Ability",
1133 "Auto-Negotiation Expansion"
1134 };
1135
1136 static const char *reg2name(uint8_t reg)
1137 {
1138 static char buffer[10];
1139 const char *p = buffer;
1140 if (reg < ARRAY_SIZE(mdi_reg_name)) {
1141 p = mdi_reg_name[reg];
1142 } else {
1143 snprintf(buffer, sizeof(buffer), "reg=0x%02x", reg);
1144 }
1145 return p;
1146 }
1147 #endif /* DEBUG_EEPRO100 */
1148
1149 static uint32_t eepro100_read_mdi(EEPRO100State * s)
1150 {
1151 uint32_t val = e100_read_reg4(s, SCBCtrlMDI);
1152
1153 #ifdef DEBUG_EEPRO100
1154 uint8_t raiseint = (val & BIT(29)) >> 29;
1155 uint8_t opcode = (val & BITS(27, 26)) >> 26;
1156 uint8_t phy = (val & BITS(25, 21)) >> 21;
1157 uint8_t reg = (val & BITS(20, 16)) >> 16;
1158 uint16_t data = (val & BITS(15, 0));
1159 #endif
1160 /* Emulation takes no time to finish MDI transaction. */
1161 val |= BIT(28);
1162 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1163 val, raiseint, mdi_op_name[opcode], phy,
1164 reg2name(reg), data));
1165 return val;
1166 }
1167
1168 static void eepro100_write_mdi(EEPRO100State *s)
1169 {
1170 uint32_t val = e100_read_reg4(s, SCBCtrlMDI);
1171 uint8_t raiseint = (val & BIT(29)) >> 29;
1172 uint8_t opcode = (val & BITS(27, 26)) >> 26;
1173 uint8_t phy = (val & BITS(25, 21)) >> 21;
1174 uint8_t reg = (val & BITS(20, 16)) >> 16;
1175 uint16_t data = (val & BITS(15, 0));
1176 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1177 val, raiseint, mdi_op_name[opcode], phy, reg2name(reg), data));
1178 if (phy != 1) {
1179 /* Unsupported PHY address. */
1180 #if 0
1181 logout("phy must be 1 but is %u\n", phy);
1182 #endif
1183 data = 0;
1184 } else if (opcode != 1 && opcode != 2) {
1185 /* Unsupported opcode. */
1186 logout("opcode must be 1 or 2 but is %u\n", opcode);
1187 data = 0;
1188 } else if (reg > 6) {
1189 /* Unsupported register. */
1190 logout("register must be 0...6 but is %u\n", reg);
1191 data = 0;
1192 } else {
1193 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1194 val, raiseint, mdi_op_name[opcode], phy,
1195 reg2name(reg), data));
1196 if (opcode == 1) {
1197 /* MDI write */
1198 switch (reg) {
1199 case 0: /* Control Register */
1200 if (data & 0x8000) {
1201 /* Reset status and control registers to default. */
1202 s->mdimem[0] = eepro100_mdi_default[0];
1203 s->mdimem[1] = eepro100_mdi_default[1];
1204 data = s->mdimem[reg];
1205 } else {
1206 /* Restart Auto Configuration = Normal Operation */
1207 data &= ~0x0200;
1208 }
1209 break;
1210 case 1: /* Status Register */
1211 missing("not writable");
1212 data = s->mdimem[reg];
1213 break;
1214 case 2: /* PHY Identification Register (Word 1) */
1215 case 3: /* PHY Identification Register (Word 2) */
1216 missing("not implemented");
1217 break;
1218 case 4: /* Auto-Negotiation Advertisement Register */
1219 case 5: /* Auto-Negotiation Link Partner Ability Register */
1220 break;
1221 case 6: /* Auto-Negotiation Expansion Register */
1222 default:
1223 missing("not implemented");
1224 }
1225 s->mdimem[reg] = data;
1226 } else if (opcode == 2) {
1227 /* MDI read */
1228 switch (reg) {
1229 case 0: /* Control Register */
1230 if (data & 0x8000) {
1231 /* Reset status and control registers to default. */
1232 s->mdimem[0] = eepro100_mdi_default[0];
1233 s->mdimem[1] = eepro100_mdi_default[1];
1234 }
1235 break;
1236 case 1: /* Status Register */
1237 s->mdimem[reg] |= 0x0020;
1238 break;
1239 case 2: /* PHY Identification Register (Word 1) */
1240 case 3: /* PHY Identification Register (Word 2) */
1241 case 4: /* Auto-Negotiation Advertisement Register */
1242 break;
1243 case 5: /* Auto-Negotiation Link Partner Ability Register */
1244 s->mdimem[reg] = 0x41fe;
1245 break;
1246 case 6: /* Auto-Negotiation Expansion Register */
1247 s->mdimem[reg] = 0x0001;
1248 break;
1249 }
1250 data = s->mdimem[reg];
1251 }
1252 /* Emulation takes no time to finish MDI transaction.
1253 * Set MDI bit in SCB status register. */
1254 s->mem[SCBAck] |= 0x08;
1255 val |= BIT(28);
1256 if (raiseint) {
1257 eepro100_mdi_interrupt(s);
1258 }
1259 }
1260 val = (val & 0xffff0000) + data;
1261 e100_write_reg4(s, SCBCtrlMDI, val);
1262 }
1263
1264 /*****************************************************************************
1265 *
1266 * Port emulation.
1267 *
1268 ****************************************************************************/
1269
1270 #define PORT_SOFTWARE_RESET 0
1271 #define PORT_SELFTEST 1
1272 #define PORT_SELECTIVE_RESET 2
1273 #define PORT_DUMP 3
1274 #define PORT_SELECTION_MASK 3
1275
1276 typedef struct {
1277 uint32_t st_sign; /* Self Test Signature */
1278 uint32_t st_result; /* Self Test Results */
1279 } eepro100_selftest_t;
1280
1281 static uint32_t eepro100_read_port(EEPRO100State * s)
1282 {
1283 return 0;
1284 }
1285
1286 static void eepro100_write_port(EEPRO100State *s)
1287 {
1288 uint32_t val = e100_read_reg4(s, SCBPort);
1289 uint32_t address = (val & ~PORT_SELECTION_MASK);
1290 uint8_t selection = (val & PORT_SELECTION_MASK);
1291 switch (selection) {
1292 case PORT_SOFTWARE_RESET:
1293 nic_reset(s);
1294 break;
1295 case PORT_SELFTEST:
1296 TRACE(OTHER, logout("selftest address=0x%08x\n", address));
1297 eepro100_selftest_t data;
1298 pci_dma_read(&s->dev, address, (uint8_t *) &data, sizeof(data));
1299 data.st_sign = 0xffffffff;
1300 data.st_result = 0;
1301 pci_dma_write(&s->dev, address, (uint8_t *) &data, sizeof(data));
1302 break;
1303 case PORT_SELECTIVE_RESET:
1304 TRACE(OTHER, logout("selective reset, selftest address=0x%08x\n", address));
1305 nic_selective_reset(s);
1306 break;
1307 default:
1308 logout("val=0x%08x\n", val);
1309 missing("unknown port selection");
1310 }
1311 }
1312
1313 /*****************************************************************************
1314 *
1315 * General hardware emulation.
1316 *
1317 ****************************************************************************/
1318
1319 static uint8_t eepro100_read1(EEPRO100State * s, uint32_t addr)
1320 {
1321 uint8_t val = 0;
1322 if (addr <= sizeof(s->mem) - sizeof(val)) {
1323 val = s->mem[addr];
1324 }
1325
1326 switch (addr) {
1327 case SCBStatus:
1328 case SCBAck:
1329 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1330 break;
1331 case SCBCmd:
1332 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1333 #if 0
1334 val = eepro100_read_command(s);
1335 #endif
1336 break;
1337 case SCBIntmask:
1338 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1339 break;
1340 case SCBPort + 3:
1341 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1342 break;
1343 case SCBeeprom:
1344 val = eepro100_read_eeprom(s);
1345 break;
1346 case SCBCtrlMDI:
1347 case SCBCtrlMDI + 1:
1348 case SCBCtrlMDI + 2:
1349 case SCBCtrlMDI + 3:
1350 val = (uint8_t)(eepro100_read_mdi(s) >> (8 * (addr & 3)));
1351 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1352 break;
1353 case SCBpmdr: /* Power Management Driver Register */
1354 val = 0;
1355 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1356 break;
1357 case SCBgctrl: /* General Control Register */
1358 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1359 break;
1360 case SCBgstat: /* General Status Register */
1361 /* 100 Mbps full duplex, valid link */
1362 val = 0x07;
1363 TRACE(OTHER, logout("addr=General Status val=%02x\n", val));
1364 break;
1365 default:
1366 logout("addr=%s val=0x%02x\n", regname(addr), val);
1367 missing("unknown byte read");
1368 }
1369 return val;
1370 }
1371
1372 static uint16_t eepro100_read2(EEPRO100State * s, uint32_t addr)
1373 {
1374 uint16_t val = 0;
1375 if (addr <= sizeof(s->mem) - sizeof(val)) {
1376 val = e100_read_reg2(s, addr);
1377 }
1378
1379 switch (addr) {
1380 case SCBStatus:
1381 case SCBCmd:
1382 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1383 break;
1384 case SCBeeprom:
1385 val = eepro100_read_eeprom(s);
1386 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1387 break;
1388 case SCBCtrlMDI:
1389 case SCBCtrlMDI + 2:
1390 val = (uint16_t)(eepro100_read_mdi(s) >> (8 * (addr & 3)));
1391 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1392 break;
1393 default:
1394 logout("addr=%s val=0x%04x\n", regname(addr), val);
1395 missing("unknown word read");
1396 }
1397 return val;
1398 }
1399
1400 static uint32_t eepro100_read4(EEPRO100State * s, uint32_t addr)
1401 {
1402 uint32_t val = 0;
1403 if (addr <= sizeof(s->mem) - sizeof(val)) {
1404 val = e100_read_reg4(s, addr);
1405 }
1406
1407 switch (addr) {
1408 case SCBStatus:
1409 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1410 break;
1411 case SCBPointer:
1412 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1413 break;
1414 case SCBPort:
1415 val = eepro100_read_port(s);
1416 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1417 break;
1418 case SCBflash:
1419 val = eepro100_read_eeprom(s);
1420 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1421 break;
1422 case SCBCtrlMDI:
1423 val = eepro100_read_mdi(s);
1424 break;
1425 default:
1426 logout("addr=%s val=0x%08x\n", regname(addr), val);
1427 missing("unknown longword read");
1428 }
1429 return val;
1430 }
1431
1432 static void eepro100_write1(EEPRO100State * s, uint32_t addr, uint8_t val)
1433 {
1434 /* SCBStatus is readonly. */
1435 if (addr > SCBStatus && addr <= sizeof(s->mem) - sizeof(val)) {
1436 s->mem[addr] = val;
1437 }
1438
1439 switch (addr) {
1440 case SCBStatus:
1441 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1442 break;
1443 case SCBAck:
1444 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1445 eepro100_acknowledge(s);
1446 break;
1447 case SCBCmd:
1448 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1449 eepro100_write_command(s, val);
1450 break;
1451 case SCBIntmask:
1452 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1453 if (val & BIT(1)) {
1454 eepro100_swi_interrupt(s);
1455 }
1456 eepro100_interrupt(s, 0);
1457 break;
1458 case SCBPointer:
1459 case SCBPointer + 1:
1460 case SCBPointer + 2:
1461 case SCBPointer + 3:
1462 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1463 break;
1464 case SCBPort:
1465 case SCBPort + 1:
1466 case SCBPort + 2:
1467 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1468 break;
1469 case SCBPort + 3:
1470 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1471 eepro100_write_port(s);
1472 break;
1473 case SCBFlow: /* does not exist on 82557 */
1474 case SCBFlow + 1:
1475 case SCBFlow + 2:
1476 case SCBpmdr: /* does not exist on 82557 */
1477 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1478 break;
1479 case SCBeeprom:
1480 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1481 eepro100_write_eeprom(s->eeprom, val);
1482 break;
1483 case SCBCtrlMDI:
1484 case SCBCtrlMDI + 1:
1485 case SCBCtrlMDI + 2:
1486 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1487 break;
1488 case SCBCtrlMDI + 3:
1489 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1490 eepro100_write_mdi(s);
1491 break;
1492 default:
1493 logout("addr=%s val=0x%02x\n", regname(addr), val);
1494 missing("unknown byte write");
1495 }
1496 }
1497
1498 static void eepro100_write2(EEPRO100State * s, uint32_t addr, uint16_t val)
1499 {
1500 /* SCBStatus is readonly. */
1501 if (addr > SCBStatus && addr <= sizeof(s->mem) - sizeof(val)) {
1502 e100_write_reg2(s, addr, val);
1503 }
1504
1505 switch (addr) {
1506 case SCBStatus:
1507 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1508 s->mem[SCBAck] = (val >> 8);
1509 eepro100_acknowledge(s);
1510 break;
1511 case SCBCmd:
1512 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1513 eepro100_write_command(s, val);
1514 eepro100_write1(s, SCBIntmask, val >> 8);
1515 break;
1516 case SCBPointer:
1517 case SCBPointer + 2:
1518 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1519 break;
1520 case SCBPort:
1521 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1522 break;
1523 case SCBPort + 2:
1524 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1525 eepro100_write_port(s);
1526 break;
1527 case SCBeeprom:
1528 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1529 eepro100_write_eeprom(s->eeprom, val);
1530 break;
1531 case SCBCtrlMDI:
1532 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1533 break;
1534 case SCBCtrlMDI + 2:
1535 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1536 eepro100_write_mdi(s);
1537 break;
1538 default:
1539 logout("addr=%s val=0x%04x\n", regname(addr), val);
1540 missing("unknown word write");
1541 }
1542 }
1543
1544 static void eepro100_write4(EEPRO100State * s, uint32_t addr, uint32_t val)
1545 {
1546 if (addr <= sizeof(s->mem) - sizeof(val)) {
1547 e100_write_reg4(s, addr, val);
1548 }
1549
1550 switch (addr) {
1551 case SCBPointer:
1552 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1553 break;
1554 case SCBPort:
1555 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1556 eepro100_write_port(s);
1557 break;
1558 case SCBflash:
1559 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1560 val = val >> 16;
1561 eepro100_write_eeprom(s->eeprom, val);
1562 break;
1563 case SCBCtrlMDI:
1564 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1565 eepro100_write_mdi(s);
1566 break;
1567 default:
1568 logout("addr=%s val=0x%08x\n", regname(addr), val);
1569 missing("unknown longword write");
1570 }
1571 }
1572
1573 static uint64_t eepro100_read(void *opaque, target_phys_addr_t addr,
1574 unsigned size)
1575 {
1576 EEPRO100State *s = opaque;
1577
1578 switch (size) {
1579 case 1: return eepro100_read1(s, addr);
1580 case 2: return eepro100_read2(s, addr);
1581 case 4: return eepro100_read4(s, addr);
1582 default: abort();
1583 }
1584 }
1585
1586 static void eepro100_write(void *opaque, target_phys_addr_t addr,
1587 uint64_t data, unsigned size)
1588 {
1589 EEPRO100State *s = opaque;
1590
1591 switch (size) {
1592 case 1: return eepro100_write1(s, addr, data);
1593 case 2: return eepro100_write2(s, addr, data);
1594 case 4: return eepro100_write4(s, addr, data);
1595 default: abort();
1596 }
1597 }
1598
1599 static const MemoryRegionOps eepro100_ops = {
1600 .read = eepro100_read,
1601 .write = eepro100_write,
1602 .endianness = DEVICE_LITTLE_ENDIAN,
1603 };
1604
1605 static int nic_can_receive(VLANClientState *nc)
1606 {
1607 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1608 TRACE(RXTX, logout("%p\n", s));
1609 return get_ru_state(s) == ru_ready;
1610 #if 0
1611 return !eepro100_buffer_full(s);
1612 #endif
1613 }
1614
1615 static ssize_t nic_receive(VLANClientState *nc, const uint8_t * buf, size_t size)
1616 {
1617 /* TODO:
1618 * - Magic packets should set bit 30 in power management driver register.
1619 * - Interesting packets should set bit 29 in power management driver register.
1620 */
1621 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1622 uint16_t rfd_status = 0xa000;
1623 #if defined(CONFIG_PAD_RECEIVED_FRAMES)
1624 uint8_t min_buf[60];
1625 #endif
1626 static const uint8_t broadcast_macaddr[6] =
1627 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1628
1629 #if defined(CONFIG_PAD_RECEIVED_FRAMES)
1630 /* Pad to minimum Ethernet frame length */
1631 if (size < sizeof(min_buf)) {
1632 memcpy(min_buf, buf, size);
1633 memset(&min_buf[size], 0, sizeof(min_buf) - size);
1634 buf = min_buf;
1635 size = sizeof(min_buf);
1636 }
1637 #endif
1638
1639 if (s->configuration[8] & 0x80) {
1640 /* CSMA is disabled. */
1641 logout("%p received while CSMA is disabled\n", s);
1642 return -1;
1643 #if !defined(CONFIG_PAD_RECEIVED_FRAMES)
1644 } else if (size < 64 && (s->configuration[7] & BIT(0))) {
1645 /* Short frame and configuration byte 7/0 (discard short receive) set:
1646 * Short frame is discarded */
1647 logout("%p received short frame (%zu byte)\n", s, size);
1648 s->statistics.rx_short_frame_errors++;
1649 return -1;
1650 #endif
1651 } else if ((size > MAX_ETH_FRAME_SIZE + 4) && !(s->configuration[18] & BIT(3))) {
1652 /* Long frame and configuration byte 18/3 (long receive ok) not set:
1653 * Long frames are discarded. */
1654 logout("%p received long frame (%zu byte), ignored\n", s, size);
1655 return -1;
1656 } else if (memcmp(buf, s->conf.macaddr.a, 6) == 0) { /* !!! */
1657 /* Frame matches individual address. */
1658 /* TODO: check configuration byte 15/4 (ignore U/L). */
1659 TRACE(RXTX, logout("%p received frame for me, len=%zu\n", s, size));
1660 } else if (memcmp(buf, broadcast_macaddr, 6) == 0) {
1661 /* Broadcast frame. */
1662 TRACE(RXTX, logout("%p received broadcast, len=%zu\n", s, size));
1663 rfd_status |= 0x0002;
1664 } else if (buf[0] & 0x01) {
1665 /* Multicast frame. */
1666 TRACE(RXTX, logout("%p received multicast, len=%zu,%s\n", s, size, nic_dump(buf, size)));
1667 if (s->configuration[21] & BIT(3)) {
1668 /* Multicast all bit is set, receive all multicast frames. */
1669 } else {
1670 unsigned mcast_idx = compute_mcast_idx(buf);
1671 assert(mcast_idx < 64);
1672 if (s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))) {
1673 /* Multicast frame is allowed in hash table. */
1674 } else if (s->configuration[15] & BIT(0)) {
1675 /* Promiscuous: receive all. */
1676 rfd_status |= 0x0004;
1677 } else {
1678 TRACE(RXTX, logout("%p multicast ignored\n", s));
1679 return -1;
1680 }
1681 }
1682 /* TODO: Next not for promiscuous mode? */
1683 rfd_status |= 0x0002;
1684 } else if (s->configuration[15] & BIT(0)) {
1685 /* Promiscuous: receive all. */
1686 TRACE(RXTX, logout("%p received frame in promiscuous mode, len=%zu\n", s, size));
1687 rfd_status |= 0x0004;
1688 } else if (s->configuration[20] & BIT(6)) {
1689 /* Multiple IA bit set. */
1690 unsigned mcast_idx = compute_mcast_idx(buf);
1691 assert(mcast_idx < 64);
1692 if (s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))) {
1693 TRACE(RXTX, logout("%p accepted, multiple IA bit set\n", s));
1694 } else {
1695 TRACE(RXTX, logout("%p frame ignored, multiple IA bit set\n", s));
1696 return -1;
1697 }
1698 } else {
1699 TRACE(RXTX, logout("%p received frame, ignored, len=%zu,%s\n", s, size,
1700 nic_dump(buf, size)));
1701 return size;
1702 }
1703
1704 if (get_ru_state(s) != ru_ready) {
1705 /* No resources available. */
1706 logout("no resources, state=%u\n", get_ru_state(s));
1707 /* TODO: RNR interrupt only at first failed frame? */
1708 eepro100_rnr_interrupt(s);
1709 s->statistics.rx_resource_errors++;
1710 #if 0
1711 assert(!"no resources");
1712 #endif
1713 return -1;
1714 }
1715 /* !!! */
1716 eepro100_rx_t rx;
1717 pci_dma_read(&s->dev, s->ru_base + s->ru_offset,
1718 (uint8_t *) &rx, sizeof(eepro100_rx_t));
1719 uint16_t rfd_command = le16_to_cpu(rx.command);
1720 uint16_t rfd_size = le16_to_cpu(rx.size);
1721
1722 if (size > rfd_size) {
1723 logout("Receive buffer (%" PRId16 " bytes) too small for data "
1724 "(%zu bytes); data truncated\n", rfd_size, size);
1725 size = rfd_size;
1726 }
1727 #if !defined(CONFIG_PAD_RECEIVED_FRAMES)
1728 if (size < 64) {
1729 rfd_status |= 0x0080;
1730 }
1731 #endif
1732 TRACE(OTHER, logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n",
1733 rfd_command, rx.link, rx.rx_buf_addr, rfd_size));
1734 stw_le_pci_dma(&s->dev, s->ru_base + s->ru_offset +
1735 offsetof(eepro100_rx_t, status), rfd_status);
1736 stw_le_pci_dma(&s->dev, s->ru_base + s->ru_offset +
1737 offsetof(eepro100_rx_t, count), size);
1738 /* Early receive interrupt not supported. */
1739 #if 0
1740 eepro100_er_interrupt(s);
1741 #endif
1742 /* Receive CRC Transfer not supported. */
1743 if (s->configuration[18] & BIT(2)) {
1744 missing("Receive CRC Transfer");
1745 return -1;
1746 }
1747 /* TODO: check stripping enable bit. */
1748 #if 0
1749 assert(!(s->configuration[17] & BIT(0)));
1750 #endif
1751 pci_dma_write(&s->dev, s->ru_base + s->ru_offset +
1752 sizeof(eepro100_rx_t), buf, size);
1753 s->statistics.rx_good_frames++;
1754 eepro100_fr_interrupt(s);
1755 s->ru_offset = le32_to_cpu(rx.link);
1756 if (rfd_command & COMMAND_EL) {
1757 /* EL bit is set, so this was the last frame. */
1758 logout("receive: Running out of frames\n");
1759 set_ru_state(s, ru_suspended);
1760 }
1761 if (rfd_command & COMMAND_S) {
1762 /* S bit is set. */
1763 set_ru_state(s, ru_suspended);
1764 }
1765 return size;
1766 }
1767
1768 static const VMStateDescription vmstate_eepro100 = {
1769 .version_id = 3,
1770 .minimum_version_id = 2,
1771 .minimum_version_id_old = 2,
1772 .fields = (VMStateField []) {
1773 VMSTATE_PCI_DEVICE(dev, EEPRO100State),
1774 VMSTATE_UNUSED(32),
1775 VMSTATE_BUFFER(mult, EEPRO100State),
1776 VMSTATE_BUFFER(mem, EEPRO100State),
1777 /* Save all members of struct between scb_stat and mem. */
1778 VMSTATE_UINT8(scb_stat, EEPRO100State),
1779 VMSTATE_UINT8(int_stat, EEPRO100State),
1780 VMSTATE_UNUSED(3*4),
1781 VMSTATE_MACADDR(conf.macaddr, EEPRO100State),
1782 VMSTATE_UNUSED(19*4),
1783 VMSTATE_UINT16_ARRAY(mdimem, EEPRO100State, 32),
1784 /* The eeprom should be saved and restored by its own routines. */
1785 VMSTATE_UINT32(device, EEPRO100State),
1786 /* TODO check device. */
1787 VMSTATE_UINT32(cu_base, EEPRO100State),
1788 VMSTATE_UINT32(cu_offset, EEPRO100State),
1789 VMSTATE_UINT32(ru_base, EEPRO100State),
1790 VMSTATE_UINT32(ru_offset, EEPRO100State),
1791 VMSTATE_UINT32(statsaddr, EEPRO100State),
1792 /* Save eepro100_stats_t statistics. */
1793 VMSTATE_UINT32(statistics.tx_good_frames, EEPRO100State),
1794 VMSTATE_UINT32(statistics.tx_max_collisions, EEPRO100State),
1795 VMSTATE_UINT32(statistics.tx_late_collisions, EEPRO100State),
1796 VMSTATE_UINT32(statistics.tx_underruns, EEPRO100State),
1797 VMSTATE_UINT32(statistics.tx_lost_crs, EEPRO100State),
1798 VMSTATE_UINT32(statistics.tx_deferred, EEPRO100State),
1799 VMSTATE_UINT32(statistics.tx_single_collisions, EEPRO100State),
1800 VMSTATE_UINT32(statistics.tx_multiple_collisions, EEPRO100State),
1801 VMSTATE_UINT32(statistics.tx_total_collisions, EEPRO100State),
1802 VMSTATE_UINT32(statistics.rx_good_frames, EEPRO100State),
1803 VMSTATE_UINT32(statistics.rx_crc_errors, EEPRO100State),
1804 VMSTATE_UINT32(statistics.rx_alignment_errors, EEPRO100State),
1805 VMSTATE_UINT32(statistics.rx_resource_errors, EEPRO100State),
1806 VMSTATE_UINT32(statistics.rx_overrun_errors, EEPRO100State),
1807 VMSTATE_UINT32(statistics.rx_cdt_errors, EEPRO100State),
1808 VMSTATE_UINT32(statistics.rx_short_frame_errors, EEPRO100State),
1809 VMSTATE_UINT32(statistics.fc_xmt_pause, EEPRO100State),
1810 VMSTATE_UINT32(statistics.fc_rcv_pause, EEPRO100State),
1811 VMSTATE_UINT32(statistics.fc_rcv_unsupported, EEPRO100State),
1812 VMSTATE_UINT16(statistics.xmt_tco_frames, EEPRO100State),
1813 VMSTATE_UINT16(statistics.rcv_tco_frames, EEPRO100State),
1814 /* Configuration bytes. */
1815 VMSTATE_BUFFER(configuration, EEPRO100State),
1816 VMSTATE_END_OF_LIST()
1817 }
1818 };
1819
1820 static void nic_cleanup(VLANClientState *nc)
1821 {
1822 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1823
1824 s->nic = NULL;
1825 }
1826
1827 static int pci_nic_uninit(PCIDevice *pci_dev)
1828 {
1829 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1830
1831 memory_region_destroy(&s->mmio_bar);
1832 memory_region_destroy(&s->io_bar);
1833 memory_region_destroy(&s->flash_bar);
1834 vmstate_unregister(&pci_dev->qdev, s->vmstate, s);
1835 eeprom93xx_free(&pci_dev->qdev, s->eeprom);
1836 qemu_del_vlan_client(&s->nic->nc);
1837 return 0;
1838 }
1839
1840 static NetClientInfo net_eepro100_info = {
1841 .type = NET_CLIENT_TYPE_NIC,
1842 .size = sizeof(NICState),
1843 .can_receive = nic_can_receive,
1844 .receive = nic_receive,
1845 .cleanup = nic_cleanup,
1846 };
1847
1848 static int e100_nic_init(PCIDevice *pci_dev)
1849 {
1850 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1851 E100PCIDeviceInfo *e100_device = DO_UPCAST(E100PCIDeviceInfo, pci.qdev,
1852 pci_dev->qdev.info);
1853
1854 TRACE(OTHER, logout("\n"));
1855
1856 s->device = e100_device->device;
1857
1858 e100_pci_reset(s, e100_device);
1859
1860 /* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM,
1861 * i82559 and later support 64 or 256 word EEPROM. */
1862 s->eeprom = eeprom93xx_new(&pci_dev->qdev, EEPROM_SIZE);
1863
1864 /* Handler for memory-mapped I/O */
1865 memory_region_init_io(&s->mmio_bar, &eepro100_ops, s, "eepro100-mmio",
1866 PCI_MEM_SIZE);
1867 pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->mmio_bar);
1868 memory_region_init_io(&s->io_bar, &eepro100_ops, s, "eepro100-io",
1869 PCI_IO_SIZE);
1870 pci_register_bar(&s->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
1871 /* FIXME: flash aliases to mmio?! */
1872 memory_region_init_io(&s->flash_bar, &eepro100_ops, s, "eepro100-flash",
1873 PCI_FLASH_SIZE);
1874 pci_register_bar(&s->dev, 2, 0, &s->flash_bar);
1875
1876 qemu_macaddr_default_if_unset(&s->conf.macaddr);
1877 logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6));
1878
1879 nic_reset(s);
1880
1881 s->nic = qemu_new_nic(&net_eepro100_info, &s->conf,
1882 pci_dev->qdev.info->name, pci_dev->qdev.id, s);
1883
1884 qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
1885 TRACE(OTHER, logout("%s\n", s->nic->nc.info_str));
1886
1887 qemu_register_reset(nic_reset, s);
1888
1889 s->vmstate = g_malloc(sizeof(vmstate_eepro100));
1890 memcpy(s->vmstate, &vmstate_eepro100, sizeof(vmstate_eepro100));
1891 s->vmstate->name = s->nic->nc.model;
1892 vmstate_register(&pci_dev->qdev, -1, s->vmstate, s);
1893
1894 add_boot_device_path(s->conf.bootindex, &pci_dev->qdev, "/ethernet-phy@0");
1895
1896 return 0;
1897 }
1898
1899 static E100PCIDeviceInfo e100_devices[] = {
1900 {
1901 .pci.qdev.name = "i82550",
1902 .pci.qdev.desc = "Intel i82550 Ethernet",
1903 .device = i82550,
1904 /* TODO: check device id. */
1905 .pci.device_id = PCI_DEVICE_ID_INTEL_82551IT,
1906 /* Revision ID: 0x0c, 0x0d, 0x0e. */
1907 .pci.revision = 0x0e,
1908 /* TODO: check size of statistical counters. */
1909 .stats_size = 80,
1910 /* TODO: check extended tcb support. */
1911 .has_extended_tcb_support = true,
1912 .power_management = true,
1913 },{
1914 .pci.qdev.name = "i82551",
1915 .pci.qdev.desc = "Intel i82551 Ethernet",
1916 .device = i82551,
1917 .pci.device_id = PCI_DEVICE_ID_INTEL_82551IT,
1918 /* Revision ID: 0x0f, 0x10. */
1919 .pci.revision = 0x0f,
1920 /* TODO: check size of statistical counters. */
1921 .stats_size = 80,
1922 .has_extended_tcb_support = true,
1923 .power_management = true,
1924 },{
1925 .pci.qdev.name = "i82557a",
1926 .pci.qdev.desc = "Intel i82557A Ethernet",
1927 .device = i82557A,
1928 .pci.device_id = PCI_DEVICE_ID_INTEL_82557,
1929 .pci.revision = 0x01,
1930 .power_management = false,
1931 },{
1932 .pci.qdev.name = "i82557b",
1933 .pci.qdev.desc = "Intel i82557B Ethernet",
1934 .device = i82557B,
1935 .pci.device_id = PCI_DEVICE_ID_INTEL_82557,
1936 .pci.revision = 0x02,
1937 .power_management = false,
1938 },{
1939 .pci.qdev.name = "i82557c",
1940 .pci.qdev.desc = "Intel i82557C Ethernet",
1941 .device = i82557C,
1942 .pci.device_id = PCI_DEVICE_ID_INTEL_82557,
1943 .pci.revision = 0x03,
1944 .power_management = false,
1945 },{
1946 .pci.qdev.name = "i82558a",
1947 .pci.qdev.desc = "Intel i82558A Ethernet",
1948 .device = i82558A,
1949 .pci.device_id = PCI_DEVICE_ID_INTEL_82557,
1950 .pci.revision = 0x04,
1951 .stats_size = 76,
1952 .has_extended_tcb_support = true,
1953 .power_management = true,
1954 },{
1955 .pci.qdev.name = "i82558b",
1956 .pci.qdev.desc = "Intel i82558B Ethernet",
1957 .device = i82558B,
1958 .pci.device_id = PCI_DEVICE_ID_INTEL_82557,
1959 .pci.revision = 0x05,
1960 .stats_size = 76,
1961 .has_extended_tcb_support = true,
1962 .power_management = true,
1963 },{
1964 .pci.qdev.name = "i82559a",
1965 .pci.qdev.desc = "Intel i82559A Ethernet",
1966 .device = i82559A,
1967 .pci.device_id = PCI_DEVICE_ID_INTEL_82557,
1968 .pci.revision = 0x06,
1969 .stats_size = 80,
1970 .has_extended_tcb_support = true,
1971 .power_management = true,
1972 },{
1973 .pci.qdev.name = "i82559b",
1974 .pci.qdev.desc = "Intel i82559B Ethernet",
1975 .device = i82559B,
1976 .pci.device_id = PCI_DEVICE_ID_INTEL_82557,
1977 .pci.revision = 0x07,
1978 .stats_size = 80,
1979 .has_extended_tcb_support = true,
1980 .power_management = true,
1981 },{
1982 .pci.qdev.name = "i82559c",
1983 .pci.qdev.desc = "Intel i82559C Ethernet",
1984 .device = i82559C,
1985 .pci.device_id = PCI_DEVICE_ID_INTEL_82557,
1986 #if 0
1987 .pci.revision = 0x08,
1988 #endif
1989 /* TODO: Windows wants revision id 0x0c. */
1990 .pci.revision = 0x0c,
1991 #if EEPROM_SIZE > 0
1992 .pci.subsystem_vendor_id = PCI_VENDOR_ID_INTEL,
1993 .pci.subsystem_id = 0x0040,
1994 #endif
1995 .stats_size = 80,
1996 .has_extended_tcb_support = true,
1997 .power_management = true,
1998 },{
1999 .pci.qdev.name = "i82559er",
2000 .pci.qdev.desc = "Intel i82559ER Ethernet",
2001 .device = i82559ER,
2002 .pci.device_id = PCI_DEVICE_ID_INTEL_82551IT,
2003 .pci.revision = 0x09,
2004 .stats_size = 80,
2005 .has_extended_tcb_support = true,
2006 .power_management = true,
2007 },{
2008 .pci.qdev.name = "i82562",
2009 .pci.qdev.desc = "Intel i82562 Ethernet",
2010 .device = i82562,
2011 /* TODO: check device id. */
2012 .pci.device_id = PCI_DEVICE_ID_INTEL_82551IT,
2013 /* TODO: wrong revision id. */
2014 .pci.revision = 0x0e,
2015 .stats_size = 80,
2016 .has_extended_tcb_support = true,
2017 .power_management = true,
2018 },{
2019 /* Toshiba Tecra 8200. */
2020 .pci.qdev.name = "i82801",
2021 .pci.qdev.desc = "Intel i82801 Ethernet",
2022 .device = i82801,
2023 .pci.device_id = 0x2449,
2024 .pci.revision = 0x03,
2025 .stats_size = 80,
2026 .has_extended_tcb_support = true,
2027 .power_management = true,
2028 }
2029 };
2030
2031 static Property e100_properties[] = {
2032 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2033 DEFINE_PROP_END_OF_LIST(),
2034 };
2035
2036 static void eepro100_register_devices(void)
2037 {
2038 size_t i;
2039 for (i = 0; i < ARRAY_SIZE(e100_devices); i++) {
2040 PCIDeviceInfo *pci_dev = &e100_devices[i].pci;
2041 /* We use the same rom file for all device ids.
2042 QEMU fixes the device id during rom load. */
2043 pci_dev->vendor_id = PCI_VENDOR_ID_INTEL;
2044 pci_dev->class_id = PCI_CLASS_NETWORK_ETHERNET;
2045 pci_dev->romfile = "pxe-eepro100.rom";
2046 pci_dev->init = e100_nic_init;
2047 pci_dev->exit = pci_nic_uninit;
2048 pci_dev->qdev.props = e100_properties;
2049 pci_dev->qdev.size = sizeof(EEPRO100State);
2050 pci_qdev_register(pci_dev);
2051 }
2052 }
2053
2054 device_init(eepro100_register_devices)
QEmu