4 * Copyright (c) 2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
33 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
35 # define PCI_DPRINTF(format, ...) do { } while (0)
41 pci_set_irq_fn set_irq
;
42 pci_map_irq_fn map_irq
;
43 pci_hotplug_fn hotplug
;
44 uint32_t config_reg
; /* XXX: suppress */
46 PCIDevice
*devices
[256];
47 PCIDevice
*parent_dev
;
49 QLIST_HEAD(, PCIBus
) child
; /* this will be replaced by qdev later */
50 QLIST_ENTRY(PCIBus
) sibling
;/* this will be replaced by qdev later */
52 /* The bus IRQ state is the logical OR of the connected devices.
53 Keep a count of the number of devices with raised IRQs. */
58 static void pcibus_dev_print(Monitor
*mon
, DeviceState
*dev
, int indent
);
60 static struct BusInfo pci_bus_info
= {
62 .size
= sizeof(PCIBus
),
63 .print_dev
= pcibus_dev_print
,
64 .props
= (Property
[]) {
65 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice
, devfn
, -1),
66 DEFINE_PROP_END_OF_LIST()
70 static void pci_update_mappings(PCIDevice
*d
);
71 static void pci_set_irq(void *opaque
, int irq_num
, int level
);
73 target_phys_addr_t pci_mem_base
;
74 static uint16_t pci_default_sub_vendor_id
= PCI_SUBVENDOR_ID_REDHAT_QUMRANET
;
75 static uint16_t pci_default_sub_device_id
= PCI_SUBDEVICE_ID_QEMU
;
80 QLIST_ENTRY(PCIHostBus
) next
;
82 static QLIST_HEAD(, PCIHostBus
) host_buses
;
84 static const VMStateDescription vmstate_pcibus
= {
87 .minimum_version_id
= 1,
88 .minimum_version_id_old
= 1,
89 .fields
= (VMStateField
[]) {
90 VMSTATE_INT32_EQUAL(nirq
, PCIBus
),
91 VMSTATE_VARRAY_INT32(irq_count
, PCIBus
, nirq
, 0, vmstate_info_int32
, int32_t),
96 static int pci_bar(PCIDevice
*d
, int reg
)
100 if (reg
!= PCI_ROM_SLOT
)
101 return PCI_BASE_ADDRESS_0
+ reg
* 4;
103 type
= d
->config
[PCI_HEADER_TYPE
] & ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
104 return type
== PCI_HEADER_TYPE_BRIDGE
? PCI_ROM_ADDRESS1
: PCI_ROM_ADDRESS
;
107 static inline int pci_irq_state(PCIDevice
*d
, int irq_num
)
109 return (d
->irq_state
>> irq_num
) & 0x1;
112 static inline void pci_set_irq_state(PCIDevice
*d
, int irq_num
, int level
)
114 d
->irq_state
&= ~(0x1 << irq_num
);
115 d
->irq_state
|= level
<< irq_num
;
118 static void pci_change_irq_level(PCIDevice
*pci_dev
, int irq_num
, int change
)
123 irq_num
= bus
->map_irq(pci_dev
, irq_num
);
126 pci_dev
= bus
->parent_dev
;
128 bus
->irq_count
[irq_num
] += change
;
129 bus
->set_irq(bus
->irq_opaque
, irq_num
, bus
->irq_count
[irq_num
] != 0);
132 /* Update interrupt status bit in config space on interrupt
134 static void pci_update_irq_status(PCIDevice
*dev
)
136 if (dev
->irq_state
) {
137 dev
->config
[PCI_STATUS
] |= PCI_STATUS_INTERRUPT
;
139 dev
->config
[PCI_STATUS
] &= ~PCI_STATUS_INTERRUPT
;
143 static void pci_device_reset(PCIDevice
*dev
)
148 pci_update_irq_status(dev
);
149 dev
->config
[PCI_COMMAND
] &= ~(PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
|
151 dev
->config
[PCI_CACHE_LINE_SIZE
] = 0x0;
152 dev
->config
[PCI_INTERRUPT_LINE
] = 0x0;
153 for (r
= 0; r
< PCI_NUM_REGIONS
; ++r
) {
154 if (!dev
->io_regions
[r
].size
) {
157 pci_set_long(dev
->config
+ pci_bar(dev
, r
), dev
->io_regions
[r
].type
);
159 pci_update_mappings(dev
);
162 static void pci_bus_reset(void *opaque
)
164 PCIBus
*bus
= opaque
;
167 for (i
= 0; i
< bus
->nirq
; i
++) {
168 bus
->irq_count
[i
] = 0;
170 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); ++i
) {
171 if (bus
->devices
[i
]) {
172 pci_device_reset(bus
->devices
[i
]);
177 static void pci_host_bus_register(int domain
, PCIBus
*bus
)
179 struct PCIHostBus
*host
;
180 host
= qemu_mallocz(sizeof(*host
));
181 host
->domain
= domain
;
183 QLIST_INSERT_HEAD(&host_buses
, host
, next
);
186 PCIBus
*pci_find_root_bus(int domain
)
188 struct PCIHostBus
*host
;
190 QLIST_FOREACH(host
, &host_buses
, next
) {
191 if (host
->domain
== domain
) {
199 void pci_bus_new_inplace(PCIBus
*bus
, DeviceState
*parent
,
200 const char *name
, int devfn_min
)
202 qbus_create_inplace(&bus
->qbus
, &pci_bus_info
, parent
, name
);
203 bus
->devfn_min
= devfn_min
;
206 QLIST_INIT(&bus
->child
);
207 pci_host_bus_register(0, bus
); /* for now only pci domain 0 is supported */
209 vmstate_register(-1, &vmstate_pcibus
, bus
);
210 qemu_register_reset(pci_bus_reset
, bus
);
213 PCIBus
*pci_bus_new(DeviceState
*parent
, const char *name
, int devfn_min
)
217 bus
= qemu_mallocz(sizeof(*bus
));
218 bus
->qbus
.qdev_allocated
= 1;
219 pci_bus_new_inplace(bus
, parent
, name
, devfn_min
);
223 void pci_bus_irqs(PCIBus
*bus
, pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
224 void *irq_opaque
, int nirq
)
226 bus
->set_irq
= set_irq
;
227 bus
->map_irq
= map_irq
;
228 bus
->irq_opaque
= irq_opaque
;
230 bus
->irq_count
= qemu_mallocz(nirq
* sizeof(bus
->irq_count
[0]));
233 void pci_bus_hotplug(PCIBus
*bus
, pci_hotplug_fn hotplug
)
235 bus
->qbus
.allow_hotplug
= 1;
236 bus
->hotplug
= hotplug
;
239 PCIBus
*pci_register_bus(DeviceState
*parent
, const char *name
,
240 pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
241 void *irq_opaque
, int devfn_min
, int nirq
)
245 bus
= pci_bus_new(parent
, name
, devfn_min
);
246 pci_bus_irqs(bus
, set_irq
, map_irq
, irq_opaque
, nirq
);
250 static void pci_register_secondary_bus(PCIBus
*parent
,
253 pci_map_irq_fn map_irq
,
256 qbus_create_inplace(&bus
->qbus
, &pci_bus_info
, &dev
->qdev
, name
);
257 bus
->map_irq
= map_irq
;
258 bus
->parent_dev
= dev
;
260 QLIST_INIT(&bus
->child
);
261 QLIST_INSERT_HEAD(&parent
->child
, bus
, sibling
);
264 static void pci_unregister_secondary_bus(PCIBus
*bus
)
266 assert(QLIST_EMPTY(&bus
->child
));
267 QLIST_REMOVE(bus
, sibling
);
270 int pci_bus_num(PCIBus
*s
)
273 return 0; /* pci host bridge */
274 return s
->parent_dev
->config
[PCI_SECONDARY_BUS
];
277 static int get_pci_config_device(QEMUFile
*f
, void *pv
, size_t size
)
279 PCIDevice
*s
= container_of(pv
, PCIDevice
, config
);
283 assert(size
== pci_config_size(s
));
284 config
= qemu_malloc(size
);
286 qemu_get_buffer(f
, config
, size
);
287 for (i
= 0; i
< size
; ++i
) {
288 if ((config
[i
] ^ s
->config
[i
]) & s
->cmask
[i
] & ~s
->wmask
[i
]) {
293 memcpy(s
->config
, config
, size
);
295 pci_update_mappings(s
);
301 /* just put buffer */
302 static void put_pci_config_device(QEMUFile
*f
, void *pv
, size_t size
)
304 const uint8_t **v
= pv
;
305 assert(size
== pci_config_size(container_of(pv
, PCIDevice
, config
)));
306 qemu_put_buffer(f
, *v
, size
);
309 static VMStateInfo vmstate_info_pci_config
= {
310 .name
= "pci config",
311 .get
= get_pci_config_device
,
312 .put
= put_pci_config_device
,
315 static int get_pci_irq_state(QEMUFile
*f
, void *pv
, size_t size
)
317 PCIDevice
*s
= container_of(pv
, PCIDevice
, config
);
318 uint32_t irq_state
[PCI_NUM_PINS
];
320 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
321 irq_state
[i
] = qemu_get_be32(f
);
322 if (irq_state
[i
] != 0x1 && irq_state
[i
] != 0) {
323 fprintf(stderr
, "irq state %d: must be 0 or 1.\n",
329 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
330 pci_set_irq_state(s
, i
, irq_state
[i
]);
336 static void put_pci_irq_state(QEMUFile
*f
, void *pv
, size_t size
)
339 PCIDevice
*s
= container_of(pv
, PCIDevice
, config
);
341 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
342 qemu_put_be32(f
, pci_irq_state(s
, i
));
346 static VMStateInfo vmstate_info_pci_irq_state
= {
347 .name
= "pci irq state",
348 .get
= get_pci_irq_state
,
349 .put
= put_pci_irq_state
,
352 const VMStateDescription vmstate_pci_device
= {
355 .minimum_version_id
= 1,
356 .minimum_version_id_old
= 1,
357 .fields
= (VMStateField
[]) {
358 VMSTATE_INT32_LE(version_id
, PCIDevice
),
359 VMSTATE_BUFFER_UNSAFE_INFO(config
, PCIDevice
, 0,
360 vmstate_info_pci_config
,
361 PCI_CONFIG_SPACE_SIZE
),
362 VMSTATE_BUFFER_UNSAFE_INFO(irq_state
, PCIDevice
, 2,
363 vmstate_info_pci_irq_state
,
364 PCI_NUM_PINS
* sizeof(int32_t)),
365 VMSTATE_END_OF_LIST()
369 const VMStateDescription vmstate_pcie_device
= {
372 .minimum_version_id
= 1,
373 .minimum_version_id_old
= 1,
374 .fields
= (VMStateField
[]) {
375 VMSTATE_INT32_LE(version_id
, PCIDevice
),
376 VMSTATE_BUFFER_UNSAFE_INFO(config
, PCIDevice
, 0,
377 vmstate_info_pci_config
,
378 PCIE_CONFIG_SPACE_SIZE
),
379 VMSTATE_BUFFER_UNSAFE_INFO(irq_state
, PCIDevice
, 2,
380 vmstate_info_pci_irq_state
,
381 PCI_NUM_PINS
* sizeof(int32_t)),
382 VMSTATE_END_OF_LIST()
386 static inline const VMStateDescription
*pci_get_vmstate(PCIDevice
*s
)
388 return pci_is_express(s
) ? &vmstate_pcie_device
: &vmstate_pci_device
;
391 void pci_device_save(PCIDevice
*s
, QEMUFile
*f
)
393 /* Clear interrupt status bit: it is implicit
394 * in irq_state which we are saving.
395 * This makes us compatible with old devices
396 * which never set or clear this bit. */
397 s
->config
[PCI_STATUS
] &= ~PCI_STATUS_INTERRUPT
;
398 vmstate_save_state(f
, pci_get_vmstate(s
), s
);
399 /* Restore the interrupt status bit. */
400 pci_update_irq_status(s
);
403 int pci_device_load(PCIDevice
*s
, QEMUFile
*f
)
406 ret
= vmstate_load_state(f
, pci_get_vmstate(s
), s
, s
->version_id
);
407 /* Restore the interrupt status bit. */
408 pci_update_irq_status(s
);
412 static int pci_set_default_subsystem_id(PCIDevice
*pci_dev
)
416 id
= (void*)(&pci_dev
->config
[PCI_SUBVENDOR_ID
]);
417 id
[0] = cpu_to_le16(pci_default_sub_vendor_id
);
418 id
[1] = cpu_to_le16(pci_default_sub_device_id
);
423 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error
425 static int pci_parse_devaddr(const char *addr
, int *domp
, int *busp
, unsigned *slotp
)
430 unsigned long dom
= 0, bus
= 0;
434 val
= strtoul(p
, &e
, 16);
440 val
= strtoul(p
, &e
, 16);
447 val
= strtoul(p
, &e
, 16);
453 if (dom
> 0xffff || bus
> 0xff || val
> 0x1f)
461 /* Note: QEMU doesn't implement domains other than 0 */
462 if (!pci_find_bus(pci_find_root_bus(dom
), bus
))
471 int pci_read_devaddr(Monitor
*mon
, const char *addr
, int *domp
, int *busp
,
474 /* strip legacy tag */
475 if (!strncmp(addr
, "pci_addr=", 9)) {
478 if (pci_parse_devaddr(addr
, domp
, busp
, slotp
)) {
479 monitor_printf(mon
, "Invalid pci address\n");
485 PCIBus
*pci_get_bus_devfn(int *devfnp
, const char *devaddr
)
492 return pci_find_bus(pci_find_root_bus(0), 0);
495 if (pci_parse_devaddr(devaddr
, &dom
, &bus
, &slot
) < 0) {
500 return pci_find_bus(pci_find_root_bus(0), bus
);
503 static void pci_init_cmask(PCIDevice
*dev
)
505 pci_set_word(dev
->cmask
+ PCI_VENDOR_ID
, 0xffff);
506 pci_set_word(dev
->cmask
+ PCI_DEVICE_ID
, 0xffff);
507 dev
->cmask
[PCI_STATUS
] = PCI_STATUS_CAP_LIST
;
508 dev
->cmask
[PCI_REVISION_ID
] = 0xff;
509 dev
->cmask
[PCI_CLASS_PROG
] = 0xff;
510 pci_set_word(dev
->cmask
+ PCI_CLASS_DEVICE
, 0xffff);
511 dev
->cmask
[PCI_HEADER_TYPE
] = 0xff;
512 dev
->cmask
[PCI_CAPABILITY_LIST
] = 0xff;
515 static void pci_init_wmask(PCIDevice
*dev
)
517 int config_size
= pci_config_size(dev
);
519 dev
->wmask
[PCI_CACHE_LINE_SIZE
] = 0xff;
520 dev
->wmask
[PCI_INTERRUPT_LINE
] = 0xff;
521 pci_set_word(dev
->wmask
+ PCI_COMMAND
,
522 PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
);
524 memset(dev
->wmask
+ PCI_CONFIG_HEADER_SIZE
, 0xff,
525 config_size
- PCI_CONFIG_HEADER_SIZE
);
528 static void pci_init_wmask_bridge(PCIDevice
*d
)
530 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
531 PCI_SEC_LETENCY_TIMER */
532 memset(d
->wmask
+ PCI_PRIMARY_BUS
, 0xff, 4);
535 d
->wmask
[PCI_IO_BASE
] = PCI_IO_RANGE_MASK
& 0xff;
536 d
->wmask
[PCI_IO_LIMIT
] = PCI_IO_RANGE_MASK
& 0xff;
537 pci_set_word(d
->wmask
+ PCI_MEMORY_BASE
,
538 PCI_MEMORY_RANGE_MASK
& 0xffff);
539 pci_set_word(d
->wmask
+ PCI_MEMORY_LIMIT
,
540 PCI_MEMORY_RANGE_MASK
& 0xffff);
541 pci_set_word(d
->wmask
+ PCI_PREF_MEMORY_BASE
,
542 PCI_PREF_RANGE_MASK
& 0xffff);
543 pci_set_word(d
->wmask
+ PCI_PREF_MEMORY_LIMIT
,
544 PCI_PREF_RANGE_MASK
& 0xffff);
546 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
547 memset(d
->wmask
+ PCI_PREF_BASE_UPPER32
, 0xff, 8);
549 pci_set_word(d
->wmask
+ PCI_BRIDGE_CONTROL
, 0xffff);
552 static void pci_config_alloc(PCIDevice
*pci_dev
)
554 int config_size
= pci_config_size(pci_dev
);
556 pci_dev
->config
= qemu_mallocz(config_size
);
557 pci_dev
->cmask
= qemu_mallocz(config_size
);
558 pci_dev
->wmask
= qemu_mallocz(config_size
);
559 pci_dev
->used
= qemu_mallocz(config_size
);
562 static void pci_config_free(PCIDevice
*pci_dev
)
564 qemu_free(pci_dev
->config
);
565 qemu_free(pci_dev
->cmask
);
566 qemu_free(pci_dev
->wmask
);
567 qemu_free(pci_dev
->used
);
570 /* -1 for devfn means auto assign */
571 static PCIDevice
*do_pci_register_device(PCIDevice
*pci_dev
, PCIBus
*bus
,
572 const char *name
, int devfn
,
573 PCIConfigReadFunc
*config_read
,
574 PCIConfigWriteFunc
*config_write
,
578 for(devfn
= bus
->devfn_min
; devfn
< ARRAY_SIZE(bus
->devices
);
580 if (!bus
->devices
[devfn
])
583 qemu_error("PCI: no devfn available for %s, all in use\n", name
);
586 } else if (bus
->devices
[devfn
]) {
587 qemu_error("PCI: devfn %d not available for %s, in use by %s\n", devfn
,
588 name
, bus
->devices
[devfn
]->name
);
592 pci_dev
->devfn
= devfn
;
593 pstrcpy(pci_dev
->name
, sizeof(pci_dev
->name
), name
);
594 pci_dev
->irq_state
= 0;
595 pci_config_alloc(pci_dev
);
597 header_type
&= ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
598 if (header_type
== PCI_HEADER_TYPE_NORMAL
) {
599 pci_set_default_subsystem_id(pci_dev
);
601 pci_init_cmask(pci_dev
);
602 pci_init_wmask(pci_dev
);
603 if (header_type
== PCI_HEADER_TYPE_BRIDGE
) {
604 pci_init_wmask_bridge(pci_dev
);
608 config_read
= pci_default_read_config
;
610 config_write
= pci_default_write_config
;
611 pci_dev
->config_read
= config_read
;
612 pci_dev
->config_write
= config_write
;
613 bus
->devices
[devfn
] = pci_dev
;
614 pci_dev
->irq
= qemu_allocate_irqs(pci_set_irq
, pci_dev
, PCI_NUM_PINS
);
615 pci_dev
->version_id
= 2; /* Current pci device vmstate version */
619 PCIDevice
*pci_register_device(PCIBus
*bus
, const char *name
,
620 int instance_size
, int devfn
,
621 PCIConfigReadFunc
*config_read
,
622 PCIConfigWriteFunc
*config_write
)
626 pci_dev
= qemu_mallocz(instance_size
);
627 pci_dev
= do_pci_register_device(pci_dev
, bus
, name
, devfn
,
628 config_read
, config_write
,
629 PCI_HEADER_TYPE_NORMAL
);
630 if (pci_dev
== NULL
) {
631 hw_error("PCI: can't register device\n");
635 static target_phys_addr_t
pci_to_cpu_addr(target_phys_addr_t addr
)
637 return addr
+ pci_mem_base
;
640 static void pci_unregister_io_regions(PCIDevice
*pci_dev
)
645 for(i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
646 r
= &pci_dev
->io_regions
[i
];
647 if (!r
->size
|| r
->addr
== PCI_BAR_UNMAPPED
)
649 if (r
->type
== PCI_BASE_ADDRESS_SPACE_IO
) {
650 isa_unassign_ioport(r
->addr
, r
->filtered_size
);
652 cpu_register_physical_memory(pci_to_cpu_addr(r
->addr
),
659 static int pci_unregister_device(DeviceState
*dev
)
661 PCIDevice
*pci_dev
= DO_UPCAST(PCIDevice
, qdev
, dev
);
662 PCIDeviceInfo
*info
= DO_UPCAST(PCIDeviceInfo
, qdev
, dev
->info
);
666 ret
= info
->exit(pci_dev
);
670 pci_unregister_io_regions(pci_dev
);
672 qemu_free_irqs(pci_dev
->irq
);
673 pci_dev
->bus
->devices
[pci_dev
->devfn
] = NULL
;
674 pci_config_free(pci_dev
);
678 void pci_register_bar(PCIDevice
*pci_dev
, int region_num
,
679 pcibus_t size
, int type
,
680 PCIMapIORegionFunc
*map_func
)
686 if ((unsigned int)region_num
>= PCI_NUM_REGIONS
)
689 if (size
& (size
-1)) {
690 fprintf(stderr
, "ERROR: PCI region size must be pow2 "
691 "type=0x%x, size=0x%"FMT_PCIBUS
"\n", type
, size
);
695 r
= &pci_dev
->io_regions
[region_num
];
696 r
->addr
= PCI_BAR_UNMAPPED
;
698 r
->filtered_size
= size
;
700 r
->map_func
= map_func
;
703 addr
= pci_bar(pci_dev
, region_num
);
704 if (region_num
== PCI_ROM_SLOT
) {
705 /* ROM enable bit is writeable */
706 wmask
|= PCI_ROM_ADDRESS_ENABLE
;
708 pci_set_long(pci_dev
->config
+ addr
, type
);
709 if (!(r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) &&
710 r
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
711 pci_set_quad(pci_dev
->wmask
+ addr
, wmask
);
712 pci_set_quad(pci_dev
->cmask
+ addr
, ~0ULL);
714 pci_set_long(pci_dev
->wmask
+ addr
, wmask
& 0xffffffff);
715 pci_set_long(pci_dev
->cmask
+ addr
, 0xffffffff);
719 static uint32_t pci_config_get_io_base(PCIDevice
*d
,
720 uint32_t base
, uint32_t base_upper16
)
724 val
= ((uint32_t)d
->config
[base
] & PCI_IO_RANGE_MASK
) << 8;
725 if (d
->config
[base
] & PCI_IO_RANGE_TYPE_32
) {
726 val
|= (uint32_t)pci_get_word(d
->config
+ base_upper16
) << 16;
731 static pcibus_t
pci_config_get_memory_base(PCIDevice
*d
, uint32_t base
)
733 return ((pcibus_t
)pci_get_word(d
->config
+ base
) & PCI_MEMORY_RANGE_MASK
)
737 static pcibus_t
pci_config_get_pref_base(PCIDevice
*d
,
738 uint32_t base
, uint32_t upper
)
743 tmp
= (pcibus_t
)pci_get_word(d
->config
+ base
);
744 val
= (tmp
& PCI_PREF_RANGE_MASK
) << 16;
745 if (tmp
& PCI_PREF_RANGE_TYPE_64
) {
746 val
|= (pcibus_t
)pci_get_long(d
->config
+ upper
) << 32;
751 static pcibus_t
pci_bridge_get_base(PCIDevice
*bridge
, uint8_t type
)
754 if (type
& PCI_BASE_ADDRESS_SPACE_IO
) {
755 base
= pci_config_get_io_base(bridge
,
756 PCI_IO_BASE
, PCI_IO_BASE_UPPER16
);
758 if (type
& PCI_BASE_ADDRESS_MEM_PREFETCH
) {
759 base
= pci_config_get_pref_base(
760 bridge
, PCI_PREF_MEMORY_BASE
, PCI_PREF_BASE_UPPER32
);
762 base
= pci_config_get_memory_base(bridge
, PCI_MEMORY_BASE
);
769 static pcibus_t
pci_bridge_get_limit(PCIDevice
*bridge
, uint8_t type
)
772 if (type
& PCI_BASE_ADDRESS_SPACE_IO
) {
773 limit
= pci_config_get_io_base(bridge
,
774 PCI_IO_LIMIT
, PCI_IO_LIMIT_UPPER16
);
775 limit
|= 0xfff; /* PCI bridge spec 3.2.5.6. */
777 if (type
& PCI_BASE_ADDRESS_MEM_PREFETCH
) {
778 limit
= pci_config_get_pref_base(
779 bridge
, PCI_PREF_MEMORY_LIMIT
, PCI_PREF_LIMIT_UPPER32
);
781 limit
= pci_config_get_memory_base(bridge
, PCI_MEMORY_LIMIT
);
783 limit
|= 0xfffff; /* PCI bridge spec 3.2.5.{1, 8}. */
788 static void pci_bridge_filter(PCIDevice
*d
, pcibus_t
*addr
, pcibus_t
*size
,
791 pcibus_t base
= *addr
;
792 pcibus_t limit
= *addr
+ *size
- 1;
795 for (br
= d
->bus
->parent_dev
; br
; br
= br
->bus
->parent_dev
) {
796 uint16_t cmd
= pci_get_word(d
->config
+ PCI_COMMAND
);
798 if (type
& PCI_BASE_ADDRESS_SPACE_IO
) {
799 if (!(cmd
& PCI_COMMAND_IO
)) {
803 if (!(cmd
& PCI_COMMAND_MEMORY
)) {
808 base
= MAX(base
, pci_bridge_get_base(br
, type
));
809 limit
= MIN(limit
, pci_bridge_get_limit(br
, type
));
816 *size
= limit
- base
+ 1;
819 *addr
= PCI_BAR_UNMAPPED
;
823 static pcibus_t
pci_bar_address(PCIDevice
*d
,
824 int reg
, uint8_t type
, pcibus_t size
)
826 pcibus_t new_addr
, last_addr
;
827 int bar
= pci_bar(d
, reg
);
828 uint16_t cmd
= pci_get_word(d
->config
+ PCI_COMMAND
);
830 if (type
& PCI_BASE_ADDRESS_SPACE_IO
) {
831 if (!(cmd
& PCI_COMMAND_IO
)) {
832 return PCI_BAR_UNMAPPED
;
834 new_addr
= pci_get_long(d
->config
+ bar
) & ~(size
- 1);
835 last_addr
= new_addr
+ size
- 1;
836 /* NOTE: we have only 64K ioports on PC */
837 if (last_addr
<= new_addr
|| new_addr
== 0 || last_addr
> UINT16_MAX
) {
838 return PCI_BAR_UNMAPPED
;
843 if (!(cmd
& PCI_COMMAND_MEMORY
)) {
844 return PCI_BAR_UNMAPPED
;
846 if (type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
847 new_addr
= pci_get_quad(d
->config
+ bar
);
849 new_addr
= pci_get_long(d
->config
+ bar
);
851 /* the ROM slot has a specific enable bit */
852 if (reg
== PCI_ROM_SLOT
&& !(new_addr
& PCI_ROM_ADDRESS_ENABLE
)) {
853 return PCI_BAR_UNMAPPED
;
855 new_addr
&= ~(size
- 1);
856 last_addr
= new_addr
+ size
- 1;
857 /* NOTE: we do not support wrapping */
858 /* XXX: as we cannot support really dynamic
859 mappings, we handle specific values as invalid
861 if (last_addr
<= new_addr
|| new_addr
== 0 ||
862 last_addr
== PCI_BAR_UNMAPPED
) {
863 return PCI_BAR_UNMAPPED
;
866 /* Now pcibus_t is 64bit.
867 * Check if 32 bit BAR wraps around explicitly.
868 * Without this, PC ide doesn't work well.
869 * TODO: remove this work around.
871 if (!(type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) && last_addr
>= UINT32_MAX
) {
872 return PCI_BAR_UNMAPPED
;
876 * OS is allowed to set BAR beyond its addressable
877 * bits. For example, 32 bit OS can set 64bit bar
878 * to >4G. Check it. TODO: we might need to support
879 * it in the future for e.g. PAE.
881 if (last_addr
>= TARGET_PHYS_ADDR_MAX
) {
882 return PCI_BAR_UNMAPPED
;
888 static void pci_update_mappings(PCIDevice
*d
)
892 pcibus_t new_addr
, filtered_size
;
894 for(i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
895 r
= &d
->io_regions
[i
];
897 /* this region isn't registered */
901 new_addr
= pci_bar_address(d
, i
, r
->type
, r
->size
);
903 /* bridge filtering */
904 filtered_size
= r
->size
;
905 if (new_addr
!= PCI_BAR_UNMAPPED
) {
906 pci_bridge_filter(d
, &new_addr
, &filtered_size
, r
->type
);
909 /* This bar isn't changed */
910 if (new_addr
== r
->addr
&& filtered_size
== r
->filtered_size
)
913 /* now do the real mapping */
914 if (r
->addr
!= PCI_BAR_UNMAPPED
) {
915 if (r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) {
917 /* NOTE: specific hack for IDE in PC case:
918 only one byte must be mapped. */
919 class = pci_get_word(d
->config
+ PCI_CLASS_DEVICE
);
920 if (class == 0x0101 && r
->size
== 4) {
921 isa_unassign_ioport(r
->addr
+ 2, 1);
923 isa_unassign_ioport(r
->addr
, r
->filtered_size
);
926 cpu_register_physical_memory(pci_to_cpu_addr(r
->addr
),
929 qemu_unregister_coalesced_mmio(r
->addr
, r
->filtered_size
);
933 r
->filtered_size
= filtered_size
;
934 if (r
->addr
!= PCI_BAR_UNMAPPED
) {
936 * TODO: currently almost all the map funcions assumes
937 * filtered_size == size and addr & ~(size - 1) == addr.
938 * However with bridge filtering, they aren't always true.
939 * Teach them such cases, such that filtered_size < size and
940 * addr & (size - 1) != 0.
942 r
->map_func(d
, i
, r
->addr
, r
->filtered_size
, r
->type
);
947 uint32_t pci_default_read_config(PCIDevice
*d
,
948 uint32_t address
, int len
)
951 assert(len
== 1 || len
== 2 || len
== 4);
952 len
= MIN(len
, pci_config_size(d
) - address
);
953 memcpy(&val
, d
->config
+ address
, len
);
954 return le32_to_cpu(val
);
957 void pci_default_write_config(PCIDevice
*d
, uint32_t addr
, uint32_t val
, int l
)
960 uint32_t config_size
= pci_config_size(d
);
962 for (i
= 0; i
< l
&& addr
+ i
< config_size
; val
>>= 8, ++i
) {
963 uint8_t wmask
= d
->wmask
[addr
+ i
];
964 d
->config
[addr
+ i
] = (d
->config
[addr
+ i
] & ~wmask
) | (val
& wmask
);
966 if (ranges_overlap(addr
, l
, PCI_BASE_ADDRESS_0
, 24) ||
967 ranges_overlap(addr
, l
, PCI_ROM_ADDRESS
, 4) ||
968 ranges_overlap(addr
, l
, PCI_ROM_ADDRESS1
, 4) ||
969 range_covers_byte(addr
, l
, PCI_COMMAND
))
970 pci_update_mappings(d
);
973 /***********************************************************/
974 /* generic PCI irq support */
976 /* 0 <= irq_num <= 3. level must be 0 or 1 */
977 static void pci_set_irq(void *opaque
, int irq_num
, int level
)
979 PCIDevice
*pci_dev
= opaque
;
982 change
= level
- pci_irq_state(pci_dev
, irq_num
);
986 pci_set_irq_state(pci_dev
, irq_num
, level
);
987 pci_update_irq_status(pci_dev
);
988 pci_change_irq_level(pci_dev
, irq_num
, change
);
991 /***********************************************************/
992 /* monitor info on PCI */
999 static const pci_class_desc pci_class_descriptions
[] =
1001 { 0x0100, "SCSI controller"},
1002 { 0x0101, "IDE controller"},
1003 { 0x0102, "Floppy controller"},
1004 { 0x0103, "IPI controller"},
1005 { 0x0104, "RAID controller"},
1006 { 0x0106, "SATA controller"},
1007 { 0x0107, "SAS controller"},
1008 { 0x0180, "Storage controller"},
1009 { 0x0200, "Ethernet controller"},
1010 { 0x0201, "Token Ring controller"},
1011 { 0x0202, "FDDI controller"},
1012 { 0x0203, "ATM controller"},
1013 { 0x0280, "Network controller"},
1014 { 0x0300, "VGA controller"},
1015 { 0x0301, "XGA controller"},
1016 { 0x0302, "3D controller"},
1017 { 0x0380, "Display controller"},
1018 { 0x0400, "Video controller"},
1019 { 0x0401, "Audio controller"},
1021 { 0x0480, "Multimedia controller"},
1022 { 0x0500, "RAM controller"},
1023 { 0x0501, "Flash controller"},
1024 { 0x0580, "Memory controller"},
1025 { 0x0600, "Host bridge"},
1026 { 0x0601, "ISA bridge"},
1027 { 0x0602, "EISA bridge"},
1028 { 0x0603, "MC bridge"},
1029 { 0x0604, "PCI bridge"},
1030 { 0x0605, "PCMCIA bridge"},
1031 { 0x0606, "NUBUS bridge"},
1032 { 0x0607, "CARDBUS bridge"},
1033 { 0x0608, "RACEWAY bridge"},
1034 { 0x0680, "Bridge"},
1035 { 0x0c03, "USB controller"},
1039 static void pci_info_device(PCIBus
*bus
, PCIDevice
*d
)
1041 Monitor
*mon
= cur_mon
;
1044 const pci_class_desc
*desc
;
1046 monitor_printf(mon
, " Bus %2d, device %3d, function %d:\n",
1047 pci_bus_num(d
->bus
),
1048 PCI_SLOT(d
->devfn
), PCI_FUNC(d
->devfn
));
1049 class = pci_get_word(d
->config
+ PCI_CLASS_DEVICE
);
1050 monitor_printf(mon
, " ");
1051 desc
= pci_class_descriptions
;
1052 while (desc
->desc
&& class != desc
->class)
1055 monitor_printf(mon
, "%s", desc
->desc
);
1057 monitor_printf(mon
, "Class %04x", class);
1059 monitor_printf(mon
, ": PCI device %04x:%04x\n",
1060 pci_get_word(d
->config
+ PCI_VENDOR_ID
),
1061 pci_get_word(d
->config
+ PCI_DEVICE_ID
));
1063 if (d
->config
[PCI_INTERRUPT_PIN
] != 0) {
1064 monitor_printf(mon
, " IRQ %d.\n",
1065 d
->config
[PCI_INTERRUPT_LINE
]);
1067 if (class == 0x0604) {
1071 monitor_printf(mon
, " BUS %d.\n", d
->config
[0x19]);
1072 monitor_printf(mon
, " secondary bus %d.\n",
1073 d
->config
[PCI_SECONDARY_BUS
]);
1074 monitor_printf(mon
, " subordinate bus %d.\n",
1075 d
->config
[PCI_SUBORDINATE_BUS
]);
1077 base
= pci_bridge_get_base(d
, PCI_BASE_ADDRESS_SPACE_IO
);
1078 limit
= pci_bridge_get_limit(d
, PCI_BASE_ADDRESS_SPACE_IO
);
1079 monitor_printf(mon
, " IO range [0x%04"PRIx64
", 0x%04"PRIx64
"]\n",
1082 base
= pci_bridge_get_base(d
, PCI_BASE_ADDRESS_SPACE_MEMORY
);
1083 limit
= pci_bridge_get_limit(d
, PCI_BASE_ADDRESS_SPACE_MEMORY
);
1085 " memory range [0x%08"PRIx64
", 0x%08"PRIx64
"]\n",
1088 base
= pci_bridge_get_base(d
, PCI_BASE_ADDRESS_SPACE_MEMORY
|
1089 PCI_BASE_ADDRESS_MEM_PREFETCH
);
1090 limit
= pci_bridge_get_limit(d
, PCI_BASE_ADDRESS_SPACE_MEMORY
|
1091 PCI_BASE_ADDRESS_MEM_PREFETCH
);
1092 monitor_printf(mon
, " prefetchable memory range "
1093 "[0x%08"PRIx64
", 0x%08"PRIx64
"]\n", base
, limit
);
1095 for(i
= 0;i
< PCI_NUM_REGIONS
; i
++) {
1096 r
= &d
->io_regions
[i
];
1098 monitor_printf(mon
, " BAR%d: ", i
);
1099 if (r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) {
1100 monitor_printf(mon
, "I/O at 0x%04"FMT_PCIBUS
1101 " [0x%04"FMT_PCIBUS
"].\n",
1102 r
->addr
, r
->addr
+ r
->size
- 1);
1104 const char *type
= r
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
?
1105 "64 bit" : "32 bit";
1106 const char *prefetch
=
1107 r
->type
& PCI_BASE_ADDRESS_MEM_PREFETCH
?
1108 " prefetchable" : "";
1110 monitor_printf(mon
, "%s%s memory at 0x%08"FMT_PCIBUS
1111 " [0x%08"FMT_PCIBUS
"].\n",
1113 r
->addr
, r
->addr
+ r
->size
- 1);
1117 monitor_printf(mon
, " id \"%s\"\n", d
->qdev
.id
? d
->qdev
.id
: "");
1118 if (class == 0x0604 && d
->config
[0x19] != 0) {
1119 pci_for_each_device(bus
, d
->config
[0x19], pci_info_device
);
1123 static void pci_for_each_device_under_bus(PCIBus
*bus
,
1124 void (*fn
)(PCIBus
*b
, PCIDevice
*d
))
1129 for(devfn
= 0; devfn
< ARRAY_SIZE(bus
->devices
); devfn
++) {
1130 d
= bus
->devices
[devfn
];
1136 void pci_for_each_device(PCIBus
*bus
, int bus_num
,
1137 void (*fn
)(PCIBus
*b
, PCIDevice
*d
))
1139 bus
= pci_find_bus(bus
, bus_num
);
1142 pci_for_each_device_under_bus(bus
, fn
);
1146 void pci_info(Monitor
*mon
)
1148 struct PCIHostBus
*host
;
1149 QLIST_FOREACH(host
, &host_buses
, next
) {
1150 pci_for_each_device(host
->bus
, 0, pci_info_device
);
1154 static const char * const pci_nic_models
[] = {
1166 static const char * const pci_nic_names
[] = {
1178 /* Initialize a PCI NIC. */
1179 /* FIXME callers should check for failure, but don't */
1180 PCIDevice
*pci_nic_init(NICInfo
*nd
, const char *default_model
,
1181 const char *default_devaddr
)
1183 const char *devaddr
= nd
->devaddr
? nd
->devaddr
: default_devaddr
;
1190 i
= qemu_find_nic_model(nd
, pci_nic_models
, default_model
);
1194 bus
= pci_get_bus_devfn(&devfn
, devaddr
);
1196 qemu_error("Invalid PCI device address %s for device %s\n",
1197 devaddr
, pci_nic_names
[i
]);
1201 pci_dev
= pci_create(bus
, devfn
, pci_nic_names
[i
]);
1202 dev
= &pci_dev
->qdev
;
1204 dev
->id
= qemu_strdup(nd
->name
);
1205 qdev_set_nic_properties(dev
, nd
);
1206 if (qdev_init(dev
) < 0)
1211 PCIDevice
*pci_nic_init_nofail(NICInfo
*nd
, const char *default_model
,
1212 const char *default_devaddr
)
1216 if (qemu_show_nic_models(nd
->model
, pci_nic_models
))
1219 res
= pci_nic_init(nd
, default_model
, default_devaddr
);
1233 static void pci_bridge_update_mappings_fn(PCIBus
*b
, PCIDevice
*d
)
1235 pci_update_mappings(d
);
1238 static void pci_bridge_update_mappings(PCIBus
*b
)
1242 pci_for_each_device_under_bus(b
, pci_bridge_update_mappings_fn
);
1244 QLIST_FOREACH(child
, &b
->child
, sibling
) {
1245 pci_bridge_update_mappings(child
);
1249 static void pci_bridge_write_config(PCIDevice
*d
,
1250 uint32_t address
, uint32_t val
, int len
)
1252 pci_default_write_config(d
, address
, val
, len
);
1254 if (/* io base/limit */
1255 ranges_overlap(address
, len
, PCI_IO_BASE
, 2) ||
1257 /* memory base/limit, prefetchable base/limit and
1258 io base/limit upper 16 */
1259 ranges_overlap(address
, len
, PCI_MEMORY_BASE
, 20)) {
1260 pci_bridge_update_mappings(d
->bus
);
1264 PCIBus
*pci_find_bus(PCIBus
*bus
, int bus_num
)
1271 if (pci_bus_num(bus
) == bus_num
) {
1276 QLIST_FOREACH(sec
, &bus
->child
, sibling
) {
1278 if (!bus
->parent_dev
/* pci host bridge */
1279 || (pci_bus_num(sec
) <= bus_num
&&
1280 bus
->parent_dev
->config
[PCI_SUBORDINATE_BUS
])) {
1281 return pci_find_bus(sec
, bus_num
);
1288 PCIDevice
*pci_find_device(PCIBus
*bus
, int bus_num
, int slot
, int function
)
1290 bus
= pci_find_bus(bus
, bus_num
);
1295 return bus
->devices
[PCI_DEVFN(slot
, function
)];
1298 static int pci_bridge_initfn(PCIDevice
*dev
)
1300 PCIBridge
*s
= DO_UPCAST(PCIBridge
, dev
, dev
);
1302 pci_config_set_vendor_id(s
->dev
.config
, s
->vid
);
1303 pci_config_set_device_id(s
->dev
.config
, s
->did
);
1305 pci_set_word(dev
->config
+ PCI_STATUS
,
1306 PCI_STATUS_66MHZ
| PCI_STATUS_FAST_BACK
);
1307 pci_config_set_class(dev
->config
, PCI_CLASS_BRIDGE_PCI
);
1308 dev
->config
[PCI_HEADER_TYPE
] = PCI_HEADER_TYPE_BRIDGE
;
1309 pci_set_word(dev
->config
+ PCI_SEC_STATUS
,
1310 PCI_STATUS_66MHZ
| PCI_STATUS_FAST_BACK
);
1314 static int pci_bridge_exitfn(PCIDevice
*pci_dev
)
1316 PCIBridge
*s
= DO_UPCAST(PCIBridge
, dev
, pci_dev
);
1317 PCIBus
*bus
= &s
->bus
;
1318 pci_unregister_secondary_bus(bus
);
1322 PCIBus
*pci_bridge_init(PCIBus
*bus
, int devfn
, uint16_t vid
, uint16_t did
,
1323 pci_map_irq_fn map_irq
, const char *name
)
1328 dev
= pci_create(bus
, devfn
, "pci-bridge");
1329 qdev_prop_set_uint32(&dev
->qdev
, "vendorid", vid
);
1330 qdev_prop_set_uint32(&dev
->qdev
, "deviceid", did
);
1331 qdev_init_nofail(&dev
->qdev
);
1333 s
= DO_UPCAST(PCIBridge
, dev
, dev
);
1334 pci_register_secondary_bus(bus
, &s
->bus
, &s
->dev
, map_irq
, name
);
1338 PCIDevice
*pci_bridge_get_device(PCIBus
*bus
)
1340 return bus
->parent_dev
;
1343 static int pci_qdev_init(DeviceState
*qdev
, DeviceInfo
*base
)
1345 PCIDevice
*pci_dev
= (PCIDevice
*)qdev
;
1346 PCIDeviceInfo
*info
= container_of(base
, PCIDeviceInfo
, qdev
);
1350 /* initialize cap_present for pci_is_express() and pci_config_size() */
1351 if (info
->is_express
) {
1352 pci_dev
->cap_present
|= QEMU_PCI_CAP_EXPRESS
;
1355 bus
= FROM_QBUS(PCIBus
, qdev_get_parent_bus(qdev
));
1356 devfn
= pci_dev
->devfn
;
1357 pci_dev
= do_pci_register_device(pci_dev
, bus
, base
->name
, devfn
,
1358 info
->config_read
, info
->config_write
,
1360 if (pci_dev
== NULL
)
1362 rc
= info
->init(pci_dev
);
1365 if (qdev
->hotplugged
)
1366 bus
->hotplug(pci_dev
, 1);
1370 static int pci_unplug_device(DeviceState
*qdev
)
1372 PCIDevice
*dev
= DO_UPCAST(PCIDevice
, qdev
, qdev
);
1374 dev
->bus
->hotplug(dev
, 0);
1378 void pci_qdev_register(PCIDeviceInfo
*info
)
1380 info
->qdev
.init
= pci_qdev_init
;
1381 info
->qdev
.unplug
= pci_unplug_device
;
1382 info
->qdev
.exit
= pci_unregister_device
;
1383 info
->qdev
.bus_info
= &pci_bus_info
;
1384 qdev_register(&info
->qdev
);
1387 void pci_qdev_register_many(PCIDeviceInfo
*info
)
1389 while (info
->qdev
.name
) {
1390 pci_qdev_register(info
);
1395 PCIDevice
*pci_create(PCIBus
*bus
, int devfn
, const char *name
)
1399 dev
= qdev_create(&bus
->qbus
, name
);
1400 qdev_prop_set_uint32(dev
, "addr", devfn
);
1401 return DO_UPCAST(PCIDevice
, qdev
, dev
);
1404 PCIDevice
*pci_create_simple(PCIBus
*bus
, int devfn
, const char *name
)
1406 PCIDevice
*dev
= pci_create(bus
, devfn
, name
);
1407 qdev_init_nofail(&dev
->qdev
);
1411 static int pci_find_space(PCIDevice
*pdev
, uint8_t size
)
1413 int config_size
= pci_config_size(pdev
);
1414 int offset
= PCI_CONFIG_HEADER_SIZE
;
1416 for (i
= PCI_CONFIG_HEADER_SIZE
; i
< config_size
; ++i
)
1419 else if (i
- offset
+ 1 == size
)
1424 static uint8_t pci_find_capability_list(PCIDevice
*pdev
, uint8_t cap_id
,
1429 if (!(pdev
->config
[PCI_STATUS
] & PCI_STATUS_CAP_LIST
))
1432 for (prev
= PCI_CAPABILITY_LIST
; (next
= pdev
->config
[prev
]);
1433 prev
= next
+ PCI_CAP_LIST_NEXT
)
1434 if (pdev
->config
[next
+ PCI_CAP_LIST_ID
] == cap_id
)
1442 static void pci_map_option_rom(PCIDevice
*pdev
, int region_num
, pcibus_t addr
, pcibus_t size
, int type
)
1444 cpu_register_physical_memory(addr
, size
, pdev
->rom_offset
);
1447 /* Add an option rom for the device */
1448 int pci_add_option_rom(PCIDevice
*pdev
, const char *name
)
1454 path
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, name
);
1456 path
= qemu_strdup(name
);
1459 size
= get_image_size(path
);
1460 if (size
& (size
- 1)) {
1461 size
= 1 << qemu_fls(size
);
1464 pdev
->rom_offset
= qemu_ram_alloc(size
);
1466 ptr
= qemu_get_ram_ptr(pdev
->rom_offset
);
1467 load_image(path
, ptr
);
1470 pci_register_bar(pdev
, PCI_ROM_SLOT
, size
,
1471 0, pci_map_option_rom
);
1476 /* Reserve space and add capability to the linked list in pci config space */
1477 int pci_add_capability(PCIDevice
*pdev
, uint8_t cap_id
, uint8_t size
)
1479 uint8_t offset
= pci_find_space(pdev
, size
);
1480 uint8_t *config
= pdev
->config
+ offset
;
1483 config
[PCI_CAP_LIST_ID
] = cap_id
;
1484 config
[PCI_CAP_LIST_NEXT
] = pdev
->config
[PCI_CAPABILITY_LIST
];
1485 pdev
->config
[PCI_CAPABILITY_LIST
] = offset
;
1486 pdev
->config
[PCI_STATUS
] |= PCI_STATUS_CAP_LIST
;
1487 memset(pdev
->used
+ offset
, 0xFF, size
);
1488 /* Make capability read-only by default */
1489 memset(pdev
->wmask
+ offset
, 0, size
);
1490 /* Check capability by default */
1491 memset(pdev
->cmask
+ offset
, 0xFF, size
);
1495 /* Unlink capability from the pci config space. */
1496 void pci_del_capability(PCIDevice
*pdev
, uint8_t cap_id
, uint8_t size
)
1498 uint8_t prev
, offset
= pci_find_capability_list(pdev
, cap_id
, &prev
);
1501 pdev
->config
[prev
] = pdev
->config
[offset
+ PCI_CAP_LIST_NEXT
];
1502 /* Make capability writeable again */
1503 memset(pdev
->wmask
+ offset
, 0xff, size
);
1504 /* Clear cmask as device-specific registers can't be checked */
1505 memset(pdev
->cmask
+ offset
, 0, size
);
1506 memset(pdev
->used
+ offset
, 0, size
);
1508 if (!pdev
->config
[PCI_CAPABILITY_LIST
])
1509 pdev
->config
[PCI_STATUS
] &= ~PCI_STATUS_CAP_LIST
;
1512 /* Reserve space for capability at a known offset (to call after load). */
1513 void pci_reserve_capability(PCIDevice
*pdev
, uint8_t offset
, uint8_t size
)
1515 memset(pdev
->used
+ offset
, 0xff, size
);
1518 uint8_t pci_find_capability(PCIDevice
*pdev
, uint8_t cap_id
)
1520 return pci_find_capability_list(pdev
, cap_id
, NULL
);
1523 static void pcibus_dev_print(Monitor
*mon
, DeviceState
*dev
, int indent
)
1525 PCIDevice
*d
= (PCIDevice
*)dev
;
1526 const pci_class_desc
*desc
;
1531 class = pci_get_word(d
->config
+ PCI_CLASS_DEVICE
);
1532 desc
= pci_class_descriptions
;
1533 while (desc
->desc
&& class != desc
->class)
1536 snprintf(ctxt
, sizeof(ctxt
), "%s", desc
->desc
);
1538 snprintf(ctxt
, sizeof(ctxt
), "Class %04x", class);
1541 monitor_printf(mon
, "%*sclass %s, addr %02x:%02x.%x, "
1542 "pci id %04x:%04x (sub %04x:%04x)\n",
1544 d
->config
[PCI_SECONDARY_BUS
],
1545 PCI_SLOT(d
->devfn
), PCI_FUNC(d
->devfn
),
1546 pci_get_word(d
->config
+ PCI_VENDOR_ID
),
1547 pci_get_word(d
->config
+ PCI_DEVICE_ID
),
1548 pci_get_word(d
->config
+ PCI_SUBSYSTEM_VENDOR_ID
),
1549 pci_get_word(d
->config
+ PCI_SUBSYSTEM_ID
));
1550 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
1551 r
= &d
->io_regions
[i
];
1554 monitor_printf(mon
, "%*sbar %d: %s at 0x%"FMT_PCIBUS
1555 " [0x%"FMT_PCIBUS
"]\n",
1557 i
, r
->type
& PCI_BASE_ADDRESS_SPACE_IO
? "i/o" : "mem",
1558 r
->addr
, r
->addr
+ r
->size
- 1);
1562 static PCIDeviceInfo bridge_info
= {
1563 .qdev
.name
= "pci-bridge",
1564 .qdev
.size
= sizeof(PCIBridge
),
1565 .init
= pci_bridge_initfn
,
1566 .exit
= pci_bridge_exitfn
,
1567 .config_write
= pci_bridge_write_config
,
1568 .qdev
.props
= (Property
[]) {
1569 DEFINE_PROP_HEX32("vendorid", PCIBridge
, vid
, 0),
1570 DEFINE_PROP_HEX32("deviceid", PCIBridge
, did
, 0),
1571 DEFINE_PROP_END_OF_LIST(),
1575 static void pci_register_devices(void)
1577 pci_qdev_register(&bridge_info
);
1580 device_init(pci_register_devices
)