hw/misc/aspeed_scu.c

   1 /*
   2  * ASPEED System Control Unit
   3  *
   4  * Andrew Jeffery <andrew@aj.id.au>
   5  *
   6  * Copyright 2016 IBM Corp.
   7  *
   8  * This code is licensed under the GPL version 2 or later.  See
   9  * the COPYING file in the top-level directory.
  10  */
  11
  12 #include "qemu/osdep.h"
  13 #include "hw/misc/aspeed_scu.h"
  14 #include "hw/qdev-properties.h"
  15 #include "qapi/error.h"
  16 #include "qapi/visitor.h"
  17 #include "qemu/bitops.h"
  18 #include "qemu/log.h"
  19 #include "trace.h"
  20
  21 #define TO_REG(offset) ((offset) >> 2)
  22
  23 #define PROT_KEY             TO_REG(0x00)
  24 #define SYS_RST_CTRL         TO_REG(0x04)
  25 #define CLK_SEL              TO_REG(0x08)
  26 #define CLK_STOP_CTRL        TO_REG(0x0C)
  27 #define FREQ_CNTR_CTRL       TO_REG(0x10)
  28 #define FREQ_CNTR_EVAL       TO_REG(0x14)
  29 #define IRQ_CTRL             TO_REG(0x18)
  30 #define D2PLL_PARAM          TO_REG(0x1C)
  31 #define MPLL_PARAM           TO_REG(0x20)
  32 #define HPLL_PARAM           TO_REG(0x24)
  33 #define FREQ_CNTR_RANGE      TO_REG(0x28)
  34 #define MISC_CTRL1           TO_REG(0x2C)
  35 #define PCI_CTRL1            TO_REG(0x30)
  36 #define PCI_CTRL2            TO_REG(0x34)
  37 #define PCI_CTRL3            TO_REG(0x38)
  38 #define SYS_RST_STATUS       TO_REG(0x3C)
  39 #define SOC_SCRATCH1         TO_REG(0x40)
  40 #define SOC_SCRATCH2         TO_REG(0x44)
  41 #define MAC_CLK_DELAY        TO_REG(0x48)
  42 #define MISC_CTRL2           TO_REG(0x4C)
  43 #define VGA_SCRATCH1         TO_REG(0x50)
  44 #define VGA_SCRATCH2         TO_REG(0x54)
  45 #define VGA_SCRATCH3         TO_REG(0x58)
  46 #define VGA_SCRATCH4         TO_REG(0x5C)
  47 #define VGA_SCRATCH5         TO_REG(0x60)
  48 #define VGA_SCRATCH6         TO_REG(0x64)
  49 #define VGA_SCRATCH7         TO_REG(0x68)
  50 #define VGA_SCRATCH8         TO_REG(0x6C)
  51 #define HW_STRAP1            TO_REG(0x70)
  52 #define RNG_CTRL             TO_REG(0x74)
  53 #define RNG_DATA             TO_REG(0x78)
  54 #define SILICON_REV          TO_REG(0x7C)
  55 #define PINMUX_CTRL1         TO_REG(0x80)
  56 #define PINMUX_CTRL2         TO_REG(0x84)
  57 #define PINMUX_CTRL3         TO_REG(0x88)
  58 #define PINMUX_CTRL4         TO_REG(0x8C)
  59 #define PINMUX_CTRL5         TO_REG(0x90)
  60 #define PINMUX_CTRL6         TO_REG(0x94)
  61 #define WDT_RST_CTRL         TO_REG(0x9C)
  62 #define PINMUX_CTRL7         TO_REG(0xA0)
  63 #define PINMUX_CTRL8         TO_REG(0xA4)
  64 #define PINMUX_CTRL9         TO_REG(0xA8)
  65 #define WAKEUP_EN            TO_REG(0xC0)
  66 #define WAKEUP_CTRL          TO_REG(0xC4)
  67 #define HW_STRAP2            TO_REG(0xD0)
  68 #define FREE_CNTR4           TO_REG(0xE0)
  69 #define FREE_CNTR4_EXT       TO_REG(0xE4)
  70 #define CPU2_CTRL            TO_REG(0x100)
  71 #define CPU2_BASE_SEG1       TO_REG(0x104)
  72 #define CPU2_BASE_SEG2       TO_REG(0x108)
  73 #define CPU2_BASE_SEG3       TO_REG(0x10C)
  74 #define CPU2_BASE_SEG4       TO_REG(0x110)
  75 #define CPU2_BASE_SEG5       TO_REG(0x114)
  76 #define CPU2_CACHE_CTRL      TO_REG(0x118)
  77 #define UART_HPLL_CLK        TO_REG(0x160)
  78 #define PCIE_CTRL            TO_REG(0x180)
  79 #define BMC_MMIO_CTRL        TO_REG(0x184)
  80 #define RELOC_DECODE_BASE1   TO_REG(0x188)
  81 #define RELOC_DECODE_BASE2   TO_REG(0x18C)
  82 #define MAILBOX_DECODE_BASE  TO_REG(0x190)
  83 #define SRAM_DECODE_BASE1    TO_REG(0x194)
  84 #define SRAM_DECODE_BASE2    TO_REG(0x198)
  85 #define BMC_REV              TO_REG(0x19C)
  86 #define BMC_DEV_ID           TO_REG(0x1A4)
  87
  88 #define PROT_KEY_UNLOCK 0x1688A8A8
  89 #define SCU_IO_REGION_SIZE 0x20000
  90
  91 static const uint32_t ast2400_a0_resets[ASPEED_SCU_NR_REGS] = {
  92      [SYS_RST_CTRL]    = 0xFFCFFEDCU,
  93      [CLK_SEL]         = 0xF3F40000U,
  94      [CLK_STOP_CTRL]   = 0x19FC3E8BU,
  95      [D2PLL_PARAM]     = 0x00026108U,
  96      [MPLL_PARAM]      = 0x00030291U,
  97      [HPLL_PARAM]      = 0x00000291U,
  98      [MISC_CTRL1]      = 0x00000010U,
  99      [PCI_CTRL1]       = 0x20001A03U,
 100      [PCI_CTRL2]       = 0x20001A03U,
 101      [PCI_CTRL3]       = 0x04000030U,
 102      [SYS_RST_STATUS]  = 0x00000001U,
 103      [SOC_SCRATCH1]    = 0x000000C0U, /* SoC completed DRAM init */
 104      [MISC_CTRL2]      = 0x00000023U,
 105      [RNG_CTRL]        = 0x0000000EU,
 106      [PINMUX_CTRL2]    = 0x0000F000U,
 107      [PINMUX_CTRL3]    = 0x01000000U,
 108      [PINMUX_CTRL4]    = 0x000000FFU,
 109      [PINMUX_CTRL5]    = 0x0000A000U,
 110      [WDT_RST_CTRL]    = 0x003FFFF3U,
 111      [PINMUX_CTRL8]    = 0xFFFF0000U,
 112      [PINMUX_CTRL9]    = 0x000FFFFFU,
 113      [FREE_CNTR4]      = 0x000000FFU,
 114      [FREE_CNTR4_EXT]  = 0x000000FFU,
 115      [CPU2_BASE_SEG1]  = 0x80000000U,
 116      [CPU2_BASE_SEG4]  = 0x1E600000U,
 117      [CPU2_BASE_SEG5]  = 0xC0000000U,
 118      [UART_HPLL_CLK]   = 0x00001903U,
 119      [PCIE_CTRL]       = 0x0000007BU,
 120      [BMC_DEV_ID]      = 0x00002402U
 121 };
 122
 123 static uint64_t aspeed_scu_read(void *opaque, hwaddr offset, unsigned size)
 124 {
 125     AspeedSCUState *s = ASPEED_SCU(opaque);
 126     int reg = TO_REG(offset);
 127
 128     if (reg >= ARRAY_SIZE(s->regs)) {
 129         qemu_log_mask(LOG_GUEST_ERROR,
 130                       "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
 131                       __func__, offset);
 132         return 0;
 133     }
 134
 135     switch (reg) {
 136     case WAKEUP_EN:
 137         qemu_log_mask(LOG_GUEST_ERROR,
 138                       "%s: Read of write-only offset 0x%" HWADDR_PRIx "\n",
 139                       __func__, offset);
 140         break;
 141     }
 142
 143     return s->regs[reg];
 144 }
 145
 146 static void aspeed_scu_write(void *opaque, hwaddr offset, uint64_t data,
 147                              unsigned size)
 148 {
 149     AspeedSCUState *s = ASPEED_SCU(opaque);
 150     int reg = TO_REG(offset);
 151
 152     if (reg >= ARRAY_SIZE(s->regs)) {
 153         qemu_log_mask(LOG_GUEST_ERROR,
 154                       "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
 155                       __func__, offset);
 156         return;
 157     }
 158
 159     if (reg > PROT_KEY && reg < CPU2_BASE_SEG1 &&
 160             s->regs[PROT_KEY] != PROT_KEY_UNLOCK) {
 161         qemu_log_mask(LOG_GUEST_ERROR, "%s: SCU is locked!\n", __func__);
 162         return;
 163     }
 164
 165     trace_aspeed_scu_write(offset, size, data);
 166
 167     switch (reg) {
 168     case FREQ_CNTR_EVAL:
 169     case VGA_SCRATCH1 ... VGA_SCRATCH8:
 170     case RNG_DATA:
 171     case SILICON_REV:
 172     case FREE_CNTR4:
 173     case FREE_CNTR4_EXT:
 174         qemu_log_mask(LOG_GUEST_ERROR,
 175                       "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n",
 176                       __func__, offset);
 177         return;
 178     }
 179
 180     s->regs[reg] = data;
 181 }
 182
 183 static const MemoryRegionOps aspeed_scu_ops = {
 184     .read = aspeed_scu_read,
 185     .write = aspeed_scu_write,
 186     .endianness = DEVICE_LITTLE_ENDIAN,
 187     .valid.min_access_size = 4,
 188     .valid.max_access_size = 4,
 189     .valid.unaligned = false,
 190 };
 191
 192 static void aspeed_scu_reset(DeviceState *dev)
 193 {
 194     AspeedSCUState *s = ASPEED_SCU(dev);
 195     const uint32_t *reset;
 196
 197     switch (s->silicon_rev) {
 198     case AST2400_A0_SILICON_REV:
 199         reset = ast2400_a0_resets;
 200         break;
 201     default:
 202         g_assert_not_reached();
 203     }
 204
 205     memcpy(s->regs, reset, sizeof(s->regs));
 206     s->regs[SILICON_REV] = s->silicon_rev;
 207     s->regs[HW_STRAP1] = s->hw_strap1;
 208     s->regs[HW_STRAP2] = s->hw_strap2;
 209 }
 210
 211 static uint32_t aspeed_silicon_revs[] = { AST2400_A0_SILICON_REV, };
 212
 213 bool is_supported_silicon_rev(uint32_t silicon_rev)
 214 {
 215     int i;
 216
 217     for (i = 0; i < ARRAY_SIZE(aspeed_silicon_revs); i++) {
 218         if (silicon_rev == aspeed_silicon_revs[i]) {
 219             return true;
 220         }
 221     }
 222
 223     return false;
 224 }
 225
 226 static void aspeed_scu_realize(DeviceState *dev, Error **errp)
 227 {
 228     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 229     AspeedSCUState *s = ASPEED_SCU(dev);
 230
 231     if (!is_supported_silicon_rev(s->silicon_rev)) {
 232         error_setg(errp, "Unknown silicon revision: 0x%" PRIx32,
 233                 s->silicon_rev);
 234         return;
 235     }
 236
 237     memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_scu_ops, s,
 238                           TYPE_ASPEED_SCU, SCU_IO_REGION_SIZE);
 239
 240     sysbus_init_mmio(sbd, &s->iomem);
 241 }
 242
 243 static const VMStateDescription vmstate_aspeed_scu = {
 244     .name = "aspeed.scu",
 245     .version_id = 1,
 246     .minimum_version_id = 1,
 247     .fields = (VMStateField[]) {
 248         VMSTATE_UINT32_ARRAY(regs, AspeedSCUState, ASPEED_SCU_NR_REGS),
 249         VMSTATE_END_OF_LIST()
 250     }
 251 };
 252
 253 static Property aspeed_scu_properties[] = {
 254     DEFINE_PROP_UINT32("silicon-rev", AspeedSCUState, silicon_rev, 0),
 255     DEFINE_PROP_UINT32("hw-strap1", AspeedSCUState, hw_strap1, 0),
 256     DEFINE_PROP_UINT32("hw-strap2", AspeedSCUState, hw_strap2, 0),
 257     DEFINE_PROP_END_OF_LIST(),
 258 };
 259
 260 static void aspeed_scu_class_init(ObjectClass *klass, void *data)
 261 {
 262     DeviceClass *dc = DEVICE_CLASS(klass);
 263     dc->realize = aspeed_scu_realize;
 264     dc->reset = aspeed_scu_reset;
 265     dc->desc = "ASPEED System Control Unit";
 266     dc->vmsd = &vmstate_aspeed_scu;
 267     dc->props = aspeed_scu_properties;
 268 }
 269
 270 static const TypeInfo aspeed_scu_info = {
 271     .name = TYPE_ASPEED_SCU,
 272     .parent = TYPE_SYS_BUS_DEVICE,
 273     .instance_size = sizeof(AspeedSCUState),
 274     .class_init = aspeed_scu_class_init,
 275 };
 276
 277 static void aspeed_scu_register_types(void)
 278 {
 279     type_register_static(&aspeed_scu_info);
 280 }
 281
 282 type_init(aspeed_scu_register_types);