target-arm/helper.c

   1 #include "cpu.h"
   2 #include "internals.h"
   3 #include "exec/gdbstub.h"
   4 #include "exec/helper-proto.h"
   5 #include "qemu/host-utils.h"
   6 #include "sysemu/arch_init.h"
   7 #include "sysemu/sysemu.h"
   8 #include "qemu/bitops.h"
   9 #include "qemu/crc32c.h"
  10 #include "exec/cpu_ldst.h"
  11 #include "arm_ldst.h"
  12 #include <zlib.h> /* For crc32 */
  13
  14 #ifndef CONFIG_USER_ONLY
  15 static inline int get_phys_addr(CPUARMState *env, target_ulong address,
  16                                 int access_type, ARMMMUIdx mmu_idx,
  17                                 hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
  18                                 target_ulong *page_size);
  19
  20 /* Definitions for the PMCCNTR and PMCR registers */
  21 #define PMCRD   0x8
  22 #define PMCRC   0x4
  23 #define PMCRE   0x1
  24 #endif
  25
  26 static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
  27 {
  28     int nregs;
  29
  30     /* VFP data registers are always little-endian.  */
  31     nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
  32     if (reg < nregs) {
  33         stfq_le_p(buf, env->vfp.regs[reg]);
  34         return 8;
  35     }
  36     if (arm_feature(env, ARM_FEATURE_NEON)) {
  37         /* Aliases for Q regs.  */
  38         nregs += 16;
  39         if (reg < nregs) {
  40             stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
  41             stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
  42             return 16;
  43         }
  44     }
  45     switch (reg - nregs) {
  46     case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
  47     case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
  48     case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
  49     }
  50     return 0;
  51 }
  52
  53 static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
  54 {
  55     int nregs;
  56
  57     nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
  58     if (reg < nregs) {
  59         env->vfp.regs[reg] = ldfq_le_p(buf);
  60         return 8;
  61     }
  62     if (arm_feature(env, ARM_FEATURE_NEON)) {
  63         nregs += 16;
  64         if (reg < nregs) {
  65             env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
  66             env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
  67             return 16;
  68         }
  69     }
  70     switch (reg - nregs) {
  71     case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
  72     case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
  73     case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
  74     }
  75     return 0;
  76 }
  77
  78 static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
  79 {
  80     switch (reg) {
  81     case 0 ... 31:
  82         /* 128 bit FP register */
  83         stfq_le_p(buf, env->vfp.regs[reg * 2]);
  84         stfq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]);
  85         return 16;
  86     case 32:
  87         /* FPSR */
  88         stl_p(buf, vfp_get_fpsr(env));
  89         return 4;
  90     case 33:
  91         /* FPCR */
  92         stl_p(buf, vfp_get_fpcr(env));
  93         return 4;
  94     default:
  95         return 0;
  96     }
  97 }
  98
  99 static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
 100 {
 101     switch (reg) {
 102     case 0 ... 31:
 103         /* 128 bit FP register */
 104         env->vfp.regs[reg * 2] = ldfq_le_p(buf);
 105         env->vfp.regs[reg * 2 + 1] = ldfq_le_p(buf + 8);
 106         return 16;
 107     case 32:
 108         /* FPSR */
 109         vfp_set_fpsr(env, ldl_p(buf));
 110         return 4;
 111     case 33:
 112         /* FPCR */
 113         vfp_set_fpcr(env, ldl_p(buf));
 114         return 4;
 115     default:
 116         return 0;
 117     }
 118 }
 119
 120 static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri)
 121 {
 122     assert(ri->fieldoffset);
 123     if (cpreg_field_is_64bit(ri)) {
 124         return CPREG_FIELD64(env, ri);
 125     } else {
 126         return CPREG_FIELD32(env, ri);
 127     }
 128 }
 129
 130 static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
 131                       uint64_t value)
 132 {
 133     assert(ri->fieldoffset);
 134     if (cpreg_field_is_64bit(ri)) {
 135         CPREG_FIELD64(env, ri) = value;
 136     } else {
 137         CPREG_FIELD32(env, ri) = value;
 138     }
 139 }
 140
 141 static void *raw_ptr(CPUARMState *env, const ARMCPRegInfo *ri)
 142 {
 143     return (char *)env + ri->fieldoffset;
 144 }
 145
 146 static uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri)
 147 {
 148     /* Raw read of a coprocessor register (as needed for migration, etc). */
 149     if (ri->type & ARM_CP_CONST) {
 150         return ri->resetvalue;
 151     } else if (ri->raw_readfn) {
 152         return ri->raw_readfn(env, ri);
 153     } else if (ri->readfn) {
 154         return ri->readfn(env, ri);
 155     } else {
 156         return raw_read(env, ri);
 157     }
 158 }
 159
 160 static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
 161                              uint64_t v)
 162 {
 163     /* Raw write of a coprocessor register (as needed for migration, etc).
 164      * Note that constant registers are treated as write-ignored; the
 165      * caller should check for success by whether a readback gives the
 166      * value written.
 167      */
 168     if (ri->type & ARM_CP_CONST) {
 169         return;
 170     } else if (ri->raw_writefn) {
 171         ri->raw_writefn(env, ri, v);
 172     } else if (ri->writefn) {
 173         ri->writefn(env, ri, v);
 174     } else {
 175         raw_write(env, ri, v);
 176     }
 177 }
 178
 179 static bool raw_accessors_invalid(const ARMCPRegInfo *ri)
 180 {
 181    /* Return true if the regdef would cause an assertion if you called
 182     * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
 183     * program bug for it not to have the NO_RAW flag).
 184     * NB that returning false here doesn't necessarily mean that calling
 185     * read/write_raw_cp_reg() is safe, because we can't distinguish "has
 186     * read/write access functions which are safe for raw use" from "has
 187     * read/write access functions which have side effects but has forgotten
 188     * to provide raw access functions".
 189     * The tests here line up with the conditions in read/write_raw_cp_reg()
 190     * and assertions in raw_read()/raw_write().
 191     */
 192     if ((ri->type & ARM_CP_CONST) ||
 193         ri->fieldoffset ||
 194         ((ri->raw_writefn || ri->writefn) && (ri->raw_readfn || ri->readfn))) {
 195         return false;
 196     }
 197     return true;
 198 }
 199
 200 bool write_cpustate_to_list(ARMCPU *cpu)
 201 {
 202     /* Write the coprocessor state from cpu->env to the (index,value) list. */
 203     int i;
 204     bool ok = true;
 205
 206     for (i = 0; i < cpu->cpreg_array_len; i++) {
 207         uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
 208         const ARMCPRegInfo *ri;
 209
 210         ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 211         if (!ri) {
 212             ok = false;
 213             continue;
 214         }
 215         if (ri->type & ARM_CP_NO_RAW) {
 216             continue;
 217         }
 218         cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri);
 219     }
 220     return ok;
 221 }
 222
 223 bool write_list_to_cpustate(ARMCPU *cpu)
 224 {
 225     int i;
 226     bool ok = true;
 227
 228     for (i = 0; i < cpu->cpreg_array_len; i++) {
 229         uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
 230         uint64_t v = cpu->cpreg_values[i];
 231         const ARMCPRegInfo *ri;
 232
 233         ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 234         if (!ri) {
 235             ok = false;
 236             continue;
 237         }
 238         if (ri->type & ARM_CP_NO_RAW) {
 239             continue;
 240         }
 241         /* Write value and confirm it reads back as written
 242          * (to catch read-only registers and partially read-only
 243          * registers where the incoming migration value doesn't match)
 244          */
 245         write_raw_cp_reg(&cpu->env, ri, v);
 246         if (read_raw_cp_reg(&cpu->env, ri) != v) {
 247             ok = false;
 248         }
 249     }
 250     return ok;
 251 }
 252
 253 static void add_cpreg_to_list(gpointer key, gpointer opaque)
 254 {
 255     ARMCPU *cpu = opaque;
 256     uint64_t regidx;
 257     const ARMCPRegInfo *ri;
 258
 259     regidx = *(uint32_t *)key;
 260     ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 261
 262     if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
 263         cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
 264         /* The value array need not be initialized at this point */
 265         cpu->cpreg_array_len++;
 266     }
 267 }
 268
 269 static void count_cpreg(gpointer key, gpointer opaque)
 270 {
 271     ARMCPU *cpu = opaque;
 272     uint64_t regidx;
 273     const ARMCPRegInfo *ri;
 274
 275     regidx = *(uint32_t *)key;
 276     ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 277
 278     if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
 279         cpu->cpreg_array_len++;
 280     }
 281 }
 282
 283 static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
 284 {
 285     uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a);
 286     uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b);
 287
 288     if (aidx > bidx) {
 289         return 1;
 290     }
 291     if (aidx < bidx) {
 292         return -1;
 293     }
 294     return 0;
 295 }
 296
 297 static void cpreg_make_keylist(gpointer key, gpointer value, gpointer udata)
 298 {
 299     GList **plist = udata;
 300
 301     *plist = g_list_prepend(*plist, key);
 302 }
 303
 304 void init_cpreg_list(ARMCPU *cpu)
 305 {
 306     /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
 307      * Note that we require cpreg_tuples[] to be sorted by key ID.
 308      */
 309     GList *keys = NULL;
 310     int arraylen;
 311
 312     g_hash_table_foreach(cpu->cp_regs, cpreg_make_keylist, &keys);
 313
 314     keys = g_list_sort(keys, cpreg_key_compare);
 315
 316     cpu->cpreg_array_len = 0;
 317
 318     g_list_foreach(keys, count_cpreg, cpu);
 319
 320     arraylen = cpu->cpreg_array_len;
 321     cpu->cpreg_indexes = g_new(uint64_t, arraylen);
 322     cpu->cpreg_values = g_new(uint64_t, arraylen);
 323     cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen);
 324     cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen);
 325     cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
 326     cpu->cpreg_array_len = 0;
 327
 328     g_list_foreach(keys, add_cpreg_to_list, cpu);
 329
 330     assert(cpu->cpreg_array_len == arraylen);
 331
 332     g_list_free(keys);
 333 }
 334
 335 static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 336 {
 337     ARMCPU *cpu = arm_env_get_cpu(env);
 338
 339     raw_write(env, ri, value);
 340     tlb_flush(CPU(cpu), 1); /* Flush TLB as domain not tracked in TLB */
 341 }
 342
 343 static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 344 {
 345     ARMCPU *cpu = arm_env_get_cpu(env);
 346
 347     if (raw_read(env, ri) != value) {
 348         /* Unlike real hardware the qemu TLB uses virtual addresses,
 349          * not modified virtual addresses, so this causes a TLB flush.
 350          */
 351         tlb_flush(CPU(cpu), 1);
 352         raw_write(env, ri, value);
 353     }
 354 }
 355
 356 static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 357                              uint64_t value)
 358 {
 359     ARMCPU *cpu = arm_env_get_cpu(env);
 360
 361     if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_MPU)
 362         && !extended_addresses_enabled(env)) {
 363         /* For VMSA (when not using the LPAE long descriptor page table
 364          * format) this register includes the ASID, so do a TLB flush.
 365          * For PMSA it is purely a process ID and no action is needed.
 366          */
 367         tlb_flush(CPU(cpu), 1);
 368     }
 369     raw_write(env, ri, value);
 370 }
 371
 372 static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
 373                           uint64_t value)
 374 {
 375     /* Invalidate all (TLBIALL) */
 376     ARMCPU *cpu = arm_env_get_cpu(env);
 377
 378     tlb_flush(CPU(cpu), 1);
 379 }
 380
 381 static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
 382                           uint64_t value)
 383 {
 384     /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
 385     ARMCPU *cpu = arm_env_get_cpu(env);
 386
 387     tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
 388 }
 389
 390 static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
 391                            uint64_t value)
 392 {
 393     /* Invalidate by ASID (TLBIASID) */
 394     ARMCPU *cpu = arm_env_get_cpu(env);
 395
 396     tlb_flush(CPU(cpu), value == 0);
 397 }
 398
 399 static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
 400                            uint64_t value)
 401 {
 402     /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
 403     ARMCPU *cpu = arm_env_get_cpu(env);
 404
 405     tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
 406 }
 407
 408 /* IS variants of TLB operations must affect all cores */
 409 static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 410                              uint64_t value)
 411 {
 412     CPUState *other_cs;
 413
 414     CPU_FOREACH(other_cs) {
 415         tlb_flush(other_cs, 1);
 416     }
 417 }
 418
 419 static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 420                              uint64_t value)
 421 {
 422     CPUState *other_cs;
 423
 424     CPU_FOREACH(other_cs) {
 425         tlb_flush(other_cs, value == 0);
 426     }
 427 }
 428
 429 static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 430                              uint64_t value)
 431 {
 432     CPUState *other_cs;
 433
 434     CPU_FOREACH(other_cs) {
 435         tlb_flush_page(other_cs, value & TARGET_PAGE_MASK);
 436     }
 437 }
 438
 439 static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 440                              uint64_t value)
 441 {
 442     CPUState *other_cs;
 443
 444     CPU_FOREACH(other_cs) {
 445         tlb_flush_page(other_cs, value & TARGET_PAGE_MASK);
 446     }
 447 }
 448
 449 static const ARMCPRegInfo cp_reginfo[] = {
 450     /* Define the secure and non-secure FCSE identifier CP registers
 451      * separately because there is no secure bank in V8 (no _EL3).  This allows
 452      * the secure register to be properly reset and migrated. There is also no
 453      * v8 EL1 version of the register so the non-secure instance stands alone.
 454      */
 455     { .name = "FCSEIDR(NS)",
 456       .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0,
 457       .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS,
 458       .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_ns),
 459       .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
 460     { .name = "FCSEIDR(S)",
 461       .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0,
 462       .access = PL1_RW, .secure = ARM_CP_SECSTATE_S,
 463       .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_s),
 464       .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
 465     /* Define the secure and non-secure context identifier CP registers
 466      * separately because there is no secure bank in V8 (no _EL3).  This allows
 467      * the secure register to be properly reset and migrated.  In the
 468      * non-secure case, the 32-bit register will have reset and migration
 469      * disabled during registration as it is handled by the 64-bit instance.
 470      */
 471     { .name = "CONTEXTIDR_EL1", .state = ARM_CP_STATE_BOTH,
 472       .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
 473       .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS,
 474       .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[1]),
 475       .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
 476     { .name = "CONTEXTIDR(S)", .state = ARM_CP_STATE_AA32,
 477       .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
 478       .access = PL1_RW, .secure = ARM_CP_SECSTATE_S,
 479       .fieldoffset = offsetof(CPUARMState, cp15.contextidr_s),
 480       .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
 481     REGINFO_SENTINEL
 482 };
 483
 484 static const ARMCPRegInfo not_v8_cp_reginfo[] = {
 485     /* NB: Some of these registers exist in v8 but with more precise
 486      * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
 487      */
 488     /* MMU Domain access control / MPU write buffer control */
 489     { .name = "DACR",
 490       .cp = 15, .opc1 = CP_ANY, .crn = 3, .crm = CP_ANY, .opc2 = CP_ANY,
 491       .access = PL1_RW, .resetvalue = 0,
 492       .writefn = dacr_write, .raw_writefn = raw_write,
 493       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s),
 494                              offsetoflow32(CPUARMState, cp15.dacr_ns) } },
 495     /* ??? This covers not just the impdef TLB lockdown registers but also
 496      * some v7VMSA registers relating to TEX remap, so it is overly broad.
 497      */
 498     { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = CP_ANY,
 499       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
 500     /* Cache maintenance ops; some of this space may be overridden later. */
 501     { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
 502       .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
 503       .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
 504     REGINFO_SENTINEL
 505 };
 506
 507 static const ARMCPRegInfo not_v6_cp_reginfo[] = {
 508     /* Not all pre-v6 cores implemented this WFI, so this is slightly
 509      * over-broad.
 510      */
 511     { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
 512       .access = PL1_W, .type = ARM_CP_WFI },
 513     REGINFO_SENTINEL
 514 };
 515
 516 static const ARMCPRegInfo not_v7_cp_reginfo[] = {
 517     /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
 518      * is UNPREDICTABLE; we choose to NOP as most implementations do).
 519      */
 520     { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
 521       .access = PL1_W, .type = ARM_CP_WFI },
 522     /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
 523      * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
 524      * OMAPCP will override this space.
 525      */
 526     { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0,
 527       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data),
 528       .resetvalue = 0 },
 529     { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1,
 530       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn),
 531       .resetvalue = 0 },
 532     /* v6 doesn't have the cache ID registers but Linux reads them anyway */
 533     { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
 534       .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
 535       .resetvalue = 0 },
 536     /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
 537      * implementing it as RAZ means the "debug architecture version" bits
 538      * will read as a reserved value, which should cause Linux to not try
 539      * to use the debug hardware.
 540      */
 541     { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
 542       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
 543     /* MMU TLB control. Note that the wildcarding means we cover not just
 544      * the unified TLB ops but also the dside/iside/inner-shareable variants.
 545      */
 546     { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
 547       .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write,
 548       .type = ARM_CP_NO_RAW },
 549     { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY,
 550       .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write,
 551       .type = ARM_CP_NO_RAW },
 552     { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY,
 553       .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write,
 554       .type = ARM_CP_NO_RAW },
 555     { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY,
 556       .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write,
 557       .type = ARM_CP_NO_RAW },
 558     REGINFO_SENTINEL
 559 };
 560
 561 static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 562                         uint64_t value)
 563 {
 564     uint32_t mask = 0;
 565
 566     /* In ARMv8 most bits of CPACR_EL1 are RES0. */
 567     if (!arm_feature(env, ARM_FEATURE_V8)) {
 568         /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
 569          * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
 570          * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
 571          */
 572         if (arm_feature(env, ARM_FEATURE_VFP)) {
 573             /* VFP coprocessor: cp10 & cp11 [23:20] */
 574             mask |= (1 << 31) | (1 << 30) | (0xf << 20);
 575
 576             if (!arm_feature(env, ARM_FEATURE_NEON)) {
 577                 /* ASEDIS [31] bit is RAO/WI */
 578                 value |= (1 << 31);
 579             }
 580
 581             /* VFPv3 and upwards with NEON implement 32 double precision
 582              * registers (D0-D31).
 583              */
 584             if (!arm_feature(env, ARM_FEATURE_NEON) ||
 585                     !arm_feature(env, ARM_FEATURE_VFP3)) {
 586                 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
 587                 value |= (1 << 30);
 588             }
 589         }
 590         value &= mask;
 591     }
 592     env->cp15.cpacr_el1 = value;
 593 }
 594
 595 static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri)
 596 {
 597     if (arm_feature(env, ARM_FEATURE_V8)) {
 598         /* Check if CPACR accesses are to be trapped to EL2 */
 599         if (arm_current_el(env) == 1 &&
 600             (env->cp15.cptr_el[2] & CPTR_TCPAC) && !arm_is_secure(env)) {
 601             return CP_ACCESS_TRAP_EL2;
 602         /* Check if CPACR accesses are to be trapped to EL3 */
 603         } else if (arm_current_el(env) < 3 &&
 604                    (env->cp15.cptr_el[3] & CPTR_TCPAC)) {
 605             return CP_ACCESS_TRAP_EL3;
 606         }
 607     }
 608
 609     return CP_ACCESS_OK;
 610 }
 611
 612 static CPAccessResult cptr_access(CPUARMState *env, const ARMCPRegInfo *ri)
 613 {
 614     /* Check if CPTR accesses are set to trap to EL3 */
 615     if (arm_current_el(env) == 2 && (env->cp15.cptr_el[3] & CPTR_TCPAC)) {
 616         return CP_ACCESS_TRAP_EL3;
 617     }
 618
 619     return CP_ACCESS_OK;
 620 }
 621
 622 static const ARMCPRegInfo v6_cp_reginfo[] = {
 623     /* prefetch by MVA in v6, NOP in v7 */
 624     { .name = "MVA_prefetch",
 625       .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
 626       .access = PL1_W, .type = ARM_CP_NOP },
 627     { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
 628       .access = PL0_W, .type = ARM_CP_NOP },
 629     { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
 630       .access = PL0_W, .type = ARM_CP_NOP },
 631     { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
 632       .access = PL0_W, .type = ARM_CP_NOP },
 633     { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
 634       .access = PL1_RW,
 635       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ifar_s),
 636                              offsetof(CPUARMState, cp15.ifar_ns) },
 637       .resetvalue = 0, },
 638     /* Watchpoint Fault Address Register : should actually only be present
 639      * for 1136, 1176, 11MPCore.
 640      */
 641     { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 642       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
 643     { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
 644       .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access,
 645       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1),
 646       .resetvalue = 0, .writefn = cpacr_write },
 647     REGINFO_SENTINEL
 648 };
 649
 650 static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri)
 651 {
 652     /* Performance monitor registers user accessibility is controlled
 653      * by PMUSERENR.
 654      */
 655     if (arm_current_el(env) == 0 && !env->cp15.c9_pmuserenr) {
 656         return CP_ACCESS_TRAP;
 657     }
 658     return CP_ACCESS_OK;
 659 }
 660
 661 #ifndef CONFIG_USER_ONLY
 662
 663 static inline bool arm_ccnt_enabled(CPUARMState *env)
 664 {
 665     /* This does not support checking PMCCFILTR_EL0 register */
 666
 667     if (!(env->cp15.c9_pmcr & PMCRE)) {
 668         return false;
 669     }
 670
 671     return true;
 672 }
 673
 674 void pmccntr_sync(CPUARMState *env)
 675 {
 676     uint64_t temp_ticks;
 677
 678     temp_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL),
 679                           get_ticks_per_sec(), 1000000);
 680
 681     if (env->cp15.c9_pmcr & PMCRD) {
 682         /* Increment once every 64 processor clock cycles */
 683         temp_ticks /= 64;
 684     }
 685
 686     if (arm_ccnt_enabled(env)) {
 687         env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
 688     }
 689 }
 690
 691 static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 692                        uint64_t value)
 693 {
 694     pmccntr_sync(env);
 695
 696     if (value & PMCRC) {
 697         /* The counter has been reset */
 698         env->cp15.c15_ccnt = 0;
 699     }
 700
 701     /* only the DP, X, D and E bits are writable */
 702     env->cp15.c9_pmcr &= ~0x39;
 703     env->cp15.c9_pmcr |= (value & 0x39);
 704
 705     pmccntr_sync(env);
 706 }
 707
 708 static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 709 {
 710     uint64_t total_ticks;
 711
 712     if (!arm_ccnt_enabled(env)) {
 713         /* Counter is disabled, do not change value */
 714         return env->cp15.c15_ccnt;
 715     }
 716
 717     total_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL),
 718                            get_ticks_per_sec(), 1000000);
 719
 720     if (env->cp15.c9_pmcr & PMCRD) {
 721         /* Increment once every 64 processor clock cycles */
 722         total_ticks /= 64;
 723     }
 724     return total_ticks - env->cp15.c15_ccnt;
 725 }
 726
 727 static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 728                         uint64_t value)
 729 {
 730     uint64_t total_ticks;
 731
 732     if (!arm_ccnt_enabled(env)) {
 733         /* Counter is disabled, set the absolute value */
 734         env->cp15.c15_ccnt = value;
 735         return;
 736     }
 737
 738     total_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL),
 739                            get_ticks_per_sec(), 1000000);
 740
 741     if (env->cp15.c9_pmcr & PMCRD) {
 742         /* Increment once every 64 processor clock cycles */
 743         total_ticks /= 64;
 744     }
 745     env->cp15.c15_ccnt = total_ticks - value;
 746 }
 747
 748 static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri,
 749                             uint64_t value)
 750 {
 751     uint64_t cur_val = pmccntr_read(env, NULL);
 752
 753     pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value));
 754 }
 755
 756 #else /* CONFIG_USER_ONLY */
 757
 758 void pmccntr_sync(CPUARMState *env)
 759 {
 760 }
 761
 762 #endif
 763
 764 static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 765                             uint64_t value)
 766 {
 767     pmccntr_sync(env);
 768     env->cp15.pmccfiltr_el0 = value & 0x7E000000;
 769     pmccntr_sync(env);
 770 }
 771
 772 static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
 773                             uint64_t value)
 774 {
 775     value &= (1 << 31);
 776     env->cp15.c9_pmcnten |= value;
 777 }
 778
 779 static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 780                              uint64_t value)
 781 {
 782     value &= (1 << 31);
 783     env->cp15.c9_pmcnten &= ~value;
 784 }
 785
 786 static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 787                          uint64_t value)
 788 {
 789     env->cp15.c9_pmovsr &= ~value;
 790 }
 791
 792 static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
 793                              uint64_t value)
 794 {
 795     env->cp15.c9_pmxevtyper = value & 0xff;
 796 }
 797
 798 static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 799                             uint64_t value)
 800 {
 801     env->cp15.c9_pmuserenr = value & 1;
 802 }
 803
 804 static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
 805                              uint64_t value)
 806 {
 807     /* We have no event counters so only the C bit can be changed */
 808     value &= (1 << 31);
 809     env->cp15.c9_pminten |= value;
 810 }
 811
 812 static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 813                              uint64_t value)
 814 {
 815     value &= (1 << 31);
 816     env->cp15.c9_pminten &= ~value;
 817 }
 818
 819 static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
 820                        uint64_t value)
 821 {
 822     /* Note that even though the AArch64 view of this register has bits
 823      * [10:0] all RES0 we can only mask the bottom 5, to comply with the
 824      * architectural requirements for bits which are RES0 only in some
 825      * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
 826      * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
 827      */
 828     raw_write(env, ri, value & ~0x1FULL);
 829 }
 830
 831 static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 832 {
 833     /* We only mask off bits that are RES0 both for AArch64 and AArch32.
 834      * For bits that vary between AArch32/64, code needs to check the
 835      * current execution mode before directly using the feature bit.
 836      */
 837     uint32_t valid_mask = SCR_AARCH64_MASK | SCR_AARCH32_MASK;
 838
 839     if (!arm_feature(env, ARM_FEATURE_EL2)) {
 840         valid_mask &= ~SCR_HCE;
 841
 842         /* On ARMv7, SMD (or SCD as it is called in v7) is only
 843          * supported if EL2 exists. The bit is UNK/SBZP when
 844          * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
 845          * when EL2 is unavailable.
 846          * On ARMv8, this bit is always available.
 847          */
 848         if (arm_feature(env, ARM_FEATURE_V7) &&
 849             !arm_feature(env, ARM_FEATURE_V8)) {
 850             valid_mask &= ~SCR_SMD;
 851         }
 852     }
 853
 854     /* Clear all-context RES0 bits.  */
 855     value &= valid_mask;
 856     raw_write(env, ri, value);
 857 }
 858
 859 static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 860 {
 861     ARMCPU *cpu = arm_env_get_cpu(env);
 862
 863     /* Acquire the CSSELR index from the bank corresponding to the CCSIDR
 864      * bank
 865      */
 866     uint32_t index = A32_BANKED_REG_GET(env, csselr,
 867                                         ri->secure & ARM_CP_SECSTATE_S);
 868
 869     return cpu->ccsidr[index];
 870 }
 871
 872 static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 873                          uint64_t value)
 874 {
 875     raw_write(env, ri, value & 0xf);
 876 }
 877
 878 static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 879 {
 880     CPUState *cs = ENV_GET_CPU(env);
 881     uint64_t ret = 0;
 882
 883     if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
 884         ret |= CPSR_I;
 885     }
 886     if (cs->interrupt_request & CPU_INTERRUPT_FIQ) {
 887         ret |= CPSR_F;
 888     }
 889     /* External aborts are not possible in QEMU so A bit is always clear */
 890     return ret;
 891 }
 892
 893 static const ARMCPRegInfo v7_cp_reginfo[] = {
 894     /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
 895     { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
 896       .access = PL1_W, .type = ARM_CP_NOP },
 897     /* Performance monitors are implementation defined in v7,
 898      * but with an ARM recommended set of registers, which we
 899      * follow (although we don't actually implement any counters)
 900      *
 901      * Performance registers fall into three categories:
 902      *  (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
 903      *  (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
 904      *  (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
 905      * For the cases controlled by PMUSERENR we must set .access to PL0_RW
 906      * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
 907      */
 908     { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
 909       .access = PL0_RW, .type = ARM_CP_ALIAS,
 910       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
 911       .writefn = pmcntenset_write,
 912       .accessfn = pmreg_access,
 913       .raw_writefn = raw_write },
 914     { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64,
 915       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1,
 916       .access = PL0_RW, .accessfn = pmreg_access,
 917       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0,
 918       .writefn = pmcntenset_write, .raw_writefn = raw_write },
 919     { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
 920       .access = PL0_RW,
 921       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
 922       .accessfn = pmreg_access,
 923       .writefn = pmcntenclr_write,
 924       .type = ARM_CP_ALIAS },
 925     { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64,
 926       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2,
 927       .access = PL0_RW, .accessfn = pmreg_access,
 928       .type = ARM_CP_ALIAS,
 929       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
 930       .writefn = pmcntenclr_write },
 931     { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
 932       .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
 933       .accessfn = pmreg_access,
 934       .writefn = pmovsr_write,
 935       .raw_writefn = raw_write },
 936     /* Unimplemented so WI. */
 937     { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
 938       .access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP },
 939     /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
 940      * We choose to RAZ/WI.
 941      */
 942     { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
 943       .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
 944       .accessfn = pmreg_access },
 945 #ifndef CONFIG_USER_ONLY
 946     { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
 947       .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO,
 948       .readfn = pmccntr_read, .writefn = pmccntr_write32,
 949       .accessfn = pmreg_access },
 950     { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64,
 951       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0,
 952       .access = PL0_RW, .accessfn = pmreg_access,
 953       .type = ARM_CP_IO,
 954       .readfn = pmccntr_read, .writefn = pmccntr_write, },
 955 #endif
 956     { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64,
 957       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7,
 958       .writefn = pmccfiltr_write,
 959       .access = PL0_RW, .accessfn = pmreg_access,
 960       .type = ARM_CP_IO,
 961       .fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0),
 962       .resetvalue = 0, },
 963     { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
 964       .access = PL0_RW,
 965       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
 966       .accessfn = pmreg_access, .writefn = pmxevtyper_write,
 967       .raw_writefn = raw_write },
 968     /* Unimplemented, RAZ/WI. */
 969     { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
 970       .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
 971       .accessfn = pmreg_access },
 972     { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
 973       .access = PL0_R | PL1_RW,
 974       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
 975       .resetvalue = 0,
 976       .writefn = pmuserenr_write, .raw_writefn = raw_write },
 977     { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
 978       .access = PL1_RW,
 979       .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
 980       .resetvalue = 0,
 981       .writefn = pmintenset_write, .raw_writefn = raw_write },
 982     { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
 983       .access = PL1_RW, .type = ARM_CP_ALIAS,
 984       .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
 985       .resetvalue = 0, .writefn = pmintenclr_write, },
 986     { .name = "VBAR", .state = ARM_CP_STATE_BOTH,
 987       .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
 988       .access = PL1_RW, .writefn = vbar_write,
 989       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s),
 990                              offsetof(CPUARMState, cp15.vbar_ns) },
 991       .resetvalue = 0 },
 992     { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
 993       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
 994       .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_RAW },
 995     { .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
 996       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
 997       .access = PL1_RW, .writefn = csselr_write, .resetvalue = 0,
 998       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s),
 999                              offsetof(CPUARMState, cp15.csselr_ns) } },
1000     /* Auxiliary ID register: this actually has an IMPDEF value but for now
1001      * just RAZ for all cores:
1002      */
1003     { .name = "AIDR", .state = ARM_CP_STATE_BOTH,
1004       .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7,
1005       .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1006     /* Auxiliary fault status registers: these also are IMPDEF, and we
1007      * choose to RAZ/WI for all cores.
1008      */
1009     { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH,
1010       .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0,
1011       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1012     { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH,
1013       .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1,
1014       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1015     /* MAIR can just read-as-written because we don't implement caches
1016      * and so don't need to care about memory attributes.
1017      */
1018     { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64,
1019       .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0,
1020       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]),
1021       .resetvalue = 0 },
1022     /* For non-long-descriptor page tables these are PRRR and NMRR;
1023      * regardless they still act as reads-as-written for QEMU.
1024      * The override is necessary because of the overly-broad TLB_LOCKDOWN
1025      * definition.
1026      */
1027      /* MAIR0/1 are defined separately from their 64-bit counterpart which
1028       * allows them to assign the correct fieldoffset based on the endianness
1029       * handled in the field definitions.
1030       */
1031     { .name = "MAIR0", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE,
1032       .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW,
1033       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair0_s),
1034                              offsetof(CPUARMState, cp15.mair0_ns) },
1035       .resetfn = arm_cp_reset_ignore },
1036     { .name = "MAIR1", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE,
1037       .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW,
1038       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair1_s),
1039                              offsetof(CPUARMState, cp15.mair1_ns) },
1040       .resetfn = arm_cp_reset_ignore },
1041     { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH,
1042       .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0,
1043       .type = ARM_CP_NO_RAW, .access = PL1_R, .readfn = isr_read },
1044     /* 32 bit ITLB invalidates */
1045     { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0,
1046       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write },
1047     { .name = "ITLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1,
1048       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
1049     { .name = "ITLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 2,
1050       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write },
1051     /* 32 bit DTLB invalidates */
1052     { .name = "DTLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 0,
1053       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write },
1054     { .name = "DTLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1,
1055       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
1056     { .name = "DTLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 2,
1057       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write },
1058     /* 32 bit TLB invalidates */
1059     { .name = "TLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
1060       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write },
1061     { .name = "TLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
1062       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
1063     { .name = "TLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
1064       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write },
1065     { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
1066       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write },
1067     REGINFO_SENTINEL
1068 };
1069
1070 static const ARMCPRegInfo v7mp_cp_reginfo[] = {
1071     /* 32 bit TLB invalidates, Inner Shareable */
1072     { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
1073       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_is_write },
1074     { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
1075       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write },
1076     { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
1077       .type = ARM_CP_NO_RAW, .access = PL1_W,
1078       .writefn = tlbiasid_is_write },
1079     { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
1080       .type = ARM_CP_NO_RAW, .access = PL1_W,
1081       .writefn = tlbimvaa_is_write },
1082     REGINFO_SENTINEL
1083 };
1084
1085 static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1086                         uint64_t value)
1087 {
1088     value &= 1;
1089     env->teecr = value;
1090 }
1091
1092 static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri)
1093 {
1094     if (arm_current_el(env) == 0 && (env->teecr & 1)) {
1095         return CP_ACCESS_TRAP;
1096     }
1097     return CP_ACCESS_OK;
1098 }
1099
1100 static const ARMCPRegInfo t2ee_cp_reginfo[] = {
1101     { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
1102       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
1103       .resetvalue = 0,
1104       .writefn = teecr_write },
1105     { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
1106       .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
1107       .accessfn = teehbr_access, .resetvalue = 0 },
1108     REGINFO_SENTINEL
1109 };
1110
1111 static const ARMCPRegInfo v6k_cp_reginfo[] = {
1112     { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64,
1113       .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0,
1114       .access = PL0_RW,
1115       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[0]), .resetvalue = 0 },
1116     { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
1117       .access = PL0_RW,
1118       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrurw_s),
1119                              offsetoflow32(CPUARMState, cp15.tpidrurw_ns) },
1120       .resetfn = arm_cp_reset_ignore },
1121     { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64,
1122       .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
1123       .access = PL0_R|PL1_W,
1124       .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]),
1125       .resetvalue = 0},
1126     { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
1127       .access = PL0_R|PL1_W,
1128       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s),
1129                              offsetoflow32(CPUARMState, cp15.tpidruro_ns) },
1130       .resetfn = arm_cp_reset_ignore },
1131     { .name = "TPIDR_EL1", .state = ARM_CP_STATE_AA64,
1132       .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0,
1133       .access = PL1_RW,
1134       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[1]), .resetvalue = 0 },
1135     { .name = "TPIDRPRW", .opc1 = 0, .cp = 15, .crn = 13, .crm = 0, .opc2 = 4,
1136       .access = PL1_RW,
1137       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrprw_s),
1138                              offsetoflow32(CPUARMState, cp15.tpidrprw_ns) },
1139       .resetvalue = 0 },
1140     REGINFO_SENTINEL
1141 };
1142
1143 #ifndef CONFIG_USER_ONLY
1144
1145 static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri)
1146 {
1147     /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero */
1148     if (arm_current_el(env) == 0 && !extract32(env->cp15.c14_cntkctl, 0, 2)) {
1149         return CP_ACCESS_TRAP;
1150     }
1151     return CP_ACCESS_OK;
1152 }
1153
1154 static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx)
1155 {
1156     /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
1157     if (arm_current_el(env) == 0 &&
1158         !extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
1159         return CP_ACCESS_TRAP;
1160     }
1161     return CP_ACCESS_OK;
1162 }
1163
1164 static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx)
1165 {
1166     /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
1167      * EL0[PV]TEN is zero.
1168      */
1169     if (arm_current_el(env) == 0 &&
1170         !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
1171         return CP_ACCESS_TRAP;
1172     }
1173     return CP_ACCESS_OK;
1174 }
1175
1176 static CPAccessResult gt_pct_access(CPUARMState *env,
1177                                          const ARMCPRegInfo *ri)
1178 {
1179     return gt_counter_access(env, GTIMER_PHYS);
1180 }
1181
1182 static CPAccessResult gt_vct_access(CPUARMState *env,
1183                                          const ARMCPRegInfo *ri)
1184 {
1185     return gt_counter_access(env, GTIMER_VIRT);
1186 }
1187
1188 static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri)
1189 {
1190     return gt_timer_access(env, GTIMER_PHYS);
1191 }
1192
1193 static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri)
1194 {
1195     return gt_timer_access(env, GTIMER_VIRT);
1196 }
1197
1198 static uint64_t gt_get_countervalue(CPUARMState *env)
1199 {
1200     return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE;
1201 }
1202
1203 static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
1204 {
1205     ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
1206
1207     if (gt->ctl & 1) {
1208         /* Timer enabled: calculate and set current ISTATUS, irq, and
1209          * reset timer to when ISTATUS next has to change
1210          */
1211         uint64_t count = gt_get_countervalue(&cpu->env);
1212         /* Note that this must be unsigned 64 bit arithmetic: */
1213         int istatus = count >= gt->cval;
1214         uint64_t nexttick;
1215
1216         gt->ctl = deposit32(gt->ctl, 2, 1, istatus);
1217         qemu_set_irq(cpu->gt_timer_outputs[timeridx],
1218                      (istatus && !(gt->ctl & 2)));
1219         if (istatus) {
1220             /* Next transition is when count rolls back over to zero */
1221             nexttick = UINT64_MAX;
1222         } else {
1223             /* Next transition is when we hit cval */
1224             nexttick = gt->cval;
1225         }
1226         /* Note that the desired next expiry time might be beyond the
1227          * signed-64-bit range of a QEMUTimer -- in this case we just
1228          * set the timer for as far in the future as possible. When the
1229          * timer expires we will reset the timer for any remaining period.
1230          */
1231         if (nexttick > INT64_MAX / GTIMER_SCALE) {
1232             nexttick = INT64_MAX / GTIMER_SCALE;
1233         }
1234         timer_mod(cpu->gt_timer[timeridx], nexttick);
1235     } else {
1236         /* Timer disabled: ISTATUS and timer output always clear */
1237         gt->ctl &= ~4;
1238         qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0);
1239         timer_del(cpu->gt_timer[timeridx]);
1240     }
1241 }
1242
1243 static void gt_cnt_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1244 {
1245     ARMCPU *cpu = arm_env_get_cpu(env);
1246     int timeridx = ri->opc1 & 1;
1247
1248     timer_del(cpu->gt_timer[timeridx]);
1249 }
1250
1251 static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
1252 {
1253     return gt_get_countervalue(env);
1254 }
1255
1256 static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1257                           uint64_t value)
1258 {
1259     int timeridx = ri->opc1 & 1;
1260
1261     env->cp15.c14_timer[timeridx].cval = value;
1262     gt_recalc_timer(arm_env_get_cpu(env), timeridx);
1263 }
1264
1265 static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1266 {
1267     int timeridx = ri->crm & 1;
1268
1269     return (uint32_t)(env->cp15.c14_timer[timeridx].cval -
1270                       gt_get_countervalue(env));
1271 }
1272
1273 static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1274                           uint64_t value)
1275 {
1276     int timeridx = ri->crm & 1;
1277
1278     env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) +
1279                                          sextract64(value, 0, 32);
1280     gt_recalc_timer(arm_env_get_cpu(env), timeridx);
1281 }
1282
1283 static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1284                          uint64_t value)
1285 {
1286     ARMCPU *cpu = arm_env_get_cpu(env);
1287     int timeridx = ri->crm & 1;
1288     uint32_t oldval = env->cp15.c14_timer[timeridx].ctl;
1289
1290     env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value);
1291     if ((oldval ^ value) & 1) {
1292         /* Enable toggled */
1293         gt_recalc_timer(cpu, timeridx);
1294     } else if ((oldval ^ value) & 2) {
1295         /* IMASK toggled: don't need to recalculate,
1296          * just set the interrupt line based on ISTATUS
1297          */
1298         qemu_set_irq(cpu->gt_timer_outputs[timeridx],
1299                      (oldval & 4) && !(value & 2));
1300     }
1301 }
1302
1303 void arm_gt_ptimer_cb(void *opaque)
1304 {
1305     ARMCPU *cpu = opaque;
1306
1307     gt_recalc_timer(cpu, GTIMER_PHYS);
1308 }
1309
1310 void arm_gt_vtimer_cb(void *opaque)
1311 {
1312     ARMCPU *cpu = opaque;
1313
1314     gt_recalc_timer(cpu, GTIMER_VIRT);
1315 }
1316
1317 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1318     /* Note that CNTFRQ is purely reads-as-written for the benefit
1319      * of software; writing it doesn't actually change the timer frequency.
1320      * Our reset value matches the fixed frequency we implement the timer at.
1321      */
1322     { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0,
1323       .type = ARM_CP_ALIAS,
1324       .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
1325       .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq),
1326       .resetfn = arm_cp_reset_ignore,
1327     },
1328     { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64,
1329       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0,
1330       .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
1331       .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq),
1332       .resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE,
1333     },
1334     /* overall control: mostly access permissions */
1335     { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH,
1336       .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0,
1337       .access = PL1_RW,
1338       .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl),
1339       .resetvalue = 0,
1340     },
1341     /* per-timer control */
1342     { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
1343       .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
1344       .accessfn = gt_ptimer_access,
1345       .fieldoffset = offsetoflow32(CPUARMState,
1346                                    cp15.c14_timer[GTIMER_PHYS].ctl),
1347       .resetfn = arm_cp_reset_ignore,
1348       .writefn = gt_ctl_write, .raw_writefn = raw_write,
1349     },
1350     { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64,
1351       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1,
1352       .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1353       .accessfn = gt_ptimer_access,
1354       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
1355       .resetvalue = 0,
1356       .writefn = gt_ctl_write, .raw_writefn = raw_write,
1357     },
1358     { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1,
1359       .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
1360       .accessfn = gt_vtimer_access,
1361       .fieldoffset = offsetoflow32(CPUARMState,
1362                                    cp15.c14_timer[GTIMER_VIRT].ctl),
1363       .resetfn = arm_cp_reset_ignore,
1364       .writefn = gt_ctl_write, .raw_writefn = raw_write,
1365     },
1366     { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64,
1367       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1,
1368       .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1369       .accessfn = gt_vtimer_access,
1370       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
1371       .resetvalue = 0,
1372       .writefn = gt_ctl_write, .raw_writefn = raw_write,
1373     },
1374     /* TimerValue views: a 32 bit downcounting view of the underlying state */
1375     { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
1376       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1377       .accessfn = gt_ptimer_access,
1378       .readfn = gt_tval_read, .writefn = gt_tval_write,
1379     },
1380     { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64,
1381       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0,
1382       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1383       .accessfn = gt_ptimer_access,
1384       .readfn = gt_tval_read, .writefn = gt_tval_write,
1385     },
1386     { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0,
1387       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1388       .accessfn = gt_vtimer_access,
1389       .readfn = gt_tval_read, .writefn = gt_tval_write,
1390     },
1391     { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64,
1392       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0,
1393       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1394       .accessfn = gt_vtimer_access,
1395       .readfn = gt_tval_read, .writefn = gt_tval_write,
1396     },
1397     /* The counter itself */
1398     { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0,
1399       .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
1400       .accessfn = gt_pct_access,
1401       .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
1402     },
1403     { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64,
1404       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1,
1405       .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
1406       .accessfn = gt_pct_access,
1407       .readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
1408     },
1409     { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1,
1410       .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
1411       .accessfn = gt_vct_access,
1412       .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
1413     },
1414     { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64,
1415       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2,
1416       .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
1417       .accessfn = gt_vct_access,
1418       .readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
1419     },
1420     /* Comparison value, indicating when the timer goes off */
1421     { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2,
1422       .access = PL1_RW | PL0_R,
1423       .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
1424       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1425       .accessfn = gt_ptimer_access, .resetfn = arm_cp_reset_ignore,
1426       .writefn = gt_cval_write, .raw_writefn = raw_write,
1427     },
1428     { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64,
1429       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2,
1430       .access = PL1_RW | PL0_R,
1431       .type = ARM_CP_IO,
1432       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1433       .resetvalue = 0, .accessfn = gt_ptimer_access,
1434       .writefn = gt_cval_write, .raw_writefn = raw_write,
1435     },
1436     { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3,
1437       .access = PL1_RW | PL0_R,
1438       .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
1439       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1440       .accessfn = gt_vtimer_access, .resetfn = arm_cp_reset_ignore,
1441       .writefn = gt_cval_write, .raw_writefn = raw_write,
1442     },
1443     { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64,
1444       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2,
1445       .access = PL1_RW | PL0_R,
1446       .type = ARM_CP_IO,
1447       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1448       .resetvalue = 0, .accessfn = gt_vtimer_access,
1449       .writefn = gt_cval_write, .raw_writefn = raw_write,
1450     },
1451     REGINFO_SENTINEL
1452 };
1453
1454 #else
1455 /* In user-mode none of the generic timer registers are accessible,
1456  * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs,
1457  * so instead just don't register any of them.
1458  */
1459 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1460     REGINFO_SENTINEL
1461 };
1462
1463 #endif
1464
1465 static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1466 {
1467     if (arm_feature(env, ARM_FEATURE_LPAE)) {
1468         raw_write(env, ri, value);
1469     } else if (arm_feature(env, ARM_FEATURE_V7)) {
1470         raw_write(env, ri, value & 0xfffff6ff);
1471     } else {
1472         raw_write(env, ri, value & 0xfffff1ff);
1473     }
1474 }
1475
1476 #ifndef CONFIG_USER_ONLY
1477 /* get_phys_addr() isn't present for user-mode-only targets */
1478
1479 static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri)
1480 {
1481     if (ri->opc2 & 4) {
1482         /* Other states are only available with TrustZone; in
1483          * a non-TZ implementation these registers don't exist
1484          * at all, which is an Uncategorized trap. This underdecoding
1485          * is safe because the reginfo is NO_RAW.
1486          */
1487         return CP_ACCESS_TRAP_UNCATEGORIZED;
1488     }
1489     return CP_ACCESS_OK;
1490 }
1491
1492 static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
1493                              int access_type, ARMMMUIdx mmu_idx)
1494 {
1495     hwaddr phys_addr;
1496     target_ulong page_size;
1497     int prot;
1498     int ret;
1499     uint64_t par64;
1500     MemTxAttrs attrs = {};
1501
1502     ret = get_phys_addr(env, value, access_type, mmu_idx,
1503                         &phys_addr, &attrs, &prot, &page_size);
1504     if (extended_addresses_enabled(env)) {
1505         /* ret is a DFSR/IFSR value for the long descriptor
1506          * translation table format, but with WnR always clear.
1507          * Convert it to a 64-bit PAR.
1508          */
1509         par64 = (1 << 11); /* LPAE bit always set */
1510         if (ret == 0) {
1511             par64 |= phys_addr & ~0xfffULL;
1512             if (!attrs.secure) {
1513                 par64 |= (1 << 9); /* NS */
1514             }
1515             /* We don't set the ATTR or SH fields in the PAR. */
1516         } else {
1517             par64 |= 1; /* F */
1518             par64 |= (ret & 0x3f) << 1; /* FS */
1519             /* Note that S2WLK and FSTAGE are always zero, because we don't
1520              * implement virtualization and therefore there can't be a stage 2
1521              * fault.
1522              */
1523         }
1524     } else {
1525         /* ret is a DFSR/IFSR value for the short descriptor
1526          * translation table format (with WnR always clear).
1527          * Convert it to a 32-bit PAR.
1528          */
1529         if (ret == 0) {
1530             /* We do not set any attribute bits in the PAR */
1531             if (page_size == (1 << 24)
1532                 && arm_feature(env, ARM_FEATURE_V7)) {
1533                 par64 = (phys_addr & 0xff000000) | (1 << 1);
1534             } else {
1535                 par64 = phys_addr & 0xfffff000;
1536             }
1537             if (!attrs.secure) {
1538                 par64 |= (1 << 9); /* NS */
1539             }
1540         } else {
1541             par64 = ((ret & (1 << 10)) >> 5) | ((ret & (1 << 12)) >> 6) |
1542                     ((ret & 0xf) << 1) | 1;
1543         }
1544     }
1545     return par64;
1546 }
1547
1548 static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1549 {
1550     int access_type = ri->opc2 & 1;
1551     uint64_t par64;
1552     ARMMMUIdx mmu_idx;
1553     int el = arm_current_el(env);
1554     bool secure = arm_is_secure_below_el3(env);
1555
1556     switch (ri->opc2 & 6) {
1557     case 0:
1558         /* stage 1 current state PL1: ATS1CPR, ATS1CPW */
1559         switch (el) {
1560         case 3:
1561             mmu_idx = ARMMMUIdx_S1E3;
1562             break;
1563         case 2:
1564             mmu_idx = ARMMMUIdx_S1NSE1;
1565             break;
1566         case 1:
1567             mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1;
1568             break;
1569         default:
1570             g_assert_not_reached();
1571         }
1572         break;
1573     case 2:
1574         /* stage 1 current state PL0: ATS1CUR, ATS1CUW */
1575         switch (el) {
1576         case 3:
1577             mmu_idx = ARMMMUIdx_S1SE0;
1578             break;
1579         case 2:
1580             mmu_idx = ARMMMUIdx_S1NSE0;
1581             break;
1582         case 1:
1583             mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0;
1584             break;
1585         default:
1586             g_assert_not_reached();
1587         }
1588         break;
1589     case 4:
1590         /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
1591         mmu_idx = ARMMMUIdx_S12NSE1;
1592         break;
1593     case 6:
1594         /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
1595         mmu_idx = ARMMMUIdx_S12NSE0;
1596         break;
1597     default:
1598         g_assert_not_reached();
1599     }
1600
1601     par64 = do_ats_write(env, value, access_type, mmu_idx);
1602
1603     A32_BANKED_CURRENT_REG_SET(env, par, par64);
1604 }
1605
1606 static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
1607                         uint64_t value)
1608 {
1609     int access_type = ri->opc2 & 1;
1610     ARMMMUIdx mmu_idx;
1611     int secure = arm_is_secure_below_el3(env);
1612
1613     switch (ri->opc2 & 6) {
1614     case 0:
1615         switch (ri->opc1) {
1616         case 0: /* AT S1E1R, AT S1E1W */
1617             mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1;
1618             break;
1619         case 4: /* AT S1E2R, AT S1E2W */
1620             mmu_idx = ARMMMUIdx_S1E2;
1621             break;
1622         case 6: /* AT S1E3R, AT S1E3W */
1623             mmu_idx = ARMMMUIdx_S1E3;
1624             break;
1625         default:
1626             g_assert_not_reached();
1627         }
1628         break;
1629     case 2: /* AT S1E0R, AT S1E0W */
1630         mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0;
1631         break;
1632     case 4: /* AT S12E1R, AT S12E1W */
1633         mmu_idx = ARMMMUIdx_S12NSE1;
1634         break;
1635     case 6: /* AT S12E0R, AT S12E0W */
1636         mmu_idx = ARMMMUIdx_S12NSE0;
1637         break;
1638     default:
1639         g_assert_not_reached();
1640     }
1641
1642     env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx);
1643 }
1644 #endif
1645
1646 static const ARMCPRegInfo vapa_cp_reginfo[] = {
1647     { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
1648       .access = PL1_RW, .resetvalue = 0,
1649       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.par_s),
1650                              offsetoflow32(CPUARMState, cp15.par_ns) },
1651       .writefn = par_write },
1652 #ifndef CONFIG_USER_ONLY
1653     { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
1654       .access = PL1_W, .accessfn = ats_access,
1655       .writefn = ats_write, .type = ARM_CP_NO_RAW },
1656 #endif
1657     REGINFO_SENTINEL
1658 };
1659
1660 /* Return basic MPU access permission bits.  */
1661 static uint32_t simple_mpu_ap_bits(uint32_t val)
1662 {
1663     uint32_t ret;
1664     uint32_t mask;
1665     int i;
1666     ret = 0;
1667     mask = 3;
1668     for (i = 0; i < 16; i += 2) {
1669         ret |= (val >> i) & mask;
1670         mask <<= 2;
1671     }
1672     return ret;
1673 }
1674
1675 /* Pad basic MPU access permission bits to extended format.  */
1676 static uint32_t extended_mpu_ap_bits(uint32_t val)
1677 {
1678     uint32_t ret;
1679     uint32_t mask;
1680     int i;
1681     ret = 0;
1682     mask = 3;
1683     for (i = 0; i < 16; i += 2) {
1684         ret |= (val & mask) << i;
1685         mask <<= 2;
1686     }
1687     return ret;
1688 }
1689
1690 static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
1691                                  uint64_t value)
1692 {
1693     env->cp15.pmsav5_data_ap = extended_mpu_ap_bits(value);
1694 }
1695
1696 static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
1697 {
1698     return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap);
1699 }
1700
1701 static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
1702                                  uint64_t value)
1703 {
1704     env->cp15.pmsav5_insn_ap = extended_mpu_ap_bits(value);
1705 }
1706
1707 static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
1708 {
1709     return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap);
1710 }
1711
1712 static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
1713     { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
1714       .access = PL1_RW, .type = ARM_CP_ALIAS,
1715       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
1716       .resetvalue = 0,
1717       .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
1718     { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
1719       .access = PL1_RW, .type = ARM_CP_ALIAS,
1720       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
1721       .resetvalue = 0,
1722       .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
1723     { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
1724       .access = PL1_RW,
1725       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
1726       .resetvalue = 0, },
1727     { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
1728       .access = PL1_RW,
1729       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
1730       .resetvalue = 0, },
1731     { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
1732       .access = PL1_RW,
1733       .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
1734     { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
1735       .access = PL1_RW,
1736       .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
1737     /* Protection region base and size registers */
1738     { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0,
1739       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1740       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) },
1741     { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0,
1742       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1743       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) },
1744     { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0,
1745       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1746       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) },
1747     { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0,
1748       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1749       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) },
1750     { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0,
1751       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1752       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) },
1753     { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0,
1754       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1755       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) },
1756     { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0,
1757       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1758       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) },
1759     { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0,
1760       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1761       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) },
1762     REGINFO_SENTINEL
1763 };
1764
1765 static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
1766                                  uint64_t value)
1767 {
1768     TCR *tcr = raw_ptr(env, ri);
1769     int maskshift = extract32(value, 0, 3);
1770
1771     if (!arm_feature(env, ARM_FEATURE_V8)) {
1772         if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) {
1773             /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
1774              * using Long-desciptor translation table format */
1775             value &= ~((7 << 19) | (3 << 14) | (0xf << 3));
1776         } else if (arm_feature(env, ARM_FEATURE_EL3)) {
1777             /* In an implementation that includes the Security Extensions
1778              * TTBCR has additional fields PD0 [4] and PD1 [5] for
1779              * Short-descriptor translation table format.
1780              */
1781             value &= TTBCR_PD1 | TTBCR_PD0 | TTBCR_N;
1782         } else {
1783             value &= TTBCR_N;
1784         }
1785     }
1786
1787     /* Update the masks corresponding to the the TCR bank being written
1788      * Note that we always calculate mask and base_mask, but
1789      * they are only used for short-descriptor tables (ie if EAE is 0);
1790      * for long-descriptor tables the TCR fields are used differently
1791      * and the mask and base_mask values are meaningless.
1792      */
1793     tcr->raw_tcr = value;
1794     tcr->mask = ~(((uint32_t)0xffffffffu) >> maskshift);
1795     tcr->base_mask = ~((uint32_t)0x3fffu >> maskshift);
1796 }
1797
1798 static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1799                              uint64_t value)
1800 {
1801     ARMCPU *cpu = arm_env_get_cpu(env);
1802
1803     if (arm_feature(env, ARM_FEATURE_LPAE)) {
1804         /* With LPAE the TTBCR could result in a change of ASID
1805          * via the TTBCR.A1 bit, so do a TLB flush.
1806          */
1807         tlb_flush(CPU(cpu), 1);
1808     }
1809     vmsa_ttbcr_raw_write(env, ri, value);
1810 }
1811
1812 static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1813 {
1814     TCR *tcr = raw_ptr(env, ri);
1815
1816     /* Reset both the TCR as well as the masks corresponding to the bank of
1817      * the TCR being reset.
1818      */
1819     tcr->raw_tcr = 0;
1820     tcr->mask = 0;
1821     tcr->base_mask = 0xffffc000u;
1822 }
1823
1824 static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
1825                                uint64_t value)
1826 {
1827     ARMCPU *cpu = arm_env_get_cpu(env);
1828     TCR *tcr = raw_ptr(env, ri);
1829
1830     /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
1831     tlb_flush(CPU(cpu), 1);
1832     tcr->raw_tcr = value;
1833 }
1834
1835 static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1836                             uint64_t value)
1837 {
1838     /* 64 bit accesses to the TTBRs can change the ASID and so we
1839      * must flush the TLB.
1840      */
1841     if (cpreg_field_is_64bit(ri)) {
1842         ARMCPU *cpu = arm_env_get_cpu(env);
1843
1844         tlb_flush(CPU(cpu), 1);
1845     }
1846     raw_write(env, ri, value);
1847 }
1848
1849 static const ARMCPRegInfo vmsa_cp_reginfo[] = {
1850     { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
1851       .access = PL1_RW, .type = ARM_CP_ALIAS,
1852       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dfsr_s),
1853                              offsetoflow32(CPUARMState, cp15.dfsr_ns) },
1854       .resetfn = arm_cp_reset_ignore, },
1855     { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
1856       .access = PL1_RW, .resetvalue = 0,
1857       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.ifsr_s),
1858                              offsetoflow32(CPUARMState, cp15.ifsr_ns) } },
1859     { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64,
1860       .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0,
1861       .access = PL1_RW,
1862       .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, },
1863     { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
1864       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0,
1865       .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
1866       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
1867                              offsetof(CPUARMState, cp15.ttbr0_ns) } },
1868     { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH,
1869       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1,
1870       .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
1871       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
1872                              offsetof(CPUARMState, cp15.ttbr1_ns) } },
1873     { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64,
1874       .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
1875       .access = PL1_RW, .writefn = vmsa_tcr_el1_write,
1876       .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
1877       .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) },
1878     { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
1879       .access = PL1_RW, .type = ARM_CP_ALIAS, .writefn = vmsa_ttbcr_write,
1880       .resetfn = arm_cp_reset_ignore, .raw_writefn = vmsa_ttbcr_raw_write,
1881       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]),
1882                              offsetoflow32(CPUARMState, cp15.tcr_el[1])} },
1883     { .name = "FAR_EL1", .state = ARM_CP_STATE_AA64,
1884       .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
1885       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]),
1886       .resetvalue = 0, },
1887     { .name = "DFAR", .cp = 15, .opc1 = 0, .crn = 6, .crm = 0, .opc2 = 0,
1888       .access = PL1_RW, .resetvalue = 0,
1889       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.dfar_s),
1890                              offsetof(CPUARMState, cp15.dfar_ns) } },
1891     REGINFO_SENTINEL
1892 };
1893
1894 static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
1895                                 uint64_t value)
1896 {
1897     env->cp15.c15_ticonfig = value & 0xe7;
1898     /* The OS_TYPE bit in this register changes the reported CPUID! */
1899     env->cp15.c0_cpuid = (value & (1 << 5)) ?
1900         ARM_CPUID_TI915T : ARM_CPUID_TI925T;
1901 }
1902
1903 static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,
1904                                 uint64_t value)
1905 {
1906     env->cp15.c15_threadid = value & 0xffff;
1907 }
1908
1909 static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
1910                            uint64_t value)
1911 {
1912     /* Wait-for-interrupt (deprecated) */
1913     cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT);
1914 }
1915
1916 static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
1917                                   uint64_t value)
1918 {
1919     /* On OMAP there are registers indicating the max/min index of dcache lines
1920      * containing a dirty line; cache flush operations have to reset these.
1921      */
1922     env->cp15.c15_i_max = 0x000;
1923     env->cp15.c15_i_min = 0xff0;
1924 }
1925
1926 static const ARMCPRegInfo omap_cp_reginfo[] = {
1927     { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
1928       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
1929       .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]),
1930       .resetvalue = 0, },
1931     { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
1932       .access = PL1_RW, .type = ARM_CP_NOP },
1933     { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
1934       .access = PL1_RW,
1935       .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
1936       .writefn = omap_ticonfig_write },
1937     { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,
1938       .access = PL1_RW,
1939       .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
1940     { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
1941       .access = PL1_RW, .resetvalue = 0xff0,
1942       .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },
1943     { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,
1944       .access = PL1_RW,
1945       .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
1946       .writefn = omap_threadid_write },
1947     { .name = "TI925T_STATUS", .cp = 15, .crn = 15,
1948       .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
1949       .type = ARM_CP_NO_RAW,
1950       .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
1951     /* TODO: Peripheral port remap register:
1952      * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
1953      * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
1954      * when MMU is off.
1955      */
1956     { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
1957       .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
1958       .type = ARM_CP_OVERRIDE | ARM_CP_NO_RAW,
1959       .writefn = omap_cachemaint_write },
1960     { .name = "C9", .cp = 15, .crn = 9,
1961       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
1962       .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
1963     REGINFO_SENTINEL
1964 };
1965
1966 static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
1967                               uint64_t value)
1968 {
1969     env->cp15.c15_cpar = value & 0x3fff;
1970 }
1971
1972 static const ARMCPRegInfo xscale_cp_reginfo[] = {
1973     { .name = "XSCALE_CPAR",
1974       .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
1975       .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
1976       .writefn = xscale_cpar_write, },
1977     { .name = "XSCALE_AUXCR",
1978       .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
1979       .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
1980       .resetvalue = 0, },
1981     /* XScale specific cache-lockdown: since we have no cache we NOP these
1982      * and hope the guest does not really rely on cache behaviour.
1983      */
1984     { .name = "XSCALE_LOCK_ICACHE_LINE",
1985       .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
1986       .access = PL1_W, .type = ARM_CP_NOP },
1987     { .name = "XSCALE_UNLOCK_ICACHE",
1988       .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
1989       .access = PL1_W, .type = ARM_CP_NOP },
1990     { .name = "XSCALE_DCACHE_LOCK",
1991       .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 0,
1992       .access = PL1_RW, .type = ARM_CP_NOP },
1993     { .name = "XSCALE_UNLOCK_DCACHE",
1994       .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1,
1995       .access = PL1_W, .type = ARM_CP_NOP },
1996     REGINFO_SENTINEL
1997 };
1998
1999 static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
2000     /* RAZ/WI the whole crn=15 space, when we don't have a more specific
2001      * implementation of this implementation-defined space.
2002      * Ideally this should eventually disappear in favour of actually
2003      * implementing the correct behaviour for all cores.
2004      */
2005     { .name = "C15_IMPDEF", .cp = 15, .crn = 15,
2006       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
2007       .access = PL1_RW,
2008       .type = ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_OVERRIDE,
2009       .resetvalue = 0 },
2010     REGINFO_SENTINEL
2011 };
2012
2013 static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
2014     /* Cache status: RAZ because we have no cache so it's always clean */
2015     { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
2016       .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2017       .resetvalue = 0 },
2018     REGINFO_SENTINEL
2019 };
2020
2021 static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
2022     /* We never have a a block transfer operation in progress */
2023     { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
2024       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2025       .resetvalue = 0 },
2026     /* The cache ops themselves: these all NOP for QEMU */
2027     { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
2028       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2029     { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
2030       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2031     { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
2032       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2033     { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
2034       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2035     { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
2036       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2037     { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
2038       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2039     REGINFO_SENTINEL
2040 };
2041
2042 static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
2043     /* The cache test-and-clean instructions always return (1 << 30)
2044      * to indicate that there are no dirty cache lines.
2045      */
2046     { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
2047       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2048       .resetvalue = (1 << 30) },
2049     { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
2050       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2051       .resetvalue = (1 << 30) },
2052     REGINFO_SENTINEL
2053 };
2054
2055 static const ARMCPRegInfo strongarm_cp_reginfo[] = {
2056     /* Ignore ReadBuffer accesses */
2057     { .name = "C9_READBUFFER", .cp = 15, .crn = 9,
2058       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
2059       .access = PL1_RW, .resetvalue = 0,
2060       .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_RAW },
2061     REGINFO_SENTINEL
2062 };
2063
2064 static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2065 {
2066     CPUState *cs = CPU(arm_env_get_cpu(env));
2067     uint32_t mpidr = cs->cpu_index;
2068     /* We don't support setting cluster ID ([8..11]) (known as Aff1
2069      * in later ARM ARM versions), or any of the higher affinity level fields,
2070      * so these bits always RAZ.
2071      */
2072     if (arm_feature(env, ARM_FEATURE_V7MP)) {
2073         mpidr |= (1U << 31);
2074         /* Cores which are uniprocessor (non-coherent)
2075          * but still implement the MP extensions set
2076          * bit 30. (For instance, A9UP.) However we do
2077          * not currently model any of those cores.
2078          */
2079     }
2080     return mpidr;
2081 }
2082
2083 static const ARMCPRegInfo mpidr_cp_reginfo[] = {
2084     { .name = "MPIDR", .state = ARM_CP_STATE_BOTH,
2085       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
2086       .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW },
2087     REGINFO_SENTINEL
2088 };
2089
2090 static const ARMCPRegInfo lpae_cp_reginfo[] = {
2091     /* NOP AMAIR0/1: the override is because these clash with the rather
2092      * broadly specified TLB_LOCKDOWN entry in the generic cp_reginfo.
2093      */
2094     { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH,
2095       .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
2096       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
2097       .resetvalue = 0 },
2098     /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
2099     { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
2100       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
2101       .resetvalue = 0 },
2102     { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0,
2103       .access = PL1_RW, .type = ARM_CP_64BIT, .resetvalue = 0,
2104       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.par_s),
2105                              offsetof(CPUARMState, cp15.par_ns)} },
2106     { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0,
2107       .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
2108       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
2109                              offsetof(CPUARMState, cp15.ttbr0_ns) },
2110       .writefn = vmsa_ttbr_write, .resetfn = arm_cp_reset_ignore },
2111     { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
2112       .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
2113       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
2114                              offsetof(CPUARMState, cp15.ttbr1_ns) },
2115       .writefn = vmsa_ttbr_write, .resetfn = arm_cp_reset_ignore },
2116     REGINFO_SENTINEL
2117 };
2118
2119 static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2120 {
2121     return vfp_get_fpcr(env);
2122 }
2123
2124 static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2125                             uint64_t value)
2126 {
2127     vfp_set_fpcr(env, value);
2128 }
2129
2130 static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2131 {
2132     return vfp_get_fpsr(env);
2133 }
2134
2135 static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2136                             uint64_t value)
2137 {
2138     vfp_set_fpsr(env, value);
2139 }
2140
2141 static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri)
2142 {
2143     if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UMA)) {
2144         return CP_ACCESS_TRAP;
2145     }
2146     return CP_ACCESS_OK;
2147 }
2148
2149 static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri,
2150                             uint64_t value)
2151 {
2152     env->daif = value & PSTATE_DAIF;
2153 }
2154
2155 static CPAccessResult aa64_cacheop_access(CPUARMState *env,
2156                                           const ARMCPRegInfo *ri)
2157 {
2158     /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless
2159      * SCTLR_EL1.UCI is set.
2160      */
2161     if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCI)) {
2162         return CP_ACCESS_TRAP;
2163     }
2164     return CP_ACCESS_OK;
2165 }
2166
2167 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
2168  * Page D4-1736 (DDI0487A.b)
2169  */
2170
2171 static void tlbi_aa64_va_write(CPUARMState *env, const ARMCPRegInfo *ri,
2172                                uint64_t value)
2173 {
2174     /* Invalidate by VA (AArch64 version) */
2175     ARMCPU *cpu = arm_env_get_cpu(env);
2176     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2177
2178     tlb_flush_page(CPU(cpu), pageaddr);
2179 }
2180
2181 static void tlbi_aa64_vaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
2182                                 uint64_t value)
2183 {
2184     /* Invalidate by VA, all ASIDs (AArch64 version) */
2185     ARMCPU *cpu = arm_env_get_cpu(env);
2186     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2187
2188     tlb_flush_page(CPU(cpu), pageaddr);
2189 }
2190
2191 static void tlbi_aa64_asid_write(CPUARMState *env, const ARMCPRegInfo *ri,
2192                                  uint64_t value)
2193 {
2194     /* Invalidate by ASID (AArch64 version) */
2195     ARMCPU *cpu = arm_env_get_cpu(env);
2196     int asid = extract64(value, 48, 16);
2197     tlb_flush(CPU(cpu), asid == 0);
2198 }
2199
2200 static void tlbi_aa64_va_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2201                                   uint64_t value)
2202 {
2203     CPUState *other_cs;
2204     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2205
2206     CPU_FOREACH(other_cs) {
2207         tlb_flush_page(other_cs, pageaddr);
2208     }
2209 }
2210
2211 static void tlbi_aa64_vaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2212                                   uint64_t value)
2213 {
2214     CPUState *other_cs;
2215     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2216
2217     CPU_FOREACH(other_cs) {
2218         tlb_flush_page(other_cs, pageaddr);
2219     }
2220 }
2221
2222 static void tlbi_aa64_asid_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2223                                   uint64_t value)
2224 {
2225     CPUState *other_cs;
2226     int asid = extract64(value, 48, 16);
2227
2228     CPU_FOREACH(other_cs) {
2229         tlb_flush(other_cs, asid == 0);
2230     }
2231 }
2232
2233 static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri)
2234 {
2235     /* We don't implement EL2, so the only control on DC ZVA is the
2236      * bit in the SCTLR which can prohibit access for EL0.
2237      */
2238     if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_DZE)) {
2239         return CP_ACCESS_TRAP;
2240     }
2241     return CP_ACCESS_OK;
2242 }
2243
2244 static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri)
2245 {
2246     ARMCPU *cpu = arm_env_get_cpu(env);
2247     int dzp_bit = 1 << 4;
2248
2249     /* DZP indicates whether DC ZVA access is allowed */
2250     if (aa64_zva_access(env, NULL) == CP_ACCESS_OK) {
2251         dzp_bit = 0;
2252     }
2253     return cpu->dcz_blocksize | dzp_bit;
2254 }
2255
2256 static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri)
2257 {
2258     if (!(env->pstate & PSTATE_SP)) {
2259         /* Access to SP_EL0 is undefined if it's being used as
2260          * the stack pointer.
2261          */
2262         return CP_ACCESS_TRAP_UNCATEGORIZED;
2263     }
2264     return CP_ACCESS_OK;
2265 }
2266
2267 static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri)
2268 {
2269     return env->pstate & PSTATE_SP;
2270 }
2271
2272 static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
2273 {
2274     update_spsel(env, val);
2275 }
2276
2277 static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2278                         uint64_t value)
2279 {
2280     ARMCPU *cpu = arm_env_get_cpu(env);
2281
2282     if (raw_read(env, ri) == value) {
2283         /* Skip the TLB flush if nothing actually changed; Linux likes
2284          * to do a lot of pointless SCTLR writes.
2285          */
2286         return;
2287     }
2288
2289     raw_write(env, ri, value);
2290     /* ??? Lots of these bits are not implemented.  */
2291     /* This may enable/disable the MMU, so do a TLB flush.  */
2292     tlb_flush(CPU(cpu), 1);
2293 }
2294
2295 static const ARMCPRegInfo v8_cp_reginfo[] = {
2296     /* Minimal set of EL0-visible registers. This will need to be expanded
2297      * significantly for system emulation of AArch64 CPUs.
2298      */
2299     { .name = "NZCV", .state = ARM_CP_STATE_AA64,
2300       .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2,
2301       .access = PL0_RW, .type = ARM_CP_NZCV },
2302     { .name = "DAIF", .state = ARM_CP_STATE_AA64,
2303       .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2,
2304       .type = ARM_CP_NO_RAW,
2305       .access = PL0_RW, .accessfn = aa64_daif_access,
2306       .fieldoffset = offsetof(CPUARMState, daif),
2307       .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore },
2308     { .name = "FPCR", .state = ARM_CP_STATE_AA64,
2309       .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4,
2310       .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write },
2311     { .name = "FPSR", .state = ARM_CP_STATE_AA64,
2312       .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4,
2313       .access = PL0_RW, .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write },
2314     { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64,
2315       .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0,
2316       .access = PL0_R, .type = ARM_CP_NO_RAW,
2317       .readfn = aa64_dczid_read },
2318     { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64,
2319       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1,
2320       .access = PL0_W, .type = ARM_CP_DC_ZVA,
2321 #ifndef CONFIG_USER_ONLY
2322       /* Avoid overhead of an access check that always passes in user-mode */
2323       .accessfn = aa64_zva_access,
2324 #endif
2325     },
2326     { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64,
2327       .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2,
2328       .access = PL1_R, .type = ARM_CP_CURRENTEL },
2329     /* Cache ops: all NOPs since we don't emulate caches */
2330     { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64,
2331       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
2332       .access = PL1_W, .type = ARM_CP_NOP },
2333     { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64,
2334       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
2335       .access = PL1_W, .type = ARM_CP_NOP },
2336     { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64,
2337       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1,
2338       .access = PL0_W, .type = ARM_CP_NOP,
2339       .accessfn = aa64_cacheop_access },
2340     { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64,
2341       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
2342       .access = PL1_W, .type = ARM_CP_NOP },
2343     { .name = "DC_ISW", .state = ARM_CP_STATE_AA64,
2344       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
2345       .access = PL1_W, .type = ARM_CP_NOP },
2346     { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64,
2347       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1,
2348       .access = PL0_W, .type = ARM_CP_NOP,
2349       .accessfn = aa64_cacheop_access },
2350     { .name = "DC_CSW", .state = ARM_CP_STATE_AA64,
2351       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
2352       .access = PL1_W, .type = ARM_CP_NOP },
2353     { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64,
2354       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1,
2355       .access = PL0_W, .type = ARM_CP_NOP,
2356       .accessfn = aa64_cacheop_access },
2357     { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64,
2358       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1,
2359       .access = PL0_W, .type = ARM_CP_NOP,
2360       .accessfn = aa64_cacheop_access },
2361     { .name = "DC_CISW", .state = ARM_CP_STATE_AA64,
2362       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
2363       .access = PL1_W, .type = ARM_CP_NOP },
2364     /* TLBI operations */
2365     { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
2366       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
2367       .access = PL1_W, .type = ARM_CP_NO_RAW,
2368       .writefn = tlbiall_is_write },
2369     { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
2370       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
2371       .access = PL1_W, .type = ARM_CP_NO_RAW,
2372       .writefn = tlbi_aa64_va_is_write },
2373     { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
2374       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
2375       .access = PL1_W, .type = ARM_CP_NO_RAW,
2376       .writefn = tlbi_aa64_asid_is_write },
2377     { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
2378       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
2379       .access = PL1_W, .type = ARM_CP_NO_RAW,
2380       .writefn = tlbi_aa64_vaa_is_write },
2381     { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
2382       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
2383       .access = PL1_W, .type = ARM_CP_NO_RAW,
2384       .writefn = tlbi_aa64_va_is_write },
2385     { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
2386       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
2387       .access = PL1_W, .type = ARM_CP_NO_RAW,
2388       .writefn = tlbi_aa64_vaa_is_write },
2389     { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
2390       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
2391       .access = PL1_W, .type = ARM_CP_NO_RAW,
2392       .writefn = tlbiall_write },
2393     { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64,
2394       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
2395       .access = PL1_W, .type = ARM_CP_NO_RAW,
2396       .writefn = tlbi_aa64_va_write },
2397     { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64,
2398       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
2399       .access = PL1_W, .type = ARM_CP_NO_RAW,
2400       .writefn = tlbi_aa64_asid_write },
2401     { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64,
2402       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
2403       .access = PL1_W, .type = ARM_CP_NO_RAW,
2404       .writefn = tlbi_aa64_vaa_write },
2405     { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64,
2406       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
2407       .access = PL1_W, .type = ARM_CP_NO_RAW,
2408       .writefn = tlbi_aa64_va_write },
2409     { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64,
2410       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
2411       .access = PL1_W, .type = ARM_CP_NO_RAW,
2412       .writefn = tlbi_aa64_vaa_write },
2413 #ifndef CONFIG_USER_ONLY
2414     /* 64 bit address translation operations */
2415     { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
2416       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0,
2417       .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
2418     { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64,
2419       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1,
2420       .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
2421     { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64,
2422       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2,
2423       .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
2424     { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64,
2425       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3,
2426       .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
2427 #endif
2428     /* TLB invalidate last level of translation table walk */
2429     { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
2430       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write },
2431     { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
2432       .type = ARM_CP_NO_RAW, .access = PL1_W,
2433       .writefn = tlbimvaa_is_write },
2434     { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
2435       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
2436     { .name = "TLBIMVAAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
2437       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write },
2438     /* 32 bit cache operations */
2439     { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
2440       .type = ARM_CP_NOP, .access = PL1_W },
2441     { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6,
2442       .type = ARM_CP_NOP, .access = PL1_W },
2443     { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
2444       .type = ARM_CP_NOP, .access = PL1_W },
2445     { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1,
2446       .type = ARM_CP_NOP, .access = PL1_W },
2447     { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6,
2448       .type = ARM_CP_NOP, .access = PL1_W },
2449     { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7,
2450       .type = ARM_CP_NOP, .access = PL1_W },
2451     { .name = "DCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
2452       .type = ARM_CP_NOP, .access = PL1_W },
2453     { .name = "DCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
2454       .type = ARM_CP_NOP, .access = PL1_W },
2455     { .name = "DCCMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 1,
2456       .type = ARM_CP_NOP, .access = PL1_W },
2457     { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
2458       .type = ARM_CP_NOP, .access = PL1_W },
2459     { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1,
2460       .type = ARM_CP_NOP, .access = PL1_W },
2461     { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1,
2462       .type = ARM_CP_NOP, .access = PL1_W },
2463     { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
2464       .type = ARM_CP_NOP, .access = PL1_W },
2465     /* MMU Domain access control / MPU write buffer control */
2466     { .name = "DACR", .cp = 15, .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0,
2467       .access = PL1_RW, .resetvalue = 0,
2468       .writefn = dacr_write, .raw_writefn = raw_write,
2469       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s),
2470                              offsetoflow32(CPUARMState, cp15.dacr_ns) } },
2471     { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64,
2472       .type = ARM_CP_ALIAS,
2473       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1,
2474       .access = PL1_RW,
2475       .fieldoffset = offsetof(CPUARMState, elr_el[1]) },
2476     { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64,
2477       .type = ARM_CP_ALIAS,
2478       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0,
2479       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[1]) },
2480     /* We rely on the access checks not allowing the guest to write to the
2481      * state field when SPSel indicates that it's being used as the stack
2482      * pointer.
2483      */
2484     { .name = "SP_EL0", .state = ARM_CP_STATE_AA64,
2485       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0,
2486       .access = PL1_RW, .accessfn = sp_el0_access,
2487       .type = ARM_CP_ALIAS,
2488       .fieldoffset = offsetof(CPUARMState, sp_el[0]) },
2489     { .name = "SP_EL1", .state = ARM_CP_STATE_AA64,
2490       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0,
2491       .access = PL2_RW, .type = ARM_CP_ALIAS,
2492       .fieldoffset = offsetof(CPUARMState, sp_el[1]) },
2493     { .name = "SPSel", .state = ARM_CP_STATE_AA64,
2494       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0,
2495       .type = ARM_CP_NO_RAW,
2496       .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write },
2497     REGINFO_SENTINEL
2498 };
2499
2500 /* Used to describe the behaviour of EL2 regs when EL2 does not exist.  */
2501 static const ARMCPRegInfo v8_el3_no_el2_cp_reginfo[] = {
2502     { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
2503       .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
2504       .access = PL2_RW,
2505       .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
2506     { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64,
2507       .type = ARM_CP_NO_RAW,
2508       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
2509       .access = PL2_RW,
2510       .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
2511     { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,
2512       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
2513       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
2514     REGINFO_SENTINEL
2515 };
2516
2517 static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
2518 {
2519     ARMCPU *cpu = arm_env_get_cpu(env);
2520     uint64_t valid_mask = HCR_MASK;
2521
2522     if (arm_feature(env, ARM_FEATURE_EL3)) {
2523         valid_mask &= ~HCR_HCD;
2524     } else {
2525         valid_mask &= ~HCR_TSC;
2526     }
2527
2528     /* Clear RES0 bits.  */
2529     value &= valid_mask;
2530
2531     /* These bits change the MMU setup:
2532      * HCR_VM enables stage 2 translation
2533      * HCR_PTW forbids certain page-table setups
2534      * HCR_DC Disables stage1 and enables stage2 translation
2535      */
2536     if ((raw_read(env, ri) ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) {
2537         tlb_flush(CPU(cpu), 1);
2538     }
2539     raw_write(env, ri, value);
2540 }
2541
2542 static const ARMCPRegInfo v8_el2_cp_reginfo[] = {
2543     { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64,
2544       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
2545       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2),
2546       .writefn = hcr_write },
2547     { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64,
2548       .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0,
2549       .access = PL2_RW, .resetvalue = 0,
2550       .writefn = dacr_write, .raw_writefn = raw_write,
2551       .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) },
2552     { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64,
2553       .type = ARM_CP_ALIAS,
2554       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1,
2555       .access = PL2_RW,
2556       .fieldoffset = offsetof(CPUARMState, elr_el[2]) },
2557     { .name = "ESR_EL2", .state = ARM_CP_STATE_AA64,
2558       .type = ARM_CP_ALIAS,
2559       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0,
2560       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) },
2561     { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64,
2562       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1,
2563       .access = PL2_RW, .resetvalue = 0,
2564       .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) },
2565     { .name = "FAR_EL2", .state = ARM_CP_STATE_AA64,
2566       .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0,
2567       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) },
2568     { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64,
2569       .type = ARM_CP_ALIAS,
2570       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0,
2571       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[6]) },
2572     { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
2573       .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
2574       .access = PL2_RW, .writefn = vbar_write,
2575       .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]),
2576       .resetvalue = 0 },
2577     { .name = "SP_EL2", .state = ARM_CP_STATE_AA64,
2578       .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 1, .opc2 = 0,
2579       .access = PL3_RW, .type = ARM_CP_ALIAS,
2580       .fieldoffset = offsetof(CPUARMState, sp_el[2]) },
2581     { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,
2582       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
2583       .access = PL2_RW, .accessfn = cptr_access, .resetvalue = 0,
2584       .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[2]) },
2585     REGINFO_SENTINEL
2586 };
2587
2588 static const ARMCPRegInfo el3_cp_reginfo[] = {
2589     { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64,
2590       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0,
2591       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3),
2592       .resetvalue = 0, .writefn = scr_write },
2593     { .name = "SCR",  .type = ARM_CP_ALIAS,
2594       .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0,
2595       .access = PL3_RW, .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3),
2596       .resetfn = arm_cp_reset_ignore, .writefn = scr_write },
2597     { .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64,
2598       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1,
2599       .access = PL3_RW, .resetvalue = 0,
2600       .fieldoffset = offsetof(CPUARMState, cp15.sder) },
2601     { .name = "SDER",
2602       .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 1,
2603       .access = PL3_RW, .resetvalue = 0,
2604       .fieldoffset = offsetoflow32(CPUARMState, cp15.sder) },
2605       /* TODO: Implement NSACR trapping of secure EL1 accesses to EL3 */
2606     { .name = "NSACR", .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
2607       .access = PL3_W | PL1_R, .resetvalue = 0,
2608       .fieldoffset = offsetof(CPUARMState, cp15.nsacr) },
2609     { .name = "MVBAR", .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
2610       .access = PL3_RW, .writefn = vbar_write, .resetvalue = 0,
2611       .fieldoffset = offsetof(CPUARMState, cp15.mvbar) },
2612     { .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64,
2613       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0,
2614       .access = PL3_RW, .raw_writefn = raw_write, .writefn = sctlr_write,
2615       .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]) },
2616     { .name = "TTBR0_EL3", .state = ARM_CP_STATE_AA64,
2617       .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 0,
2618       .access = PL3_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
2619       .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[3]) },
2620     { .name = "TCR_EL3", .state = ARM_CP_STATE_AA64,
2621       .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 2,
2622       .access = PL3_RW, .writefn = vmsa_tcr_el1_write,
2623       .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
2624       .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) },
2625     { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64,
2626       .type = ARM_CP_ALIAS,
2627       .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1,
2628       .access = PL3_RW,
2629       .fieldoffset = offsetof(CPUARMState, elr_el[3]) },
2630     { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64,
2631       .type = ARM_CP_ALIAS,
2632       .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0,
2633       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) },
2634     { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64,
2635       .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0,
2636       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) },
2637     { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64,
2638       .type = ARM_CP_ALIAS,
2639       .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0,
2640       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[7]) },
2641     { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64,
2642       .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0,
2643       .access = PL3_RW, .writefn = vbar_write,
2644       .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]),
2645       .resetvalue = 0 },
2646     { .name = "CPTR_EL3", .state = ARM_CP_STATE_AA64,
2647       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 2,
2648       .access = PL3_RW, .accessfn = cptr_access, .resetvalue = 0,
2649       .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[3]) },
2650     REGINFO_SENTINEL
2651 };
2652
2653 static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri)
2654 {
2655     /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64,
2656      * but the AArch32 CTR has its own reginfo struct)
2657      */
2658     if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCT)) {
2659         return CP_ACCESS_TRAP;
2660     }
2661     return CP_ACCESS_OK;
2662 }
2663
2664 static const ARMCPRegInfo debug_cp_reginfo[] = {
2665     /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
2666      * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1;
2667      * unlike DBGDRAR it is never accessible from EL0.
2668      * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64
2669      * accessor.
2670      */
2671     { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
2672       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2673     { .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64,
2674       .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
2675       .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2676     { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
2677       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2678     /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */
2679     { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH,
2680       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
2681       .access = PL1_RW,
2682       .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1),
2683       .resetvalue = 0 },
2684     /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1.
2685      * We don't implement the configurable EL0 access.
2686      */
2687     { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_BOTH,
2688       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
2689       .type = ARM_CP_ALIAS,
2690       .access = PL1_R,
2691       .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1),
2692       .resetfn = arm_cp_reset_ignore },
2693     /* We define a dummy WI OSLAR_EL1, because Linux writes to it. */
2694     { .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH,
2695       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
2696       .access = PL1_W, .type = ARM_CP_NOP },
2697     /* Dummy OSDLR_EL1: 32-bit Linux will read this */
2698     { .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH,
2699       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4,
2700       .access = PL1_RW, .type = ARM_CP_NOP },
2701     /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't
2702      * implement vector catch debug events yet.
2703      */
2704     { .name = "DBGVCR",
2705       .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
2706       .access = PL1_RW, .type = ARM_CP_NOP },
2707     REGINFO_SENTINEL
2708 };
2709
2710 static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
2711     /* 64 bit access versions of the (dummy) debug registers */
2712     { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
2713       .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
2714     { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
2715       .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
2716     REGINFO_SENTINEL
2717 };
2718
2719 void hw_watchpoint_update(ARMCPU *cpu, int n)
2720 {
2721     CPUARMState *env = &cpu->env;
2722     vaddr len = 0;
2723     vaddr wvr = env->cp15.dbgwvr[n];
2724     uint64_t wcr = env->cp15.dbgwcr[n];
2725     int mask;
2726     int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
2727
2728     if (env->cpu_watchpoint[n]) {
2729         cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]);
2730         env->cpu_watchpoint[n] = NULL;
2731     }
2732
2733     if (!extract64(wcr, 0, 1)) {
2734         /* E bit clear : watchpoint disabled */
2735         return;
2736     }
2737
2738     switch (extract64(wcr, 3, 2)) {
2739     case 0:
2740         /* LSC 00 is reserved and must behave as if the wp is disabled */
2741         return;
2742     case 1:
2743         flags |= BP_MEM_READ;
2744         break;
2745     case 2:
2746         flags |= BP_MEM_WRITE;
2747         break;
2748     case 3:
2749         flags |= BP_MEM_ACCESS;
2750         break;
2751     }
2752
2753     /* Attempts to use both MASK and BAS fields simultaneously are
2754      * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
2755      * thus generating a watchpoint for every byte in the masked region.
2756      */
2757     mask = extract64(wcr, 24, 4);
2758     if (mask == 1 || mask == 2) {
2759         /* Reserved values of MASK; we must act as if the mask value was
2760          * some non-reserved value, or as if the watchpoint were disabled.
2761          * We choose the latter.
2762          */
2763         return;
2764     } else if (mask) {
2765         /* Watchpoint covers an aligned area up to 2GB in size */
2766         len = 1ULL << mask;
2767         /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE
2768          * whether the watchpoint fires when the unmasked bits match; we opt
2769          * to generate the exceptions.
2770          */
2771         wvr &= ~(len - 1);
2772     } else {
2773         /* Watchpoint covers bytes defined by the byte address select bits */
2774         int bas = extract64(wcr, 5, 8);
2775         int basstart;
2776
2777         if (bas == 0) {
2778             /* This must act as if the watchpoint is disabled */
2779             return;
2780         }
2781
2782         if (extract64(wvr, 2, 1)) {
2783             /* Deprecated case of an only 4-aligned address. BAS[7:4] are
2784              * ignored, and BAS[3:0] define which bytes to watch.
2785              */
2786             bas &= 0xf;
2787         }
2788         /* The BAS bits are supposed to be programmed to indicate a contiguous
2789          * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether
2790          * we fire for each byte in the word/doubleword addressed by the WVR.
2791          * We choose to ignore any non-zero bits after the first range of 1s.
2792          */
2793         basstart = ctz32(bas);
2794         len = cto32(bas >> basstart);
2795         wvr += basstart;
2796     }
2797
2798     cpu_watchpoint_insert(CPU(cpu), wvr, len, flags,
2799                           &env->cpu_watchpoint[n]);
2800 }
2801
2802 void hw_watchpoint_update_all(ARMCPU *cpu)
2803 {
2804     int i;
2805     CPUARMState *env = &cpu->env;
2806
2807     /* Completely clear out existing QEMU watchpoints and our array, to
2808      * avoid possible stale entries following migration load.
2809      */
2810     cpu_watchpoint_remove_all(CPU(cpu), BP_CPU);
2811     memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint));
2812
2813     for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) {
2814         hw_watchpoint_update(cpu, i);
2815     }
2816 }
2817
2818 static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2819                          uint64_t value)
2820 {
2821     ARMCPU *cpu = arm_env_get_cpu(env);
2822     int i = ri->crm;
2823
2824     /* Bits [63:49] are hardwired to the value of bit [48]; that is, the
2825      * register reads and behaves as if values written are sign extended.
2826      * Bits [1:0] are RES0.
2827      */
2828     value = sextract64(value, 0, 49) & ~3ULL;
2829
2830     raw_write(env, ri, value);
2831     hw_watchpoint_update(cpu, i);
2832 }
2833
2834 static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2835                          uint64_t value)
2836 {
2837     ARMCPU *cpu = arm_env_get_cpu(env);
2838     int i = ri->crm;
2839
2840     raw_write(env, ri, value);
2841     hw_watchpoint_update(cpu, i);
2842 }
2843
2844 void hw_breakpoint_update(ARMCPU *cpu, int n)
2845 {
2846     CPUARMState *env = &cpu->env;
2847     uint64_t bvr = env->cp15.dbgbvr[n];
2848     uint64_t bcr = env->cp15.dbgbcr[n];
2849     vaddr addr;
2850     int bt;
2851     int flags = BP_CPU;
2852
2853     if (env->cpu_breakpoint[n]) {
2854         cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]);
2855         env->cpu_breakpoint[n] = NULL;
2856     }
2857
2858     if (!extract64(bcr, 0, 1)) {
2859         /* E bit clear : watchpoint disabled */
2860         return;
2861     }
2862
2863     bt = extract64(bcr, 20, 4);
2864
2865     switch (bt) {
2866     case 4: /* unlinked address mismatch (reserved if AArch64) */
2867     case 5: /* linked address mismatch (reserved if AArch64) */
2868         qemu_log_mask(LOG_UNIMP,
2869                       "arm: address mismatch breakpoint types not implemented");
2870         return;
2871     case 0: /* unlinked address match */
2872     case 1: /* linked address match */
2873     {
2874         /* Bits [63:49] are hardwired to the value of bit [48]; that is,
2875          * we behave as if the register was sign extended. Bits [1:0] are
2876          * RES0. The BAS field is used to allow setting breakpoints on 16
2877          * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether
2878          * a bp will fire if the addresses covered by the bp and the addresses
2879          * covered by the insn overlap but the insn doesn't start at the
2880          * start of the bp address range. We choose to require the insn and
2881          * the bp to have the same address. The constraints on writing to
2882          * BAS enforced in dbgbcr_write mean we have only four cases:
2883          *  0b0000  => no breakpoint
2884          *  0b0011  => breakpoint on addr
2885          *  0b1100  => breakpoint on addr + 2
2886          *  0b1111  => breakpoint on addr
2887          * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
2888          */
2889         int bas = extract64(bcr, 5, 4);
2890         addr = sextract64(bvr, 0, 49) & ~3ULL;
2891         if (bas == 0) {
2892             return;
2893         }
2894         if (bas == 0xc) {
2895             addr += 2;
2896         }
2897         break;
2898     }
2899     case 2: /* unlinked context ID match */
2900     case 8: /* unlinked VMID match (reserved if no EL2) */
2901     case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
2902         qemu_log_mask(LOG_UNIMP,
2903                       "arm: unlinked context breakpoint types not implemented");
2904         return;
2905     case 9: /* linked VMID match (reserved if no EL2) */
2906     case 11: /* linked context ID and VMID match (reserved if no EL2) */
2907     case 3: /* linked context ID match */
2908     default:
2909         /* We must generate no events for Linked context matches (unless
2910          * they are linked to by some other bp/wp, which is handled in
2911          * updates for the linking bp/wp). We choose to also generate no events
2912          * for reserved values.
2913          */
2914         return;
2915     }
2916
2917     cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]);
2918 }
2919
2920 void hw_breakpoint_update_all(ARMCPU *cpu)
2921 {
2922     int i;
2923     CPUARMState *env = &cpu->env;
2924
2925     /* Completely clear out existing QEMU breakpoints and our array, to
2926      * avoid possible stale entries following migration load.
2927      */
2928     cpu_breakpoint_remove_all(CPU(cpu), BP_CPU);
2929     memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint));
2930
2931     for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) {
2932         hw_breakpoint_update(cpu, i);
2933     }
2934 }
2935
2936 static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2937                          uint64_t value)
2938 {
2939     ARMCPU *cpu = arm_env_get_cpu(env);
2940     int i = ri->crm;
2941
2942     raw_write(env, ri, value);
2943     hw_breakpoint_update(cpu, i);
2944 }
2945
2946 static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2947                          uint64_t value)
2948 {
2949     ARMCPU *cpu = arm_env_get_cpu(env);
2950     int i = ri->crm;
2951
2952     /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only
2953      * copy of BAS[0].
2954      */
2955     value = deposit64(value, 6, 1, extract64(value, 5, 1));
2956     value = deposit64(value, 8, 1, extract64(value, 7, 1));
2957
2958     raw_write(env, ri, value);
2959     hw_breakpoint_update(cpu, i);
2960 }
2961
2962 static void define_debug_regs(ARMCPU *cpu)
2963 {
2964     /* Define v7 and v8 architectural debug registers.
2965      * These are just dummy implementations for now.
2966      */
2967     int i;
2968     int wrps, brps, ctx_cmps;
2969     ARMCPRegInfo dbgdidr = {
2970         .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
2971         .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = cpu->dbgdidr,
2972     };
2973
2974     /* Note that all these register fields hold "number of Xs minus 1". */
2975     brps = extract32(cpu->dbgdidr, 24, 4);
2976     wrps = extract32(cpu->dbgdidr, 28, 4);
2977     ctx_cmps = extract32(cpu->dbgdidr, 20, 4);
2978
2979     assert(ctx_cmps <= brps);
2980
2981     /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties
2982      * of the debug registers such as number of breakpoints;
2983      * check that if they both exist then they agree.
2984      */
2985     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
2986         assert(extract32(cpu->id_aa64dfr0, 12, 4) == brps);
2987         assert(extract32(cpu->id_aa64dfr0, 20, 4) == wrps);
2988         assert(extract32(cpu->id_aa64dfr0, 28, 4) == ctx_cmps);
2989     }
2990
2991     define_one_arm_cp_reg(cpu, &dbgdidr);
2992     define_arm_cp_regs(cpu, debug_cp_reginfo);
2993
2994     if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) {
2995         define_arm_cp_regs(cpu, debug_lpae_cp_reginfo);
2996     }
2997
2998     for (i = 0; i < brps + 1; i++) {
2999         ARMCPRegInfo dbgregs[] = {
3000             { .name = "DBGBVR", .state = ARM_CP_STATE_BOTH,
3001               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4,
3002               .access = PL1_RW,
3003               .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]),
3004               .writefn = dbgbvr_write, .raw_writefn = raw_write
3005             },
3006             { .name = "DBGBCR", .state = ARM_CP_STATE_BOTH,
3007               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5,
3008               .access = PL1_RW,
3009               .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]),
3010               .writefn = dbgbcr_write, .raw_writefn = raw_write
3011             },
3012             REGINFO_SENTINEL
3013         };
3014         define_arm_cp_regs(cpu, dbgregs);
3015     }
3016
3017     for (i = 0; i < wrps + 1; i++) {
3018         ARMCPRegInfo dbgregs[] = {
3019             { .name = "DBGWVR", .state = ARM_CP_STATE_BOTH,
3020               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6,
3021               .access = PL1_RW,
3022               .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]),
3023               .writefn = dbgwvr_write, .raw_writefn = raw_write
3024             },
3025             { .name = "DBGWCR", .state = ARM_CP_STATE_BOTH,
3026               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7,
3027               .access = PL1_RW,
3028               .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]),
3029               .writefn = dbgwcr_write, .raw_writefn = raw_write
3030             },
3031             REGINFO_SENTINEL
3032         };
3033         define_arm_cp_regs(cpu, dbgregs);
3034     }
3035 }
3036
3037 void register_cp_regs_for_features(ARMCPU *cpu)
3038 {
3039     /* Register all the coprocessor registers based on feature bits */
3040     CPUARMState *env = &cpu->env;
3041     if (arm_feature(env, ARM_FEATURE_M)) {
3042         /* M profile has no coprocessor registers */
3043         return;
3044     }
3045
3046     define_arm_cp_regs(cpu, cp_reginfo);
3047     if (!arm_feature(env, ARM_FEATURE_V8)) {
3048         /* Must go early as it is full of wildcards that may be
3049          * overridden by later definitions.
3050          */
3051         define_arm_cp_regs(cpu, not_v8_cp_reginfo);
3052     }
3053
3054     if (arm_feature(env, ARM_FEATURE_V6)) {
3055         /* The ID registers all have impdef reset values */
3056         ARMCPRegInfo v6_idregs[] = {
3057             { .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH,
3058               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
3059               .access = PL1_R, .type = ARM_CP_CONST,
3060               .resetvalue = cpu->id_pfr0 },
3061             { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH,
3062               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1,
3063               .access = PL1_R, .type = ARM_CP_CONST,
3064               .resetvalue = cpu->id_pfr1 },
3065             { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH,
3066               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
3067               .access = PL1_R, .type = ARM_CP_CONST,
3068               .resetvalue = cpu->id_dfr0 },
3069             { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH,
3070               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3,
3071               .access = PL1_R, .type = ARM_CP_CONST,
3072               .resetvalue = cpu->id_afr0 },
3073             { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH,
3074               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4,
3075               .access = PL1_R, .type = ARM_CP_CONST,
3076               .resetvalue = cpu->id_mmfr0 },
3077             { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH,
3078               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5,
3079               .access = PL1_R, .type = ARM_CP_CONST,
3080               .resetvalue = cpu->id_mmfr1 },
3081             { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH,
3082               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6,
3083               .access = PL1_R, .type = ARM_CP_CONST,
3084               .resetvalue = cpu->id_mmfr2 },
3085             { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH,
3086               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7,
3087               .access = PL1_R, .type = ARM_CP_CONST,
3088               .resetvalue = cpu->id_mmfr3 },
3089             { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH,
3090               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
3091               .access = PL1_R, .type = ARM_CP_CONST,
3092               .resetvalue = cpu->id_isar0 },
3093             { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH,
3094               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1,
3095               .access = PL1_R, .type = ARM_CP_CONST,
3096               .resetvalue = cpu->id_isar1 },
3097             { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH,
3098               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
3099               .access = PL1_R, .type = ARM_CP_CONST,
3100               .resetvalue = cpu->id_isar2 },
3101             { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH,
3102               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3,
3103               .access = PL1_R, .type = ARM_CP_CONST,
3104               .resetvalue = cpu->id_isar3 },
3105             { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH,
3106               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4,
3107               .access = PL1_R, .type = ARM_CP_CONST,
3108               .resetvalue = cpu->id_isar4 },
3109             { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH,
3110               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5,
3111               .access = PL1_R, .type = ARM_CP_CONST,
3112               .resetvalue = cpu->id_isar5 },
3113             /* 6..7 are as yet unallocated and must RAZ */
3114             { .name = "ID_ISAR6", .cp = 15, .crn = 0, .crm = 2,
3115               .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
3116               .resetvalue = 0 },
3117             { .name = "ID_ISAR7", .cp = 15, .crn = 0, .crm = 2,
3118               .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
3119               .resetvalue = 0 },
3120             REGINFO_SENTINEL
3121         };
3122         define_arm_cp_regs(cpu, v6_idregs);
3123         define_arm_cp_regs(cpu, v6_cp_reginfo);
3124     } else {
3125         define_arm_cp_regs(cpu, not_v6_cp_reginfo);
3126     }
3127     if (arm_feature(env, ARM_FEATURE_V6K)) {
3128         define_arm_cp_regs(cpu, v6k_cp_reginfo);
3129     }
3130     if (arm_feature(env, ARM_FEATURE_V7MP)) {
3131         define_arm_cp_regs(cpu, v7mp_cp_reginfo);
3132     }
3133     if (arm_feature(env, ARM_FEATURE_V7)) {
3134         /* v7 performance monitor control register: same implementor
3135          * field as main ID register, and we implement only the cycle
3136          * count register.
3137          */
3138 #ifndef CONFIG_USER_ONLY
3139         ARMCPRegInfo pmcr = {
3140             .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
3141             .access = PL0_RW,
3142             .type = ARM_CP_IO | ARM_CP_ALIAS,
3143             .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr),
3144             .accessfn = pmreg_access, .writefn = pmcr_write,
3145             .raw_writefn = raw_write,
3146         };
3147         ARMCPRegInfo pmcr64 = {
3148             .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64,
3149             .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0,
3150             .access = PL0_RW, .accessfn = pmreg_access,
3151             .type = ARM_CP_IO,
3152             .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
3153             .resetvalue = cpu->midr & 0xff000000,
3154             .writefn = pmcr_write, .raw_writefn = raw_write,
3155         };
3156         define_one_arm_cp_reg(cpu, &pmcr);
3157         define_one_arm_cp_reg(cpu, &pmcr64);
3158 #endif
3159         ARMCPRegInfo clidr = {
3160             .name = "CLIDR", .state = ARM_CP_STATE_BOTH,
3161             .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
3162             .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr
3163         };
3164         define_one_arm_cp_reg(cpu, &clidr);
3165         define_arm_cp_regs(cpu, v7_cp_reginfo);
3166         define_debug_regs(cpu);
3167     } else {
3168         define_arm_cp_regs(cpu, not_v7_cp_reginfo);
3169     }
3170     if (arm_feature(env, ARM_FEATURE_V8)) {
3171         /* AArch64 ID registers, which all have impdef reset values */
3172         ARMCPRegInfo v8_idregs[] = {
3173             { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64,
3174               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0,
3175               .access = PL1_R, .type = ARM_CP_CONST,
3176               .resetvalue = cpu->id_aa64pfr0 },
3177             { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64,
3178               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1,
3179               .access = PL1_R, .type = ARM_CP_CONST,
3180               .resetvalue = cpu->id_aa64pfr1},
3181             { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
3182               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
3183               .access = PL1_R, .type = ARM_CP_CONST,
3184               /* We mask out the PMUVer field, because we don't currently
3185                * implement the PMU. Not advertising it prevents the guest
3186                * from trying to use it and getting UNDEFs on registers we
3187                * don't implement.
3188                */
3189               .resetvalue = cpu->id_aa64dfr0 & ~0xf00 },
3190             { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
3191               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
3192               .access = PL1_R, .type = ARM_CP_CONST,
3193               .resetvalue = cpu->id_aa64dfr1 },
3194             { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64,
3195               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4,
3196               .access = PL1_R, .type = ARM_CP_CONST,
3197               .resetvalue = cpu->id_aa64afr0 },
3198             { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64,
3199               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5,
3200               .access = PL1_R, .type = ARM_CP_CONST,
3201               .resetvalue = cpu->id_aa64afr1 },
3202             { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64,
3203               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0,
3204               .access = PL1_R, .type = ARM_CP_CONST,
3205               .resetvalue = cpu->id_aa64isar0 },
3206             { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64,
3207               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1,
3208               .access = PL1_R, .type = ARM_CP_CONST,
3209               .resetvalue = cpu->id_aa64isar1 },
3210             { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64,
3211               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
3212               .access = PL1_R, .type = ARM_CP_CONST,
3213               .resetvalue = cpu->id_aa64mmfr0 },
3214             { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64,
3215               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1,
3216               .access = PL1_R, .type = ARM_CP_CONST,
3217               .resetvalue = cpu->id_aa64mmfr1 },
3218             { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64,
3219               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0,
3220               .access = PL1_R, .type = ARM_CP_CONST,
3221               .resetvalue = cpu->mvfr0 },
3222             { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64,
3223               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1,
3224               .access = PL1_R, .type = ARM_CP_CONST,
3225               .resetvalue = cpu->mvfr1 },
3226             { .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64,
3227               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
3228               .access = PL1_R, .type = ARM_CP_CONST,
3229               .resetvalue = cpu->mvfr2 },
3230             REGINFO_SENTINEL
3231         };
3232         /* RVBAR_EL1 is only implemented if EL1 is the highest EL */
3233         if (!arm_feature(env, ARM_FEATURE_EL3) &&
3234             !arm_feature(env, ARM_FEATURE_EL2)) {
3235             ARMCPRegInfo rvbar = {
3236                 .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64,
3237                 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
3238                 .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar
3239             };
3240             define_one_arm_cp_reg(cpu, &rvbar);
3241         }
3242         define_arm_cp_regs(cpu, v8_idregs);
3243         define_arm_cp_regs(cpu, v8_cp_reginfo);
3244     }
3245     if (arm_feature(env, ARM_FEATURE_EL2)) {
3246         define_arm_cp_regs(cpu, v8_el2_cp_reginfo);
3247         /* RVBAR_EL2 is only implemented if EL2 is the highest EL */
3248         if (!arm_feature(env, ARM_FEATURE_EL3)) {
3249             ARMCPRegInfo rvbar = {
3250                 .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64,
3251                 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1,
3252                 .type = ARM_CP_CONST, .access = PL2_R, .resetvalue = cpu->rvbar
3253             };
3254             define_one_arm_cp_reg(cpu, &rvbar);
3255         }
3256     } else {
3257         /* If EL2 is missing but higher ELs are enabled, we need to
3258          * register the no_el2 reginfos.
3259          */
3260         if (arm_feature(env, ARM_FEATURE_EL3)) {
3261             define_arm_cp_regs(cpu, v8_el3_no_el2_cp_reginfo);
3262         }
3263     }
3264     if (arm_feature(env, ARM_FEATURE_EL3)) {
3265         define_arm_cp_regs(cpu, el3_cp_reginfo);
3266         ARMCPRegInfo rvbar = {
3267             .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64,
3268             .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1,
3269             .type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar
3270         };
3271         define_one_arm_cp_reg(cpu, &rvbar);
3272     }
3273     if (arm_feature(env, ARM_FEATURE_MPU)) {
3274         /* These are the MPU registers prior to PMSAv6. Any new
3275          * PMSA core later than the ARM946 will require that we
3276          * implement the PMSAv6 or PMSAv7 registers, which are
3277          * completely different.
3278          */
3279         assert(!arm_feature(env, ARM_FEATURE_V6));
3280         define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
3281     } else {
3282         define_arm_cp_regs(cpu, vmsa_cp_reginfo);
3283     }
3284     if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
3285         define_arm_cp_regs(cpu, t2ee_cp_reginfo);
3286     }
3287     if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
3288         define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
3289     }
3290     if (arm_feature(env, ARM_FEATURE_VAPA)) {
3291         define_arm_cp_regs(cpu, vapa_cp_reginfo);
3292     }
3293     if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) {
3294         define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo);
3295     }
3296     if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) {
3297         define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo);
3298     }
3299     if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) {
3300         define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo);
3301     }
3302     if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
3303         define_arm_cp_regs(cpu, omap_cp_reginfo);
3304     }
3305     if (arm_feature(env, ARM_FEATURE_STRONGARM)) {
3306         define_arm_cp_regs(cpu, strongarm_cp_reginfo);
3307     }
3308     if (arm_feature(env, ARM_FEATURE_XSCALE)) {
3309         define_arm_cp_regs(cpu, xscale_cp_reginfo);
3310     }
3311     if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
3312         define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
3313     }
3314     if (arm_feature(env, ARM_FEATURE_LPAE)) {
3315         define_arm_cp_regs(cpu, lpae_cp_reginfo);
3316     }
3317     /* Slightly awkwardly, the OMAP and StrongARM cores need all of
3318      * cp15 crn=0 to be writes-ignored, whereas for other cores they should
3319      * be read-only (ie write causes UNDEF exception).
3320      */
3321     {
3322         ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] = {
3323             /* Pre-v8 MIDR space.
3324              * Note that the MIDR isn't a simple constant register because
3325              * of the TI925 behaviour where writes to another register can
3326              * cause the MIDR value to change.
3327              *
3328              * Unimplemented registers in the c15 0 0 0 space default to
3329              * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
3330              * and friends override accordingly.
3331              */
3332             { .name = "MIDR",
3333               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY,
3334               .access = PL1_R, .resetvalue = cpu->midr,
3335               .writefn = arm_cp_write_ignore, .raw_writefn = raw_write,
3336               .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
3337               .type = ARM_CP_OVERRIDE },
3338             /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
3339             { .name = "DUMMY",
3340               .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY,
3341               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
3342             { .name = "DUMMY",
3343               .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY,
3344               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
3345             { .name = "DUMMY",
3346               .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY,
3347               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
3348             { .name = "DUMMY",
3349               .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY,
3350               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
3351             { .name = "DUMMY",
3352               .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
3353               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
3354             REGINFO_SENTINEL
3355         };
3356         ARMCPRegInfo id_v8_midr_cp_reginfo[] = {
3357             /* v8 MIDR -- the wildcard isn't necessary, and nor is the
3358              * variable-MIDR TI925 behaviour. Instead we have a single
3359              * (strictly speaking IMPDEF) alias of the MIDR, REVIDR.
3360              */
3361             { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH,
3362               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0,
3363               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->midr },
3364             { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH,
3365               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6,
3366               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->midr },
3367             REGINFO_SENTINEL
3368         };
3369         ARMCPRegInfo id_cp_reginfo[] = {
3370             /* These are common to v8 and pre-v8 */
3371             { .name = "CTR",
3372               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
3373               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
3374             { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64,
3375               .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0,
3376               .access = PL0_R, .accessfn = ctr_el0_access,
3377               .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
3378             /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
3379             { .name = "TCMTR",
3380               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2,
3381               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
3382             { .name = "TLBTR",
3383               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
3384               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
3385             REGINFO_SENTINEL
3386         };
3387         ARMCPRegInfo crn0_wi_reginfo = {
3388             .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
3389             .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
3390             .type = ARM_CP_NOP | ARM_CP_OVERRIDE
3391         };
3392         if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
3393             arm_feature(env, ARM_FEATURE_STRONGARM)) {
3394             ARMCPRegInfo *r;
3395             /* Register the blanket "writes ignored" value first to cover the
3396              * whole space. Then update the specific ID registers to allow write
3397              * access, so that they ignore writes rather than causing them to
3398              * UNDEF.
3399              */
3400             define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
3401             for (r = id_pre_v8_midr_cp_reginfo;
3402                  r->type != ARM_CP_SENTINEL; r++) {
3403                 r->access = PL1_RW;
3404             }
3405             for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
3406                 r->access = PL1_RW;
3407             }
3408         }
3409         if (arm_feature(env, ARM_FEATURE_V8)) {
3410             define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo);
3411         } else {
3412             define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo);
3413         }
3414         define_arm_cp_regs(cpu, id_cp_reginfo);
3415     }
3416
3417     if (arm_feature(env, ARM_FEATURE_MPIDR)) {
3418         define_arm_cp_regs(cpu, mpidr_cp_reginfo);
3419     }
3420
3421     if (arm_feature(env, ARM_FEATURE_AUXCR)) {
3422         ARMCPRegInfo auxcr = {
3423             .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH,
3424             .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1,
3425             .access = PL1_RW, .type = ARM_CP_CONST,
3426             .resetvalue = cpu->reset_auxcr
3427         };
3428         define_one_arm_cp_reg(cpu, &auxcr);
3429     }
3430
3431     if (arm_feature(env, ARM_FEATURE_CBAR)) {
3432         if (arm_feature(env, ARM_FEATURE_AARCH64)) {
3433             /* 32 bit view is [31:18] 0...0 [43:32]. */
3434             uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18)
3435                 | extract64(cpu->reset_cbar, 32, 12);
3436             ARMCPRegInfo cbar_reginfo[] = {
3437                 { .name = "CBAR",
3438                   .type = ARM_CP_CONST,
3439                   .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
3440                   .access = PL1_R, .resetvalue = cpu->reset_cbar },
3441                 { .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64,
3442                   .type = ARM_CP_CONST,
3443                   .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0,
3444                   .access = PL1_R, .resetvalue = cbar32 },
3445                 REGINFO_SENTINEL
3446             };
3447             /* We don't implement a r/w 64 bit CBAR currently */
3448             assert(arm_feature(env, ARM_FEATURE_CBAR_RO));
3449             define_arm_cp_regs(cpu, cbar_reginfo);
3450         } else {
3451             ARMCPRegInfo cbar = {
3452                 .name = "CBAR",
3453                 .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
3454                 .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
3455                 .fieldoffset = offsetof(CPUARMState,
3456                                         cp15.c15_config_base_address)
3457             };
3458             if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
3459                 cbar.access = PL1_R;
3460                 cbar.fieldoffset = 0;
3461                 cbar.type = ARM_CP_CONST;
3462             }
3463             define_one_arm_cp_reg(cpu, &cbar);
3464         }
3465     }
3466
3467     /* Generic registers whose values depend on the implementation */
3468     {
3469         ARMCPRegInfo sctlr = {
3470             .name = "SCTLR", .state = ARM_CP_STATE_BOTH,
3471             .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
3472             .access = PL1_RW,
3473             .bank_fieldoffsets = { offsetof(CPUARMState, cp15.sctlr_s),
3474                                    offsetof(CPUARMState, cp15.sctlr_ns) },
3475             .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
3476             .raw_writefn = raw_write,
3477         };
3478         if (arm_feature(env, ARM_FEATURE_XSCALE)) {
3479             /* Normally we would always end the TB on an SCTLR write, but Linux
3480              * arch/arm/mach-pxa/sleep.S expects two instructions following
3481              * an MMU enable to execute from cache.  Imitate this behaviour.
3482              */
3483             sctlr.type |= ARM_CP_SUPPRESS_TB_END;
3484         }
3485         define_one_arm_cp_reg(cpu, &sctlr);
3486     }
3487 }
3488
3489 ARMCPU *cpu_arm_init(const char *cpu_model)
3490 {
3491     return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model));
3492 }
3493
3494 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
3495 {
3496     CPUState *cs = CPU(cpu);
3497     CPUARMState *env = &cpu->env;
3498
3499     if (arm_feature(env, ARM_FEATURE_AARCH64)) {
3500         gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
3501                                  aarch64_fpu_gdb_set_reg,
3502                                  34, "aarch64-fpu.xml", 0);
3503     } else if (arm_feature(env, ARM_FEATURE_NEON)) {
3504         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
3505                                  51, "arm-neon.xml", 0);
3506     } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
3507         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
3508                                  35, "arm-vfp3.xml", 0);
3509     } else if (arm_feature(env, ARM_FEATURE_VFP)) {
3510         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
3511                                  19, "arm-vfp.xml", 0);
3512     }
3513 }
3514
3515 /* Sort alphabetically by type name, except for "any". */
3516 static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
3517 {
3518     ObjectClass *class_a = (ObjectClass *)a;
3519     ObjectClass *class_b = (ObjectClass *)b;
3520     const char *name_a, *name_b;
3521
3522     name_a = object_class_get_name(class_a);
3523     name_b = object_class_get_name(class_b);
3524     if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) {
3525         return 1;
3526     } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) {
3527         return -1;
3528     } else {
3529         return strcmp(name_a, name_b);
3530     }
3531 }
3532
3533 static void arm_cpu_list_entry(gpointer data, gpointer user_data)
3534 {
3535     ObjectClass *oc = data;
3536     CPUListState *s = user_data;
3537     const char *typename;
3538     char *name;
3539
3540     typename = object_class_get_name(oc);
3541     name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU));
3542     (*s->cpu_fprintf)(s->file, "  %s\n",
3543                       name);
3544     g_free(name);
3545 }
3546
3547 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
3548 {
3549     CPUListState s = {
3550         .file = f,
3551         .cpu_fprintf = cpu_fprintf,
3552     };
3553     GSList *list;
3554
3555     list = object_class_get_list(TYPE_ARM_CPU, false);
3556     list = g_slist_sort(list, arm_cpu_list_compare);
3557     (*cpu_fprintf)(f, "Available CPUs:\n");
3558     g_slist_foreach(list, arm_cpu_list_entry, &s);
3559     g_slist_free(list);
3560 #ifdef CONFIG_KVM
3561     /* The 'host' CPU type is dynamically registered only if KVM is
3562      * enabled, so we have to special-case it here:
3563      */
3564     (*cpu_fprintf)(f, "  host (only available in KVM mode)\n");
3565 #endif
3566 }
3567
3568 static void arm_cpu_add_definition(gpointer data, gpointer user_data)
3569 {
3570     ObjectClass *oc = data;
3571     CpuDefinitionInfoList **cpu_list = user_data;
3572     CpuDefinitionInfoList *entry;
3573     CpuDefinitionInfo *info;
3574     const char *typename;
3575
3576     typename = object_class_get_name(oc);
3577     info = g_malloc0(sizeof(*info));
3578     info->name = g_strndup(typename,
3579                            strlen(typename) - strlen("-" TYPE_ARM_CPU));
3580
3581     entry = g_malloc0(sizeof(*entry));
3582     entry->value = info;
3583     entry->next = *cpu_list;
3584     *cpu_list = entry;
3585 }
3586
3587 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
3588 {
3589     CpuDefinitionInfoList *cpu_list = NULL;
3590     GSList *list;
3591
3592     list = object_class_get_list(TYPE_ARM_CPU, false);
3593     g_slist_foreach(list, arm_cpu_add_definition, &cpu_list);
3594     g_slist_free(list);
3595
3596     return cpu_list;
3597 }
3598
3599 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
3600                                    void *opaque, int state, int secstate,
3601                                    int crm, int opc1, int opc2)
3602 {
3603     /* Private utility function for define_one_arm_cp_reg_with_opaque():
3604      * add a single reginfo struct to the hash table.
3605      */
3606     uint32_t *key = g_new(uint32_t, 1);
3607     ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
3608     int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
3609     int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0;
3610
3611     /* Reset the secure state to the specific incoming state.  This is
3612      * necessary as the register may have been defined with both states.
3613      */
3614     r2->secure = secstate;
3615
3616     if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
3617         /* Register is banked (using both entries in array).
3618          * Overwriting fieldoffset as the array is only used to define
3619          * banked registers but later only fieldoffset is used.
3620          */
3621         r2->fieldoffset = r->bank_fieldoffsets[ns];
3622     }
3623
3624     if (state == ARM_CP_STATE_AA32) {
3625         if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
3626             /* If the register is banked then we don't need to migrate or
3627              * reset the 32-bit instance in certain cases:
3628              *
3629              * 1) If the register has both 32-bit and 64-bit instances then we
3630              *    can count on the 64-bit instance taking care of the
3631              *    non-secure bank.
3632              * 2) If ARMv8 is enabled then we can count on a 64-bit version
3633              *    taking care of the secure bank.  This requires that separate
3634              *    32 and 64-bit definitions are provided.
3635              */
3636             if ((r->state == ARM_CP_STATE_BOTH && ns) ||
3637                 (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) {
3638                 r2->type |= ARM_CP_ALIAS;
3639                 r2->resetfn = arm_cp_reset_ignore;
3640             }
3641         } else if ((secstate != r->secure) && !ns) {
3642             /* The register is not banked so we only want to allow migration of
3643              * the non-secure instance.
3644              */
3645             r2->type |= ARM_CP_ALIAS;
3646             r2->resetfn = arm_cp_reset_ignore;
3647         }
3648
3649         if (r->state == ARM_CP_STATE_BOTH) {
3650             /* We assume it is a cp15 register if the .cp field is left unset.
3651              */
3652             if (r2->cp == 0) {
3653                 r2->cp = 15;
3654             }
3655
3656 #ifdef HOST_WORDS_BIGENDIAN
3657             if (r2->fieldoffset) {
3658                 r2->fieldoffset += sizeof(uint32_t);
3659             }
3660 #endif
3661         }
3662     }
3663     if (state == ARM_CP_STATE_AA64) {
3664         /* To allow abbreviation of ARMCPRegInfo
3665          * definitions, we treat cp == 0 as equivalent to
3666          * the value for "standard guest-visible sysreg".
3667          * STATE_BOTH definitions are also always "standard
3668          * sysreg" in their AArch64 view (the .cp value may
3669          * be non-zero for the benefit of the AArch32 view).
3670          */
3671         if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) {
3672             r2->cp = CP_REG_ARM64_SYSREG_CP;
3673         }
3674         *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
3675                                   r2->opc0, opc1, opc2);
3676     } else {
3677         *key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2);
3678     }
3679     if (opaque) {
3680         r2->opaque = opaque;
3681     }
3682     /* reginfo passed to helpers is correct for the actual access,
3683      * and is never ARM_CP_STATE_BOTH:
3684      */
3685     r2->state = state;
3686     /* Make sure reginfo passed to helpers for wildcarded regs
3687      * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
3688      */
3689     r2->crm = crm;
3690     r2->opc1 = opc1;
3691     r2->opc2 = opc2;
3692     /* By convention, for wildcarded registers only the first
3693      * entry is used for migration; the others are marked as
3694      * ALIAS so we don't try to transfer the register
3695      * multiple times. Special registers (ie NOP/WFI) are
3696      * never migratable and not even raw-accessible.
3697      */
3698     if ((r->type & ARM_CP_SPECIAL)) {
3699         r2->type |= ARM_CP_NO_RAW;
3700     }
3701     if (((r->crm == CP_ANY) && crm != 0) ||
3702         ((r->opc1 == CP_ANY) && opc1 != 0) ||
3703         ((r->opc2 == CP_ANY) && opc2 != 0)) {
3704         r2->type |= ARM_CP_ALIAS;
3705     }
3706
3707     /* Check that raw accesses are either forbidden or handled. Note that
3708      * we can't assert this earlier because the setup of fieldoffset for
3709      * banked registers has to be done first.
3710      */
3711     if (!(r2->type & ARM_CP_NO_RAW)) {
3712         assert(!raw_accessors_invalid(r2));
3713     }
3714
3715     /* Overriding of an existing definition must be explicitly
3716      * requested.
3717      */
3718     if (!(r->type & ARM_CP_OVERRIDE)) {
3719         ARMCPRegInfo *oldreg;
3720         oldreg = g_hash_table_lookup(cpu->cp_regs, key);
3721         if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
3722             fprintf(stderr, "Register redefined: cp=%d %d bit "
3723                     "crn=%d crm=%d opc1=%d opc2=%d, "
3724                     "was %s, now %s\n", r2->cp, 32 + 32 * is64,
3725                     r2->crn, r2->crm, r2->opc1, r2->opc2,
3726                     oldreg->name, r2->name);
3727             g_assert_not_reached();
3728         }
3729     }
3730     g_hash_table_insert(cpu->cp_regs, key, r2);
3731 }
3732
3733
3734 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
3735                                        const ARMCPRegInfo *r, void *opaque)
3736 {
3737     /* Define implementations of coprocessor registers.
3738      * We store these in a hashtable because typically
3739      * there are less than 150 registers in a space which
3740      * is 16*16*16*8*8 = 262144 in size.
3741      * Wildcarding is supported for the crm, opc1 and opc2 fields.
3742      * If a register is defined twice then the second definition is
3743      * used, so this can be used to define some generic registers and
3744      * then override them with implementation specific variations.
3745      * At least one of the original and the second definition should
3746      * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
3747      * against accidental use.
3748      *
3749      * The state field defines whether the register is to be
3750      * visible in the AArch32 or AArch64 execution state. If the
3751      * state is set to ARM_CP_STATE_BOTH then we synthesise a
3752      * reginfo structure for the AArch32 view, which sees the lower
3753      * 32 bits of the 64 bit register.
3754      *
3755      * Only registers visible in AArch64 may set r->opc0; opc0 cannot
3756      * be wildcarded. AArch64 registers are always considered to be 64
3757      * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
3758      * the register, if any.
3759      */
3760     int crm, opc1, opc2, state;
3761     int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
3762     int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
3763     int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
3764     int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
3765     int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
3766     int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
3767     /* 64 bit registers have only CRm and Opc1 fields */
3768     assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
3769     /* op0 only exists in the AArch64 encodings */
3770     assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0));
3771     /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
3772     assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT));
3773     /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
3774      * encodes a minimum access level for the register. We roll this
3775      * runtime check into our general permission check code, so check
3776      * here that the reginfo's specified permissions are strict enough
3777      * to encompass the generic architectural permission check.
3778      */
3779     if (r->state != ARM_CP_STATE_AA32) {
3780         int mask = 0;
3781         switch (r->opc1) {
3782         case 0: case 1: case 2:
3783             /* min_EL EL1 */
3784             mask = PL1_RW;
3785             break;
3786         case 3:
3787             /* min_EL EL0 */
3788             mask = PL0_RW;
3789             break;
3790         case 4:
3791             /* min_EL EL2 */
3792             mask = PL2_RW;
3793             break;
3794         case 5:
3795             /* unallocated encoding, so not possible */
3796             assert(false);
3797             break;
3798         case 6:
3799             /* min_EL EL3 */
3800             mask = PL3_RW;
3801             break;
3802         case 7:
3803             /* min_EL EL1, secure mode only (we don't check the latter) */
3804             mask = PL1_RW;
3805             break;
3806         default:
3807             /* broken reginfo with out-of-range opc1 */
3808             assert(false);
3809             break;
3810         }
3811         /* assert our permissions are not too lax (stricter is fine) */
3812         assert((r->access & ~mask) == 0);
3813     }
3814
3815     /* Check that the register definition has enough info to handle
3816      * reads and writes if they are permitted.
3817      */
3818     if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
3819         if (r->access & PL3_R) {
3820             assert((r->fieldoffset ||
3821                    (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) ||
3822                    r->readfn);
3823         }
3824         if (r->access & PL3_W) {
3825             assert((r->fieldoffset ||
3826                    (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) ||
3827                    r->writefn);
3828         }
3829     }
3830     /* Bad type field probably means missing sentinel at end of reg list */
3831     assert(cptype_valid(r->type));
3832     for (crm = crmmin; crm <= crmmax; crm++) {
3833         for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
3834             for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
3835                 for (state = ARM_CP_STATE_AA32;
3836                      state <= ARM_CP_STATE_AA64; state++) {
3837                     if (r->state != state && r->state != ARM_CP_STATE_BOTH) {
3838                         continue;
3839                     }
3840                     if (state == ARM_CP_STATE_AA32) {
3841                         /* Under AArch32 CP registers can be common
3842                          * (same for secure and non-secure world) or banked.
3843                          */
3844                         switch (r->secure) {
3845                         case ARM_CP_SECSTATE_S:
3846                         case ARM_CP_SECSTATE_NS:
3847                             add_cpreg_to_hashtable(cpu, r, opaque, state,
3848                                                    r->secure, crm, opc1, opc2);
3849                             break;
3850                         default:
3851                             add_cpreg_to_hashtable(cpu, r, opaque, state,
3852                                                    ARM_CP_SECSTATE_S,
3853                                                    crm, opc1, opc2);
3854                             add_cpreg_to_hashtable(cpu, r, opaque, state,
3855                                                    ARM_CP_SECSTATE_NS,
3856                                                    crm, opc1, opc2);
3857                             break;
3858                         }
3859                     } else {
3860                         /* AArch64 registers get mapped to non-secure instance
3861                          * of AArch32 */
3862                         add_cpreg_to_hashtable(cpu, r, opaque, state,
3863                                                ARM_CP_SECSTATE_NS,
3864                                                crm, opc1, opc2);
3865                     }
3866                 }
3867             }
3868         }
3869     }
3870 }
3871
3872 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
3873                                     const ARMCPRegInfo *regs, void *opaque)
3874 {
3875     /* Define a whole list of registers */
3876     const ARMCPRegInfo *r;
3877     for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
3878         define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
3879     }
3880 }
3881
3882 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp)
3883 {
3884     return g_hash_table_lookup(cpregs, &encoded_cp);
3885 }
3886
3887 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
3888                          uint64_t value)
3889 {
3890     /* Helper coprocessor write function for write-ignore registers */
3891 }
3892
3893 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri)
3894 {
3895     /* Helper coprocessor write function for read-as-zero registers */
3896     return 0;
3897 }
3898
3899 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque)
3900 {
3901     /* Helper coprocessor reset function for do-nothing-on-reset registers */
3902 }
3903
3904 static int bad_mode_switch(CPUARMState *env, int mode)
3905 {
3906     /* Return true if it is not valid for us to switch to
3907      * this CPU mode (ie all the UNPREDICTABLE cases in
3908      * the ARM ARM CPSRWriteByInstr pseudocode).
3909      */
3910     switch (mode) {
3911     case ARM_CPU_MODE_USR:
3912     case ARM_CPU_MODE_SYS:
3913     case ARM_CPU_MODE_SVC:
3914     case ARM_CPU_MODE_ABT:
3915     case ARM_CPU_MODE_UND:
3916     case ARM_CPU_MODE_IRQ:
3917     case ARM_CPU_MODE_FIQ:
3918         return 0;
3919     case ARM_CPU_MODE_MON:
3920         return !arm_is_secure(env);
3921     default:
3922         return 1;
3923     }
3924 }
3925
3926 uint32_t cpsr_read(CPUARMState *env)
3927 {
3928     int ZF;
3929     ZF = (env->ZF == 0);
3930     return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
3931         (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
3932         | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
3933         | ((env->condexec_bits & 0xfc) << 8)
3934         | (env->GE << 16) | (env->daif & CPSR_AIF);
3935 }
3936
3937 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
3938 {
3939     uint32_t changed_daif;
3940
3941     if (mask & CPSR_NZCV) {
3942         env->ZF = (~val) & CPSR_Z;
3943         env->NF = val;
3944         env->CF = (val >> 29) & 1;
3945         env->VF = (val << 3) & 0x80000000;
3946     }
3947     if (mask & CPSR_Q)
3948         env->QF = ((val & CPSR_Q) != 0);
3949     if (mask & CPSR_T)
3950         env->thumb = ((val & CPSR_T) != 0);
3951     if (mask & CPSR_IT_0_1) {
3952         env->condexec_bits &= ~3;
3953         env->condexec_bits |= (val >> 25) & 3;
3954     }
3955     if (mask & CPSR_IT_2_7) {
3956         env->condexec_bits &= 3;
3957         env->condexec_bits |= (val >> 8) & 0xfc;
3958     }
3959     if (mask & CPSR_GE) {
3960         env->GE = (val >> 16) & 0xf;
3961     }
3962
3963     /* In a V7 implementation that includes the security extensions but does
3964      * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
3965      * whether non-secure software is allowed to change the CPSR_F and CPSR_A
3966      * bits respectively.
3967      *
3968      * In a V8 implementation, it is permitted for privileged software to
3969      * change the CPSR A/F bits regardless of the SCR.AW/FW bits.
3970      */
3971     if (!arm_feature(env, ARM_FEATURE_V8) &&
3972         arm_feature(env, ARM_FEATURE_EL3) &&
3973         !arm_feature(env, ARM_FEATURE_EL2) &&
3974         !arm_is_secure(env)) {
3975
3976         changed_daif = (env->daif ^ val) & mask;
3977
3978         if (changed_daif & CPSR_A) {
3979             /* Check to see if we are allowed to change the masking of async
3980              * abort exceptions from a non-secure state.
3981              */
3982             if (!(env->cp15.scr_el3 & SCR_AW)) {
3983                 qemu_log_mask(LOG_GUEST_ERROR,
3984                               "Ignoring attempt to switch CPSR_A flag from "
3985                               "non-secure world with SCR.AW bit clear\n");
3986                 mask &= ~CPSR_A;
3987             }
3988         }
3989
3990         if (changed_daif & CPSR_F) {
3991             /* Check to see if we are allowed to change the masking of FIQ
3992              * exceptions from a non-secure state.
3993              */
3994             if (!(env->cp15.scr_el3 & SCR_FW)) {
3995                 qemu_log_mask(LOG_GUEST_ERROR,
3996                               "Ignoring attempt to switch CPSR_F flag from "
3997                               "non-secure world with SCR.FW bit clear\n");
3998                 mask &= ~CPSR_F;
3999             }
4000
4001             /* Check whether non-maskable FIQ (NMFI) support is enabled.
4002              * If this bit is set software is not allowed to mask
4003              * FIQs, but is allowed to set CPSR_F to 0.
4004              */
4005             if ((A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_NMFI) &&
4006                 (val & CPSR_F)) {
4007                 qemu_log_mask(LOG_GUEST_ERROR,
4008                               "Ignoring attempt to enable CPSR_F flag "
4009                               "(non-maskable FIQ [NMFI] support enabled)\n");
4010                 mask &= ~CPSR_F;
4011             }
4012         }
4013     }
4014
4015     env->daif &= ~(CPSR_AIF & mask);
4016     env->daif |= val & CPSR_AIF & mask;
4017
4018     if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
4019         if (bad_mode_switch(env, val & CPSR_M)) {
4020             /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
4021              * We choose to ignore the attempt and leave the CPSR M field
4022              * untouched.
4023              */
4024             mask &= ~CPSR_M;
4025         } else {
4026             switch_mode(env, val & CPSR_M);
4027         }
4028     }
4029     mask &= ~CACHED_CPSR_BITS;
4030     env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
4031 }
4032
4033 /* Sign/zero extend */
4034 uint32_t HELPER(sxtb16)(uint32_t x)
4035 {
4036     uint32_t res;
4037     res = (uint16_t)(int8_t)x;
4038     res |= (uint32_t)(int8_t)(x >> 16) << 16;
4039     return res;
4040 }
4041
4042 uint32_t HELPER(uxtb16)(uint32_t x)
4043 {
4044     uint32_t res;
4045     res = (uint16_t)(uint8_t)x;
4046     res |= (uint32_t)(uint8_t)(x >> 16) << 16;
4047     return res;
4048 }
4049
4050 uint32_t HELPER(clz)(uint32_t x)
4051 {
4052     return clz32(x);
4053 }
4054
4055 int32_t HELPER(sdiv)(int32_t num, int32_t den)
4056 {
4057     if (den == 0)
4058       return 0;
4059     if (num == INT_MIN && den == -1)
4060       return INT_MIN;
4061     return num / den;
4062 }
4063
4064 uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
4065 {
4066     if (den == 0)
4067       return 0;
4068     return num / den;
4069 }
4070
4071 uint32_t HELPER(rbit)(uint32_t x)
4072 {
4073     x =  ((x & 0xff000000) >> 24)
4074        | ((x & 0x00ff0000) >> 8)
4075        | ((x & 0x0000ff00) << 8)
4076        | ((x & 0x000000ff) << 24);
4077     x =  ((x & 0xf0f0f0f0) >> 4)
4078        | ((x & 0x0f0f0f0f) << 4);
4079     x =  ((x & 0x88888888) >> 3)
4080        | ((x & 0x44444444) >> 1)
4081        | ((x & 0x22222222) << 1)
4082        | ((x & 0x11111111) << 3);
4083     return x;
4084 }
4085
4086 #if defined(CONFIG_USER_ONLY)
4087
4088 /* These should probably raise undefined insn exceptions.  */
4089 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
4090 {
4091     ARMCPU *cpu = arm_env_get_cpu(env);
4092
4093     cpu_abort(CPU(cpu), "v7m_msr %d\n", reg);
4094 }
4095
4096 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
4097 {
4098     ARMCPU *cpu = arm_env_get_cpu(env);
4099
4100     cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg);
4101     return 0;
4102 }
4103
4104 void switch_mode(CPUARMState *env, int mode)
4105 {
4106     ARMCPU *cpu = arm_env_get_cpu(env);
4107
4108     if (mode != ARM_CPU_MODE_USR) {
4109         cpu_abort(CPU(cpu), "Tried to switch out of user mode\n");
4110     }
4111 }
4112
4113 void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
4114 {
4115     ARMCPU *cpu = arm_env_get_cpu(env);
4116
4117     cpu_abort(CPU(cpu), "banked r13 write\n");
4118 }
4119
4120 uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
4121 {
4122     ARMCPU *cpu = arm_env_get_cpu(env);
4123
4124     cpu_abort(CPU(cpu), "banked r13 read\n");
4125     return 0;
4126 }
4127
4128 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
4129                                  uint32_t cur_el, bool secure)
4130 {
4131     return 1;
4132 }
4133
4134 void aarch64_sync_64_to_32(CPUARMState *env)
4135 {
4136     g_assert_not_reached();
4137 }
4138
4139 #else
4140
4141 /* Map CPU modes onto saved register banks.  */
4142 int bank_number(int mode)
4143 {
4144     switch (mode) {
4145     case ARM_CPU_MODE_USR:
4146     case ARM_CPU_MODE_SYS:
4147         return 0;
4148     case ARM_CPU_MODE_SVC:
4149         return 1;
4150     case ARM_CPU_MODE_ABT:
4151         return 2;
4152     case ARM_CPU_MODE_UND:
4153         return 3;
4154     case ARM_CPU_MODE_IRQ:
4155         return 4;
4156     case ARM_CPU_MODE_FIQ:
4157         return 5;
4158     case ARM_CPU_MODE_HYP:
4159         return 6;
4160     case ARM_CPU_MODE_MON:
4161         return 7;
4162     }
4163     hw_error("bank number requested for bad CPSR mode value 0x%x\n", mode);
4164 }
4165
4166 void switch_mode(CPUARMState *env, int mode)
4167 {
4168     int old_mode;
4169     int i;
4170
4171     old_mode = env->uncached_cpsr & CPSR_M;
4172     if (mode == old_mode)
4173         return;
4174
4175     if (old_mode == ARM_CPU_MODE_FIQ) {
4176         memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
4177         memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
4178     } else if (mode == ARM_CPU_MODE_FIQ) {
4179         memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
4180         memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
4181     }
4182
4183     i = bank_number(old_mode);
4184     env->banked_r13[i] = env->regs[13];
4185     env->banked_r14[i] = env->regs[14];
4186     env->banked_spsr[i] = env->spsr;
4187
4188     i = bank_number(mode);
4189     env->regs[13] = env->banked_r13[i];
4190     env->regs[14] = env->banked_r14[i];
4191     env->spsr = env->banked_spsr[i];
4192 }
4193
4194 /* Physical Interrupt Target EL Lookup Table
4195  *
4196  * [ From ARM ARM section G1.13.4 (Table G1-15) ]
4197  *
4198  * The below multi-dimensional table is used for looking up the target
4199  * exception level given numerous condition criteria.  Specifically, the
4200  * target EL is based on SCR and HCR routing controls as well as the
4201  * currently executing EL and secure state.
4202  *
4203  *    Dimensions:
4204  *    target_el_table[2][2][2][2][2][4]
4205  *                    |  |  |  |  |  +--- Current EL
4206  *                    |  |  |  |  +------ Non-secure(0)/Secure(1)
4207  *                    |  |  |  +--------- HCR mask override
4208  *                    |  |  +------------ SCR exec state control
4209  *                    |  +--------------- SCR mask override
4210  *                    +------------------ 32-bit(0)/64-bit(1) EL3
4211  *
4212  *    The table values are as such:
4213  *    0-3 = EL0-EL3
4214  *     -1 = Cannot occur
4215  *
4216  * The ARM ARM target EL table includes entries indicating that an "exception
4217  * is not taken".  The two cases where this is applicable are:
4218  *    1) An exception is taken from EL3 but the SCR does not have the exception
4219  *    routed to EL3.
4220  *    2) An exception is taken from EL2 but the HCR does not have the exception
4221  *    routed to EL2.
4222  * In these two cases, the below table contain a target of EL1.  This value is
4223  * returned as it is expected that the consumer of the table data will check
4224  * for "target EL >= current EL" to ensure the exception is not taken.
4225  *
4226  *            SCR     HCR
4227  *         64  EA     AMO                 From
4228  *        BIT IRQ     IMO      Non-secure         Secure
4229  *        EL3 FIQ  RW FMO   EL0 EL1 EL2 EL3   EL0 EL1 EL2 EL3
4230  */
4231 const int8_t target_el_table[2][2][2][2][2][4] = {
4232     {{{{/* 0   0   0   0 */{ 1,  1,  2, -1 },{ 3, -1, -1,  3 },},
4233        {/* 0   0   0   1 */{ 2,  2,  2, -1 },{ 3, -1, -1,  3 },},},
4234       {{/* 0   0   1   0 */{ 1,  1,  2, -1 },{ 3, -1, -1,  3 },},
4235        {/* 0   0   1   1 */{ 2,  2,  2, -1 },{ 3, -1, -1,  3 },},},},
4236      {{{/* 0   1   0   0 */{ 3,  3,  3, -1 },{ 3, -1, -1,  3 },},
4237        {/* 0   1   0   1 */{ 3,  3,  3, -1 },{ 3, -1, -1,  3 },},},
4238       {{/* 0   1   1   0 */{ 3,  3,  3, -1 },{ 3, -1, -1,  3 },},
4239        {/* 0   1   1   1 */{ 3,  3,  3, -1 },{ 3, -1, -1,  3 },},},},},
4240     {{{{/* 1   0   0   0 */{ 1,  1,  2, -1 },{ 1,  1, -1,  1 },},
4241        {/* 1   0   0   1 */{ 2,  2,  2, -1 },{ 1,  1, -1,  1 },},},
4242       {{/* 1   0   1   0 */{ 1,  1,  1, -1 },{ 1,  1, -1,  1 },},
4243        {/* 1   0   1   1 */{ 2,  2,  2, -1 },{ 1,  1, -1,  1 },},},},
4244      {{{/* 1   1   0   0 */{ 3,  3,  3, -1 },{ 3,  3, -1,  3 },},
4245        {/* 1   1   0   1 */{ 3,  3,  3, -1 },{ 3,  3, -1,  3 },},},
4246       {{/* 1   1   1   0 */{ 3,  3,  3, -1 },{ 3,  3, -1,  3 },},
4247        {/* 1   1   1   1 */{ 3,  3,  3, -1 },{ 3,  3, -1,  3 },},},},},
4248 };
4249
4250 /*
4251  * Determine the target EL for physical exceptions
4252  */
4253 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
4254                                  uint32_t cur_el, bool secure)
4255 {
4256     CPUARMState *env = cs->env_ptr;
4257     int rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW);
4258     int scr;
4259     int hcr;
4260     int target_el;
4261     int is64 = arm_el_is_aa64(env, 3);
4262
4263     switch (excp_idx) {
4264     case EXCP_IRQ:
4265         scr = ((env->cp15.scr_el3 & SCR_IRQ) == SCR_IRQ);
4266         hcr = ((env->cp15.hcr_el2 & HCR_IMO) == HCR_IMO);
4267         break;
4268     case EXCP_FIQ:
4269         scr = ((env->cp15.scr_el3 & SCR_FIQ) == SCR_FIQ);
4270         hcr = ((env->cp15.hcr_el2 & HCR_FMO) == HCR_FMO);
4271         break;
4272     default:
4273         scr = ((env->cp15.scr_el3 & SCR_EA) == SCR_EA);
4274         hcr = ((env->cp15.hcr_el2 & HCR_AMO) == HCR_AMO);
4275         break;
4276     };
4277
4278     /* If HCR.TGE is set then HCR is treated as being 1 */
4279     hcr |= ((env->cp15.hcr_el2 & HCR_TGE) == HCR_TGE);
4280
4281     /* Perform a table-lookup for the target EL given the current state */
4282     target_el = target_el_table[is64][scr][rw][hcr][secure][cur_el];
4283
4284     assert(target_el > 0);
4285
4286     return target_el;
4287 }
4288
4289 static void v7m_push(CPUARMState *env, uint32_t val)
4290 {
4291     CPUState *cs = CPU(arm_env_get_cpu(env));
4292
4293     env->regs[13] -= 4;
4294     stl_phys(cs->as, env->regs[13], val);
4295 }
4296
4297 static uint32_t v7m_pop(CPUARMState *env)
4298 {
4299     CPUState *cs = CPU(arm_env_get_cpu(env));
4300     uint32_t val;
4301
4302     val = ldl_phys(cs->as, env->regs[13]);
4303     env->regs[13] += 4;
4304     return val;
4305 }
4306
4307 /* Switch to V7M main or process stack pointer.  */
4308 static void switch_v7m_sp(CPUARMState *env, int process)
4309 {
4310     uint32_t tmp;
4311     if (env->v7m.current_sp != process) {
4312         tmp = env->v7m.other_sp;
4313         env->v7m.other_sp = env->regs[13];
4314         env->regs[13] = tmp;
4315         env->v7m.current_sp = process;
4316     }
4317 }
4318
4319 static void do_v7m_exception_exit(CPUARMState *env)
4320 {
4321     uint32_t type;
4322     uint32_t xpsr;
4323
4324     type = env->regs[15];
4325     if (env->v7m.exception != 0)
4326         armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
4327
4328     /* Switch to the target stack.  */
4329     switch_v7m_sp(env, (type & 4) != 0);
4330     /* Pop registers.  */
4331     env->regs[0] = v7m_pop(env);
4332     env->regs[1] = v7m_pop(env);
4333     env->regs[2] = v7m_pop(env);
4334     env->regs[3] = v7m_pop(env);
4335     env->regs[12] = v7m_pop(env);
4336     env->regs[14] = v7m_pop(env);
4337     env->regs[15] = v7m_pop(env);
4338     if (env->regs[15] & 1) {
4339         qemu_log_mask(LOG_GUEST_ERROR,
4340                       "M profile return from interrupt with misaligned "
4341                       "PC is UNPREDICTABLE\n");
4342         /* Actual hardware seems to ignore the lsbit, and there are several
4343          * RTOSes out there which incorrectly assume the r15 in the stack
4344          * frame should be a Thumb-style "lsbit indicates ARM/Thumb" value.
4345          */
4346         env->regs[15] &= ~1U;
4347     }
4348     xpsr = v7m_pop(env);
4349     xpsr_write(env, xpsr, 0xfffffdff);
4350     /* Undo stack alignment.  */
4351     if (xpsr & 0x200)
4352         env->regs[13] |= 4;
4353     /* ??? The exception return type specifies Thread/Handler mode.  However
4354        this is also implied by the xPSR value. Not sure what to do
4355        if there is a mismatch.  */
4356     /* ??? Likewise for mismatches between the CONTROL register and the stack
4357        pointer.  */
4358 }
4359
4360 void arm_v7m_cpu_do_interrupt(CPUState *cs)
4361 {
4362     ARMCPU *cpu = ARM_CPU(cs);
4363     CPUARMState *env = &cpu->env;
4364     uint32_t xpsr = xpsr_read(env);
4365     uint32_t lr;
4366     uint32_t addr;
4367
4368     arm_log_exception(cs->exception_index);
4369
4370     lr = 0xfffffff1;
4371     if (env->v7m.current_sp)
4372         lr |= 4;
4373     if (env->v7m.exception == 0)
4374         lr |= 8;
4375
4376     /* For exceptions we just mark as pending on the NVIC, and let that
4377        handle it.  */
4378     /* TODO: Need to escalate if the current priority is higher than the
4379        one we're raising.  */
4380     switch (cs->exception_index) {
4381     case EXCP_UDEF:
4382         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
4383         return;
4384     case EXCP_SWI:
4385         /* The PC already points to the next instruction.  */
4386         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
4387         return;
4388     case EXCP_PREFETCH_ABORT:
4389     case EXCP_DATA_ABORT:
4390         /* TODO: if we implemented the MPU registers, this is where we
4391          * should set the MMFAR, etc from exception.fsr and exception.vaddress.
4392          */
4393         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
4394         return;
4395     case EXCP_BKPT:
4396         if (semihosting_enabled) {
4397             int nr;
4398             nr = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
4399             if (nr == 0xab) {
4400                 env->regs[15] += 2;
4401                 env->regs[0] = do_arm_semihosting(env);
4402                 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
4403                 return;
4404             }
4405         }
4406         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
4407         return;
4408     case EXCP_IRQ:
4409         env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
4410         break;
4411     case EXCP_EXCEPTION_EXIT:
4412         do_v7m_exception_exit(env);
4413         return;
4414     default:
4415         cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
4416         return; /* Never happens.  Keep compiler happy.  */
4417     }
4418
4419     /* Align stack pointer.  */
4420     /* ??? Should only do this if Configuration Control Register
4421        STACKALIGN bit is set.  */
4422     if (env->regs[13] & 4) {
4423         env->regs[13] -= 4;
4424         xpsr |= 0x200;
4425     }
4426     /* Switch to the handler mode.  */
4427     v7m_push(env, xpsr);
4428     v7m_push(env, env->regs[15]);
4429     v7m_push(env, env->regs[14]);
4430     v7m_push(env, env->regs[12]);
4431     v7m_push(env, env->regs[3]);
4432     v7m_push(env, env->regs[2]);
4433     v7m_push(env, env->regs[1]);
4434     v7m_push(env, env->regs[0]);
4435     switch_v7m_sp(env, 0);
4436     /* Clear IT bits */
4437     env->condexec_bits = 0;
4438     env->regs[14] = lr;
4439     addr = ldl_phys(cs->as, env->v7m.vecbase + env->v7m.exception * 4);
4440     env->regs[15] = addr & 0xfffffffe;
4441     env->thumb = addr & 1;
4442 }
4443
4444 /* Function used to synchronize QEMU's AArch64 register set with AArch32
4445  * register set.  This is necessary when switching between AArch32 and AArch64
4446  * execution state.
4447  */
4448 void aarch64_sync_32_to_64(CPUARMState *env)
4449 {
4450     int i;
4451     uint32_t mode = env->uncached_cpsr & CPSR_M;
4452
4453     /* We can blanket copy R[0:7] to X[0:7] */
4454     for (i = 0; i < 8; i++) {
4455         env->xregs[i] = env->regs[i];
4456     }
4457
4458     /* Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
4459      * Otherwise, they come from the banked user regs.
4460      */
4461     if (mode == ARM_CPU_MODE_FIQ) {
4462         for (i = 8; i < 13; i++) {
4463             env->xregs[i] = env->usr_regs[i - 8];
4464         }
4465     } else {
4466         for (i = 8; i < 13; i++) {
4467             env->xregs[i] = env->regs[i];
4468         }
4469     }
4470
4471     /* Registers x13-x23 are the various mode SP and FP registers. Registers
4472      * r13 and r14 are only copied if we are in that mode, otherwise we copy
4473      * from the mode banked register.
4474      */
4475     if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) {
4476         env->xregs[13] = env->regs[13];
4477         env->xregs[14] = env->regs[14];
4478     } else {
4479         env->xregs[13] = env->banked_r13[bank_number(ARM_CPU_MODE_USR)];
4480         /* HYP is an exception in that it is copied from r14 */
4481         if (mode == ARM_CPU_MODE_HYP) {
4482             env->xregs[14] = env->regs[14];
4483         } else {
4484             env->xregs[14] = env->banked_r14[bank_number(ARM_CPU_MODE_USR)];
4485         }
4486     }
4487
4488     if (mode == ARM_CPU_MODE_HYP) {
4489         env->xregs[15] = env->regs[13];
4490     } else {
4491         env->xregs[15] = env->banked_r13[bank_number(ARM_CPU_MODE_HYP)];
4492     }
4493
4494     if (mode == ARM_CPU_MODE_IRQ) {
4495         env->xregs[16] = env->regs[13];
4496         env->xregs[17] = env->regs[14];
4497     } else {
4498         env->xregs[16] = env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)];
4499         env->xregs[17] = env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)];
4500     }
4501
4502     if (mode == ARM_CPU_MODE_SVC) {
4503         env->xregs[18] = env->regs[13];
4504         env->xregs[19] = env->regs[14];
4505     } else {
4506         env->xregs[18] = env->banked_r13[bank_number(ARM_CPU_MODE_SVC)];
4507         env->xregs[19] = env->banked_r14[bank_number(ARM_CPU_MODE_SVC)];
4508     }
4509
4510     if (mode == ARM_CPU_MODE_ABT) {
4511         env->xregs[20] = env->regs[13];
4512         env->xregs[21] = env->regs[14];
4513     } else {
4514         env->xregs[20] = env->banked_r13[bank_number(ARM_CPU_MODE_ABT)];
4515         env->xregs[21] = env->banked_r14[bank_number(ARM_CPU_MODE_ABT)];
4516     }
4517
4518     if (mode == ARM_CPU_MODE_UND) {
4519         env->xregs[22] = env->regs[13];
4520         env->xregs[23] = env->regs[14];
4521     } else {
4522         env->xregs[22] = env->banked_r13[bank_number(ARM_CPU_MODE_UND)];
4523         env->xregs[23] = env->banked_r14[bank_number(ARM_CPU_MODE_UND)];
4524     }
4525
4526     /* Registers x24-x30 are mapped to r8-r14 in FIQ mode.  If we are in FIQ
4527      * mode, then we can copy from r8-r14.  Otherwise, we copy from the
4528      * FIQ bank for r8-r14.
4529      */
4530     if (mode == ARM_CPU_MODE_FIQ) {
4531         for (i = 24; i < 31; i++) {
4532             env->xregs[i] = env->regs[i - 16];   /* X[24:30] <- R[8:14] */
4533         }
4534     } else {
4535         for (i = 24; i < 29; i++) {
4536             env->xregs[i] = env->fiq_regs[i - 24];
4537         }
4538         env->xregs[29] = env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)];
4539         env->xregs[30] = env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)];
4540     }
4541
4542     env->pc = env->regs[15];
4543 }
4544
4545 /* Function used to synchronize QEMU's AArch32 register set with AArch64
4546  * register set.  This is necessary when switching between AArch32 and AArch64
4547  * execution state.
4548  */
4549 void aarch64_sync_64_to_32(CPUARMState *env)
4550 {
4551     int i;
4552     uint32_t mode = env->uncached_cpsr & CPSR_M;
4553
4554     /* We can blanket copy X[0:7] to R[0:7] */
4555     for (i = 0; i < 8; i++) {
4556         env->regs[i] = env->xregs[i];
4557     }
4558
4559     /* Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
4560      * Otherwise, we copy x8-x12 into the banked user regs.
4561      */
4562     if (mode == ARM_CPU_MODE_FIQ) {
4563         for (i = 8; i < 13; i++) {
4564             env->usr_regs[i - 8] = env->xregs[i];
4565         }
4566     } else {
4567         for (i = 8; i < 13; i++) {
4568             env->regs[i] = env->xregs[i];
4569         }
4570     }
4571
4572     /* Registers r13 & r14 depend on the current mode.
4573      * If we are in a given mode, we copy the corresponding x registers to r13
4574      * and r14.  Otherwise, we copy the x register to the banked r13 and r14
4575      * for the mode.
4576      */
4577     if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) {
4578         env->regs[13] = env->xregs[13];
4579         env->regs[14] = env->xregs[14];
4580     } else {
4581         env->banked_r13[bank_number(ARM_CPU_MODE_USR)] = env->xregs[13];
4582
4583         /* HYP is an exception in that it does not have its own banked r14 but
4584          * shares the USR r14
4585          */
4586         if (mode == ARM_CPU_MODE_HYP) {
4587             env->regs[14] = env->xregs[14];
4588         } else {
4589             env->banked_r14[bank_number(ARM_CPU_MODE_USR)] = env->xregs[14];
4590         }
4591     }
4592
4593     if (mode == ARM_CPU_MODE_HYP) {
4594         env->regs[13] = env->xregs[15];
4595     } else {
4596         env->banked_r13[bank_number(ARM_CPU_MODE_HYP)] = env->xregs[15];
4597     }
4598
4599     if (mode == ARM_CPU_MODE_IRQ) {
4600         env->regs[13] = env->xregs[16];
4601         env->regs[14] = env->xregs[17];
4602     } else {
4603         env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[16];
4604         env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[17];
4605     }
4606
4607     if (mode == ARM_CPU_MODE_SVC) {
4608         env->regs[13] = env->xregs[18];
4609         env->regs[14] = env->xregs[19];
4610     } else {
4611         env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[18];
4612         env->banked_r14[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[19];
4613     }
4614
4615     if (mode == ARM_CPU_MODE_ABT) {
4616         env->regs[13] = env->xregs[20];
4617         env->regs[14] = env->xregs[21];
4618     } else {
4619         env->banked_r13[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[20];
4620         env->banked_r14[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[21];
4621     }
4622
4623     if (mode == ARM_CPU_MODE_UND) {
4624         env->regs[13] = env->xregs[22];
4625         env->regs[14] = env->xregs[23];
4626     } else {
4627         env->banked_r13[bank_number(ARM_CPU_MODE_UND)] = env->xregs[22];
4628         env->banked_r14[bank_number(ARM_CPU_MODE_UND)] = env->xregs[23];
4629     }
4630
4631     /* Registers x24-x30 are mapped to r8-r14 in FIQ mode.  If we are in FIQ
4632      * mode, then we can copy to r8-r14.  Otherwise, we copy to the
4633      * FIQ bank for r8-r14.
4634      */
4635     if (mode == ARM_CPU_MODE_FIQ) {
4636         for (i = 24; i < 31; i++) {
4637             env->regs[i - 16] = env->xregs[i];   /* X[24:30] -> R[8:14] */
4638         }
4639     } else {
4640         for (i = 24; i < 29; i++) {
4641             env->fiq_regs[i - 24] = env->xregs[i];
4642         }
4643         env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[29];
4644         env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[30];
4645     }
4646
4647     env->regs[15] = env->pc;
4648 }
4649
4650 /* Handle a CPU exception.  */
4651 void arm_cpu_do_interrupt(CPUState *cs)
4652 {
4653     ARMCPU *cpu = ARM_CPU(cs);
4654     CPUARMState *env = &cpu->env;
4655     uint32_t addr;
4656     uint32_t mask;
4657     int new_mode;
4658     uint32_t offset;
4659     uint32_t moe;
4660
4661     assert(!IS_M(env));
4662
4663     arm_log_exception(cs->exception_index);
4664
4665     if (arm_is_psci_call(cpu, cs->exception_index)) {
4666         arm_handle_psci_call(cpu);
4667         qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n");
4668         return;
4669     }
4670
4671     /* If this is a debug exception we must update the DBGDSCR.MOE bits */
4672     switch (env->exception.syndrome >> ARM_EL_EC_SHIFT) {
4673     case EC_BREAKPOINT:
4674     case EC_BREAKPOINT_SAME_EL:
4675         moe = 1;
4676         break;
4677     case EC_WATCHPOINT:
4678     case EC_WATCHPOINT_SAME_EL:
4679         moe = 10;
4680         break;
4681     case EC_AA32_BKPT:
4682         moe = 3;
4683         break;
4684     case EC_VECTORCATCH:
4685         moe = 5;
4686         break;
4687     default:
4688         moe = 0;
4689         break;
4690     }
4691
4692     if (moe) {
4693         env->cp15.mdscr_el1 = deposit64(env->cp15.mdscr_el1, 2, 4, moe);
4694     }
4695
4696     /* TODO: Vectored interrupt controller.  */
4697     switch (cs->exception_index) {
4698     case EXCP_UDEF:
4699         new_mode = ARM_CPU_MODE_UND;
4700         addr = 0x04;
4701         mask = CPSR_I;
4702         if (env->thumb)
4703             offset = 2;
4704         else
4705             offset = 4;
4706         break;
4707     case EXCP_SWI:
4708         if (semihosting_enabled) {
4709             /* Check for semihosting interrupt.  */
4710             if (env->thumb) {
4711                 mask = arm_lduw_code(env, env->regs[15] - 2, env->bswap_code)
4712                     & 0xff;
4713             } else {
4714                 mask = arm_ldl_code(env, env->regs[15] - 4, env->bswap_code)
4715                     & 0xffffff;
4716             }
4717             /* Only intercept calls from privileged modes, to provide some
4718                semblance of security.  */
4719             if (((mask == 0x123456 && !env->thumb)
4720                     || (mask == 0xab && env->thumb))
4721                   && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
4722                 env->regs[0] = do_arm_semihosting(env);
4723                 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
4724                 return;
4725             }
4726         }
4727         new_mode = ARM_CPU_MODE_SVC;
4728         addr = 0x08;
4729         mask = CPSR_I;
4730         /* The PC already points to the next instruction.  */
4731         offset = 0;
4732         break;
4733     case EXCP_BKPT:
4734         /* See if this is a semihosting syscall.  */
4735         if (env->thumb && semihosting_enabled) {
4736             mask = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
4737             if (mask == 0xab
4738                   && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
4739                 env->regs[15] += 2;
4740                 env->regs[0] = do_arm_semihosting(env);
4741                 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
4742                 return;
4743             }
4744         }
4745         env->exception.fsr = 2;
4746         /* Fall through to prefetch abort.  */
4747     case EXCP_PREFETCH_ABORT:
4748         A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr);
4749         A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress);
4750         qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n",
4751                       env->exception.fsr, (uint32_t)env->exception.vaddress);
4752         new_mode = ARM_CPU_MODE_ABT;
4753         addr = 0x0c;
4754         mask = CPSR_A | CPSR_I;
4755         offset = 4;
4756         break;
4757     case EXCP_DATA_ABORT:
4758         A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr);
4759         A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress);
4760         qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n",
4761                       env->exception.fsr,
4762                       (uint32_t)env->exception.vaddress);
4763         new_mode = ARM_CPU_MODE_ABT;
4764         addr = 0x10;
4765         mask = CPSR_A | CPSR_I;
4766         offset = 8;
4767         break;
4768     case EXCP_IRQ:
4769         new_mode = ARM_CPU_MODE_IRQ;
4770         addr = 0x18;
4771         /* Disable IRQ and imprecise data aborts.  */
4772         mask = CPSR_A | CPSR_I;
4773         offset = 4;
4774         if (env->cp15.scr_el3 & SCR_IRQ) {
4775             /* IRQ routed to monitor mode */
4776             new_mode = ARM_CPU_MODE_MON;
4777             mask |= CPSR_F;
4778         }
4779         break;
4780     case EXCP_FIQ:
4781         new_mode = ARM_CPU_MODE_FIQ;
4782         addr = 0x1c;
4783         /* Disable FIQ, IRQ and imprecise data aborts.  */
4784         mask = CPSR_A | CPSR_I | CPSR_F;
4785         if (env->cp15.scr_el3 & SCR_FIQ) {
4786             /* FIQ routed to monitor mode */
4787             new_mode = ARM_CPU_MODE_MON;
4788         }
4789         offset = 4;
4790         break;
4791     case EXCP_SMC:
4792         new_mode = ARM_CPU_MODE_MON;
4793         addr = 0x08;
4794         mask = CPSR_A | CPSR_I | CPSR_F;
4795         offset = 0;
4796         break;
4797     default:
4798         cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
4799         return; /* Never happens.  Keep compiler happy.  */
4800     }
4801
4802     if (new_mode == ARM_CPU_MODE_MON) {
4803         addr += env->cp15.mvbar;
4804     } else if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
4805         /* High vectors. When enabled, base address cannot be remapped. */
4806         addr += 0xffff0000;
4807     } else {
4808         /* ARM v7 architectures provide a vector base address register to remap
4809          * the interrupt vector table.
4810          * This register is only followed in non-monitor mode, and is banked.
4811          * Note: only bits 31:5 are valid.
4812          */
4813         addr += A32_BANKED_CURRENT_REG_GET(env, vbar);
4814     }
4815
4816     if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
4817         env->cp15.scr_el3 &= ~SCR_NS;
4818     }
4819
4820     switch_mode (env, new_mode);
4821     /* For exceptions taken to AArch32 we must clear the SS bit in both
4822      * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
4823      */
4824     env->uncached_cpsr &= ~PSTATE_SS;
4825     env->spsr = cpsr_read(env);
4826     /* Clear IT bits.  */
4827     env->condexec_bits = 0;
4828     /* Switch to the new mode, and to the correct instruction set.  */
4829     env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
4830     env->daif |= mask;
4831     /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
4832      * and we should just guard the thumb mode on V4 */
4833     if (arm_feature(env, ARM_FEATURE_V4T)) {
4834         env->thumb = (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_TE) != 0;
4835     }
4836     env->regs[14] = env->regs[15] + offset;
4837     env->regs[15] = addr;
4838     cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
4839 }
4840
4841
4842 /* Return the exception level which controls this address translation regime */
4843 static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx)
4844 {
4845     switch (mmu_idx) {
4846     case ARMMMUIdx_S2NS:
4847     case ARMMMUIdx_S1E2:
4848         return 2;
4849     case ARMMMUIdx_S1E3:
4850         return 3;
4851     case ARMMMUIdx_S1SE0:
4852         return arm_el_is_aa64(env, 3) ? 1 : 3;
4853     case ARMMMUIdx_S1SE1:
4854     case ARMMMUIdx_S1NSE0:
4855     case ARMMMUIdx_S1NSE1:
4856         return 1;
4857     default:
4858         g_assert_not_reached();
4859     }
4860 }
4861
4862 /* Return true if this address translation regime is secure */
4863 static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx)
4864 {
4865     switch (mmu_idx) {
4866     case ARMMMUIdx_S12NSE0:
4867     case ARMMMUIdx_S12NSE1:
4868     case ARMMMUIdx_S1NSE0:
4869     case ARMMMUIdx_S1NSE1:
4870     case ARMMMUIdx_S1E2:
4871     case ARMMMUIdx_S2NS:
4872         return false;
4873     case ARMMMUIdx_S1E3:
4874     case ARMMMUIdx_S1SE0:
4875     case ARMMMUIdx_S1SE1:
4876         return true;
4877     default:
4878         g_assert_not_reached();
4879     }
4880 }
4881
4882 /* Return the SCTLR value which controls this address translation regime */
4883 static inline uint32_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx)
4884 {
4885     return env->cp15.sctlr_el[regime_el(env, mmu_idx)];
4886 }
4887
4888 /* Return true if the specified stage of address translation is disabled */
4889 static inline bool regime_translation_disabled(CPUARMState *env,
4890                                                ARMMMUIdx mmu_idx)
4891 {
4892     if (mmu_idx == ARMMMUIdx_S2NS) {
4893         return (env->cp15.hcr_el2 & HCR_VM) == 0;
4894     }
4895     return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0;
4896 }
4897
4898 /* Return the TCR controlling this translation regime */
4899 static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx)
4900 {
4901     if (mmu_idx == ARMMMUIdx_S2NS) {
4902         /* TODO: return VTCR_EL2 */
4903         g_assert_not_reached();
4904     }
4905     return &env->cp15.tcr_el[regime_el(env, mmu_idx)];
4906 }
4907
4908 /* Return the TTBR associated with this translation regime */
4909 static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx,
4910                                    int ttbrn)
4911 {
4912     if (mmu_idx == ARMMMUIdx_S2NS) {
4913         /* TODO: return VTTBR_EL2 */
4914         g_assert_not_reached();
4915     }
4916     if (ttbrn == 0) {
4917         return env->cp15.ttbr0_el[regime_el(env, mmu_idx)];
4918     } else {
4919         return env->cp15.ttbr1_el[regime_el(env, mmu_idx)];
4920     }
4921 }
4922
4923 /* Return true if the translation regime is using LPAE format page tables */
4924 static inline bool regime_using_lpae_format(CPUARMState *env,
4925                                             ARMMMUIdx mmu_idx)
4926 {
4927     int el = regime_el(env, mmu_idx);
4928     if (el == 2 || arm_el_is_aa64(env, el)) {
4929         return true;
4930     }
4931     if (arm_feature(env, ARM_FEATURE_LPAE)
4932         && (regime_tcr(env, mmu_idx)->raw_tcr & TTBCR_EAE)) {
4933         return true;
4934     }
4935     return false;
4936 }
4937
4938 static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx)
4939 {
4940     switch (mmu_idx) {
4941     case ARMMMUIdx_S1SE0:
4942     case ARMMMUIdx_S1NSE0:
4943         return true;
4944     default:
4945         return false;
4946     case ARMMMUIdx_S12NSE0:
4947     case ARMMMUIdx_S12NSE1:
4948         g_assert_not_reached();
4949     }
4950 }
4951
4952 /* Translate section/page access permissions to page
4953  * R/W protection flags
4954  *
4955  * @env:         CPUARMState
4956  * @mmu_idx:     MMU index indicating required translation regime
4957  * @ap:          The 3-bit access permissions (AP[2:0])
4958  * @domain_prot: The 2-bit domain access permissions
4959  */
4960 static inline int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx,
4961                                 int ap, int domain_prot)
4962 {
4963     bool is_user = regime_is_user(env, mmu_idx);
4964
4965     if (domain_prot == 3) {
4966         return PAGE_READ | PAGE_WRITE;
4967     }
4968
4969     switch (ap) {
4970     case 0:
4971         if (arm_feature(env, ARM_FEATURE_V7)) {
4972             return 0;
4973         }
4974         switch (regime_sctlr(env, mmu_idx) & (SCTLR_S | SCTLR_R)) {
4975         case SCTLR_S:
4976             return is_user ? 0 : PAGE_READ;
4977         case SCTLR_R:
4978             return PAGE_READ;
4979         default:
4980             return 0;
4981         }
4982     case 1:
4983         return is_user ? 0 : PAGE_READ | PAGE_WRITE;
4984     case 2:
4985         if (is_user) {
4986             return PAGE_READ;
4987         } else {
4988             return PAGE_READ | PAGE_WRITE;
4989         }
4990     case 3:
4991         return PAGE_READ | PAGE_WRITE;
4992     case 4: /* Reserved.  */
4993         return 0;
4994     case 5:
4995         return is_user ? 0 : PAGE_READ;
4996     case 6:
4997         return PAGE_READ;
4998     case 7:
4999         if (!arm_feature(env, ARM_FEATURE_V6K)) {
5000             return 0;
5001         }
5002         return PAGE_READ;
5003     default:
5004         g_assert_not_reached();
5005     }
5006 }
5007
5008 /* Translate section/page access permissions to page
5009  * R/W protection flags.
5010  *
5011  * @ap:      The 2-bit simple AP (AP[2:1])
5012  * @is_user: TRUE if accessing from PL0
5013  */
5014 static inline int simple_ap_to_rw_prot_is_user(int ap, bool is_user)
5015 {
5016     switch (ap) {
5017     case 0:
5018         return is_user ? 0 : PAGE_READ | PAGE_WRITE;
5019     case 1:
5020         return PAGE_READ | PAGE_WRITE;
5021     case 2:
5022         return is_user ? 0 : PAGE_READ;
5023     case 3:
5024         return PAGE_READ;
5025     default:
5026         g_assert_not_reached();
5027     }
5028 }
5029
5030 static inline int
5031 simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap)
5032 {
5033     return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx));
5034 }
5035
5036 /* Translate section/page access permissions to protection flags
5037  *
5038  * @env:     CPUARMState
5039  * @mmu_idx: MMU index indicating required translation regime
5040  * @is_aa64: TRUE if AArch64
5041  * @ap:      The 2-bit simple AP (AP[2:1])
5042  * @ns:      NS (non-secure) bit
5043  * @xn:      XN (execute-never) bit
5044  * @pxn:     PXN (privileged execute-never) bit
5045  */
5046 static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64,
5047                       int ap, int ns, int xn, int pxn)
5048 {
5049     bool is_user = regime_is_user(env, mmu_idx);
5050     int prot_rw, user_rw;
5051     bool have_wxn;
5052     int wxn = 0;
5053
5054     assert(mmu_idx != ARMMMUIdx_S2NS);
5055
5056     user_rw = simple_ap_to_rw_prot_is_user(ap, true);
5057     if (is_user) {
5058         prot_rw = user_rw;
5059     } else {
5060         prot_rw = simple_ap_to_rw_prot_is_user(ap, false);
5061     }
5062
5063     if (ns && arm_is_secure(env) && (env->cp15.scr_el3 & SCR_SIF)) {
5064         return prot_rw;
5065     }
5066
5067     /* TODO have_wxn should be replaced with
5068      *   ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2)
5069      * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE
5070      * compatible processors have EL2, which is required for [U]WXN.
5071      */
5072     have_wxn = arm_feature(env, ARM_FEATURE_LPAE);
5073
5074     if (have_wxn) {
5075         wxn = regime_sctlr(env, mmu_idx) & SCTLR_WXN;
5076     }
5077
5078     if (is_aa64) {
5079         switch (regime_el(env, mmu_idx)) {
5080         case 1:
5081             if (!is_user) {
5082                 xn = pxn || (user_rw & PAGE_WRITE);
5083             }
5084             break;
5085         case 2:
5086         case 3:
5087             break;
5088         }
5089     } else if (arm_feature(env, ARM_FEATURE_V7)) {
5090         switch (regime_el(env, mmu_idx)) {
5091         case 1:
5092         case 3:
5093             if (is_user) {
5094                 xn = xn || !(user_rw & PAGE_READ);
5095             } else {
5096                 int uwxn = 0;
5097                 if (have_wxn) {
5098                     uwxn = regime_sctlr(env, mmu_idx) & SCTLR_UWXN;
5099                 }
5100                 xn = xn || !(prot_rw & PAGE_READ) || pxn ||
5101                      (uwxn && (user_rw & PAGE_WRITE));
5102             }
5103             break;
5104         case 2:
5105             break;
5106         }
5107     } else {
5108         xn = wxn = 0;
5109     }
5110
5111     if (xn || (wxn && (prot_rw & PAGE_WRITE))) {
5112         return prot_rw;
5113     }
5114     return prot_rw | PAGE_EXEC;
5115 }
5116
5117 static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx,
5118                                      uint32_t *table, uint32_t address)
5119 {
5120     /* Note that we can only get here for an AArch32 PL0/PL1 lookup */
5121     TCR *tcr = regime_tcr(env, mmu_idx);
5122
5123     if (address & tcr->mask) {
5124         if (tcr->raw_tcr & TTBCR_PD1) {
5125             /* Translation table walk disabled for TTBR1 */
5126             return false;
5127         }
5128         *table = regime_ttbr(env, mmu_idx, 1) & 0xffffc000;
5129     } else {
5130         if (tcr->raw_tcr & TTBCR_PD0) {
5131             /* Translation table walk disabled for TTBR0 */
5132             return false;
5133         }
5134         *table = regime_ttbr(env, mmu_idx, 0) & tcr->base_mask;
5135     }
5136     *table |= (address >> 18) & 0x3ffc;
5137     return true;
5138 }
5139
5140 /* All loads done in the course of a page table walk go through here.
5141  * TODO: rather than ignoring errors from physical memory reads (which
5142  * are external aborts in ARM terminology) we should propagate this
5143  * error out so that we can turn it into a Data Abort if this walk
5144  * was being done for a CPU load/store or an address translation instruction
5145  * (but not if it was for a debug access).
5146  */
5147 static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure)
5148 {
5149     MemTxAttrs attrs = {};
5150
5151     attrs.secure = is_secure;
5152     return address_space_ldl(cs->as, addr, attrs, NULL);
5153 }
5154
5155 static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure)
5156 {
5157     MemTxAttrs attrs = {};
5158
5159     attrs.secure = is_secure;
5160     return address_space_ldq(cs->as, addr, attrs, NULL);
5161 }
5162
5163 static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type,
5164                             ARMMMUIdx mmu_idx, hwaddr *phys_ptr,
5165                             int *prot, target_ulong *page_size)
5166 {
5167     CPUState *cs = CPU(arm_env_get_cpu(env));
5168     int code;
5169     uint32_t table;
5170     uint32_t desc;
5171     int type;
5172     int ap;
5173     int domain = 0;
5174     int domain_prot;
5175     hwaddr phys_addr;
5176     uint32_t dacr;
5177
5178     /* Pagetable walk.  */
5179     /* Lookup l1 descriptor.  */
5180     if (!get_level1_table_address(env, mmu_idx, &table, address)) {
5181         /* Section translation fault if page walk is disabled by PD0 or PD1 */
5182         code = 5;
5183         goto do_fault;
5184     }
5185     desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx));
5186     type = (desc & 3);
5187     domain = (desc >> 5) & 0x0f;
5188     if (regime_el(env, mmu_idx) == 1) {
5189         dacr = env->cp15.dacr_ns;
5190     } else {
5191         dacr = env->cp15.dacr_s;
5192     }
5193     domain_prot = (dacr >> (domain * 2)) & 3;
5194     if (type == 0) {
5195         /* Section translation fault.  */
5196         code = 5;
5197         goto do_fault;
5198     }
5199     if (domain_prot == 0 || domain_prot == 2) {
5200         if (type == 2)
5201             code = 9; /* Section domain fault.  */
5202         else
5203             code = 11; /* Page domain fault.  */
5204         goto do_fault;
5205     }
5206     if (type == 2) {
5207         /* 1Mb section.  */
5208         phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
5209         ap = (desc >> 10) & 3;
5210         code = 13;
5211         *page_size = 1024 * 1024;
5212     } else {
5213         /* Lookup l2 entry.  */
5214         if (type == 1) {
5215             /* Coarse pagetable.  */
5216             table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
5217         } else {
5218             /* Fine pagetable.  */
5219             table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
5220         }
5221         desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx));
5222         switch (desc & 3) {
5223         case 0: /* Page translation fault.  */
5224             code = 7;
5225             goto do_fault;
5226         case 1: /* 64k page.  */
5227             phys_addr = (desc & 0xffff0000) | (address & 0xffff);
5228             ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
5229             *page_size = 0x10000;
5230             break;
5231         case 2: /* 4k page.  */
5232             phys_addr = (desc & 0xfffff000) | (address & 0xfff);
5233             ap = (desc >> (4 + ((address >> 9) & 6))) & 3;
5234             *page_size = 0x1000;
5235             break;
5236         case 3: /* 1k page.  */
5237             if (type == 1) {
5238                 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
5239                     phys_addr = (desc & 0xfffff000) | (address & 0xfff);
5240                 } else {
5241                     /* Page translation fault.  */
5242                     code = 7;
5243                     goto do_fault;
5244                 }
5245             } else {
5246                 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
5247             }
5248             ap = (desc >> 4) & 3;
5249             *page_size = 0x400;
5250             break;
5251         default:
5252             /* Never happens, but compiler isn't smart enough to tell.  */
5253             abort();
5254         }
5255         code = 15;
5256     }
5257     *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
5258     *prot |= *prot ? PAGE_EXEC : 0;
5259     if (!(*prot & (1 << access_type))) {
5260         /* Access permission fault.  */
5261         goto do_fault;
5262     }
5263     *phys_ptr = phys_addr;
5264     return 0;
5265 do_fault:
5266     return code | (domain << 4);
5267 }
5268
5269 static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type,
5270                             ARMMMUIdx mmu_idx, hwaddr *phys_ptr,
5271                             MemTxAttrs *attrs,
5272                             int *prot, target_ulong *page_size)
5273 {
5274     CPUState *cs = CPU(arm_env_get_cpu(env));
5275     int code;
5276     uint32_t table;
5277     uint32_t desc;
5278     uint32_t xn;
5279     uint32_t pxn = 0;
5280     int type;
5281     int ap;
5282     int domain = 0;
5283     int domain_prot;
5284     hwaddr phys_addr;
5285     uint32_t dacr;
5286     bool ns;
5287
5288     /* Pagetable walk.  */
5289     /* Lookup l1 descriptor.  */
5290     if (!get_level1_table_address(env, mmu_idx, &table, address)) {
5291         /* Section translation fault if page walk is disabled by PD0 or PD1 */
5292         code = 5;
5293         goto do_fault;
5294     }
5295     desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx));
5296     type = (desc & 3);
5297     if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
5298         /* Section translation fault, or attempt to use the encoding
5299          * which is Reserved on implementations without PXN.
5300          */
5301         code = 5;
5302         goto do_fault;
5303     }
5304     if ((type == 1) || !(desc & (1 << 18))) {
5305         /* Page or Section.  */
5306         domain = (desc >> 5) & 0x0f;
5307     }
5308     if (regime_el(env, mmu_idx) == 1) {
5309         dacr = env->cp15.dacr_ns;
5310     } else {
5311         dacr = env->cp15.dacr_s;
5312     }
5313     domain_prot = (dacr >> (domain * 2)) & 3;
5314     if (domain_prot == 0 || domain_prot == 2) {
5315         if (type != 1) {
5316             code = 9; /* Section domain fault.  */
5317         } else {
5318             code = 11; /* Page domain fault.  */
5319         }
5320         goto do_fault;
5321     }
5322     if (type != 1) {
5323         if (desc & (1 << 18)) {
5324             /* Supersection.  */
5325             phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
5326             *page_size = 0x1000000;
5327         } else {
5328             /* Section.  */
5329             phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
5330             *page_size = 0x100000;
5331         }
5332         ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
5333         xn = desc & (1 << 4);
5334         pxn = desc & 1;
5335         code = 13;
5336         ns = extract32(desc, 19, 1);
5337     } else {
5338         if (arm_feature(env, ARM_FEATURE_PXN)) {
5339             pxn = (desc >> 2) & 1;
5340         }
5341         ns = extract32(desc, 3, 1);
5342         /* Lookup l2 entry.  */
5343         table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
5344         desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx));
5345         ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
5346         switch (desc & 3) {
5347         case 0: /* Page translation fault.  */
5348             code = 7;
5349             goto do_fault;
5350         case 1: /* 64k page.  */
5351             phys_addr = (desc & 0xffff0000) | (address & 0xffff);
5352             xn = desc & (1 << 15);
5353             *page_size = 0x10000;
5354             break;
5355         case 2: case 3: /* 4k page.  */
5356             phys_addr = (desc & 0xfffff000) | (address & 0xfff);
5357             xn = desc & 1;
5358             *page_size = 0x1000;
5359             break;
5360         default:
5361             /* Never happens, but compiler isn't smart enough to tell.  */
5362             abort();
5363         }
5364         code = 15;
5365     }
5366     if (domain_prot == 3) {
5367         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
5368     } else {
5369         if (pxn && !regime_is_user(env, mmu_idx)) {
5370             xn = 1;
5371         }
5372         if (xn && access_type == 2)
5373             goto do_fault;
5374
5375         if (arm_feature(env, ARM_FEATURE_V6K) &&
5376                 (regime_sctlr(env, mmu_idx) & SCTLR_AFE)) {
5377             /* The simplified model uses AP[0] as an access control bit.  */
5378             if ((ap & 1) == 0) {
5379                 /* Access flag fault.  */
5380                 code = (code == 15) ? 6 : 3;
5381                 goto do_fault;
5382             }
5383             *prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1);
5384         } else {
5385             *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
5386         }
5387         if (*prot && !xn) {
5388             *prot |= PAGE_EXEC;
5389         }
5390         if (!(*prot & (1 << access_type))) {
5391             /* Access permission fault.  */
5392             goto do_fault;
5393         }
5394     }
5395     if (ns) {
5396         /* The NS bit will (as required by the architecture) have no effect if
5397          * the CPU doesn't support TZ or this is a non-secure translation
5398          * regime, because the attribute will already be non-secure.
5399          */
5400         attrs->secure = false;
5401     }
5402     *phys_ptr = phys_addr;
5403     return 0;
5404 do_fault:
5405     return code | (domain << 4);
5406 }
5407
5408 /* Fault type for long-descriptor MMU fault reporting; this corresponds
5409  * to bits [5..2] in the STATUS field in long-format DFSR/IFSR.
5410  */
5411 typedef enum {
5412     translation_fault = 1,
5413     access_fault = 2,
5414     permission_fault = 3,
5415 } MMUFaultType;
5416
5417 static int get_phys_addr_lpae(CPUARMState *env, target_ulong address,
5418                               int access_type, ARMMMUIdx mmu_idx,
5419                               hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
5420                               target_ulong *page_size_ptr)
5421 {
5422     CPUState *cs = CPU(arm_env_get_cpu(env));
5423     /* Read an LPAE long-descriptor translation table. */
5424     MMUFaultType fault_type = translation_fault;
5425     uint32_t level = 1;
5426     uint32_t epd;
5427     int32_t tsz;
5428     uint32_t tg;
5429     uint64_t ttbr;
5430     int ttbr_select;
5431     hwaddr descaddr, descmask;
5432     uint32_t tableattrs;
5433     target_ulong page_size;
5434     uint32_t attrs;
5435     int32_t granule_sz = 9;
5436     int32_t va_size = 32;
5437     int32_t tbi = 0;
5438     TCR *tcr = regime_tcr(env, mmu_idx);
5439     int ap, ns, xn, pxn;
5440     uint32_t el = regime_el(env, mmu_idx);
5441     bool ttbr1_valid = true;
5442
5443     /* TODO:
5444      * This code does not handle the different format TCR for VTCR_EL2.
5445      * This code also does not support shareability levels.
5446      * Attribute and permission bit handling should also be checked when adding
5447      * support for those page table walks.
5448      */
5449     if (arm_el_is_aa64(env, el)) {
5450         va_size = 64;
5451         if (el > 1) {
5452             tbi = extract64(tcr->raw_tcr, 20, 1);
5453         } else {
5454             if (extract64(address, 55, 1)) {
5455                 tbi = extract64(tcr->raw_tcr, 38, 1);
5456             } else {
5457                 tbi = extract64(tcr->raw_tcr, 37, 1);
5458             }
5459         }
5460         tbi *= 8;
5461
5462         /* If we are in 64-bit EL2 or EL3 then there is no TTBR1, so mark it
5463          * invalid.
5464          */
5465         if (el > 1) {
5466             ttbr1_valid = false;
5467         }
5468     }
5469
5470     /* Determine whether this address is in the region controlled by
5471      * TTBR0 or TTBR1 (or if it is in neither region and should fault).
5472      * This is a Non-secure PL0/1 stage 1 translation, so controlled by
5473      * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
5474      */
5475     uint32_t t0sz = extract32(tcr->raw_tcr, 0, 6);
5476     if (va_size == 64) {
5477         t0sz = MIN(t0sz, 39);
5478         t0sz = MAX(t0sz, 16);
5479     }
5480     uint32_t t1sz = extract32(tcr->raw_tcr, 16, 6);
5481     if (va_size == 64) {
5482         t1sz = MIN(t1sz, 39);
5483         t1sz = MAX(t1sz, 16);
5484     }
5485     if (t0sz && !extract64(address, va_size - t0sz, t0sz - tbi)) {
5486         /* there is a ttbr0 region and we are in it (high bits all zero) */
5487         ttbr_select = 0;
5488     } else if (ttbr1_valid && t1sz &&
5489                !extract64(~address, va_size - t1sz, t1sz - tbi)) {
5490         /* there is a ttbr1 region and we are in it (high bits all one) */
5491         ttbr_select = 1;
5492     } else if (!t0sz) {
5493         /* ttbr0 region is "everything not in the ttbr1 region" */
5494         ttbr_select = 0;
5495     } else if (!t1sz && ttbr1_valid) {
5496         /* ttbr1 region is "everything not in the ttbr0 region" */
5497         ttbr_select = 1;
5498     } else {
5499         /* in the gap between the two regions, this is a Translation fault */
5500         fault_type = translation_fault;
5501         goto do_fault;
5502     }
5503
5504     /* Note that QEMU ignores shareability and cacheability attributes,
5505      * so we don't need to do anything with the SH, ORGN, IRGN fields
5506      * in the TTBCR.  Similarly, TTBCR:A1 selects whether we get the
5507      * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
5508      * implement any ASID-like capability so we can ignore it (instead
5509      * we will always flush the TLB any time the ASID is changed).
5510      */
5511     if (ttbr_select == 0) {
5512         ttbr = regime_ttbr(env, mmu_idx, 0);
5513         epd = extract32(tcr->raw_tcr, 7, 1);
5514         tsz = t0sz;
5515
5516         tg = extract32(tcr->raw_tcr, 14, 2);
5517         if (tg == 1) { /* 64KB pages */
5518             granule_sz = 13;
5519         }
5520         if (tg == 2) { /* 16KB pages */
5521             granule_sz = 11;
5522         }
5523     } else {
5524         /* We should only be here if TTBR1 is valid */
5525         assert(ttbr1_valid);
5526
5527         ttbr = regime_ttbr(env, mmu_idx, 1);
5528         epd = extract32(tcr->raw_tcr, 23, 1);
5529         tsz = t1sz;
5530
5531         tg = extract32(tcr->raw_tcr, 30, 2);
5532         if (tg == 3)  { /* 64KB pages */
5533             granule_sz = 13;
5534         }
5535         if (tg == 1) { /* 16KB pages */
5536             granule_sz = 11;
5537         }
5538     }
5539
5540     /* Here we should have set up all the parameters for the translation:
5541      * va_size, ttbr, epd, tsz, granule_sz, tbi
5542      */
5543
5544     if (epd) {
5545         /* Translation table walk disabled => Translation fault on TLB miss
5546          * Note: This is always 0 on 64-bit EL2 and EL3.
5547          */
5548         goto do_fault;
5549     }
5550
5551     /* The starting level depends on the virtual address size (which can be
5552      * up to 48 bits) and the translation granule size. It indicates the number
5553      * of strides (granule_sz bits at a time) needed to consume the bits
5554      * of the input address. In the pseudocode this is:
5555      *  level = 4 - RoundUp((inputsize - grainsize) / stride)
5556      * where their 'inputsize' is our 'va_size - tsz', 'grainsize' is
5557      * our 'granule_sz + 3' and 'stride' is our 'granule_sz'.
5558      * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying:
5559      *     = 4 - (va_size - tsz - granule_sz - 3 + granule_sz - 1) / granule_sz
5560      *     = 4 - (va_size - tsz - 4) / granule_sz;
5561      */
5562     level = 4 - (va_size - tsz - 4) / granule_sz;
5563
5564     /* Clear the vaddr bits which aren't part of the within-region address,
5565      * so that we don't have to special case things when calculating the
5566      * first descriptor address.
5567      */
5568     if (tsz) {
5569         address &= (1ULL << (va_size - tsz)) - 1;
5570     }
5571
5572     descmask = (1ULL << (granule_sz + 3)) - 1;
5573
5574     /* Now we can extract the actual base address from the TTBR */
5575     descaddr = extract64(ttbr, 0, 48);
5576     descaddr &= ~((1ULL << (va_size - tsz - (granule_sz * (4 - level)))) - 1);
5577
5578     /* Secure accesses start with the page table in secure memory and
5579      * can be downgraded to non-secure at any step. Non-secure accesses
5580      * remain non-secure. We implement this by just ORing in the NSTable/NS
5581      * bits at each step.
5582      */
5583     tableattrs = regime_is_secure(env, mmu_idx) ? 0 : (1 << 4);
5584     for (;;) {
5585         uint64_t descriptor;
5586         bool nstable;
5587
5588         descaddr |= (address >> (granule_sz * (4 - level))) & descmask;
5589         descaddr &= ~7ULL;
5590         nstable = extract32(tableattrs, 4, 1);
5591         descriptor = arm_ldq_ptw(cs, descaddr, !nstable);
5592         if (!(descriptor & 1) ||
5593             (!(descriptor & 2) && (level == 3))) {
5594             /* Invalid, or the Reserved level 3 encoding */
5595             goto do_fault;
5596         }
5597         descaddr = descriptor & 0xfffffff000ULL;
5598
5599         if ((descriptor & 2) && (level < 3)) {
5600             /* Table entry. The top five bits are attributes which  may
5601              * propagate down through lower levels of the table (and
5602              * which are all arranged so that 0 means "no effect", so
5603              * we can gather them up by ORing in the bits at each level).
5604              */
5605             tableattrs |= extract64(descriptor, 59, 5);
5606             level++;
5607             continue;
5608         }
5609         /* Block entry at level 1 or 2, or page entry at level 3.
5610          * These are basically the same thing, although the number
5611          * of bits we pull in from the vaddr varies.
5612          */
5613         page_size = (1ULL << ((granule_sz * (4 - level)) + 3));
5614         descaddr |= (address & (page_size - 1));
5615         /* Extract attributes from the descriptor and merge with table attrs */
5616         attrs = extract64(descriptor, 2, 10)
5617             | (extract64(descriptor, 52, 12) << 10);
5618         attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
5619         attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */
5620         /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
5621          * means "force PL1 access only", which means forcing AP[1] to 0.
5622          */
5623         if (extract32(tableattrs, 2, 1)) {
5624             attrs &= ~(1 << 4);
5625         }
5626         attrs |= nstable << 3; /* NS */
5627         break;
5628     }
5629     /* Here descaddr is the final physical address, and attributes
5630      * are all in attrs.
5631      */
5632     fault_type = access_fault;
5633     if ((attrs & (1 << 8)) == 0) {
5634         /* Access flag */
5635         goto do_fault;
5636     }
5637
5638     ap = extract32(attrs, 4, 2);
5639     ns = extract32(attrs, 3, 1);
5640     xn = extract32(attrs, 12, 1);
5641     pxn = extract32(attrs, 11, 1);
5642
5643     *prot = get_S1prot(env, mmu_idx, va_size == 64, ap, ns, xn, pxn);
5644
5645     fault_type = permission_fault;
5646     if (!(*prot & (1 << access_type))) {
5647         goto do_fault;
5648     }
5649
5650     if (ns) {
5651         /* The NS bit will (as required by the architecture) have no effect if
5652          * the CPU doesn't support TZ or this is a non-secure translation
5653          * regime, because the attribute will already be non-secure.
5654          */
5655         txattrs->secure = false;
5656     }
5657     *phys_ptr = descaddr;
5658     *page_size_ptr = page_size;
5659     return 0;
5660
5661 do_fault:
5662     /* Long-descriptor format IFSR/DFSR value */
5663     return (1 << 9) | (fault_type << 2) | level;
5664 }
5665
5666 static int get_phys_addr_mpu(CPUARMState *env, uint32_t address,
5667                              int access_type, ARMMMUIdx mmu_idx,
5668                              hwaddr *phys_ptr, int *prot)
5669 {
5670     int n;
5671     uint32_t mask;
5672     uint32_t base;
5673     bool is_user = regime_is_user(env, mmu_idx);
5674
5675     *phys_ptr = address;
5676     for (n = 7; n >= 0; n--) {
5677         base = env->cp15.c6_region[n];
5678         if ((base & 1) == 0) {
5679             continue;
5680         }
5681         mask = 1 << ((base >> 1) & 0x1f);
5682         /* Keep this shift separate from the above to avoid an
5683            (undefined) << 32.  */
5684         mask = (mask << 1) - 1;
5685         if (((base ^ address) & ~mask) == 0) {
5686             break;
5687         }
5688     }
5689     if (n < 0) {
5690         return 2;
5691     }
5692
5693     if (access_type == 2) {
5694         mask = env->cp15.pmsav5_insn_ap;
5695     } else {
5696         mask = env->cp15.pmsav5_data_ap;
5697     }
5698     mask = (mask >> (n * 4)) & 0xf;
5699     switch (mask) {
5700     case 0:
5701         return 1;
5702     case 1:
5703         if (is_user) {
5704             return 1;
5705         }
5706         *prot = PAGE_READ | PAGE_WRITE;
5707         break;
5708     case 2:
5709         *prot = PAGE_READ;
5710         if (!is_user) {
5711             *prot |= PAGE_WRITE;
5712         }
5713         break;
5714     case 3:
5715         *prot = PAGE_READ | PAGE_WRITE;
5716         break;
5717     case 5:
5718         if (is_user) {
5719             return 1;
5720         }
5721         *prot = PAGE_READ;
5722         break;
5723     case 6:
5724         *prot = PAGE_READ;
5725         break;
5726     default:
5727         /* Bad permission.  */
5728         return 1;
5729     }
5730     *prot |= PAGE_EXEC;
5731     return 0;
5732 }
5733
5734 /* get_phys_addr - get the physical address for this virtual address
5735  *
5736  * Find the physical address corresponding to the given virtual address,
5737  * by doing a translation table walk on MMU based systems or using the
5738  * MPU state on MPU based systems.
5739  *
5740  * Returns 0 if the translation was successful. Otherwise, phys_ptr, attrs,
5741  * prot and page_size may not be filled in, and the return value provides
5742  * information on why the translation aborted, in the format of a
5743  * DFSR/IFSR fault register, with the following caveats:
5744  *  * we honour the short vs long DFSR format differences.
5745  *  * the WnR bit is never set (the caller must do this).
5746  *  * for MPU based systems we don't bother to return a full FSR format
5747  *    value.
5748  *
5749  * @env: CPUARMState
5750  * @address: virtual address to get physical address for
5751  * @access_type: 0 for read, 1 for write, 2 for execute
5752  * @mmu_idx: MMU index indicating required translation regime
5753  * @phys_ptr: set to the physical address corresponding to the virtual address
5754  * @attrs: set to the memory transaction attributes to use
5755  * @prot: set to the permissions for the page containing phys_ptr
5756  * @page_size: set to the size of the page containing phys_ptr
5757  */
5758 static inline int get_phys_addr(CPUARMState *env, target_ulong address,
5759                                 int access_type, ARMMMUIdx mmu_idx,
5760                                 hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
5761                                 target_ulong *page_size)
5762 {
5763     if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
5764         /* TODO: when we support EL2 we should here call ourselves recursively
5765          * to do the stage 1 and then stage 2 translations. The arm_ld*_ptw
5766          * functions will also need changing to perform ARMMMUIdx_S2NS loads
5767          * rather than direct physical memory loads when appropriate.
5768          * For non-EL2 CPUs a stage1+stage2 translation is just stage 1.
5769          */
5770         assert(!arm_feature(env, ARM_FEATURE_EL2));
5771         mmu_idx += ARMMMUIdx_S1NSE0;
5772     }
5773
5774     /* The page table entries may downgrade secure to non-secure, but
5775      * cannot upgrade an non-secure translation regime's attributes
5776      * to secure.
5777      */
5778     attrs->secure = regime_is_secure(env, mmu_idx);
5779     attrs->user = regime_is_user(env, mmu_idx);
5780
5781     /* Fast Context Switch Extension. This doesn't exist at all in v8.
5782      * In v7 and earlier it affects all stage 1 translations.
5783      */
5784     if (address < 0x02000000 && mmu_idx != ARMMMUIdx_S2NS
5785         && !arm_feature(env, ARM_FEATURE_V8)) {
5786         if (regime_el(env, mmu_idx) == 3) {
5787             address += env->cp15.fcseidr_s;
5788         } else {
5789             address += env->cp15.fcseidr_ns;
5790         }
5791     }
5792
5793     if (regime_translation_disabled(env, mmu_idx)) {
5794         /* MMU/MPU disabled.  */
5795         *phys_ptr = address;
5796         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
5797         *page_size = TARGET_PAGE_SIZE;
5798         return 0;
5799     }
5800
5801     if (arm_feature(env, ARM_FEATURE_MPU)) {
5802         *page_size = TARGET_PAGE_SIZE;
5803         return get_phys_addr_mpu(env, address, access_type, mmu_idx, phys_ptr,
5804                                  prot);
5805     }
5806
5807     if (regime_using_lpae_format(env, mmu_idx)) {
5808         return get_phys_addr_lpae(env, address, access_type, mmu_idx, phys_ptr,
5809                                   attrs, prot, page_size);
5810     } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) {
5811         return get_phys_addr_v6(env, address, access_type, mmu_idx, phys_ptr,
5812                                 attrs, prot, page_size);
5813     } else {
5814         return get_phys_addr_v5(env, address, access_type, mmu_idx, phys_ptr,
5815                                 prot, page_size);
5816     }
5817 }
5818
5819 /* Walk the page table and (if the mapping exists) add the page
5820  * to the TLB. Return 0 on success, or an ARM DFSR/IFSR fault
5821  * register format value on failure.
5822  */
5823 int arm_tlb_fill(CPUState *cs, vaddr address,
5824                  int access_type, int mmu_idx)
5825 {
5826     ARMCPU *cpu = ARM_CPU(cs);
5827     CPUARMState *env = &cpu->env;
5828     hwaddr phys_addr;
5829     target_ulong page_size;
5830     int prot;
5831     int ret;
5832     MemTxAttrs attrs = {};
5833
5834     ret = get_phys_addr(env, address, access_type, mmu_idx, &phys_addr,
5835                         &attrs, &prot, &page_size);
5836     if (ret == 0) {
5837         /* Map a single [sub]page.  */
5838         phys_addr &= TARGET_PAGE_MASK;
5839         address &= TARGET_PAGE_MASK;
5840         tlb_set_page_with_attrs(cs, address, phys_addr, attrs,
5841                                 prot, mmu_idx, page_size);
5842         return 0;
5843     }
5844
5845     return ret;
5846 }
5847
5848 hwaddr arm_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
5849 {
5850     ARMCPU *cpu = ARM_CPU(cs);
5851     CPUARMState *env = &cpu->env;
5852     hwaddr phys_addr;
5853     target_ulong page_size;
5854     int prot;
5855     int ret;
5856     MemTxAttrs attrs = {};
5857
5858     ret = get_phys_addr(env, addr, 0, cpu_mmu_index(env), &phys_addr,
5859                         &attrs, &prot, &page_size);
5860
5861     if (ret != 0) {
5862         return -1;
5863     }
5864
5865     return phys_addr;
5866 }
5867
5868 void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
5869 {
5870     if ((env->uncached_cpsr & CPSR_M) == mode) {
5871         env->regs[13] = val;
5872     } else {
5873         env->banked_r13[bank_number(mode)] = val;
5874     }
5875 }
5876
5877 uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
5878 {
5879     if ((env->uncached_cpsr & CPSR_M) == mode) {
5880         return env->regs[13];
5881     } else {
5882         return env->banked_r13[bank_number(mode)];
5883     }
5884 }
5885
5886 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
5887 {
5888     ARMCPU *cpu = arm_env_get_cpu(env);
5889
5890     switch (reg) {
5891     case 0: /* APSR */
5892         return xpsr_read(env) & 0xf8000000;
5893     case 1: /* IAPSR */
5894         return xpsr_read(env) & 0xf80001ff;
5895     case 2: /* EAPSR */
5896         return xpsr_read(env) & 0xff00fc00;
5897     case 3: /* xPSR */
5898         return xpsr_read(env) & 0xff00fdff;
5899     case 5: /* IPSR */
5900         return xpsr_read(env) & 0x000001ff;
5901     case 6: /* EPSR */
5902         return xpsr_read(env) & 0x0700fc00;
5903     case 7: /* IEPSR */
5904         return xpsr_read(env) & 0x0700edff;
5905     case 8: /* MSP */
5906         return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
5907     case 9: /* PSP */
5908         return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
5909     case 16: /* PRIMASK */
5910         return (env->daif & PSTATE_I) != 0;
5911     case 17: /* BASEPRI */
5912     case 18: /* BASEPRI_MAX */
5913         return env->v7m.basepri;
5914     case 19: /* FAULTMASK */
5915         return (env->daif & PSTATE_F) != 0;
5916     case 20: /* CONTROL */
5917         return env->v7m.control;
5918     default:
5919         /* ??? For debugging only.  */
5920         cpu_abort(CPU(cpu), "Unimplemented system register read (%d)\n", reg);
5921         return 0;
5922     }
5923 }
5924
5925 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
5926 {
5927     ARMCPU *cpu = arm_env_get_cpu(env);
5928
5929     switch (reg) {
5930     case 0: /* APSR */
5931         xpsr_write(env, val, 0xf8000000);
5932         break;
5933     case 1: /* IAPSR */
5934         xpsr_write(env, val, 0xf8000000);
5935         break;
5936     case 2: /* EAPSR */
5937         xpsr_write(env, val, 0xfe00fc00);
5938         break;
5939     case 3: /* xPSR */
5940         xpsr_write(env, val, 0xfe00fc00);
5941         break;
5942     case 5: /* IPSR */
5943         /* IPSR bits are readonly.  */
5944         break;
5945     case 6: /* EPSR */
5946         xpsr_write(env, val, 0x0600fc00);
5947         break;
5948     case 7: /* IEPSR */
5949         xpsr_write(env, val, 0x0600fc00);
5950         break;
5951     case 8: /* MSP */
5952         if (env->v7m.current_sp)
5953             env->v7m.other_sp = val;
5954         else
5955             env->regs[13] = val;
5956         break;
5957     case 9: /* PSP */
5958         if (env->v7m.current_sp)
5959             env->regs[13] = val;
5960         else
5961             env->v7m.other_sp = val;
5962         break;
5963     case 16: /* PRIMASK */
5964         if (val & 1) {
5965             env->daif |= PSTATE_I;
5966         } else {
5967             env->daif &= ~PSTATE_I;
5968         }
5969         break;
5970     case 17: /* BASEPRI */
5971         env->v7m.basepri = val & 0xff;
5972         break;
5973     case 18: /* BASEPRI_MAX */
5974         val &= 0xff;
5975         if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
5976             env->v7m.basepri = val;
5977         break;
5978     case 19: /* FAULTMASK */
5979         if (val & 1) {
5980             env->daif |= PSTATE_F;
5981         } else {
5982             env->daif &= ~PSTATE_F;
5983         }
5984         break;
5985     case 20: /* CONTROL */
5986         env->v7m.control = val & 3;
5987         switch_v7m_sp(env, (val & 2) != 0);
5988         break;
5989     default:
5990         /* ??? For debugging only.  */
5991         cpu_abort(CPU(cpu), "Unimplemented system register write (%d)\n", reg);
5992         return;
5993     }
5994 }
5995
5996 #endif
5997
5998 void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
5999 {
6000     /* Implement DC ZVA, which zeroes a fixed-length block of memory.
6001      * Note that we do not implement the (architecturally mandated)
6002      * alignment fault for attempts to use this on Device memory
6003      * (which matches the usual QEMU behaviour of not implementing either
6004      * alignment faults or any memory attribute handling).
6005      */
6006
6007     ARMCPU *cpu = arm_env_get_cpu(env);
6008     uint64_t blocklen = 4 << cpu->dcz_blocksize;
6009     uint64_t vaddr = vaddr_in & ~(blocklen - 1);
6010
6011 #ifndef CONFIG_USER_ONLY
6012     {
6013         /* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than
6014          * the block size so we might have to do more than one TLB lookup.
6015          * We know that in fact for any v8 CPU the page size is at least 4K
6016          * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only
6017          * 1K as an artefact of legacy v5 subpage support being present in the
6018          * same QEMU executable.
6019          */
6020         int maxidx = DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE);
6021         void *hostaddr[maxidx];
6022         int try, i;
6023         unsigned mmu_idx = cpu_mmu_index(env);
6024         TCGMemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
6025
6026         for (try = 0; try < 2; try++) {
6027
6028             for (i = 0; i < maxidx; i++) {
6029                 hostaddr[i] = tlb_vaddr_to_host(env,
6030                                                 vaddr + TARGET_PAGE_SIZE * i,
6031                                                 1, mmu_idx);
6032                 if (!hostaddr[i]) {
6033                     break;
6034                 }
6035             }
6036             if (i == maxidx) {
6037                 /* If it's all in the TLB it's fair game for just writing to;
6038                  * we know we don't need to update dirty status, etc.
6039                  */
6040                 for (i = 0; i < maxidx - 1; i++) {
6041                     memset(hostaddr[i], 0, TARGET_PAGE_SIZE);
6042                 }
6043                 memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE));
6044                 return;
6045             }
6046             /* OK, try a store and see if we can populate the tlb. This
6047              * might cause an exception if the memory isn't writable,
6048              * in which case we will longjmp out of here. We must for
6049              * this purpose use the actual register value passed to us
6050              * so that we get the fault address right.
6051              */
6052             helper_ret_stb_mmu(env, vaddr_in, 0, oi, GETRA());
6053             /* Now we can populate the other TLB entries, if any */
6054             for (i = 0; i < maxidx; i++) {
6055                 uint64_t va = vaddr + TARGET_PAGE_SIZE * i;
6056                 if (va != (vaddr_in & TARGET_PAGE_MASK)) {
6057                     helper_ret_stb_mmu(env, va, 0, oi, GETRA());
6058                 }
6059             }
6060         }
6061
6062         /* Slow path (probably attempt to do this to an I/O device or
6063          * similar, or clearing of a block of code we have translations
6064          * cached for). Just do a series of byte writes as the architecture
6065          * demands. It's not worth trying to use a cpu_physical_memory_map(),
6066          * memset(), unmap() sequence here because:
6067          *  + we'd need to account for the blocksize being larger than a page
6068          *  + the direct-RAM access case is almost always going to be dealt
6069          *    with in the fastpath code above, so there's no speed benefit
6070          *  + we would have to deal with the map returning NULL because the
6071          *    bounce buffer was in use
6072          */
6073         for (i = 0; i < blocklen; i++) {
6074             helper_ret_stb_mmu(env, vaddr + i, 0, oi, GETRA());
6075         }
6076     }
6077 #else
6078     memset(g2h(vaddr), 0, blocklen);
6079 #endif
6080 }
6081
6082 /* Note that signed overflow is undefined in C.  The following routines are
6083    careful to use unsigned types where modulo arithmetic is required.
6084    Failure to do so _will_ break on newer gcc.  */
6085
6086 /* Signed saturating arithmetic.  */
6087
6088 /* Perform 16-bit signed saturating addition.  */
6089 static inline uint16_t add16_sat(uint16_t a, uint16_t b)
6090 {
6091     uint16_t res;
6092
6093     res = a + b;
6094     if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
6095         if (a & 0x8000)
6096             res = 0x8000;
6097         else
6098             res = 0x7fff;
6099     }
6100     return res;
6101 }
6102
6103 /* Perform 8-bit signed saturating addition.  */
6104 static inline uint8_t add8_sat(uint8_t a, uint8_t b)
6105 {
6106     uint8_t res;
6107
6108     res = a + b;
6109     if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
6110         if (a & 0x80)
6111             res = 0x80;
6112         else
6113             res = 0x7f;
6114     }
6115     return res;
6116 }
6117
6118 /* Perform 16-bit signed saturating subtraction.  */
6119 static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
6120 {
6121     uint16_t res;
6122
6123     res = a - b;
6124     if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
6125         if (a & 0x8000)
6126             res = 0x8000;
6127         else
6128             res = 0x7fff;
6129     }
6130     return res;
6131 }
6132
6133 /* Perform 8-bit signed saturating subtraction.  */
6134 static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
6135 {
6136     uint8_t res;
6137
6138     res = a - b;
6139     if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
6140         if (a & 0x80)
6141             res = 0x80;
6142         else
6143             res = 0x7f;
6144     }
6145     return res;
6146 }
6147
6148 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
6149 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
6150 #define ADD8(a, b, n)  RESULT(add8_sat(a, b), n, 8);
6151 #define SUB8(a, b, n)  RESULT(sub8_sat(a, b), n, 8);
6152 #define PFX q
6153
6154 #include "op_addsub.h"
6155
6156 /* Unsigned saturating arithmetic.  */
6157 static inline uint16_t add16_usat(uint16_t a, uint16_t b)
6158 {
6159     uint16_t res;
6160     res = a + b;
6161     if (res < a)
6162         res = 0xffff;
6163     return res;
6164 }
6165
6166 static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
6167 {
6168     if (a > b)
6169         return a - b;
6170     else
6171         return 0;
6172 }
6173
6174 static inline uint8_t add8_usat(uint8_t a, uint8_t b)
6175 {
6176     uint8_t res;
6177     res = a + b;
6178     if (res < a)
6179         res = 0xff;
6180     return res;
6181 }
6182
6183 static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
6184 {
6185     if (a > b)
6186         return a - b;
6187     else
6188         return 0;
6189 }
6190
6191 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
6192 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
6193 #define ADD8(a, b, n)  RESULT(add8_usat(a, b), n, 8);
6194 #define SUB8(a, b, n)  RESULT(sub8_usat(a, b), n, 8);
6195 #define PFX uq
6196
6197 #include "op_addsub.h"
6198
6199 /* Signed modulo arithmetic.  */
6200 #define SARITH16(a, b, n, op) do { \
6201     int32_t sum; \
6202     sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
6203     RESULT(sum, n, 16); \
6204     if (sum >= 0) \
6205         ge |= 3 << (n * 2); \
6206     } while(0)
6207
6208 #define SARITH8(a, b, n, op) do { \
6209     int32_t sum; \
6210     sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
6211     RESULT(sum, n, 8); \
6212     if (sum >= 0) \
6213         ge |= 1 << n; \
6214     } while(0)
6215
6216
6217 #define ADD16(a, b, n) SARITH16(a, b, n, +)
6218 #define SUB16(a, b, n) SARITH16(a, b, n, -)
6219 #define ADD8(a, b, n)  SARITH8(a, b, n, +)
6220 #define SUB8(a, b, n)  SARITH8(a, b, n, -)
6221 #define PFX s
6222 #define ARITH_GE
6223
6224 #include "op_addsub.h"
6225
6226 /* Unsigned modulo arithmetic.  */
6227 #define ADD16(a, b, n) do { \
6228     uint32_t sum; \
6229     sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
6230     RESULT(sum, n, 16); \
6231     if ((sum >> 16) == 1) \
6232         ge |= 3 << (n * 2); \
6233     } while(0)
6234
6235 #define ADD8(a, b, n) do { \
6236     uint32_t sum; \
6237     sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
6238     RESULT(sum, n, 8); \
6239     if ((sum >> 8) == 1) \
6240         ge |= 1 << n; \
6241     } while(0)
6242
6243 #define SUB16(a, b, n) do { \
6244     uint32_t sum; \
6245     sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
6246     RESULT(sum, n, 16); \
6247     if ((sum >> 16) == 0) \
6248         ge |= 3 << (n * 2); \
6249     } while(0)
6250
6251 #define SUB8(a, b, n) do { \
6252     uint32_t sum; \
6253     sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
6254     RESULT(sum, n, 8); \
6255     if ((sum >> 8) == 0) \
6256         ge |= 1 << n; \
6257     } while(0)
6258
6259 #define PFX u
6260 #define ARITH_GE
6261
6262 #include "op_addsub.h"
6263
6264 /* Halved signed arithmetic.  */
6265 #define ADD16(a, b, n) \
6266   RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
6267 #define SUB16(a, b, n) \
6268   RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
6269 #define ADD8(a, b, n) \
6270   RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
6271 #define SUB8(a, b, n) \
6272   RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
6273 #define PFX sh
6274
6275 #include "op_addsub.h"
6276
6277 /* Halved unsigned arithmetic.  */
6278 #define ADD16(a, b, n) \
6279   RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
6280 #define SUB16(a, b, n) \
6281   RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
6282 #define ADD8(a, b, n) \
6283   RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
6284 #define SUB8(a, b, n) \
6285   RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
6286 #define PFX uh
6287
6288 #include "op_addsub.h"
6289
6290 static inline uint8_t do_usad(uint8_t a, uint8_t b)
6291 {
6292     if (a > b)
6293         return a - b;
6294     else
6295         return b - a;
6296 }
6297
6298 /* Unsigned sum of absolute byte differences.  */
6299 uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
6300 {
6301     uint32_t sum;
6302     sum = do_usad(a, b);
6303     sum += do_usad(a >> 8, b >> 8);
6304     sum += do_usad(a >> 16, b >>16);
6305     sum += do_usad(a >> 24, b >> 24);
6306     return sum;
6307 }
6308
6309 /* For ARMv6 SEL instruction.  */
6310 uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
6311 {
6312     uint32_t mask;
6313
6314     mask = 0;
6315     if (flags & 1)
6316         mask |= 0xff;
6317     if (flags & 2)
6318         mask |= 0xff00;
6319     if (flags & 4)
6320         mask |= 0xff0000;
6321     if (flags & 8)
6322         mask |= 0xff000000;
6323     return (a & mask) | (b & ~mask);
6324 }
6325
6326 /* VFP support.  We follow the convention used for VFP instructions:
6327    Single precision routines have a "s" suffix, double precision a
6328    "d" suffix.  */
6329
6330 /* Convert host exception flags to vfp form.  */
6331 static inline int vfp_exceptbits_from_host(int host_bits)
6332 {
6333     int target_bits = 0;
6334
6335     if (host_bits & float_flag_invalid)
6336         target_bits |= 1;
6337     if (host_bits & float_flag_divbyzero)
6338         target_bits |= 2;
6339     if (host_bits & float_flag_overflow)
6340         target_bits |= 4;
6341     if (host_bits & (float_flag_underflow | float_flag_output_denormal))
6342         target_bits |= 8;
6343     if (host_bits & float_flag_inexact)
6344         target_bits |= 0x10;
6345     if (host_bits & float_flag_input_denormal)
6346         target_bits |= 0x80;
6347     return target_bits;
6348 }
6349
6350 uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
6351 {
6352     int i;
6353     uint32_t fpscr;
6354
6355     fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
6356             | (env->vfp.vec_len << 16)
6357             | (env->vfp.vec_stride << 20);
6358     i = get_float_exception_flags(&env->vfp.fp_status);
6359     i |= get_float_exception_flags(&env->vfp.standard_fp_status);
6360     fpscr |= vfp_exceptbits_from_host(i);
6361     return fpscr;
6362 }
6363
6364 uint32_t vfp_get_fpscr(CPUARMState *env)
6365 {
6366     return HELPER(vfp_get_fpscr)(env);
6367 }
6368
6369 /* Convert vfp exception flags to target form.  */
6370 static inline int vfp_exceptbits_to_host(int target_bits)
6371 {
6372     int host_bits = 0;
6373
6374     if (target_bits & 1)
6375         host_bits |= float_flag_invalid;
6376     if (target_bits & 2)
6377         host_bits |= float_flag_divbyzero;
6378     if (target_bits & 4)
6379         host_bits |= float_flag_overflow;
6380     if (target_bits & 8)
6381         host_bits |= float_flag_underflow;
6382     if (target_bits & 0x10)
6383         host_bits |= float_flag_inexact;
6384     if (target_bits & 0x80)
6385         host_bits |= float_flag_input_denormal;
6386     return host_bits;
6387 }
6388
6389 void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
6390 {
6391     int i;
6392     uint32_t changed;
6393
6394     changed = env->vfp.xregs[ARM_VFP_FPSCR];
6395     env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
6396     env->vfp.vec_len = (val >> 16) & 7;
6397     env->vfp.vec_stride = (val >> 20) & 3;
6398
6399     changed ^= val;
6400     if (changed & (3 << 22)) {
6401         i = (val >> 22) & 3;
6402         switch (i) {
6403         case FPROUNDING_TIEEVEN:
6404             i = float_round_nearest_even;
6405             break;
6406         case FPROUNDING_POSINF:
6407             i = float_round_up;
6408             break;
6409         case FPROUNDING_NEGINF:
6410             i = float_round_down;
6411             break;
6412         case FPROUNDING_ZERO:
6413             i = float_round_to_zero;
6414             break;
6415         }
6416         set_float_rounding_mode(i, &env->vfp.fp_status);
6417     }
6418     if (changed & (1 << 24)) {
6419         set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
6420         set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
6421     }
6422     if (changed & (1 << 25))
6423         set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
6424
6425     i = vfp_exceptbits_to_host(val);
6426     set_float_exception_flags(i, &env->vfp.fp_status);
6427     set_float_exception_flags(0, &env->vfp.standard_fp_status);
6428 }
6429
6430 void vfp_set_fpscr(CPUARMState *env, uint32_t val)
6431 {
6432     HELPER(vfp_set_fpscr)(env, val);
6433 }
6434
6435 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
6436
6437 #define VFP_BINOP(name) \
6438 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
6439 { \
6440     float_status *fpst = fpstp; \
6441     return float32_ ## name(a, b, fpst); \
6442 } \
6443 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
6444 { \
6445     float_status *fpst = fpstp; \
6446     return float64_ ## name(a, b, fpst); \
6447 }
6448 VFP_BINOP(add)
6449 VFP_BINOP(sub)
6450 VFP_BINOP(mul)
6451 VFP_BINOP(div)
6452 VFP_BINOP(min)
6453 VFP_BINOP(max)
6454 VFP_BINOP(minnum)
6455 VFP_BINOP(maxnum)
6456 #undef VFP_BINOP
6457
6458 float32 VFP_HELPER(neg, s)(float32 a)
6459 {
6460     return float32_chs(a);
6461 }
6462
6463 float64 VFP_HELPER(neg, d)(float64 a)
6464 {
6465     return float64_chs(a);
6466 }
6467
6468 float32 VFP_HELPER(abs, s)(float32 a)
6469 {
6470     return float32_abs(a);
6471 }
6472
6473 float64 VFP_HELPER(abs, d)(float64 a)
6474 {
6475     return float64_abs(a);
6476 }
6477
6478 float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
6479 {
6480     return float32_sqrt(a, &env->vfp.fp_status);
6481 }
6482
6483 float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
6484 {
6485     return float64_sqrt(a, &env->vfp.fp_status);
6486 }
6487
6488 /* XXX: check quiet/signaling case */
6489 #define DO_VFP_cmp(p, type) \
6490 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env)  \
6491 { \
6492     uint32_t flags; \
6493     switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
6494     case 0: flags = 0x6; break; \
6495     case -1: flags = 0x8; break; \
6496     case 1: flags = 0x2; break; \
6497     default: case 2: flags = 0x3; break; \
6498     } \
6499     env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
6500         | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
6501 } \
6502 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
6503 { \
6504     uint32_t flags; \
6505     switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
6506     case 0: flags = 0x6; break; \
6507     case -1: flags = 0x8; break; \
6508     case 1: flags = 0x2; break; \
6509     default: case 2: flags = 0x3; break; \
6510     } \
6511     env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
6512         | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
6513 }
6514 DO_VFP_cmp(s, float32)
6515 DO_VFP_cmp(d, float64)
6516 #undef DO_VFP_cmp
6517
6518 /* Integer to float and float to integer conversions */
6519
6520 #define CONV_ITOF(name, fsz, sign) \
6521     float##fsz HELPER(name)(uint32_t x, void *fpstp) \
6522 { \
6523     float_status *fpst = fpstp; \
6524     return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
6525 }
6526
6527 #define CONV_FTOI(name, fsz, sign, round) \
6528 uint32_t HELPER(name)(float##fsz x, void *fpstp) \
6529 { \
6530     float_status *fpst = fpstp; \
6531     if (float##fsz##_is_any_nan(x)) { \
6532         float_raise(float_flag_invalid, fpst); \
6533         return 0; \
6534     } \
6535     return float##fsz##_to_##sign##int32##round(x, fpst); \
6536 }
6537
6538 #define FLOAT_CONVS(name, p, fsz, sign) \
6539 CONV_ITOF(vfp_##name##to##p, fsz, sign) \
6540 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
6541 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
6542
6543 FLOAT_CONVS(si, s, 32, )
6544 FLOAT_CONVS(si, d, 64, )
6545 FLOAT_CONVS(ui, s, 32, u)
6546 FLOAT_CONVS(ui, d, 64, u)
6547
6548 #undef CONV_ITOF
6549 #undef CONV_FTOI
6550 #undef FLOAT_CONVS
6551
6552 /* floating point conversion */
6553 float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
6554 {
6555     float64 r = float32_to_float64(x, &env->vfp.fp_status);
6556     /* ARM requires that S<->D conversion of any kind of NaN generates
6557      * a quiet NaN by forcing the most significant frac bit to 1.
6558      */
6559     return float64_maybe_silence_nan(r);
6560 }
6561
6562 float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
6563 {
6564     float32 r =  float64_to_float32(x, &env->vfp.fp_status);
6565     /* ARM requires that S<->D conversion of any kind of NaN generates
6566      * a quiet NaN by forcing the most significant frac bit to 1.
6567      */
6568     return float32_maybe_silence_nan(r);
6569 }
6570
6571 /* VFP3 fixed point conversion.  */
6572 #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
6573 float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t  x, uint32_t shift, \
6574                                      void *fpstp) \
6575 { \
6576     float_status *fpst = fpstp; \
6577     float##fsz tmp; \
6578     tmp = itype##_to_##float##fsz(x, fpst); \
6579     return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
6580 }
6581
6582 /* Notice that we want only input-denormal exception flags from the
6583  * scalbn operation: the other possible flags (overflow+inexact if
6584  * we overflow to infinity, output-denormal) aren't correct for the
6585  * complete scale-and-convert operation.
6586  */
6587 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \
6588 uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \
6589                                              uint32_t shift, \
6590                                              void *fpstp) \
6591 { \
6592     float_status *fpst = fpstp; \
6593     int old_exc_flags = get_float_exception_flags(fpst); \
6594     float##fsz tmp; \
6595     if (float##fsz##_is_any_nan(x)) { \
6596         float_raise(float_flag_invalid, fpst); \
6597         return 0; \
6598     } \
6599     tmp = float##fsz##_scalbn(x, shift, fpst); \
6600     old_exc_flags |= get_float_exception_flags(fpst) \
6601         & float_flag_input_denormal; \
6602     set_float_exception_flags(old_exc_flags, fpst); \
6603     return float##fsz##_to_##itype##round(tmp, fpst); \
6604 }
6605
6606 #define VFP_CONV_FIX(name, p, fsz, isz, itype)                   \
6607 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype)                     \
6608 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero) \
6609 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
6610
6611 #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype)               \
6612 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype)                     \
6613 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
6614
6615 VFP_CONV_FIX(sh, d, 64, 64, int16)
6616 VFP_CONV_FIX(sl, d, 64, 64, int32)
6617 VFP_CONV_FIX_A64(sq, d, 64, 64, int64)
6618 VFP_CONV_FIX(uh, d, 64, 64, uint16)
6619 VFP_CONV_FIX(ul, d, 64, 64, uint32)
6620 VFP_CONV_FIX_A64(uq, d, 64, 64, uint64)
6621 VFP_CONV_FIX(sh, s, 32, 32, int16)
6622 VFP_CONV_FIX(sl, s, 32, 32, int32)
6623 VFP_CONV_FIX_A64(sq, s, 32, 64, int64)
6624 VFP_CONV_FIX(uh, s, 32, 32, uint16)
6625 VFP_CONV_FIX(ul, s, 32, 32, uint32)
6626 VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
6627 #undef VFP_CONV_FIX
6628 #undef VFP_CONV_FIX_FLOAT
6629 #undef VFP_CONV_FLOAT_FIX_ROUND
6630
6631 /* Set the current fp rounding mode and return the old one.
6632  * The argument is a softfloat float_round_ value.
6633  */
6634 uint32_t HELPER(set_rmode)(uint32_t rmode, CPUARMState *env)
6635 {
6636     float_status *fp_status = &env->vfp.fp_status;
6637
6638     uint32_t prev_rmode = get_float_rounding_mode(fp_status);
6639     set_float_rounding_mode(rmode, fp_status);
6640
6641     return prev_rmode;
6642 }
6643
6644 /* Set the current fp rounding mode in the standard fp status and return
6645  * the old one. This is for NEON instructions that need to change the
6646  * rounding mode but wish to use the standard FPSCR values for everything
6647  * else. Always set the rounding mode back to the correct value after
6648  * modifying it.
6649  * The argument is a softfloat float_round_ value.
6650  */
6651 uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env)
6652 {
6653     float_status *fp_status = &env->vfp.standard_fp_status;
6654
6655     uint32_t prev_rmode = get_float_rounding_mode(fp_status);
6656     set_float_rounding_mode(rmode, fp_status);
6657
6658     return prev_rmode;
6659 }
6660
6661 /* Half precision conversions.  */
6662 static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s)
6663 {
6664     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
6665     float32 r = float16_to_float32(make_float16(a), ieee, s);
6666     if (ieee) {
6667         return float32_maybe_silence_nan(r);
6668     }
6669     return r;
6670 }
6671
6672 static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s)
6673 {
6674     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
6675     float16 r = float32_to_float16(a, ieee, s);
6676     if (ieee) {
6677         r = float16_maybe_silence_nan(r);
6678     }
6679     return float16_val(r);
6680 }
6681
6682 float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
6683 {
6684     return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
6685 }
6686
6687 uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
6688 {
6689     return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
6690 }
6691
6692 float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
6693 {
6694     return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
6695 }
6696
6697 uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
6698 {
6699     return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
6700 }
6701
6702 float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, CPUARMState *env)
6703 {
6704     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
6705     float64 r = float16_to_float64(make_float16(a), ieee, &env->vfp.fp_status);
6706     if (ieee) {
6707         return float64_maybe_silence_nan(r);
6708     }
6709     return r;
6710 }
6711
6712 uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, CPUARMState *env)
6713 {
6714     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
6715     float16 r = float64_to_float16(a, ieee, &env->vfp.fp_status);
6716     if (ieee) {
6717         r = float16_maybe_silence_nan(r);
6718     }
6719     return float16_val(r);
6720 }
6721
6722 #define float32_two make_float32(0x40000000)
6723 #define float32_three make_float32(0x40400000)
6724 #define float32_one_point_five make_float32(0x3fc00000)
6725
6726 float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env)
6727 {
6728     float_status *s = &env->vfp.standard_fp_status;
6729     if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
6730         (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
6731         if (!(float32_is_zero(a) || float32_is_zero(b))) {
6732             float_raise(float_flag_input_denormal, s);
6733         }
6734         return float32_two;
6735     }
6736     return float32_sub(float32_two, float32_mul(a, b, s), s);
6737 }
6738
6739 float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
6740 {
6741     float_status *s = &env->vfp.standard_fp_status;
6742     float32 product;
6743     if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
6744         (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
6745         if (!(float32_is_zero(a) || float32_is_zero(b))) {
6746             float_raise(float_flag_input_denormal, s);
6747         }
6748         return float32_one_point_five;
6749     }
6750     product = float32_mul(a, b, s);
6751     return float32_div(float32_sub(float32_three, product, s), float32_two, s);
6752 }
6753
6754 /* NEON helpers.  */
6755
6756 /* Constants 256 and 512 are used in some helpers; we avoid relying on
6757  * int->float conversions at run-time.  */
6758 #define float64_256 make_float64(0x4070000000000000LL)
6759 #define float64_512 make_float64(0x4080000000000000LL)
6760 #define float32_maxnorm make_float32(0x7f7fffff)
6761 #define float64_maxnorm make_float64(0x7fefffffffffffffLL)
6762
6763 /* Reciprocal functions
6764  *
6765  * The algorithm that must be used to calculate the estimate
6766  * is specified by the ARM ARM, see FPRecipEstimate()
6767  */
6768
6769 static float64 recip_estimate(float64 a, float_status *real_fp_status)
6770 {
6771     /* These calculations mustn't set any fp exception flags,
6772      * so we use a local copy of the fp_status.
6773      */
6774     float_status dummy_status = *real_fp_status;
6775     float_status *s = &dummy_status;
6776     /* q = (int)(a * 512.0) */
6777     float64 q = float64_mul(float64_512, a, s);
6778     int64_t q_int = float64_to_int64_round_to_zero(q, s);
6779
6780     /* r = 1.0 / (((double)q + 0.5) / 512.0) */
6781     q = int64_to_float64(q_int, s);
6782     q = float64_add(q, float64_half, s);
6783     q = float64_div(q, float64_512, s);
6784     q = float64_div(float64_one, q, s);
6785
6786     /* s = (int)(256.0 * r + 0.5) */
6787     q = float64_mul(q, float64_256, s);
6788     q = float64_add(q, float64_half, s);
6789     q_int = float64_to_int64_round_to_zero(q, s);
6790
6791     /* return (double)s / 256.0 */
6792     return float64_div(int64_to_float64(q_int, s), float64_256, s);
6793 }
6794
6795 /* Common wrapper to call recip_estimate */
6796 static float64 call_recip_estimate(float64 num, int off, float_status *fpst)
6797 {
6798     uint64_t val64 = float64_val(num);
6799     uint64_t frac = extract64(val64, 0, 52);
6800     int64_t exp = extract64(val64, 52, 11);
6801     uint64_t sbit;
6802     float64 scaled, estimate;
6803
6804     /* Generate the scaled number for the estimate function */
6805     if (exp == 0) {
6806         if (extract64(frac, 51, 1) == 0) {
6807             exp = -1;
6808             frac = extract64(frac, 0, 50) << 2;
6809         } else {
6810             frac = extract64(frac, 0, 51) << 1;
6811         }
6812     }
6813
6814     /* scaled = '0' : '01111111110' : fraction<51:44> : Zeros(44); */
6815     scaled = make_float64((0x3feULL << 52)
6816                           | extract64(frac, 44, 8) << 44);
6817
6818     estimate = recip_estimate(scaled, fpst);
6819
6820     /* Build new result */
6821     val64 = float64_val(estimate);
6822     sbit = 0x8000000000000000ULL & val64;
6823     exp = off - exp;
6824     frac = extract64(val64, 0, 52);
6825
6826     if (exp == 0) {
6827         frac = 1ULL << 51 | extract64(frac, 1, 51);
6828     } else if (exp == -1) {
6829         frac = 1ULL << 50 | extract64(frac, 2, 50);
6830         exp = 0;
6831     }
6832
6833     return make_float64(sbit | (exp << 52) | frac);
6834 }
6835
6836 static bool round_to_inf(float_status *fpst, bool sign_bit)
6837 {
6838     switch (fpst->float_rounding_mode) {
6839     case float_round_nearest_even: /* Round to Nearest */
6840         return true;
6841     case float_round_up: /* Round to +Inf */
6842         return !sign_bit;
6843     case float_round_down: /* Round to -Inf */
6844         return sign_bit;
6845     case float_round_to_zero: /* Round to Zero */
6846         return false;
6847     }
6848
6849     g_assert_not_reached();
6850 }
6851
6852 float32 HELPER(recpe_f32)(float32 input, void *fpstp)
6853 {
6854     float_status *fpst = fpstp;
6855     float32 f32 = float32_squash_input_denormal(input, fpst);
6856     uint32_t f32_val = float32_val(f32);
6857     uint32_t f32_sbit = 0x80000000ULL & f32_val;
6858     int32_t f32_exp = extract32(f32_val, 23, 8);
6859     uint32_t f32_frac = extract32(f32_val, 0, 23);
6860     float64 f64, r64;
6861     uint64_t r64_val;
6862     int64_t r64_exp;
6863     uint64_t r64_frac;
6864
6865     if (float32_is_any_nan(f32)) {
6866         float32 nan = f32;
6867         if (float32_is_signaling_nan(f32)) {
6868             float_raise(float_flag_invalid, fpst);
6869             nan = float32_maybe_silence_nan(f32);
6870         }
6871         if (fpst->default_nan_mode) {
6872             nan =  float32_default_nan;
6873         }
6874         return nan;
6875     } else if (float32_is_infinity(f32)) {
6876         return float32_set_sign(float32_zero, float32_is_neg(f32));
6877     } else if (float32_is_zero(f32)) {
6878         float_raise(float_flag_divbyzero, fpst);
6879         return float32_set_sign(float32_infinity, float32_is_neg(f32));
6880     } else if ((f32_val & ~(1ULL << 31)) < (1ULL << 21)) {
6881         /* Abs(value) < 2.0^-128 */
6882         float_raise(float_flag_overflow | float_flag_inexact, fpst);
6883         if (round_to_inf(fpst, f32_sbit)) {
6884             return float32_set_sign(float32_infinity, float32_is_neg(f32));
6885         } else {
6886             return float32_set_sign(float32_maxnorm, float32_is_neg(f32));
6887         }
6888     } else if (f32_exp >= 253 && fpst->flush_to_zero) {
6889         float_raise(float_flag_underflow, fpst);
6890         return float32_set_sign(float32_zero, float32_is_neg(f32));
6891     }
6892
6893
6894     f64 = make_float64(((int64_t)(f32_exp) << 52) | (int64_t)(f32_frac) << 29);
6895     r64 = call_recip_estimate(f64, 253, fpst);
6896     r64_val = float64_val(r64);
6897     r64_exp = extract64(r64_val, 52, 11);
6898     r64_frac = extract64(r64_val, 0, 52);
6899
6900     /* result = sign : result_exp<7:0> : fraction<51:29>; */
6901     return make_float32(f32_sbit |
6902                         (r64_exp & 0xff) << 23 |
6903                         extract64(r64_frac, 29, 24));
6904 }
6905
6906 float64 HELPER(recpe_f64)(float64 input, void *fpstp)
6907 {
6908     float_status *fpst = fpstp;
6909     float64 f64 = float64_squash_input_denormal(input, fpst);
6910     uint64_t f64_val = float64_val(f64);
6911     uint64_t f64_sbit = 0x8000000000000000ULL & f64_val;
6912     int64_t f64_exp = extract64(f64_val, 52, 11);
6913     float64 r64;
6914     uint64_t r64_val;
6915     int64_t r64_exp;
6916     uint64_t r64_frac;
6917
6918     /* Deal with any special cases */
6919     if (float64_is_any_nan(f64)) {
6920         float64 nan = f64;
6921         if (float64_is_signaling_nan(f64)) {
6922             float_raise(float_flag_invalid, fpst);
6923             nan = float64_maybe_silence_nan(f64);
6924         }
6925         if (fpst->default_nan_mode) {
6926             nan =  float64_default_nan;
6927         }
6928         return nan;
6929     } else if (float64_is_infinity(f64)) {
6930         return float64_set_sign(float64_zero, float64_is_neg(f64));
6931     } else if (float64_is_zero(f64)) {
6932         float_raise(float_flag_divbyzero, fpst);
6933         return float64_set_sign(float64_infinity, float64_is_neg(f64));
6934     } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) {
6935         /* Abs(value) < 2.0^-1024 */
6936         float_raise(float_flag_overflow | float_flag_inexact, fpst);
6937         if (round_to_inf(fpst, f64_sbit)) {
6938             return float64_set_sign(float64_infinity, float64_is_neg(f64));
6939         } else {
6940             return float64_set_sign(float64_maxnorm, float64_is_neg(f64));
6941         }
6942     } else if (f64_exp >= 2045 && fpst->flush_to_zero) {
6943         float_raise(float_flag_underflow, fpst);
6944         return float64_set_sign(float64_zero, float64_is_neg(f64));
6945     }
6946
6947     r64 = call_recip_estimate(f64, 2045, fpst);
6948     r64_val = float64_val(r64);
6949     r64_exp = extract64(r64_val, 52, 11);
6950     r64_frac = extract64(r64_val, 0, 52);
6951
6952     /* result = sign : result_exp<10:0> : fraction<51:0> */
6953     return make_float64(f64_sbit |
6954                         ((r64_exp & 0x7ff) << 52) |
6955                         r64_frac);
6956 }
6957
6958 /* The algorithm that must be used to calculate the estimate
6959  * is specified by the ARM ARM.
6960  */
6961 static float64 recip_sqrt_estimate(float64 a, float_status *real_fp_status)
6962 {
6963     /* These calculations mustn't set any fp exception flags,
6964      * so we use a local copy of the fp_status.
6965      */
6966     float_status dummy_status = *real_fp_status;
6967     float_status *s = &dummy_status;
6968     float64 q;
6969     int64_t q_int;
6970
6971     if (float64_lt(a, float64_half, s)) {
6972         /* range 0.25 <= a < 0.5 */
6973
6974         /* a in units of 1/512 rounded down */
6975         /* q0 = (int)(a * 512.0);  */
6976         q = float64_mul(float64_512, a, s);
6977         q_int = float64_to_int64_round_to_zero(q, s);
6978
6979         /* reciprocal root r */
6980         /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0);  */
6981         q = int64_to_float64(q_int, s);
6982         q = float64_add(q, float64_half, s);
6983         q = float64_div(q, float64_512, s);
6984         q = float64_sqrt(q, s);
6985         q = float64_div(float64_one, q, s);
6986     } else {
6987         /* range 0.5 <= a < 1.0 */
6988
6989         /* a in units of 1/256 rounded down */
6990         /* q1 = (int)(a * 256.0); */
6991         q = float64_mul(float64_256, a, s);
6992         int64_t q_int = float64_to_int64_round_to_zero(q, s);
6993
6994         /* reciprocal root r */
6995         /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
6996         q = int64_to_float64(q_int, s);
6997         q = float64_add(q, float64_half, s);
6998         q = float64_div(q, float64_256, s);
6999         q = float64_sqrt(q, s);
7000         q = float64_div(float64_one, q, s);
7001     }
7002     /* r in units of 1/256 rounded to nearest */
7003     /* s = (int)(256.0 * r + 0.5); */
7004
7005     q = float64_mul(q, float64_256,s );
7006     q = float64_add(q, float64_half, s);
7007     q_int = float64_to_int64_round_to_zero(q, s);
7008
7009     /* return (double)s / 256.0;*/
7010     return float64_div(int64_to_float64(q_int, s), float64_256, s);
7011 }
7012
7013 float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
7014 {
7015     float_status *s = fpstp;
7016     float32 f32 = float32_squash_input_denormal(input, s);
7017     uint32_t val = float32_val(f32);
7018     uint32_t f32_sbit = 0x80000000 & val;
7019     int32_t f32_exp = extract32(val, 23, 8);
7020     uint32_t f32_frac = extract32(val, 0, 23);
7021     uint64_t f64_frac;
7022     uint64_t val64;
7023     int result_exp;
7024     float64 f64;
7025
7026     if (float32_is_any_nan(f32)) {
7027         float32 nan = f32;
7028         if (float32_is_signaling_nan(f32)) {
7029             float_raise(float_flag_invalid, s);
7030             nan = float32_maybe_silence_nan(f32);
7031         }
7032         if (s->default_nan_mode) {
7033             nan =  float32_default_nan;
7034         }
7035         return nan;
7036     } else if (float32_is_zero(f32)) {
7037         float_raise(float_flag_divbyzero, s);
7038         return float32_set_sign(float32_infinity, float32_is_neg(f32));
7039     } else if (float32_is_neg(f32)) {
7040         float_raise(float_flag_invalid, s);
7041         return float32_default_nan;
7042     } else if (float32_is_infinity(f32)) {
7043         return float32_zero;
7044     }
7045
7046     /* Scale and normalize to a double-precision value between 0.25 and 1.0,
7047      * preserving the parity of the exponent.  */
7048
7049     f64_frac = ((uint64_t) f32_frac) << 29;
7050     if (f32_exp == 0) {
7051         while (extract64(f64_frac, 51, 1) == 0) {
7052             f64_frac = f64_frac << 1;
7053             f32_exp = f32_exp-1;
7054         }
7055         f64_frac = extract64(f64_frac, 0, 51) << 1;
7056     }
7057
7058     if (extract64(f32_exp, 0, 1) == 0) {
7059         f64 = make_float64(((uint64_t) f32_sbit) << 32
7060                            | (0x3feULL << 52)
7061                            | f64_frac);
7062     } else {
7063         f64 = make_float64(((uint64_t) f32_sbit) << 32
7064                            | (0x3fdULL << 52)
7065                            | f64_frac);
7066     }
7067
7068     result_exp = (380 - f32_exp) / 2;
7069
7070     f64 = recip_sqrt_estimate(f64, s);
7071
7072     val64 = float64_val(f64);
7073
7074     val = ((result_exp & 0xff) << 23)
7075         | ((val64 >> 29)  & 0x7fffff);
7076     return make_float32(val);
7077 }
7078
7079 float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
7080 {
7081     float_status *s = fpstp;
7082     float64 f64 = float64_squash_input_denormal(input, s);
7083     uint64_t val = float64_val(f64);
7084     uint64_t f64_sbit = 0x8000000000000000ULL & val;
7085     int64_t f64_exp = extract64(val, 52, 11);
7086     uint64_t f64_frac = extract64(val, 0, 52);
7087     int64_t result_exp;
7088     uint64_t result_frac;
7089
7090     if (float64_is_any_nan(f64)) {
7091         float64 nan = f64;
7092         if (float64_is_signaling_nan(f64)) {
7093             float_raise(float_flag_invalid, s);
7094             nan = float64_maybe_silence_nan(f64);
7095         }
7096         if (s->default_nan_mode) {
7097             nan =  float64_default_nan;
7098         }
7099         return nan;
7100     } else if (float64_is_zero(f64)) {
7101         float_raise(float_flag_divbyzero, s);
7102         return float64_set_sign(float64_infinity, float64_is_neg(f64));
7103     } else if (float64_is_neg(f64)) {
7104         float_raise(float_flag_invalid, s);
7105         return float64_default_nan;
7106     } else if (float64_is_infinity(f64)) {
7107         return float64_zero;
7108     }
7109
7110     /* Scale and normalize to a double-precision value between 0.25 and 1.0,
7111      * preserving the parity of the exponent.  */
7112
7113     if (f64_exp == 0) {
7114         while (extract64(f64_frac, 51, 1) == 0) {
7115             f64_frac = f64_frac << 1;
7116             f64_exp = f64_exp - 1;
7117         }
7118         f64_frac = extract64(f64_frac, 0, 51) << 1;
7119     }
7120
7121     if (extract64(f64_exp, 0, 1) == 0) {
7122         f64 = make_float64(f64_sbit
7123                            | (0x3feULL << 52)
7124                            | f64_frac);
7125     } else {
7126         f64 = make_float64(f64_sbit
7127                            | (0x3fdULL << 52)
7128                            | f64_frac);
7129     }
7130
7131     result_exp = (3068 - f64_exp) / 2;
7132
7133     f64 = recip_sqrt_estimate(f64, s);
7134
7135     result_frac = extract64(float64_val(f64), 0, 52);
7136
7137     return make_float64(f64_sbit |
7138                         ((result_exp & 0x7ff) << 52) |
7139                         result_frac);
7140 }
7141
7142 uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp)
7143 {
7144     float_status *s = fpstp;
7145     float64 f64;
7146
7147     if ((a & 0x80000000) == 0) {
7148         return 0xffffffff;
7149     }
7150
7151     f64 = make_float64((0x3feULL << 52)
7152                        | ((int64_t)(a & 0x7fffffff) << 21));
7153
7154     f64 = recip_estimate(f64, s);
7155
7156     return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
7157 }
7158
7159 uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp)
7160 {
7161     float_status *fpst = fpstp;
7162     float64 f64;
7163
7164     if ((a & 0xc0000000) == 0) {
7165         return 0xffffffff;
7166     }
7167
7168     if (a & 0x80000000) {
7169         f64 = make_float64((0x3feULL << 52)
7170                            | ((uint64_t)(a & 0x7fffffff) << 21));
7171     } else { /* bits 31-30 == '01' */
7172         f64 = make_float64((0x3fdULL << 52)
7173                            | ((uint64_t)(a & 0x3fffffff) << 22));
7174     }
7175
7176     f64 = recip_sqrt_estimate(f64, fpst);
7177
7178     return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
7179 }
7180
7181 /* VFPv4 fused multiply-accumulate */
7182 float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
7183 {
7184     float_status *fpst = fpstp;
7185     return float32_muladd(a, b, c, 0, fpst);
7186 }
7187
7188 float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
7189 {
7190     float_status *fpst = fpstp;
7191     return float64_muladd(a, b, c, 0, fpst);
7192 }
7193
7194 /* ARMv8 round to integral */
7195 float32 HELPER(rints_exact)(float32 x, void *fp_status)
7196 {
7197     return float32_round_to_int(x, fp_status);
7198 }
7199
7200 float64 HELPER(rintd_exact)(float64 x, void *fp_status)
7201 {
7202     return float64_round_to_int(x, fp_status);
7203 }
7204
7205 float32 HELPER(rints)(float32 x, void *fp_status)
7206 {
7207     int old_flags = get_float_exception_flags(fp_status), new_flags;
7208     float32 ret;
7209
7210     ret = float32_round_to_int(x, fp_status);
7211
7212     /* Suppress any inexact exceptions the conversion produced */
7213     if (!(old_flags & float_flag_inexact)) {
7214         new_flags = get_float_exception_flags(fp_status);
7215         set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
7216     }
7217
7218     return ret;
7219 }
7220
7221 float64 HELPER(rintd)(float64 x, void *fp_status)
7222 {
7223     int old_flags = get_float_exception_flags(fp_status), new_flags;
7224     float64 ret;
7225
7226     ret = float64_round_to_int(x, fp_status);
7227
7228     new_flags = get_float_exception_flags(fp_status);
7229
7230     /* Suppress any inexact exceptions the conversion produced */
7231     if (!(old_flags & float_flag_inexact)) {
7232         new_flags = get_float_exception_flags(fp_status);
7233         set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
7234     }
7235
7236     return ret;
7237 }
7238
7239 /* Convert ARM rounding mode to softfloat */
7240 int arm_rmode_to_sf(int rmode)
7241 {
7242     switch (rmode) {
7243     case FPROUNDING_TIEAWAY:
7244         rmode = float_round_ties_away;
7245         break;
7246     case FPROUNDING_ODD:
7247         /* FIXME: add support for TIEAWAY and ODD */
7248         qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n",
7249                       rmode);
7250     case FPROUNDING_TIEEVEN:
7251     default:
7252         rmode = float_round_nearest_even;
7253         break;
7254     case FPROUNDING_POSINF:
7255         rmode = float_round_up;
7256         break;
7257     case FPROUNDING_NEGINF:
7258         rmode = float_round_down;
7259         break;
7260     case FPROUNDING_ZERO:
7261         rmode = float_round_to_zero;
7262         break;
7263     }
7264     return rmode;
7265 }
7266
7267 /* CRC helpers.
7268  * The upper bytes of val (above the number specified by 'bytes') must have
7269  * been zeroed out by the caller.
7270  */
7271 uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes)
7272 {
7273     uint8_t buf[4];
7274
7275     stl_le_p(buf, val);
7276
7277     /* zlib crc32 converts the accumulator and output to one's complement.  */
7278     return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff;
7279 }
7280
7281 uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes)
7282 {
7283     uint8_t buf[4];
7284
7285     stl_le_p(buf, val);
7286
7287     /* Linux crc32c converts the output to one's complement.  */
7288     return crc32c(acc, buf, bytes) ^ 0xffffffff;
7289 }