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eepro100: Set power management capability using pci_reserve_capability
[qemu.git] / hw / eepro100.c
blobc7059296bb6e345966d7f2f676e1b013af5485b9
1 /*
2 * QEMU i8255x (PRO100) emulation
3 *
4 * Copyright (C) 2006-2010 Stefan Weil
5 *
6 * Portions of the code are copies from grub / etherboot eepro100.c
7 * and linux e100.c.
8 *
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation, either version 2 of the License, or
12 * (at your option) version 3 or any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 *
22 * Tested features (i82559):
23 * PXE boot (i386) ok
24 * Linux networking (i386) ok
25 *
26 * Untested:
27 * non-i386 platforms
28 * Windows networking
29 *
30 * References:
31 *
32 * Intel 8255x 10/100 Mbps Ethernet Controller Family
33 * Open Source Software Developer Manual
34 *
35 * TODO:
36 * * PHY emulation should be separated from nic emulation.
37 * Most nic emulations could share the same phy code.
38 * * i82550 is untested. It is programmed like the i82559.
39 * * i82562 is untested. It is programmed like the i82559.
40 * * Power management (i82558 and later) is not implemented.
41 * * Wake-on-LAN is not implemented.
42 */
43
44 #include <stdbool.h> /* bool */
45 #include <stddef.h> /* offsetof */
46 #include "hw.h"
47 #include "pci.h"
48 #include "net.h"
49 #include "eeprom93xx.h"
50
51 #define KiB 1024
52
53 /* Debug EEPRO100 card. */
54 #if 0
55 # define DEBUG_EEPRO100
56 #endif
57
58 #ifdef DEBUG_EEPRO100
59 #define logout(fmt, ...) fprintf(stderr, "EE100\t%-24s" fmt, __func__, ## __VA_ARGS__)
60 #else
61 #define logout(fmt, ...) ((void)0)
62 #endif
63
64 /* Set flags to 0 to disable debug output. */
65 #define INT 1 /* interrupt related actions */
66 #define MDI 1 /* mdi related actions */
67 #define OTHER 1
68 #define RXTX 1
69 #define EEPROM 1 /* eeprom related actions */
70
71 #define TRACE(flag, command) ((flag) ? (command) : (void)0)
72
73 #define missing(text) fprintf(stderr, "eepro100: feature is missing in this emulation: " text "\n")
74
75 #define MAX_ETH_FRAME_SIZE 1514
76
77 /* This driver supports several different devices which are declared here. */
78 #define i82550 0x82550
79 #define i82551 0x82551
80 #define i82557A 0x82557a
81 #define i82557B 0x82557b
82 #define i82557C 0x82557c
83 #define i82558A 0x82558a
84 #define i82558B 0x82558b
85 #define i82559A 0x82559a
86 #define i82559B 0x82559b
87 #define i82559C 0x82559c
88 #define i82559ER 0x82559e
89 #define i82562 0x82562
90 #define i82801 0x82801
91
92 /* Use 64 word EEPROM. TODO: could be a runtime option. */
93 #define EEPROM_SIZE 64
94
95 #define PCI_MEM_SIZE (4 * KiB)
96 #define PCI_IO_SIZE 64
97 #define PCI_FLASH_SIZE (128 * KiB)
98
99 #define BIT(n) (1 << (n))
100 #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
101
102 /* The SCB accepts the following controls for the Tx and Rx units: */
103 #define CU_NOP 0x0000 /* No operation. */
104 #define CU_START 0x0010 /* CU start. */
105 #define CU_RESUME 0x0020 /* CU resume. */
106 #define CU_STATSADDR 0x0040 /* Load dump counters address. */
107 #define CU_SHOWSTATS 0x0050 /* Dump statistical counters. */
108 #define CU_CMD_BASE 0x0060 /* Load CU base address. */
109 #define CU_DUMPSTATS 0x0070 /* Dump and reset statistical counters. */
110 #define CU_SRESUME 0x00a0 /* CU static resume. */
111
112 #define RU_NOP 0x0000
113 #define RX_START 0x0001
114 #define RX_RESUME 0x0002
115 #define RU_ABORT 0x0004
116 #define RX_ADDR_LOAD 0x0006
117 #define RX_RESUMENR 0x0007
118 #define INT_MASK 0x0100
119 #define DRVR_INT 0x0200 /* Driver generated interrupt. */
120
121 typedef struct {
122 PCIDeviceInfo pci;
123 uint32_t device;
124 uint16_t device_id;
125 uint8_t revision;
126 uint8_t stats_size;
127 bool has_extended_tcb_support;
128 bool power_management;
129 } E100PCIDeviceInfo;
130
131 /* Offsets to the various registers.
132 All accesses need not be longword aligned. */
133 enum speedo_offsets {
134 SCBStatus = 0, /* Status Word. */
135 SCBAck = 1,
136 SCBCmd = 2, /* Rx/Command Unit command and status. */
137 SCBIntmask = 3,
138 SCBPointer = 4, /* General purpose pointer. */
139 SCBPort = 8, /* Misc. commands and operands. */
140 SCBflash = 12, /* Flash memory control. */
141 SCBeeprom = 14, /* EEPROM control. */
142 SCBCtrlMDI = 16, /* MDI interface control. */
143 SCBEarlyRx = 20, /* Early receive byte count. */
144 SCBFlow = 24, /* Flow Control. */
145 SCBpmdr = 27, /* Power Management Driver. */
146 SCBgctrl = 28, /* General Control. */
147 SCBgstat = 29, /* General Status. */
148 };
149
150 /* A speedo3 transmit buffer descriptor with two buffers... */
151 typedef struct {
152 uint16_t status;
153 uint16_t command;
154 uint32_t link; /* void * */
155 uint32_t tbd_array_addr; /* transmit buffer descriptor array address. */
156 uint16_t tcb_bytes; /* transmit command block byte count (in lower 14 bits */
157 uint8_t tx_threshold; /* transmit threshold */
158 uint8_t tbd_count; /* TBD number */
159 #if 0
160 /* This constitutes two "TBD" entries: hdr and data */
161 uint32_t tx_buf_addr0; /* void *, header of frame to be transmitted. */
162 int32_t tx_buf_size0; /* Length of Tx hdr. */
163 uint32_t tx_buf_addr1; /* void *, data to be transmitted. */
164 int32_t tx_buf_size1; /* Length of Tx data. */
165 #endif
166 } eepro100_tx_t;
167
168 /* Receive frame descriptor. */
169 typedef struct {
170 int16_t status;
171 uint16_t command;
172 uint32_t link; /* struct RxFD * */
173 uint32_t rx_buf_addr; /* void * */
174 uint16_t count;
175 uint16_t size;
176 char packet[MAX_ETH_FRAME_SIZE + 4];
177 } eepro100_rx_t;
178
179 typedef enum {
180 COMMAND_EL = BIT(15),
181 COMMAND_S = BIT(14),
182 COMMAND_I = BIT(13),
183 COMMAND_NC = BIT(4),
184 COMMAND_SF = BIT(3),
185 COMMAND_CMD = BITS(2, 0),
186 } scb_command_bit;
187
188 typedef enum {
189 STATUS_C = BIT(15),
190 STATUS_OK = BIT(13),
191 } scb_status_bit;
192
193 typedef struct {
194 uint32_t tx_good_frames, tx_max_collisions, tx_late_collisions,
195 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
196 tx_multiple_collisions, tx_total_collisions;
197 uint32_t rx_good_frames, rx_crc_errors, rx_alignment_errors,
198 rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
199 rx_short_frame_errors;
200 uint32_t fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
201 uint16_t xmt_tco_frames, rcv_tco_frames;
202 /* TODO: i82559 has six reserved statistics but a total of 24 dwords. */
203 uint32_t reserved[4];
204 } eepro100_stats_t;
205
206 typedef enum {
207 cu_idle = 0,
208 cu_suspended = 1,
209 cu_active = 2,
210 cu_lpq_active = 2,
211 cu_hqp_active = 3
212 } cu_state_t;
213
214 typedef enum {
215 ru_idle = 0,
216 ru_suspended = 1,
217 ru_no_resources = 2,
218 ru_ready = 4
219 } ru_state_t;
220
221 typedef struct {
222 PCIDevice dev;
223 uint8_t mult[8]; /* multicast mask array */
224 int mmio_index;
225 NICState *nic;
226 NICConf conf;
227 uint8_t scb_stat; /* SCB stat/ack byte */
228 uint8_t int_stat; /* PCI interrupt status */
229 /* region must not be saved by nic_save. */
230 uint32_t region[3]; /* PCI region addresses */
231 uint16_t mdimem[32];
232 eeprom_t *eeprom;
233 uint32_t device; /* device variant */
234 uint32_t pointer;
235 /* (cu_base + cu_offset) address the next command block in the command block list. */
236 uint32_t cu_base; /* CU base address */
237 uint32_t cu_offset; /* CU address offset */
238 /* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */
239 uint32_t ru_base; /* RU base address */
240 uint32_t ru_offset; /* RU address offset */
241 uint32_t statsaddr; /* pointer to eepro100_stats_t */
242
243 /* Temporary status information (no need to save these values),
244 * used while processing CU commands. */
245 eepro100_tx_t tx; /* transmit buffer descriptor */
246 uint32_t cb_address; /* = cu_base + cu_offset */
247
248 /* Statistical counters. Also used for wake-up packet (i82559). */
249 eepro100_stats_t statistics;
250
251 /* Configuration bytes. */
252 uint8_t configuration[22];
253
254 /* Data in mem is always in the byte order of the controller (le). */
255 uint8_t mem[PCI_MEM_SIZE];
256 /* vmstate for each particular nic */
257 VMStateDescription *vmstate;
258
259 /* Quasi static device properties (no need to save them). */
260 uint16_t stats_size;
261 bool has_extended_tcb_support;
262 } EEPRO100State;
263
264 /* Word indices in EEPROM. */
265 typedef enum {
266 EEPROM_CNFG_MDIX = 0x03,
267 EEPROM_ID = 0x05,
268 EEPROM_PHY_ID = 0x06,
269 EEPROM_VENDOR_ID = 0x0c,
270 EEPROM_CONFIG_ASF = 0x0d,
271 EEPROM_DEVICE_ID = 0x23,
272 EEPROM_SMBUS_ADDR = 0x90,
273 } EEPROMOffset;
274
275 /* Bit values for EEPROM ID word. */
276 typedef enum {
277 EEPROM_ID_MDM = BIT(0), /* Modem */
278 EEPROM_ID_STB = BIT(1), /* Standby Enable */
279 EEPROM_ID_WMR = BIT(2), /* ??? */
280 EEPROM_ID_WOL = BIT(5), /* Wake on LAN */
281 EEPROM_ID_DPD = BIT(6), /* Deep Power Down */
282 EEPROM_ID_ALT = BIT(7), /* */
283 /* BITS(10, 8) device revision */
284 EEPROM_ID_BD = BIT(11), /* boot disable */
285 EEPROM_ID_ID = BIT(13), /* id bit */
286 /* BITS(15, 14) signature */
287 EEPROM_ID_VALID = BIT(14), /* signature for valid eeprom */
288 } eeprom_id_bit;
289
290 /* Default values for MDI (PHY) registers */
291 static const uint16_t eepro100_mdi_default[] = {
292 /* MDI Registers 0 - 6, 7 */
293 0x3000, 0x780d, 0x02a8, 0x0154, 0x05e1, 0x0000, 0x0000, 0x0000,
294 /* MDI Registers 8 - 15 */
295 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
296 /* MDI Registers 16 - 31 */
297 0x0003, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
298 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
299 };
300
301 /* Readonly mask for MDI (PHY) registers */
302 static const uint16_t eepro100_mdi_mask[] = {
303 0x0000, 0xffff, 0xffff, 0xffff, 0xc01f, 0xffff, 0xffff, 0x0000,
304 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
305 0x0fff, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
306 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
307 };
308
309 /* XXX: optimize */
310 static void stl_le_phys(target_phys_addr_t addr, uint32_t val)
311 {
312 val = cpu_to_le32(val);
313 cpu_physical_memory_write(addr, (const uint8_t *)&val, sizeof(val));
314 }
315
316 #define POLYNOMIAL 0x04c11db6
317
318 /* From FreeBSD */
319 /* XXX: optimize */
320 static unsigned compute_mcast_idx(const uint8_t * ep)
321 {
322 uint32_t crc;
323 int carry, i, j;
324 uint8_t b;
325
326 crc = 0xffffffff;
327 for (i = 0; i < 6; i++) {
328 b = *ep++;
329 for (j = 0; j < 8; j++) {
330 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
331 crc <<= 1;
332 b >>= 1;
333 if (carry) {
334 crc = ((crc ^ POLYNOMIAL) | carry);
335 }
336 }
337 }
338 return (crc & BITS(7, 2)) >> 2;
339 }
340
341 #if defined(DEBUG_EEPRO100)
342 static const char *nic_dump(const uint8_t * buf, unsigned size)
343 {
344 static char dump[3 * 16 + 1];
345 char *p = &dump[0];
346 if (size > 16) {
347 size = 16;
348 }
349 while (size-- > 0) {
350 p += sprintf(p, " %02x", *buf++);
351 }
352 return dump;
353 }
354 #endif /* DEBUG_EEPRO100 */
355
356 enum scb_stat_ack {
357 stat_ack_not_ours = 0x00,
358 stat_ack_sw_gen = 0x04,
359 stat_ack_rnr = 0x10,
360 stat_ack_cu_idle = 0x20,
361 stat_ack_frame_rx = 0x40,
362 stat_ack_cu_cmd_done = 0x80,
363 stat_ack_not_present = 0xFF,
364 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
365 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
366 };
367
368 static void disable_interrupt(EEPRO100State * s)
369 {
370 if (s->int_stat) {
371 TRACE(INT, logout("interrupt disabled\n"));
372 qemu_irq_lower(s->dev.irq[0]);
373 s->int_stat = 0;
374 }
375 }
376
377 static void enable_interrupt(EEPRO100State * s)
378 {
379 if (!s->int_stat) {
380 TRACE(INT, logout("interrupt enabled\n"));
381 qemu_irq_raise(s->dev.irq[0]);
382 s->int_stat = 1;
383 }
384 }
385
386 static void eepro100_acknowledge(EEPRO100State * s)
387 {
388 s->scb_stat &= ~s->mem[SCBAck];
389 s->mem[SCBAck] = s->scb_stat;
390 if (s->scb_stat == 0) {
391 disable_interrupt(s);
392 }
393 }
394
395 static void eepro100_interrupt(EEPRO100State * s, uint8_t status)
396 {
397 uint8_t mask = ~s->mem[SCBIntmask];
398 s->mem[SCBAck] |= status;
399 status = s->scb_stat = s->mem[SCBAck];
400 status &= (mask | 0x0f);
401 #if 0
402 status &= (~s->mem[SCBIntmask] | 0x0xf);
403 #endif
404 if (status && (mask & 0x01)) {
405 /* SCB mask and SCB Bit M do not disable interrupt. */
406 enable_interrupt(s);
407 } else if (s->int_stat) {
408 disable_interrupt(s);
409 }
410 }
411
412 static void eepro100_cx_interrupt(EEPRO100State * s)
413 {
414 /* CU completed action command. */
415 /* Transmit not ok (82557 only, not in emulation). */
416 eepro100_interrupt(s, 0x80);
417 }
418
419 static void eepro100_cna_interrupt(EEPRO100State * s)
420 {
421 /* CU left the active state. */
422 eepro100_interrupt(s, 0x20);
423 }
424
425 static void eepro100_fr_interrupt(EEPRO100State * s)
426 {
427 /* RU received a complete frame. */
428 eepro100_interrupt(s, 0x40);
429 }
430
431 static void eepro100_rnr_interrupt(EEPRO100State * s)
432 {
433 /* RU is not ready. */
434 eepro100_interrupt(s, 0x10);
435 }
436
437 static void eepro100_mdi_interrupt(EEPRO100State * s)
438 {
439 /* MDI completed read or write cycle. */
440 eepro100_interrupt(s, 0x08);
441 }
442
443 static void eepro100_swi_interrupt(EEPRO100State * s)
444 {
445 /* Software has requested an interrupt. */
446 eepro100_interrupt(s, 0x04);
447 }
448
449 #if 0
450 static void eepro100_fcp_interrupt(EEPRO100State * s)
451 {
452 /* Flow control pause interrupt (82558 and later). */
453 eepro100_interrupt(s, 0x01);
454 }
455 #endif
456
457 static void e100_pci_reset(EEPRO100State * s, E100PCIDeviceInfo *e100_device)
458 {
459 uint32_t device = s->device;
460 uint8_t *pci_conf = s->dev.config;
461
462 TRACE(OTHER, logout("%p\n", s));
463
464 /* PCI Vendor ID */
465 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
466 /* PCI Device ID */
467 pci_config_set_device_id(pci_conf, e100_device->device_id);
468 /* PCI Status */
469 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
470 PCI_STATUS_FAST_BACK);
471 /* PCI Revision ID */
472 pci_config_set_revision(pci_conf, e100_device->revision);
473 pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
474 /* PCI Latency Timer */
475 pci_set_byte(pci_conf + PCI_LATENCY_TIMER, 0x20); /* latency timer = 32 clocks */
476 /* Capability Pointer is set by PCI framework. */
477 /* Minimum Grant */
478 pci_set_byte(pci_conf + PCI_MIN_GNT, 0x08);
479 /* Maximum Latency */
480 pci_set_byte(pci_conf + PCI_MAX_LAT, 0x18);
481
482 s->stats_size = e100_device->stats_size;
483 s->has_extended_tcb_support = e100_device->has_extended_tcb_support;
484
485 switch (device) {
486 case i82550:
487 case i82551:
488 case i82557A:
489 case i82557B:
490 case i82557C:
491 case i82558A:
492 case i82558B:
493 case i82559A:
494 case i82559B:
495 case i82559ER:
496 case i82562:
497 case i82801:
498 break;
499 case i82559C:
500 #if EEPROM_SIZE > 0
501 pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID, PCI_VENDOR_ID_INTEL);
502 pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, 0x0040);
503 #endif
504 break;
505 default:
506 logout("Device %X is undefined!\n", device);
507 }
508
509 /* Standard TxCB. */
510 s->configuration[6] |= BIT(4);
511
512 /* Standard statistical counters. */
513 s->configuration[6] |= BIT(5);
514
515 if (s->stats_size == 80) {
516 /* TODO: check TCO Statistical Counters bit. Documentation not clear. */
517 if (s->configuration[6] & BIT(2)) {
518 /* TCO statistical counters. */
519 assert(s->configuration[6] & BIT(5));
520 } else {
521 if (s->configuration[6] & BIT(5)) {
522 /* No extended statistical counters, i82557 compatible. */
523 s->stats_size = 64;
524 } else {
525 /* i82558 compatible. */
526 s->stats_size = 76;
527 }
528 }
529 } else {
530 if (s->configuration[6] & BIT(5)) {
531 /* No extended statistical counters. */
532 s->stats_size = 64;
533 }
534 }
535 assert(s->stats_size > 0 && s->stats_size <= sizeof(s->statistics));
536
537 if (e100_device->power_management) {
538 /* Power Management Capabilities */
539 int cfg_offset;
540 pci_reserve_capability(&s->dev, PCI_CONFIG_HEADER_SIZE,
541 0xdc - PCI_CONFIG_HEADER_SIZE);
542 cfg_offset = pci_add_capability(&s->dev, PCI_CAP_ID_PM, PCI_PM_SIZEOF);
543 assert(cfg_offset == 0xdc);
544 if (cfg_offset > 0) {
545 /* Power Management Capabilities */
546 pci_set_word(pci_conf + cfg_offset + PCI_PM_PMC, 0x7e21);
547 #if 0 /* TODO: replace dummy code for power management emulation. */
548 /* TODO: Power Management Control / Status. */
549 pci_set_word(pci_conf + cfg_offset + PCI_PM_CTRL, 0x0000);
550 /* TODO: Ethernet Power Consumption Registers (i82559 and later). */
551 pci_set_byte(pci_conf + cfg_offset + PCI_PM_PPB_EXTENSIONS, 0x0000);
552 #endif
553 }
554 }
555
556 #if EEPROM_SIZE > 0
557 if (device == i82557C || device == i82558B || device == i82559C) {
558 /*
559 TODO: get vendor id from EEPROM for i82557C or later.
560 TODO: get device id from EEPROM for i82557C or later.
561 TODO: status bit 4 can be disabled by EEPROM for i82558, i82559.
562 TODO: header type is determined by EEPROM for i82559.
563 TODO: get subsystem id from EEPROM for i82557C or later.
564 TODO: get subsystem vendor id from EEPROM for i82557C or later.
565 TODO: exp. rom baddr depends on a bit in EEPROM for i82558 or later.
566 TODO: capability pointer depends on EEPROM for i82558.
567 */
568 logout("Get device id and revision from EEPROM!!!\n");
569 }
570 #endif /* EEPROM_SIZE > 0 */
571 }
572
573 static void nic_selective_reset(EEPRO100State * s)
574 {
575 size_t i;
576 uint16_t *eeprom_contents = eeprom93xx_data(s->eeprom);
577 #if 0
578 eeprom93xx_reset(s->eeprom);
579 #endif
580 memcpy(eeprom_contents, s->conf.macaddr.a, 6);
581 eeprom_contents[EEPROM_ID] = EEPROM_ID_VALID;
582 if (s->device == i82557B || s->device == i82557C)
583 eeprom_contents[5] = 0x0100;
584 eeprom_contents[EEPROM_PHY_ID] = 1;
585 uint16_t sum = 0;
586 for (i = 0; i < EEPROM_SIZE - 1; i++) {
587 sum += eeprom_contents[i];
588 }
589 eeprom_contents[EEPROM_SIZE - 1] = 0xbaba - sum;
590 TRACE(EEPROM, logout("checksum=0x%04x\n", eeprom_contents[EEPROM_SIZE - 1]));
591
592 memset(s->mem, 0, sizeof(s->mem));
593 uint32_t val = BIT(21);
594 memcpy(&s->mem[SCBCtrlMDI], &val, sizeof(val));
595
596 assert(sizeof(s->mdimem) == sizeof(eepro100_mdi_default));
597 memcpy(&s->mdimem[0], &eepro100_mdi_default[0], sizeof(s->mdimem));
598 }
599
600 static void nic_reset(void *opaque)
601 {
602 EEPRO100State *s = opaque;
603 TRACE(OTHER, logout("%p\n", s));
604 /* TODO: Clearing of multicast table for selective reset, too? */
605 memset(&s->mult[0], 0, sizeof(s->mult));
606 nic_selective_reset(s);
607 }
608
609 #if defined(DEBUG_EEPRO100)
610 static const char * const e100_reg[PCI_IO_SIZE / 4] = {
611 "Command/Status",
612 "General Pointer",
613 "Port",
614 "EEPROM/Flash Control",
615 "MDI Control",
616 "Receive DMA Byte Count",
617 "Flow Control",
618 "General Status/Control"
619 };
620
621 static char *regname(uint32_t addr)
622 {
623 static char buf[32];
624 if (addr < PCI_IO_SIZE) {
625 const char *r = e100_reg[addr / 4];
626 if (r != 0) {
627 snprintf(buf, sizeof(buf), "%s+%u", r, addr % 4);
628 } else {
629 snprintf(buf, sizeof(buf), "0x%02x", addr);
630 }
631 } else {
632 snprintf(buf, sizeof(buf), "??? 0x%08x", addr);
633 }
634 return buf;
635 }
636 #endif /* DEBUG_EEPRO100 */
637
638 /*****************************************************************************
639 *
640 * Command emulation.
641 *
642 ****************************************************************************/
643
644 #if 0
645 static uint16_t eepro100_read_command(EEPRO100State * s)
646 {
647 uint16_t val = 0xffff;
648 TRACE(OTHER, logout("val=0x%04x\n", val));
649 return val;
650 }
651 #endif
652
653 /* Commands that can be put in a command list entry. */
654 enum commands {
655 CmdNOp = 0,
656 CmdIASetup = 1,
657 CmdConfigure = 2,
658 CmdMulticastList = 3,
659 CmdTx = 4,
660 CmdTDR = 5, /* load microcode */
661 CmdDump = 6,
662 CmdDiagnose = 7,
663
664 /* And some extra flags: */
665 CmdSuspend = 0x4000, /* Suspend after completion. */
666 CmdIntr = 0x2000, /* Interrupt after completion. */
667 CmdTxFlex = 0x0008, /* Use "Flexible mode" for CmdTx command. */
668 };
669
670 static cu_state_t get_cu_state(EEPRO100State * s)
671 {
672 return ((s->mem[SCBStatus] & BITS(7, 6)) >> 6);
673 }
674
675 static void set_cu_state(EEPRO100State * s, cu_state_t state)
676 {
677 s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(7, 6)) + (state << 6);
678 }
679
680 static ru_state_t get_ru_state(EEPRO100State * s)
681 {
682 return ((s->mem[SCBStatus] & BITS(5, 2)) >> 2);
683 }
684
685 static void set_ru_state(EEPRO100State * s, ru_state_t state)
686 {
687 s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(5, 2)) + (state << 2);
688 }
689
690 static void dump_statistics(EEPRO100State * s)
691 {
692 /* Dump statistical data. Most data is never changed by the emulation
693 * and always 0, so we first just copy the whole block and then those
694 * values which really matter.
695 * Number of data should check configuration!!!
696 */
697 cpu_physical_memory_write(s->statsaddr,
698 (uint8_t *) & s->statistics, s->stats_size);
699 stl_le_phys(s->statsaddr + 0, s->statistics.tx_good_frames);
700 stl_le_phys(s->statsaddr + 36, s->statistics.rx_good_frames);
701 stl_le_phys(s->statsaddr + 48, s->statistics.rx_resource_errors);
702 stl_le_phys(s->statsaddr + 60, s->statistics.rx_short_frame_errors);
703 #if 0
704 stw_le_phys(s->statsaddr + 76, s->statistics.xmt_tco_frames);
705 stw_le_phys(s->statsaddr + 78, s->statistics.rcv_tco_frames);
706 missing("CU dump statistical counters");
707 #endif
708 }
709
710 static void read_cb(EEPRO100State *s)
711 {
712 cpu_physical_memory_read(s->cb_address, (uint8_t *) &s->tx, sizeof(s->tx));
713 s->tx.status = le16_to_cpu(s->tx.status);
714 s->tx.command = le16_to_cpu(s->tx.command);
715 s->tx.link = le32_to_cpu(s->tx.link);
716 s->tx.tbd_array_addr = le32_to_cpu(s->tx.tbd_array_addr);
717 s->tx.tcb_bytes = le16_to_cpu(s->tx.tcb_bytes);
718 }
719
720 static void tx_command(EEPRO100State *s)
721 {
722 uint32_t tbd_array = le32_to_cpu(s->tx.tbd_array_addr);
723 uint16_t tcb_bytes = (le16_to_cpu(s->tx.tcb_bytes) & 0x3fff);
724 /* Sends larger than MAX_ETH_FRAME_SIZE are allowed, up to 2600 bytes. */
725 uint8_t buf[2600];
726 uint16_t size = 0;
727 uint32_t tbd_address = s->cb_address + 0x10;
728 TRACE(RXTX, logout
729 ("transmit, TBD array address 0x%08x, TCB byte count 0x%04x, TBD count %u\n",
730 tbd_array, tcb_bytes, s->tx.tbd_count));
731
732 if (tcb_bytes > 2600) {
733 logout("TCB byte count too large, using 2600\n");
734 tcb_bytes = 2600;
735 }
736 if (!((tcb_bytes > 0) || (tbd_array != 0xffffffff))) {
737 logout
738 ("illegal values of TBD array address and TCB byte count!\n");
739 }
740 assert(tcb_bytes <= sizeof(buf));
741 while (size < tcb_bytes) {
742 uint32_t tx_buffer_address = ldl_phys(tbd_address);
743 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
744 #if 0
745 uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
746 #endif
747 tbd_address += 8;
748 TRACE(RXTX, logout
749 ("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n",
750 tx_buffer_address, tx_buffer_size));
751 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
752 cpu_physical_memory_read(tx_buffer_address, &buf[size],
753 tx_buffer_size);
754 size += tx_buffer_size;
755 }
756 if (tbd_array == 0xffffffff) {
757 /* Simplified mode. Was already handled by code above. */
758 } else {
759 /* Flexible mode. */
760 uint8_t tbd_count = 0;
761 if (s->has_extended_tcb_support && !(s->configuration[6] & BIT(4))) {
762 /* Extended Flexible TCB. */
763 for (; tbd_count < 2; tbd_count++) {
764 uint32_t tx_buffer_address = ldl_phys(tbd_address);
765 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
766 uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
767 tbd_address += 8;
768 TRACE(RXTX, logout
769 ("TBD (extended flexible mode): buffer address 0x%08x, size 0x%04x\n",
770 tx_buffer_address, tx_buffer_size));
771 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
772 cpu_physical_memory_read(tx_buffer_address, &buf[size],
773 tx_buffer_size);
774 size += tx_buffer_size;
775 if (tx_buffer_el & 1) {
776 break;
777 }
778 }
779 }
780 tbd_address = tbd_array;
781 for (; tbd_count < s->tx.tbd_count; tbd_count++) {
782 uint32_t tx_buffer_address = ldl_phys(tbd_address);
783 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
784 uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
785 tbd_address += 8;
786 TRACE(RXTX, logout
787 ("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n",
788 tx_buffer_address, tx_buffer_size));
789 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
790 cpu_physical_memory_read(tx_buffer_address, &buf[size],
791 tx_buffer_size);
792 size += tx_buffer_size;
793 if (tx_buffer_el & 1) {
794 break;
795 }
796 }
797 }
798 TRACE(RXTX, logout("%p sending frame, len=%d,%s\n", s, size, nic_dump(buf, size)));
799 qemu_send_packet(&s->nic->nc, buf, size);
800 s->statistics.tx_good_frames++;
801 /* Transmit with bad status would raise an CX/TNO interrupt.
802 * (82557 only). Emulation never has bad status. */
803 #if 0
804 eepro100_cx_interrupt(s);
805 #endif
806 }
807
808 static void set_multicast_list(EEPRO100State *s)
809 {
810 uint16_t multicast_count = s->tx.tbd_array_addr & BITS(13, 0);
811 uint16_t i;
812 memset(&s->mult[0], 0, sizeof(s->mult));
813 TRACE(OTHER, logout("multicast list, multicast count = %u\n", multicast_count));
814 for (i = 0; i < multicast_count; i += 6) {
815 uint8_t multicast_addr[6];
816 cpu_physical_memory_read(s->cb_address + 10 + i, multicast_addr, 6);
817 TRACE(OTHER, logout("multicast entry %s\n", nic_dump(multicast_addr, 6)));
818 unsigned mcast_idx = compute_mcast_idx(multicast_addr);
819 assert(mcast_idx < 64);
820 s->mult[mcast_idx >> 3] |= (1 << (mcast_idx & 7));
821 }
822 }
823
824 static void action_command(EEPRO100State *s)
825 {
826 for (;;) {
827 bool bit_el;
828 bool bit_s;
829 bool bit_i;
830 bool bit_nc;
831 uint16_t ok_status = STATUS_OK;
832 s->cb_address = s->cu_base + s->cu_offset;
833 read_cb(s);
834 bit_el = ((s->tx.command & COMMAND_EL) != 0);
835 bit_s = ((s->tx.command & COMMAND_S) != 0);
836 bit_i = ((s->tx.command & COMMAND_I) != 0);
837 bit_nc = ((s->tx.command & COMMAND_NC) != 0);
838 #if 0
839 bool bit_sf = ((s->tx.command & COMMAND_SF) != 0);
840 #endif
841 s->cu_offset = s->tx.link;
842 TRACE(OTHER,
843 logout("val=(cu start), status=0x%04x, command=0x%04x, link=0x%08x\n",
844 s->tx.status, s->tx.command, s->tx.link));
845 switch (s->tx.command & COMMAND_CMD) {
846 case CmdNOp:
847 /* Do nothing. */
848 break;
849 case CmdIASetup:
850 cpu_physical_memory_read(s->cb_address + 8, &s->conf.macaddr.a[0], 6);
851 TRACE(OTHER, logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6)));
852 break;
853 case CmdConfigure:
854 cpu_physical_memory_read(s->cb_address + 8, &s->configuration[0],
855 sizeof(s->configuration));
856 TRACE(OTHER, logout("configuration: %s\n", nic_dump(&s->configuration[0], 16)));
857 break;
858 case CmdMulticastList:
859 set_multicast_list(s);
860 break;
861 case CmdTx:
862 if (bit_nc) {
863 missing("CmdTx: NC = 0");
864 ok_status = 0;
865 break;
866 }
867 tx_command(s);
868 break;
869 case CmdTDR:
870 TRACE(OTHER, logout("load microcode\n"));
871 /* Starting with offset 8, the command contains
872 * 64 dwords microcode which we just ignore here. */
873 break;
874 case CmdDiagnose:
875 TRACE(OTHER, logout("diagnose\n"));
876 /* Make sure error flag is not set. */
877 s->tx.status = 0;
878 break;
879 default:
880 missing("undefined command");
881 ok_status = 0;
882 break;
883 }
884 /* Write new status. */
885 stw_phys(s->cb_address, s->tx.status | ok_status | STATUS_C);
886 if (bit_i) {
887 /* CU completed action. */
888 eepro100_cx_interrupt(s);
889 }
890 if (bit_el) {
891 /* CU becomes idle. Terminate command loop. */
892 set_cu_state(s, cu_idle);
893 eepro100_cna_interrupt(s);
894 break;
895 } else if (bit_s) {
896 /* CU becomes suspended. Terminate command loop. */
897 set_cu_state(s, cu_suspended);
898 eepro100_cna_interrupt(s);
899 break;
900 } else {
901 /* More entries in list. */
902 TRACE(OTHER, logout("CU list with at least one more entry\n"));
903 }
904 }
905 TRACE(OTHER, logout("CU list empty\n"));
906 /* List is empty. Now CU is idle or suspended. */
907 }
908
909 static void eepro100_cu_command(EEPRO100State * s, uint8_t val)
910 {
911 cu_state_t cu_state;
912 switch (val) {
913 case CU_NOP:
914 /* No operation. */
915 break;
916 case CU_START:
917 cu_state = get_cu_state(s);
918 if (cu_state != cu_idle && cu_state != cu_suspended) {
919 /* Intel documentation says that CU must be idle or suspended
920 * for the CU start command. */
921 logout("unexpected CU state is %u\n", cu_state);
922 }
923 set_cu_state(s, cu_active);
924 s->cu_offset = s->pointer;
925 action_command(s);
926 break;
927 case CU_RESUME:
928 if (get_cu_state(s) != cu_suspended) {
929 logout("bad CU resume from CU state %u\n", get_cu_state(s));
930 /* Workaround for bad Linux eepro100 driver which resumes
931 * from idle state. */
932 #if 0
933 missing("cu resume");
934 #endif
935 set_cu_state(s, cu_suspended);
936 }
937 if (get_cu_state(s) == cu_suspended) {
938 TRACE(OTHER, logout("CU resuming\n"));
939 set_cu_state(s, cu_active);
940 action_command(s);
941 }
942 break;
943 case CU_STATSADDR:
944 /* Load dump counters address. */
945 s->statsaddr = s->pointer;
946 TRACE(OTHER, logout("val=0x%02x (status address)\n", val));
947 break;
948 case CU_SHOWSTATS:
949 /* Dump statistical counters. */
950 TRACE(OTHER, logout("val=0x%02x (dump stats)\n", val));
951 dump_statistics(s);
952 stl_le_phys(s->statsaddr + s->stats_size, 0xa005);
953 break;
954 case CU_CMD_BASE:
955 /* Load CU base. */
956 TRACE(OTHER, logout("val=0x%02x (CU base address)\n", val));
957 s->cu_base = s->pointer;
958 break;
959 case CU_DUMPSTATS:
960 /* Dump and reset statistical counters. */
961 TRACE(OTHER, logout("val=0x%02x (dump stats and reset)\n", val));
962 dump_statistics(s);
963 stl_le_phys(s->statsaddr + s->stats_size, 0xa007);
964 memset(&s->statistics, 0, sizeof(s->statistics));
965 break;
966 case CU_SRESUME:
967 /* CU static resume. */
968 missing("CU static resume");
969 break;
970 default:
971 missing("Undefined CU command");
972 }
973 }
974
975 static void eepro100_ru_command(EEPRO100State * s, uint8_t val)
976 {
977 switch (val) {
978 case RU_NOP:
979 /* No operation. */
980 break;
981 case RX_START:
982 /* RU start. */
983 if (get_ru_state(s) != ru_idle) {
984 logout("RU state is %u, should be %u\n", get_ru_state(s), ru_idle);
985 #if 0
986 assert(!"wrong RU state");
987 #endif
988 }
989 set_ru_state(s, ru_ready);
990 s->ru_offset = s->pointer;
991 TRACE(OTHER, logout("val=0x%02x (rx start)\n", val));
992 break;
993 case RX_RESUME:
994 /* Restart RU. */
995 if (get_ru_state(s) != ru_suspended) {
996 logout("RU state is %u, should be %u\n", get_ru_state(s),
997 ru_suspended);
998 #if 0
999 assert(!"wrong RU state");
1000 #endif
1001 }
1002 set_ru_state(s, ru_ready);
1003 break;
1004 case RU_ABORT:
1005 /* RU abort. */
1006 if (get_ru_state(s) == ru_ready) {
1007 eepro100_rnr_interrupt(s);
1008 }
1009 set_ru_state(s, ru_idle);
1010 break;
1011 case RX_ADDR_LOAD:
1012 /* Load RU base. */
1013 TRACE(OTHER, logout("val=0x%02x (RU base address)\n", val));
1014 s->ru_base = s->pointer;
1015 break;
1016 default:
1017 logout("val=0x%02x (undefined RU command)\n", val);
1018 missing("Undefined SU command");
1019 }
1020 }
1021
1022 static void eepro100_write_command(EEPRO100State * s, uint8_t val)
1023 {
1024 eepro100_ru_command(s, val & 0x0f);
1025 eepro100_cu_command(s, val & 0xf0);
1026 if ((val) == 0) {
1027 TRACE(OTHER, logout("val=0x%02x\n", val));
1028 }
1029 /* Clear command byte after command was accepted. */
1030 s->mem[SCBCmd] = 0;
1031 }
1032
1033 /*****************************************************************************
1034 *
1035 * EEPROM emulation.
1036 *
1037 ****************************************************************************/
1038
1039 #define EEPROM_CS 0x02
1040 #define EEPROM_SK 0x01
1041 #define EEPROM_DI 0x04
1042 #define EEPROM_DO 0x08
1043
1044 static uint16_t eepro100_read_eeprom(EEPRO100State * s)
1045 {
1046 uint16_t val;
1047 memcpy(&val, &s->mem[SCBeeprom], sizeof(val));
1048 if (eeprom93xx_read(s->eeprom)) {
1049 val |= EEPROM_DO;
1050 } else {
1051 val &= ~EEPROM_DO;
1052 }
1053 TRACE(EEPROM, logout("val=0x%04x\n", val));
1054 return val;
1055 }
1056
1057 static void eepro100_write_eeprom(eeprom_t * eeprom, uint8_t val)
1058 {
1059 TRACE(EEPROM, logout("val=0x%02x\n", val));
1060
1061 /* mask unwriteable bits */
1062 #if 0
1063 val = SET_MASKED(val, 0x31, eeprom->value);
1064 #endif
1065
1066 int eecs = ((val & EEPROM_CS) != 0);
1067 int eesk = ((val & EEPROM_SK) != 0);
1068 int eedi = ((val & EEPROM_DI) != 0);
1069 eeprom93xx_write(eeprom, eecs, eesk, eedi);
1070 }
1071
1072 static void eepro100_write_pointer(EEPRO100State * s, uint32_t val)
1073 {
1074 s->pointer = le32_to_cpu(val);
1075 TRACE(OTHER, logout("val=0x%08x\n", val));
1076 }
1077
1078 /*****************************************************************************
1079 *
1080 * MDI emulation.
1081 *
1082 ****************************************************************************/
1083
1084 #if defined(DEBUG_EEPRO100)
1085 static const char * const mdi_op_name[] = {
1086 "opcode 0",
1087 "write",
1088 "read",
1089 "opcode 3"
1090 };
1091
1092 static const char * const mdi_reg_name[] = {
1093 "Control",
1094 "Status",
1095 "PHY Identification (Word 1)",
1096 "PHY Identification (Word 2)",
1097 "Auto-Negotiation Advertisement",
1098 "Auto-Negotiation Link Partner Ability",
1099 "Auto-Negotiation Expansion"
1100 };
1101
1102 static const char *reg2name(uint8_t reg)
1103 {
1104 static char buffer[10];
1105 const char *p = buffer;
1106 if (reg < ARRAY_SIZE(mdi_reg_name)) {
1107 p = mdi_reg_name[reg];
1108 } else {
1109 snprintf(buffer, sizeof(buffer), "reg=0x%02x", reg);
1110 }
1111 return p;
1112 }
1113 #endif /* DEBUG_EEPRO100 */
1114
1115 static uint32_t eepro100_read_mdi(EEPRO100State * s)
1116 {
1117 uint32_t val;
1118 memcpy(&val, &s->mem[0x10], sizeof(val));
1119
1120 #ifdef DEBUG_EEPRO100
1121 uint8_t raiseint = (val & BIT(29)) >> 29;
1122 uint8_t opcode = (val & BITS(27, 26)) >> 26;
1123 uint8_t phy = (val & BITS(25, 21)) >> 21;
1124 uint8_t reg = (val & BITS(20, 16)) >> 16;
1125 uint16_t data = (val & BITS(15, 0));
1126 #endif
1127 /* Emulation takes no time to finish MDI transaction. */
1128 val |= BIT(28);
1129 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1130 val, raiseint, mdi_op_name[opcode], phy,
1131 reg2name(reg), data));
1132 return val;
1133 }
1134
1135 static void eepro100_write_mdi(EEPRO100State * s, uint32_t val)
1136 {
1137 uint8_t raiseint = (val & BIT(29)) >> 29;
1138 uint8_t opcode = (val & BITS(27, 26)) >> 26;
1139 uint8_t phy = (val & BITS(25, 21)) >> 21;
1140 uint8_t reg = (val & BITS(20, 16)) >> 16;
1141 uint16_t data = (val & BITS(15, 0));
1142 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1143 val, raiseint, mdi_op_name[opcode], phy, reg2name(reg), data));
1144 if (phy != 1) {
1145 /* Unsupported PHY address. */
1146 #if 0
1147 logout("phy must be 1 but is %u\n", phy);
1148 #endif
1149 data = 0;
1150 } else if (opcode != 1 && opcode != 2) {
1151 /* Unsupported opcode. */
1152 logout("opcode must be 1 or 2 but is %u\n", opcode);
1153 data = 0;
1154 } else if (reg > 6) {
1155 /* Unsupported register. */
1156 logout("register must be 0...6 but is %u\n", reg);
1157 data = 0;
1158 } else {
1159 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1160 val, raiseint, mdi_op_name[opcode], phy,
1161 reg2name(reg), data));
1162 if (opcode == 1) {
1163 /* MDI write */
1164 switch (reg) {
1165 case 0: /* Control Register */
1166 if (data & 0x8000) {
1167 /* Reset status and control registers to default. */
1168 s->mdimem[0] = eepro100_mdi_default[0];
1169 s->mdimem[1] = eepro100_mdi_default[1];
1170 data = s->mdimem[reg];
1171 } else {
1172 /* Restart Auto Configuration = Normal Operation */
1173 data &= ~0x0200;
1174 }
1175 break;
1176 case 1: /* Status Register */
1177 missing("not writable");
1178 data = s->mdimem[reg];
1179 break;
1180 case 2: /* PHY Identification Register (Word 1) */
1181 case 3: /* PHY Identification Register (Word 2) */
1182 missing("not implemented");
1183 break;
1184 case 4: /* Auto-Negotiation Advertisement Register */
1185 case 5: /* Auto-Negotiation Link Partner Ability Register */
1186 break;
1187 case 6: /* Auto-Negotiation Expansion Register */
1188 default:
1189 missing("not implemented");
1190 }
1191 s->mdimem[reg] = data;
1192 } else if (opcode == 2) {
1193 /* MDI read */
1194 switch (reg) {
1195 case 0: /* Control Register */
1196 if (data & 0x8000) {
1197 /* Reset status and control registers to default. */
1198 s->mdimem[0] = eepro100_mdi_default[0];
1199 s->mdimem[1] = eepro100_mdi_default[1];
1200 }
1201 break;
1202 case 1: /* Status Register */
1203 s->mdimem[reg] |= 0x0020;
1204 break;
1205 case 2: /* PHY Identification Register (Word 1) */
1206 case 3: /* PHY Identification Register (Word 2) */
1207 case 4: /* Auto-Negotiation Advertisement Register */
1208 break;
1209 case 5: /* Auto-Negotiation Link Partner Ability Register */
1210 s->mdimem[reg] = 0x41fe;
1211 break;
1212 case 6: /* Auto-Negotiation Expansion Register */
1213 s->mdimem[reg] = 0x0001;
1214 break;
1215 }
1216 data = s->mdimem[reg];
1217 }
1218 /* Emulation takes no time to finish MDI transaction.
1219 * Set MDI bit in SCB status register. */
1220 s->mem[SCBAck] |= 0x08;
1221 val |= BIT(28);
1222 if (raiseint) {
1223 eepro100_mdi_interrupt(s);
1224 }
1225 }
1226 val = (val & 0xffff0000) + data;
1227 memcpy(&s->mem[0x10], &val, sizeof(val));
1228 }
1229
1230 /*****************************************************************************
1231 *
1232 * Port emulation.
1233 *
1234 ****************************************************************************/
1235
1236 #define PORT_SOFTWARE_RESET 0
1237 #define PORT_SELFTEST 1
1238 #define PORT_SELECTIVE_RESET 2
1239 #define PORT_DUMP 3
1240 #define PORT_SELECTION_MASK 3
1241
1242 typedef struct {
1243 uint32_t st_sign; /* Self Test Signature */
1244 uint32_t st_result; /* Self Test Results */
1245 } eepro100_selftest_t;
1246
1247 static uint32_t eepro100_read_port(EEPRO100State * s)
1248 {
1249 return 0;
1250 }
1251
1252 static void eepro100_write_port(EEPRO100State * s, uint32_t val)
1253 {
1254 val = le32_to_cpu(val);
1255 uint32_t address = (val & ~PORT_SELECTION_MASK);
1256 uint8_t selection = (val & PORT_SELECTION_MASK);
1257 switch (selection) {
1258 case PORT_SOFTWARE_RESET:
1259 nic_reset(s);
1260 break;
1261 case PORT_SELFTEST:
1262 TRACE(OTHER, logout("selftest address=0x%08x\n", address));
1263 eepro100_selftest_t data;
1264 cpu_physical_memory_read(address, (uint8_t *) & data, sizeof(data));
1265 data.st_sign = 0xffffffff;
1266 data.st_result = 0;
1267 cpu_physical_memory_write(address, (uint8_t *) & data, sizeof(data));
1268 break;
1269 case PORT_SELECTIVE_RESET:
1270 TRACE(OTHER, logout("selective reset, selftest address=0x%08x\n", address));
1271 nic_selective_reset(s);
1272 break;
1273 default:
1274 logout("val=0x%08x\n", val);
1275 missing("unknown port selection");
1276 }
1277 }
1278
1279 /*****************************************************************************
1280 *
1281 * General hardware emulation.
1282 *
1283 ****************************************************************************/
1284
1285 static uint8_t eepro100_read1(EEPRO100State * s, uint32_t addr)
1286 {
1287 uint8_t val;
1288 if (addr <= sizeof(s->mem) - sizeof(val)) {
1289 memcpy(&val, &s->mem[addr], sizeof(val));
1290 }
1291
1292 switch (addr) {
1293 case SCBStatus:
1294 case SCBAck:
1295 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1296 break;
1297 case SCBCmd:
1298 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1299 #if 0
1300 val = eepro100_read_command(s);
1301 #endif
1302 break;
1303 case SCBIntmask:
1304 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1305 break;
1306 case SCBPort + 3:
1307 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1308 break;
1309 case SCBeeprom:
1310 val = eepro100_read_eeprom(s);
1311 break;
1312 case SCBpmdr: /* Power Management Driver Register */
1313 val = 0;
1314 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1315 break;
1316 case SCBgstat: /* General Status Register */
1317 /* 100 Mbps full duplex, valid link */
1318 val = 0x07;
1319 TRACE(OTHER, logout("addr=General Status val=%02x\n", val));
1320 break;
1321 default:
1322 logout("addr=%s val=0x%02x\n", regname(addr), val);
1323 missing("unknown byte read");
1324 }
1325 return val;
1326 }
1327
1328 static uint16_t eepro100_read2(EEPRO100State * s, uint32_t addr)
1329 {
1330 uint16_t val;
1331 if (addr <= sizeof(s->mem) - sizeof(val)) {
1332 memcpy(&val, &s->mem[addr], sizeof(val));
1333 }
1334
1335 switch (addr) {
1336 case SCBStatus:
1337 case SCBCmd:
1338 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1339 break;
1340 case SCBeeprom:
1341 val = eepro100_read_eeprom(s);
1342 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1343 break;
1344 default:
1345 logout("addr=%s val=0x%04x\n", regname(addr), val);
1346 missing("unknown word read");
1347 }
1348 return val;
1349 }
1350
1351 static uint32_t eepro100_read4(EEPRO100State * s, uint32_t addr)
1352 {
1353 uint32_t val;
1354 if (addr <= sizeof(s->mem) - sizeof(val)) {
1355 memcpy(&val, &s->mem[addr], sizeof(val));
1356 }
1357
1358 switch (addr) {
1359 case SCBStatus:
1360 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1361 break;
1362 case SCBPointer:
1363 #if 0
1364 val = eepro100_read_pointer(s);
1365 #endif
1366 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1367 break;
1368 case SCBPort:
1369 val = eepro100_read_port(s);
1370 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1371 break;
1372 case SCBCtrlMDI:
1373 val = eepro100_read_mdi(s);
1374 break;
1375 default:
1376 logout("addr=%s val=0x%08x\n", regname(addr), val);
1377 missing("unknown longword read");
1378 }
1379 return val;
1380 }
1381
1382 static void eepro100_write1(EEPRO100State * s, uint32_t addr, uint8_t val)
1383 {
1384 /* SCBStatus is readonly. */
1385 if (addr > SCBStatus && addr <= sizeof(s->mem) - sizeof(val)) {
1386 memcpy(&s->mem[addr], &val, sizeof(val));
1387 }
1388
1389 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1390
1391 switch (addr) {
1392 case SCBStatus:
1393 break;
1394 case SCBAck:
1395 eepro100_acknowledge(s);
1396 break;
1397 case SCBCmd:
1398 eepro100_write_command(s, val);
1399 break;
1400 case SCBIntmask:
1401 if (val & BIT(1)) {
1402 eepro100_swi_interrupt(s);
1403 }
1404 eepro100_interrupt(s, 0);
1405 break;
1406 case SCBPort + 3:
1407 case SCBFlow: /* does not exist on 82557 */
1408 case SCBFlow + 1:
1409 case SCBFlow + 2:
1410 case SCBpmdr: /* does not exist on 82557 */
1411 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1412 break;
1413 case SCBeeprom:
1414 eepro100_write_eeprom(s->eeprom, val);
1415 break;
1416 default:
1417 logout("addr=%s val=0x%02x\n", regname(addr), val);
1418 missing("unknown byte write");
1419 }
1420 }
1421
1422 static void eepro100_write2(EEPRO100State * s, uint32_t addr, uint16_t val)
1423 {
1424 /* SCBStatus is readonly. */
1425 if (addr > SCBStatus && addr <= sizeof(s->mem) - sizeof(val)) {
1426 memcpy(&s->mem[addr], &val, sizeof(val));
1427 }
1428
1429 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1430
1431 switch (addr) {
1432 case SCBStatus:
1433 s->mem[SCBAck] = (val >> 8);
1434 eepro100_acknowledge(s);
1435 break;
1436 case SCBCmd:
1437 eepro100_write_command(s, val);
1438 eepro100_write1(s, SCBIntmask, val >> 8);
1439 break;
1440 case SCBeeprom:
1441 eepro100_write_eeprom(s->eeprom, val);
1442 break;
1443 default:
1444 logout("addr=%s val=0x%04x\n", regname(addr), val);
1445 missing("unknown word write");
1446 }
1447 }
1448
1449 static void eepro100_write4(EEPRO100State * s, uint32_t addr, uint32_t val)
1450 {
1451 if (addr <= sizeof(s->mem) - sizeof(val)) {
1452 memcpy(&s->mem[addr], &val, sizeof(val));
1453 }
1454
1455 switch (addr) {
1456 case SCBPointer:
1457 eepro100_write_pointer(s, val);
1458 break;
1459 case SCBPort:
1460 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1461 eepro100_write_port(s, val);
1462 break;
1463 case SCBCtrlMDI:
1464 eepro100_write_mdi(s, val);
1465 break;
1466 default:
1467 logout("addr=%s val=0x%08x\n", regname(addr), val);
1468 missing("unknown longword write");
1469 }
1470 }
1471
1472 /*****************************************************************************
1473 *
1474 * Port mapped I/O.
1475 *
1476 ****************************************************************************/
1477
1478 static uint32_t ioport_read1(void *opaque, uint32_t addr)
1479 {
1480 EEPRO100State *s = opaque;
1481 #if 0
1482 logout("addr=%s\n", regname(addr));
1483 #endif
1484 return eepro100_read1(s, addr - s->region[1]);
1485 }
1486
1487 static uint32_t ioport_read2(void *opaque, uint32_t addr)
1488 {
1489 EEPRO100State *s = opaque;
1490 return eepro100_read2(s, addr - s->region[1]);
1491 }
1492
1493 static uint32_t ioport_read4(void *opaque, uint32_t addr)
1494 {
1495 EEPRO100State *s = opaque;
1496 return eepro100_read4(s, addr - s->region[1]);
1497 }
1498
1499 static void ioport_write1(void *opaque, uint32_t addr, uint32_t val)
1500 {
1501 EEPRO100State *s = opaque;
1502 #if 0
1503 logout("addr=%s val=0x%02x\n", regname(addr), val);
1504 #endif
1505 eepro100_write1(s, addr - s->region[1], val);
1506 }
1507
1508 static void ioport_write2(void *opaque, uint32_t addr, uint32_t val)
1509 {
1510 EEPRO100State *s = opaque;
1511 eepro100_write2(s, addr - s->region[1], val);
1512 }
1513
1514 static void ioport_write4(void *opaque, uint32_t addr, uint32_t val)
1515 {
1516 EEPRO100State *s = opaque;
1517 eepro100_write4(s, addr - s->region[1], val);
1518 }
1519
1520 /***********************************************************/
1521 /* PCI EEPRO100 definitions */
1522
1523 static void pci_map(PCIDevice * pci_dev, int region_num,
1524 pcibus_t addr, pcibus_t size, int type)
1525 {
1526 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1527
1528 TRACE(OTHER, logout("region %d, addr=0x%08"FMT_PCIBUS", "
1529 "size=0x%08"FMT_PCIBUS", type=%d\n",
1530 region_num, addr, size, type));
1531
1532 assert(region_num == 1);
1533 register_ioport_write(addr, size, 1, ioport_write1, s);
1534 register_ioport_read(addr, size, 1, ioport_read1, s);
1535 register_ioport_write(addr, size, 2, ioport_write2, s);
1536 register_ioport_read(addr, size, 2, ioport_read2, s);
1537 register_ioport_write(addr, size, 4, ioport_write4, s);
1538 register_ioport_read(addr, size, 4, ioport_read4, s);
1539
1540 s->region[region_num] = addr;
1541 }
1542
1543 /*****************************************************************************
1544 *
1545 * Memory mapped I/O.
1546 *
1547 ****************************************************************************/
1548
1549 static void pci_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1550 {
1551 EEPRO100State *s = opaque;
1552 #if 0
1553 logout("addr=%s val=0x%02x\n", regname(addr), val);
1554 #endif
1555 eepro100_write1(s, addr, val);
1556 }
1557
1558 static void pci_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1559 {
1560 EEPRO100State *s = opaque;
1561 #if 0
1562 logout("addr=%s val=0x%02x\n", regname(addr), val);
1563 #endif
1564 eepro100_write2(s, addr, val);
1565 }
1566
1567 static void pci_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1568 {
1569 EEPRO100State *s = opaque;
1570 #if 0
1571 logout("addr=%s val=0x%02x\n", regname(addr), val);
1572 #endif
1573 eepro100_write4(s, addr, val);
1574 }
1575
1576 static uint32_t pci_mmio_readb(void *opaque, target_phys_addr_t addr)
1577 {
1578 EEPRO100State *s = opaque;
1579 #if 0
1580 logout("addr=%s\n", regname(addr));
1581 #endif
1582 return eepro100_read1(s, addr);
1583 }
1584
1585 static uint32_t pci_mmio_readw(void *opaque, target_phys_addr_t addr)
1586 {
1587 EEPRO100State *s = opaque;
1588 #if 0
1589 logout("addr=%s\n", regname(addr));
1590 #endif
1591 return eepro100_read2(s, addr);
1592 }
1593
1594 static uint32_t pci_mmio_readl(void *opaque, target_phys_addr_t addr)
1595 {
1596 EEPRO100State *s = opaque;
1597 #if 0
1598 logout("addr=%s\n", regname(addr));
1599 #endif
1600 return eepro100_read4(s, addr);
1601 }
1602
1603 static CPUWriteMemoryFunc * const pci_mmio_write[] = {
1604 pci_mmio_writeb,
1605 pci_mmio_writew,
1606 pci_mmio_writel
1607 };
1608
1609 static CPUReadMemoryFunc * const pci_mmio_read[] = {
1610 pci_mmio_readb,
1611 pci_mmio_readw,
1612 pci_mmio_readl
1613 };
1614
1615 static void pci_mmio_map(PCIDevice * pci_dev, int region_num,
1616 pcibus_t addr, pcibus_t size, int type)
1617 {
1618 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1619
1620 TRACE(OTHER, logout("region %d, addr=0x%08"FMT_PCIBUS", "
1621 "size=0x%08"FMT_PCIBUS", type=%d\n",
1622 region_num, addr, size, type));
1623
1624 if (region_num == 0) {
1625 /* Map control / status registers. */
1626 cpu_register_physical_memory(addr, size, s->mmio_index);
1627 s->region[region_num] = addr;
1628 }
1629 }
1630
1631 static int nic_can_receive(VLANClientState *nc)
1632 {
1633 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1634 TRACE(RXTX, logout("%p\n", s));
1635 return get_ru_state(s) == ru_ready;
1636 #if 0
1637 return !eepro100_buffer_full(s);
1638 #endif
1639 }
1640
1641 static ssize_t nic_receive(VLANClientState *nc, const uint8_t * buf, size_t size)
1642 {
1643 /* TODO:
1644 * - Magic packets should set bit 30 in power management driver register.
1645 * - Interesting packets should set bit 29 in power management driver register.
1646 */
1647 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1648 uint16_t rfd_status = 0xa000;
1649 static const uint8_t broadcast_macaddr[6] =
1650 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1651
1652 /* TODO: check multiple IA bit. */
1653 if (s->configuration[20] & BIT(6)) {
1654 missing("Multiple IA bit");
1655 return -1;
1656 }
1657
1658 if (s->configuration[8] & 0x80) {
1659 /* CSMA is disabled. */
1660 logout("%p received while CSMA is disabled\n", s);
1661 return -1;
1662 } else if (size < 64 && (s->configuration[7] & BIT(0))) {
1663 /* Short frame and configuration byte 7/0 (discard short receive) set:
1664 * Short frame is discarded */
1665 logout("%p received short frame (%zu byte)\n", s, size);
1666 s->statistics.rx_short_frame_errors++;
1667 #if 0
1668 return -1;
1669 #endif
1670 } else if ((size > MAX_ETH_FRAME_SIZE + 4) && !(s->configuration[18] & BIT(3))) {
1671 /* Long frame and configuration byte 18/3 (long receive ok) not set:
1672 * Long frames are discarded. */
1673 logout("%p received long frame (%zu byte), ignored\n", s, size);
1674 return -1;
1675 } else if (memcmp(buf, s->conf.macaddr.a, 6) == 0) { /* !!! */
1676 /* Frame matches individual address. */
1677 /* TODO: check configuration byte 15/4 (ignore U/L). */
1678 TRACE(RXTX, logout("%p received frame for me, len=%zu\n", s, size));
1679 } else if (memcmp(buf, broadcast_macaddr, 6) == 0) {
1680 /* Broadcast frame. */
1681 TRACE(RXTX, logout("%p received broadcast, len=%zu\n", s, size));
1682 rfd_status |= 0x0002;
1683 } else if (buf[0] & 0x01) {
1684 /* Multicast frame. */
1685 TRACE(RXTX, logout("%p received multicast, len=%zu,%s\n", s, size, nic_dump(buf, size)));
1686 if (s->configuration[21] & BIT(3)) {
1687 /* Multicast all bit is set, receive all multicast frames. */
1688 } else {
1689 unsigned mcast_idx = compute_mcast_idx(buf);
1690 assert(mcast_idx < 64);
1691 if (s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))) {
1692 /* Multicast frame is allowed in hash table. */
1693 } else if (s->configuration[15] & BIT(0)) {
1694 /* Promiscuous: receive all. */
1695 rfd_status |= 0x0004;
1696 } else {
1697 TRACE(RXTX, logout("%p multicast ignored\n", s));
1698 return -1;
1699 }
1700 }
1701 /* TODO: Next not for promiscuous mode? */
1702 rfd_status |= 0x0002;
1703 } else if (s->configuration[15] & BIT(0)) {
1704 /* Promiscuous: receive all. */
1705 TRACE(RXTX, logout("%p received frame in promiscuous mode, len=%zu\n", s, size));
1706 rfd_status |= 0x0004;
1707 } else {
1708 TRACE(RXTX, logout("%p received frame, ignored, len=%zu,%s\n", s, size,
1709 nic_dump(buf, size)));
1710 return size;
1711 }
1712
1713 if (get_ru_state(s) != ru_ready) {
1714 /* No resources available. */
1715 logout("no resources, state=%u\n", get_ru_state(s));
1716 /* TODO: RNR interrupt only at first failed frame? */
1717 eepro100_rnr_interrupt(s);
1718 s->statistics.rx_resource_errors++;
1719 #if 0
1720 assert(!"no resources");
1721 #endif
1722 return -1;
1723 }
1724 /* !!! */
1725 eepro100_rx_t rx;
1726 cpu_physical_memory_read(s->ru_base + s->ru_offset, (uint8_t *) & rx,
1727 offsetof(eepro100_rx_t, packet));
1728 uint16_t rfd_command = le16_to_cpu(rx.command);
1729 uint16_t rfd_size = le16_to_cpu(rx.size);
1730
1731 if (size > rfd_size) {
1732 logout("Receive buffer (%" PRId16 " bytes) too small for data "
1733 "(%zu bytes); data truncated\n", rfd_size, size);
1734 size = rfd_size;
1735 }
1736 if (size < 64) {
1737 rfd_status |= 0x0080;
1738 }
1739 TRACE(OTHER, logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n",
1740 rfd_command, rx.link, rx.rx_buf_addr, rfd_size));
1741 stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, status),
1742 rfd_status);
1743 stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, count), size);
1744 /* Early receive interrupt not supported. */
1745 #if 0
1746 eepro100_er_interrupt(s);
1747 #endif
1748 /* Receive CRC Transfer not supported. */
1749 if (s->configuration[18] & BIT(2)) {
1750 missing("Receive CRC Transfer");
1751 return -1;
1752 }
1753 /* TODO: check stripping enable bit. */
1754 #if 0
1755 assert(!(s->configuration[17] & BIT(0)));
1756 #endif
1757 cpu_physical_memory_write(s->ru_base + s->ru_offset +
1758 offsetof(eepro100_rx_t, packet), buf, size);
1759 s->statistics.rx_good_frames++;
1760 eepro100_fr_interrupt(s);
1761 s->ru_offset = le32_to_cpu(rx.link);
1762 if (rfd_command & COMMAND_EL) {
1763 /* EL bit is set, so this was the last frame. */
1764 logout("receive: Running out of frames\n");
1765 set_ru_state(s, ru_suspended);
1766 }
1767 if (rfd_command & COMMAND_S) {
1768 /* S bit is set. */
1769 set_ru_state(s, ru_suspended);
1770 }
1771 return size;
1772 }
1773
1774 static const VMStateDescription vmstate_eepro100 = {
1775 .version_id = 3,
1776 .minimum_version_id = 2,
1777 .minimum_version_id_old = 2,
1778 .fields = (VMStateField []) {
1779 VMSTATE_PCI_DEVICE(dev, EEPRO100State),
1780 VMSTATE_UNUSED(32),
1781 VMSTATE_BUFFER(mult, EEPRO100State),
1782 VMSTATE_BUFFER(mem, EEPRO100State),
1783 /* Save all members of struct between scb_stat and mem. */
1784 VMSTATE_UINT8(scb_stat, EEPRO100State),
1785 VMSTATE_UINT8(int_stat, EEPRO100State),
1786 VMSTATE_UNUSED(3*4),
1787 VMSTATE_MACADDR(conf.macaddr, EEPRO100State),
1788 VMSTATE_UNUSED(19*4),
1789 VMSTATE_UINT16_ARRAY(mdimem, EEPRO100State, 32),
1790 /* The eeprom should be saved and restored by its own routines. */
1791 VMSTATE_UINT32(device, EEPRO100State),
1792 /* TODO check device. */
1793 VMSTATE_UINT32(pointer, EEPRO100State),
1794 VMSTATE_UINT32(cu_base, EEPRO100State),
1795 VMSTATE_UINT32(cu_offset, EEPRO100State),
1796 VMSTATE_UINT32(ru_base, EEPRO100State),
1797 VMSTATE_UINT32(ru_offset, EEPRO100State),
1798 VMSTATE_UINT32(statsaddr, EEPRO100State),
1799 /* Save eepro100_stats_t statistics. */
1800 VMSTATE_UINT32(statistics.tx_good_frames, EEPRO100State),
1801 VMSTATE_UINT32(statistics.tx_max_collisions, EEPRO100State),
1802 VMSTATE_UINT32(statistics.tx_late_collisions, EEPRO100State),
1803 VMSTATE_UINT32(statistics.tx_underruns, EEPRO100State),
1804 VMSTATE_UINT32(statistics.tx_lost_crs, EEPRO100State),
1805 VMSTATE_UINT32(statistics.tx_deferred, EEPRO100State),
1806 VMSTATE_UINT32(statistics.tx_single_collisions, EEPRO100State),
1807 VMSTATE_UINT32(statistics.tx_multiple_collisions, EEPRO100State),
1808 VMSTATE_UINT32(statistics.tx_total_collisions, EEPRO100State),
1809 VMSTATE_UINT32(statistics.rx_good_frames, EEPRO100State),
1810 VMSTATE_UINT32(statistics.rx_crc_errors, EEPRO100State),
1811 VMSTATE_UINT32(statistics.rx_alignment_errors, EEPRO100State),
1812 VMSTATE_UINT32(statistics.rx_resource_errors, EEPRO100State),
1813 VMSTATE_UINT32(statistics.rx_overrun_errors, EEPRO100State),
1814 VMSTATE_UINT32(statistics.rx_cdt_errors, EEPRO100State),
1815 VMSTATE_UINT32(statistics.rx_short_frame_errors, EEPRO100State),
1816 VMSTATE_UINT32(statistics.fc_xmt_pause, EEPRO100State),
1817 VMSTATE_UINT32(statistics.fc_rcv_pause, EEPRO100State),
1818 VMSTATE_UINT32(statistics.fc_rcv_unsupported, EEPRO100State),
1819 VMSTATE_UINT16(statistics.xmt_tco_frames, EEPRO100State),
1820 VMSTATE_UINT16(statistics.rcv_tco_frames, EEPRO100State),
1821 /* Configuration bytes. */
1822 VMSTATE_BUFFER(configuration, EEPRO100State),
1823 VMSTATE_END_OF_LIST()
1824 }
1825 };
1826
1827 static void nic_cleanup(VLANClientState *nc)
1828 {
1829 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1830
1831 s->nic = NULL;
1832 }
1833
1834 static int pci_nic_uninit(PCIDevice *pci_dev)
1835 {
1836 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1837
1838 cpu_unregister_io_memory(s->mmio_index);
1839 vmstate_unregister(s->vmstate, s);
1840 eeprom93xx_free(s->eeprom);
1841 qemu_del_vlan_client(&s->nic->nc);
1842 return 0;
1843 }
1844
1845 static NetClientInfo net_eepro100_info = {
1846 .type = NET_CLIENT_TYPE_NIC,
1847 .size = sizeof(NICState),
1848 .can_receive = nic_can_receive,
1849 .receive = nic_receive,
1850 .cleanup = nic_cleanup,
1851 };
1852
1853 static int e100_nic_init(PCIDevice *pci_dev)
1854 {
1855 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1856 E100PCIDeviceInfo *e100_device = DO_UPCAST(E100PCIDeviceInfo, pci.qdev,
1857 pci_dev->qdev.info);
1858
1859 TRACE(OTHER, logout("\n"));
1860
1861 s->device = e100_device->device;
1862
1863 e100_pci_reset(s, e100_device);
1864
1865 /* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM,
1866 * i82559 and later support 64 or 256 word EEPROM. */
1867 s->eeprom = eeprom93xx_new(EEPROM_SIZE);
1868
1869 /* Handler for memory-mapped I/O */
1870 s->mmio_index =
1871 cpu_register_io_memory(pci_mmio_read, pci_mmio_write, s);
1872
1873 pci_register_bar(&s->dev, 0, PCI_MEM_SIZE,
1874 PCI_BASE_ADDRESS_SPACE_MEMORY |
1875 PCI_BASE_ADDRESS_MEM_PREFETCH, pci_mmio_map);
1876 pci_register_bar(&s->dev, 1, PCI_IO_SIZE, PCI_BASE_ADDRESS_SPACE_IO,
1877 pci_map);
1878 pci_register_bar(&s->dev, 2, PCI_FLASH_SIZE, PCI_BASE_ADDRESS_SPACE_MEMORY,
1879 pci_mmio_map);
1880
1881 qemu_macaddr_default_if_unset(&s->conf.macaddr);
1882 logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6));
1883 assert(s->region[1] == 0);
1884
1885 nic_reset(s);
1886
1887 s->nic = qemu_new_nic(&net_eepro100_info, &s->conf,
1888 pci_dev->qdev.info->name, pci_dev->qdev.id, s);
1889
1890 qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
1891 TRACE(OTHER, logout("%s\n", s->nic->nc.info_str));
1892
1893 qemu_register_reset(nic_reset, s);
1894
1895 s->vmstate = qemu_malloc(sizeof(vmstate_eepro100));
1896 memcpy(s->vmstate, &vmstate_eepro100, sizeof(vmstate_eepro100));
1897 s->vmstate->name = s->nic->nc.model;
1898 vmstate_register(-1, s->vmstate, s);
1899
1900 return 0;
1901 }
1902
1903 static E100PCIDeviceInfo e100_devices[] = {
1904 {
1905 .pci.qdev.name = "i82550",
1906 .pci.qdev.desc = "Intel i82550 Ethernet",
1907 .device = i82550,
1908 /* TODO: check device id. */
1909 .device_id = PCI_DEVICE_ID_INTEL_82551IT,
1910 /* Revision ID: 0x0c, 0x0d, 0x0e. */
1911 .revision = 0x0e,
1912 /* TODO: check size of statistical counters. */
1913 .stats_size = 80,
1914 /* TODO: check extended tcb support. */
1915 .has_extended_tcb_support = true,
1916 .power_management = true,
1917 },{
1918 .pci.qdev.name = "i82551",
1919 .pci.qdev.desc = "Intel i82551 Ethernet",
1920 .device = i82551,
1921 .device_id = PCI_DEVICE_ID_INTEL_82551IT,
1922 /* Revision ID: 0x0f, 0x10. */
1923 .revision = 0x0f,
1924 /* TODO: check size of statistical counters. */
1925 .stats_size = 80,
1926 .has_extended_tcb_support = true,
1927 .power_management = true,
1928 },{
1929 .pci.qdev.name = "i82557a",
1930 .pci.qdev.desc = "Intel i82557A Ethernet",
1931 .device = i82557A,
1932 .device_id = PCI_DEVICE_ID_INTEL_82557,
1933 .revision = 0x01,
1934 .power_management = false,
1935 },{
1936 .pci.qdev.name = "i82557b",
1937 .pci.qdev.desc = "Intel i82557B Ethernet",
1938 .device = i82557B,
1939 .device_id = PCI_DEVICE_ID_INTEL_82557,
1940 .revision = 0x02,
1941 .power_management = false,
1942 },{
1943 .pci.qdev.name = "i82557c",
1944 .pci.qdev.desc = "Intel i82557C Ethernet",
1945 .device = i82557C,
1946 .device_id = PCI_DEVICE_ID_INTEL_82557,
1947 .revision = 0x03,
1948 .power_management = false,
1949 },{
1950 .pci.qdev.name = "i82558a",
1951 .pci.qdev.desc = "Intel i82558A Ethernet",
1952 .device = i82558A,
1953 .device_id = PCI_DEVICE_ID_INTEL_82557,
1954 .revision = 0x04,
1955 .stats_size = 76,
1956 .has_extended_tcb_support = true,
1957 .power_management = true,
1958 },{
1959 .pci.qdev.name = "i82558b",
1960 .pci.qdev.desc = "Intel i82558B Ethernet",
1961 .device = i82558B,
1962 .device_id = PCI_DEVICE_ID_INTEL_82557,
1963 .revision = 0x05,
1964 .stats_size = 76,
1965 .has_extended_tcb_support = true,
1966 .power_management = true,
1967 },{
1968 .pci.qdev.name = "i82559a",
1969 .pci.qdev.desc = "Intel i82559A Ethernet",
1970 .device = i82559A,
1971 .device_id = PCI_DEVICE_ID_INTEL_82557,
1972 .revision = 0x06,
1973 .stats_size = 80,
1974 .has_extended_tcb_support = true,
1975 .power_management = true,
1976 },{
1977 .pci.qdev.name = "i82559b",
1978 .pci.qdev.desc = "Intel i82559B Ethernet",
1979 .device = i82559B,
1980 .device_id = PCI_DEVICE_ID_INTEL_82557,
1981 .revision = 0x07,
1982 .stats_size = 80,
1983 .has_extended_tcb_support = true,
1984 .power_management = true,
1985 },{
1986 .pci.qdev.name = "i82559c",
1987 .pci.qdev.desc = "Intel i82559C Ethernet",
1988 .device = i82559C,
1989 .device_id = PCI_DEVICE_ID_INTEL_82557,
1990 #if 0
1991 .revision = 0x08,
1992 #endif
1993 /* TODO: Windows wants revision id 0x0c. */
1994 .revision = 0x0c,
1995 .stats_size = 80,
1996 .has_extended_tcb_support = true,
1997 .power_management = true,
1998 },{
1999 .pci.qdev.name = "i82559er",
2000 .pci.qdev.desc = "Intel i82559ER Ethernet",
2001 .device = i82559ER,
2002 .device_id = PCI_DEVICE_ID_INTEL_82551IT,
2003 .revision = 0x09,
2004 .stats_size = 80,
2005 .has_extended_tcb_support = true,
2006 .power_management = true,
2007 },{
2008 .pci.qdev.name = "i82562",
2009 .pci.qdev.desc = "Intel i82562 Ethernet",
2010 .device = i82562,
2011 /* TODO: check device id. */
2012 .device_id = PCI_DEVICE_ID_INTEL_82551IT,
2013 /* TODO: wrong revision id. */
2014 .revision = 0x0e,
2015 .stats_size = 80,
2016 .has_extended_tcb_support = true,
2017 .power_management = true,
2018 },{
2019 /* Toshiba Tecra 8200. */
2020 .pci.qdev.name = "i82801",
2021 .pci.qdev.desc = "Intel i82801 Ethernet",
2022 .device = i82801,
2023 .device_id = 0x2449,
2024 .revision = 0x03,
2025 .stats_size = 80,
2026 .has_extended_tcb_support = true,
2027 .power_management = true,
2028 }
2029 };
2030
2031 static Property e100_properties[] = {
2032 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2033 DEFINE_PROP_END_OF_LIST(),
2034 };
2035
2036 static void eepro100_register_devices(void)
2037 {
2038 size_t i;
2039 for (i = 0; i < ARRAY_SIZE(e100_devices); i++) {
2040 PCIDeviceInfo *pci_dev = &e100_devices[i].pci;
2041 switch (e100_devices[i].device_id) {
2042 case PCI_DEVICE_ID_INTEL_82551IT:
2043 pci_dev->romfile = "gpxe-eepro100-80861209.rom";
2044 break;
2045 case PCI_DEVICE_ID_INTEL_82557:
2046 pci_dev->romfile = "gpxe-eepro100-80861229.rom";
2047 break;
2048 case 0x2449:
2049 pci_dev->romfile = "gpxe-eepro100-80862449.rom";
2050 break;
2051 }
2052 pci_dev->init = e100_nic_init;
2053 pci_dev->exit = pci_nic_uninit;
2054 pci_dev->qdev.props = e100_properties;
2055 pci_dev->qdev.size = sizeof(EEPRO100State);
2056 pci_qdev_register(pci_dev);
2057 }
2058 }
2059
2060 device_init(eepro100_register_devices)
QEmu