hw/misc/aspeed_scu.c

   1 /*
   2  * ASPEED System Control Unit
   3  *
   4  * Andrew Jeffery <andrew@aj.id.au>
   5  *
   6  * Copyright 2016 IBM Corp.
   7  *
   8  * This code is licensed under the GPL version 2 or later.  See
   9  * the COPYING file in the top-level directory.
  10  */
  11
  12 #include "qemu/osdep.h"
  13 #include "hw/misc/aspeed_scu.h"
  14 #include "hw/qdev-properties.h"
  15 #include "qapi/error.h"
  16 #include "qapi/visitor.h"
  17 #include "qemu/bitops.h"
  18 #include "qemu/log.h"
  19 #include "crypto/random.h"
  20 #include "trace.h"
  21
  22 #define TO_REG(offset) ((offset) >> 2)
  23
  24 #define PROT_KEY             TO_REG(0x00)
  25 #define SYS_RST_CTRL         TO_REG(0x04)
  26 #define CLK_SEL              TO_REG(0x08)
  27 #define CLK_STOP_CTRL        TO_REG(0x0C)
  28 #define FREQ_CNTR_CTRL       TO_REG(0x10)
  29 #define FREQ_CNTR_EVAL       TO_REG(0x14)
  30 #define IRQ_CTRL             TO_REG(0x18)
  31 #define D2PLL_PARAM          TO_REG(0x1C)
  32 #define MPLL_PARAM           TO_REG(0x20)
  33 #define HPLL_PARAM           TO_REG(0x24)
  34 #define FREQ_CNTR_RANGE      TO_REG(0x28)
  35 #define MISC_CTRL1           TO_REG(0x2C)
  36 #define PCI_CTRL1            TO_REG(0x30)
  37 #define PCI_CTRL2            TO_REG(0x34)
  38 #define PCI_CTRL3            TO_REG(0x38)
  39 #define SYS_RST_STATUS       TO_REG(0x3C)
  40 #define SOC_SCRATCH1         TO_REG(0x40)
  41 #define SOC_SCRATCH2         TO_REG(0x44)
  42 #define MAC_CLK_DELAY        TO_REG(0x48)
  43 #define MISC_CTRL2           TO_REG(0x4C)
  44 #define VGA_SCRATCH1         TO_REG(0x50)
  45 #define VGA_SCRATCH2         TO_REG(0x54)
  46 #define VGA_SCRATCH3         TO_REG(0x58)
  47 #define VGA_SCRATCH4         TO_REG(0x5C)
  48 #define VGA_SCRATCH5         TO_REG(0x60)
  49 #define VGA_SCRATCH6         TO_REG(0x64)
  50 #define VGA_SCRATCH7         TO_REG(0x68)
  51 #define VGA_SCRATCH8         TO_REG(0x6C)
  52 #define HW_STRAP1            TO_REG(0x70)
  53 #define RNG_CTRL             TO_REG(0x74)
  54 #define RNG_DATA             TO_REG(0x78)
  55 #define SILICON_REV          TO_REG(0x7C)
  56 #define PINMUX_CTRL1         TO_REG(0x80)
  57 #define PINMUX_CTRL2         TO_REG(0x84)
  58 #define PINMUX_CTRL3         TO_REG(0x88)
  59 #define PINMUX_CTRL4         TO_REG(0x8C)
  60 #define PINMUX_CTRL5         TO_REG(0x90)
  61 #define PINMUX_CTRL6         TO_REG(0x94)
  62 #define WDT_RST_CTRL         TO_REG(0x9C)
  63 #define PINMUX_CTRL7         TO_REG(0xA0)
  64 #define PINMUX_CTRL8         TO_REG(0xA4)
  65 #define PINMUX_CTRL9         TO_REG(0xA8)
  66 #define WAKEUP_EN            TO_REG(0xC0)
  67 #define WAKEUP_CTRL          TO_REG(0xC4)
  68 #define HW_STRAP2            TO_REG(0xD0)
  69 #define FREE_CNTR4           TO_REG(0xE0)
  70 #define FREE_CNTR4_EXT       TO_REG(0xE4)
  71 #define CPU2_CTRL            TO_REG(0x100)
  72 #define CPU2_BASE_SEG1       TO_REG(0x104)
  73 #define CPU2_BASE_SEG2       TO_REG(0x108)
  74 #define CPU2_BASE_SEG3       TO_REG(0x10C)
  75 #define CPU2_BASE_SEG4       TO_REG(0x110)
  76 #define CPU2_BASE_SEG5       TO_REG(0x114)
  77 #define CPU2_CACHE_CTRL      TO_REG(0x118)
  78 #define UART_HPLL_CLK        TO_REG(0x160)
  79 #define PCIE_CTRL            TO_REG(0x180)
  80 #define BMC_MMIO_CTRL        TO_REG(0x184)
  81 #define RELOC_DECODE_BASE1   TO_REG(0x188)
  82 #define RELOC_DECODE_BASE2   TO_REG(0x18C)
  83 #define MAILBOX_DECODE_BASE  TO_REG(0x190)
  84 #define SRAM_DECODE_BASE1    TO_REG(0x194)
  85 #define SRAM_DECODE_BASE2    TO_REG(0x198)
  86 #define BMC_REV              TO_REG(0x19C)
  87 #define BMC_DEV_ID           TO_REG(0x1A4)
  88
  89 #define SCU_IO_REGION_SIZE 0x1000
  90
  91 static const uint32_t ast2400_a0_resets[ASPEED_SCU_NR_REGS] = {
  92      [SYS_RST_CTRL]    = 0xFFCFFEDCU,
  93      [CLK_SEL]         = 0xF3F40000U,
  94      [CLK_STOP_CTRL]   = 0x19FC3E8BU,
  95      [D2PLL_PARAM]     = 0x00026108U,
  96      [MPLL_PARAM]      = 0x00030291U,
  97      [HPLL_PARAM]      = 0x00000291U,
  98      [MISC_CTRL1]      = 0x00000010U,
  99      [PCI_CTRL1]       = 0x20001A03U,
 100      [PCI_CTRL2]       = 0x20001A03U,
 101      [PCI_CTRL3]       = 0x04000030U,
 102      [SYS_RST_STATUS]  = 0x00000001U,
 103      [SOC_SCRATCH1]    = 0x000000C0U, /* SoC completed DRAM init */
 104      [MISC_CTRL2]      = 0x00000023U,
 105      [RNG_CTRL]        = 0x0000000EU,
 106      [PINMUX_CTRL2]    = 0x0000F000U,
 107      [PINMUX_CTRL3]    = 0x01000000U,
 108      [PINMUX_CTRL4]    = 0x000000FFU,
 109      [PINMUX_CTRL5]    = 0x0000A000U,
 110      [WDT_RST_CTRL]    = 0x003FFFF3U,
 111      [PINMUX_CTRL8]    = 0xFFFF0000U,
 112      [PINMUX_CTRL9]    = 0x000FFFFFU,
 113      [FREE_CNTR4]      = 0x000000FFU,
 114      [FREE_CNTR4_EXT]  = 0x000000FFU,
 115      [CPU2_BASE_SEG1]  = 0x80000000U,
 116      [CPU2_BASE_SEG4]  = 0x1E600000U,
 117      [CPU2_BASE_SEG5]  = 0xC0000000U,
 118      [UART_HPLL_CLK]   = 0x00001903U,
 119      [PCIE_CTRL]       = 0x0000007BU,
 120      [BMC_DEV_ID]      = 0x00002402U
 121 };
 122
 123 /* SCU70 bit 23: 0 24Mhz. bit 11:9: 0b001 AXI:ABH ratio 2:1 */
 124 /* AST2500 revision A1 */
 125
 126 static const uint32_t ast2500_a1_resets[ASPEED_SCU_NR_REGS] = {
 127      [SYS_RST_CTRL]    = 0xFFCFFEDCU,
 128      [CLK_SEL]         = 0xF3F40000U,
 129      [CLK_STOP_CTRL]   = 0x19FC3E8BU,
 130      [D2PLL_PARAM]     = 0x00026108U,
 131      [MPLL_PARAM]      = 0x00030291U,
 132      [HPLL_PARAM]      = 0x93000400U,
 133      [MISC_CTRL1]      = 0x00000010U,
 134      [PCI_CTRL1]       = 0x20001A03U,
 135      [PCI_CTRL2]       = 0x20001A03U,
 136      [PCI_CTRL3]       = 0x04000030U,
 137      [SYS_RST_STATUS]  = 0x00000001U,
 138      [SOC_SCRATCH1]    = 0x000000C0U, /* SoC completed DRAM init */
 139      [MISC_CTRL2]      = 0x00000023U,
 140      [RNG_CTRL]        = 0x0000000EU,
 141      [PINMUX_CTRL2]    = 0x0000F000U,
 142      [PINMUX_CTRL3]    = 0x03000000U,
 143      [PINMUX_CTRL4]    = 0x00000000U,
 144      [PINMUX_CTRL5]    = 0x0000A000U,
 145      [WDT_RST_CTRL]    = 0x023FFFF3U,
 146      [PINMUX_CTRL8]    = 0xFFFF0000U,
 147      [PINMUX_CTRL9]    = 0x000FFFFFU,
 148      [FREE_CNTR4]      = 0x000000FFU,
 149      [FREE_CNTR4_EXT]  = 0x000000FFU,
 150      [CPU2_BASE_SEG1]  = 0x80000000U,
 151      [CPU2_BASE_SEG4]  = 0x1E600000U,
 152      [CPU2_BASE_SEG5]  = 0xC0000000U,
 153      [UART_HPLL_CLK]   = 0x00001903U,
 154      [PCIE_CTRL]       = 0x0000007BU,
 155      [BMC_DEV_ID]      = 0x00002402U
 156 };
 157
 158 static uint32_t aspeed_scu_get_random(void)
 159 {
 160     Error *err = NULL;
 161     uint32_t num;
 162
 163     if (qcrypto_random_bytes((uint8_t *)&num, sizeof(num), &err)) {
 164         error_report_err(err);
 165         exit(1);
 166     }
 167
 168     return num;
 169 }
 170
 171 static uint64_t aspeed_scu_read(void *opaque, hwaddr offset, unsigned size)
 172 {
 173     AspeedSCUState *s = ASPEED_SCU(opaque);
 174     int reg = TO_REG(offset);
 175
 176     if (reg >= ARRAY_SIZE(s->regs)) {
 177         qemu_log_mask(LOG_GUEST_ERROR,
 178                       "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
 179                       __func__, offset);
 180         return 0;
 181     }
 182
 183     switch (reg) {
 184     case RNG_DATA:
 185         /* On hardware, RNG_DATA works regardless of
 186          * the state of the enable bit in RNG_CTRL
 187          */
 188         s->regs[RNG_DATA] = aspeed_scu_get_random();
 189         break;
 190     case WAKEUP_EN:
 191         qemu_log_mask(LOG_GUEST_ERROR,
 192                       "%s: Read of write-only offset 0x%" HWADDR_PRIx "\n",
 193                       __func__, offset);
 194         break;
 195     }
 196
 197     return s->regs[reg];
 198 }
 199
 200 static void aspeed_scu_write(void *opaque, hwaddr offset, uint64_t data,
 201                              unsigned size)
 202 {
 203     AspeedSCUState *s = ASPEED_SCU(opaque);
 204     int reg = TO_REG(offset);
 205
 206     if (reg >= ARRAY_SIZE(s->regs)) {
 207         qemu_log_mask(LOG_GUEST_ERROR,
 208                       "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
 209                       __func__, offset);
 210         return;
 211     }
 212
 213     if (reg > PROT_KEY && reg < CPU2_BASE_SEG1 &&
 214             !s->regs[PROT_KEY]) {
 215         qemu_log_mask(LOG_GUEST_ERROR, "%s: SCU is locked!\n", __func__);
 216         return;
 217     }
 218
 219     trace_aspeed_scu_write(offset, size, data);
 220
 221     switch (reg) {
 222     case PROT_KEY:
 223         s->regs[reg] = (data == ASPEED_SCU_PROT_KEY) ? 1 : 0;
 224         return;
 225
 226     case FREQ_CNTR_EVAL:
 227     case VGA_SCRATCH1 ... VGA_SCRATCH8:
 228     case RNG_DATA:
 229     case SILICON_REV:
 230     case FREE_CNTR4:
 231     case FREE_CNTR4_EXT:
 232         qemu_log_mask(LOG_GUEST_ERROR,
 233                       "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n",
 234                       __func__, offset);
 235         return;
 236     }
 237
 238     s->regs[reg] = data;
 239 }
 240
 241 static const MemoryRegionOps aspeed_scu_ops = {
 242     .read = aspeed_scu_read,
 243     .write = aspeed_scu_write,
 244     .endianness = DEVICE_LITTLE_ENDIAN,
 245     .valid.min_access_size = 4,
 246     .valid.max_access_size = 4,
 247     .valid.unaligned = false,
 248 };
 249
 250 static void aspeed_scu_reset(DeviceState *dev)
 251 {
 252     AspeedSCUState *s = ASPEED_SCU(dev);
 253     const uint32_t *reset;
 254
 255     switch (s->silicon_rev) {
 256     case AST2400_A0_SILICON_REV:
 257     case AST2400_A1_SILICON_REV:
 258         reset = ast2400_a0_resets;
 259         break;
 260     case AST2500_A0_SILICON_REV:
 261     case AST2500_A1_SILICON_REV:
 262         reset = ast2500_a1_resets;
 263         break;
 264     default:
 265         g_assert_not_reached();
 266     }
 267
 268     memcpy(s->regs, reset, sizeof(s->regs));
 269     s->regs[SILICON_REV] = s->silicon_rev;
 270     s->regs[HW_STRAP1] = s->hw_strap1;
 271     s->regs[HW_STRAP2] = s->hw_strap2;
 272     s->regs[PROT_KEY] = s->hw_prot_key;
 273 }
 274
 275 static uint32_t aspeed_silicon_revs[] = {
 276     AST2400_A0_SILICON_REV,
 277     AST2400_A1_SILICON_REV,
 278     AST2500_A0_SILICON_REV,
 279     AST2500_A1_SILICON_REV,
 280 };
 281
 282 bool is_supported_silicon_rev(uint32_t silicon_rev)
 283 {
 284     int i;
 285
 286     for (i = 0; i < ARRAY_SIZE(aspeed_silicon_revs); i++) {
 287         if (silicon_rev == aspeed_silicon_revs[i]) {
 288             return true;
 289         }
 290     }
 291
 292     return false;
 293 }
 294
 295 static void aspeed_scu_realize(DeviceState *dev, Error **errp)
 296 {
 297     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 298     AspeedSCUState *s = ASPEED_SCU(dev);
 299
 300     if (!is_supported_silicon_rev(s->silicon_rev)) {
 301         error_setg(errp, "Unknown silicon revision: 0x%" PRIx32,
 302                 s->silicon_rev);
 303         return;
 304     }
 305
 306     memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_scu_ops, s,
 307                           TYPE_ASPEED_SCU, SCU_IO_REGION_SIZE);
 308
 309     sysbus_init_mmio(sbd, &s->iomem);
 310 }
 311
 312 static const VMStateDescription vmstate_aspeed_scu = {
 313     .name = "aspeed.scu",
 314     .version_id = 1,
 315     .minimum_version_id = 1,
 316     .fields = (VMStateField[]) {
 317         VMSTATE_UINT32_ARRAY(regs, AspeedSCUState, ASPEED_SCU_NR_REGS),
 318         VMSTATE_END_OF_LIST()
 319     }
 320 };
 321
 322 static Property aspeed_scu_properties[] = {
 323     DEFINE_PROP_UINT32("silicon-rev", AspeedSCUState, silicon_rev, 0),
 324     DEFINE_PROP_UINT32("hw-strap1", AspeedSCUState, hw_strap1, 0),
 325     DEFINE_PROP_UINT32("hw-strap2", AspeedSCUState, hw_strap2, 0),
 326     DEFINE_PROP_UINT32("hw-prot-key", AspeedSCUState, hw_prot_key, 0),
 327     DEFINE_PROP_END_OF_LIST(),
 328 };
 329
 330 static void aspeed_scu_class_init(ObjectClass *klass, void *data)
 331 {
 332     DeviceClass *dc = DEVICE_CLASS(klass);
 333     dc->realize = aspeed_scu_realize;
 334     dc->reset = aspeed_scu_reset;
 335     dc->desc = "ASPEED System Control Unit";
 336     dc->vmsd = &vmstate_aspeed_scu;
 337     dc->props = aspeed_scu_properties;
 338 }
 339
 340 static const TypeInfo aspeed_scu_info = {
 341     .name = TYPE_ASPEED_SCU,
 342     .parent = TYPE_SYS_BUS_DEVICE,
 343     .instance_size = sizeof(AspeedSCUState),
 344     .class_init = aspeed_scu_class_init,
 345 };
 346
 347 static void aspeed_scu_register_types(void)
 348 {
 349     type_register_static(&aspeed_scu_info);
 350 }
 351
 352 type_init(aspeed_scu_register_types);