hw/ide/cmd646.c

   1 /*
   2  * QEMU IDE Emulation: PCI cmd646 support.
   3  *
   4  * Copyright (c) 2003 Fabrice Bellard
   5  * Copyright (c) 2006 Openedhand Ltd.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include "qemu/osdep.h"
  26 #include "hw/hw.h"
  27 #include "hw/pci/pci.h"
  28 #include "hw/isa/isa.h"
  29 #include "sysemu/block-backend.h"
  30 #include "sysemu/sysemu.h"
  31 #include "sysemu/dma.h"
  32
  33 #include "hw/ide/pci.h"
  34 #include "trace.h"
  35
  36 /* CMD646 specific */
  37 #define CFR             0x50
  38 #define   CFR_INTR_CH0  0x04
  39 #define CNTRL           0x51
  40 #define   CNTRL_EN_CH0  0x04
  41 #define   CNTRL_EN_CH1  0x08
  42 #define ARTTIM23        0x57
  43 #define    ARTTIM23_INTR_CH1    0x10
  44 #define MRDMODE         0x71
  45 #define   MRDMODE_INTR_CH0      0x04
  46 #define   MRDMODE_INTR_CH1      0x08
  47 #define   MRDMODE_BLK_CH0       0x10
  48 #define   MRDMODE_BLK_CH1       0x20
  49 #define UDIDETCR0       0x73
  50 #define UDIDETCR1       0x7B
  51
  52 static void cmd646_update_irq(PCIDevice *pd);
  53
  54 static uint64_t cmd646_cmd_read(void *opaque, hwaddr addr,
  55                                 unsigned size)
  56 {
  57     CMD646BAR *cmd646bar = opaque;
  58
  59     if (addr != 2 || size != 1) {
  60         return ((uint64_t)1 << (size * 8)) - 1;
  61     }
  62     return ide_status_read(cmd646bar->bus, addr + 2);
  63 }
  64
  65 static void cmd646_cmd_write(void *opaque, hwaddr addr,
  66                              uint64_t data, unsigned size)
  67 {
  68     CMD646BAR *cmd646bar = opaque;
  69
  70     if (addr != 2 || size != 1) {
  71         return;
  72     }
  73     ide_cmd_write(cmd646bar->bus, addr + 2, data);
  74 }
  75
  76 static const MemoryRegionOps cmd646_cmd_ops = {
  77     .read = cmd646_cmd_read,
  78     .write = cmd646_cmd_write,
  79     .endianness = DEVICE_LITTLE_ENDIAN,
  80 };
  81
  82 static uint64_t cmd646_data_read(void *opaque, hwaddr addr,
  83                                  unsigned size)
  84 {
  85     CMD646BAR *cmd646bar = opaque;
  86
  87     if (size == 1) {
  88         return ide_ioport_read(cmd646bar->bus, addr);
  89     } else if (addr == 0) {
  90         if (size == 2) {
  91             return ide_data_readw(cmd646bar->bus, addr);
  92         } else {
  93             return ide_data_readl(cmd646bar->bus, addr);
  94         }
  95     }
  96     return ((uint64_t)1 << (size * 8)) - 1;
  97 }
  98
  99 static void cmd646_data_write(void *opaque, hwaddr addr,
 100                              uint64_t data, unsigned size)
 101 {
 102     CMD646BAR *cmd646bar = opaque;
 103
 104     if (size == 1) {
 105         ide_ioport_write(cmd646bar->bus, addr, data);
 106     } else if (addr == 0) {
 107         if (size == 2) {
 108             ide_data_writew(cmd646bar->bus, addr, data);
 109         } else {
 110             ide_data_writel(cmd646bar->bus, addr, data);
 111         }
 112     }
 113 }
 114
 115 static const MemoryRegionOps cmd646_data_ops = {
 116     .read = cmd646_data_read,
 117     .write = cmd646_data_write,
 118     .endianness = DEVICE_LITTLE_ENDIAN,
 119 };
 120
 121 static void setup_cmd646_bar(PCIIDEState *d, int bus_num)
 122 {
 123     IDEBus *bus = &d->bus[bus_num];
 124     CMD646BAR *bar = &d->cmd646_bar[bus_num];
 125
 126     bar->bus = bus;
 127     bar->pci_dev = d;
 128     memory_region_init_io(&bar->cmd, OBJECT(d), &cmd646_cmd_ops, bar,
 129                           "cmd646-cmd", 4);
 130     memory_region_init_io(&bar->data, OBJECT(d), &cmd646_data_ops, bar,
 131                           "cmd646-data", 8);
 132 }
 133
 134 static void cmd646_update_dma_interrupts(PCIDevice *pd)
 135 {
 136     /* Sync DMA interrupt status from UDMA interrupt status */
 137     if (pd->config[MRDMODE] & MRDMODE_INTR_CH0) {
 138         pd->config[CFR] |= CFR_INTR_CH0;
 139     } else {
 140         pd->config[CFR] &= ~CFR_INTR_CH0;
 141     }
 142
 143     if (pd->config[MRDMODE] & MRDMODE_INTR_CH1) {
 144         pd->config[ARTTIM23] |= ARTTIM23_INTR_CH1;
 145     } else {
 146         pd->config[ARTTIM23] &= ~ARTTIM23_INTR_CH1;
 147     }
 148 }
 149
 150 static void cmd646_update_udma_interrupts(PCIDevice *pd)
 151 {
 152     /* Sync UDMA interrupt status from DMA interrupt status */
 153     if (pd->config[CFR] & CFR_INTR_CH0) {
 154         pd->config[MRDMODE] |= MRDMODE_INTR_CH0;
 155     } else {
 156         pd->config[MRDMODE] &= ~MRDMODE_INTR_CH0;
 157     }
 158
 159     if (pd->config[ARTTIM23] & ARTTIM23_INTR_CH1) {
 160         pd->config[MRDMODE] |= MRDMODE_INTR_CH1;
 161     } else {
 162         pd->config[MRDMODE] &= ~MRDMODE_INTR_CH1;
 163     }
 164 }
 165
 166 static uint64_t bmdma_read(void *opaque, hwaddr addr,
 167                            unsigned size)
 168 {
 169     BMDMAState *bm = opaque;
 170     PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
 171     uint32_t val;
 172
 173     if (size != 1) {
 174         return ((uint64_t)1 << (size * 8)) - 1;
 175     }
 176
 177     switch(addr & 3) {
 178     case 0:
 179         val = bm->cmd;
 180         break;
 181     case 1:
 182         val = pci_dev->config[MRDMODE];
 183         break;
 184     case 2:
 185         val = bm->status;
 186         break;
 187     case 3:
 188         if (bm == &bm->pci_dev->bmdma[0]) {
 189             val = pci_dev->config[UDIDETCR0];
 190         } else {
 191             val = pci_dev->config[UDIDETCR1];
 192         }
 193         break;
 194     default:
 195         val = 0xff;
 196         break;
 197     }
 198
 199     trace_bmdma_read_cmd646(addr, val);
 200     return val;
 201 }
 202
 203 static void bmdma_write(void *opaque, hwaddr addr,
 204                         uint64_t val, unsigned size)
 205 {
 206     BMDMAState *bm = opaque;
 207     PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
 208
 209     if (size != 1) {
 210         return;
 211     }
 212
 213     trace_bmdma_write_cmd646(addr, val);
 214     switch(addr & 3) {
 215     case 0:
 216         bmdma_cmd_writeb(bm, val);
 217         break;
 218     case 1:
 219         pci_dev->config[MRDMODE] =
 220             (pci_dev->config[MRDMODE] & ~0x30) | (val & 0x30);
 221         cmd646_update_dma_interrupts(pci_dev);
 222         cmd646_update_irq(pci_dev);
 223         break;
 224     case 2:
 225         bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
 226         break;
 227     case 3:
 228         if (bm == &bm->pci_dev->bmdma[0]) {
 229             pci_dev->config[UDIDETCR0] = val;
 230         } else {
 231             pci_dev->config[UDIDETCR1] = val;
 232         }
 233         break;
 234     }
 235 }
 236
 237 static const MemoryRegionOps cmd646_bmdma_ops = {
 238     .read = bmdma_read,
 239     .write = bmdma_write,
 240 };
 241
 242 static void bmdma_setup_bar(PCIIDEState *d)
 243 {
 244     BMDMAState *bm;
 245     int i;
 246
 247     memory_region_init(&d->bmdma_bar, OBJECT(d), "cmd646-bmdma", 16);
 248     for(i = 0;i < 2; i++) {
 249         bm = &d->bmdma[i];
 250         memory_region_init_io(&bm->extra_io, OBJECT(d), &cmd646_bmdma_ops, bm,
 251                               "cmd646-bmdma-bus", 4);
 252         memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io);
 253         memory_region_init_io(&bm->addr_ioport, OBJECT(d),
 254                               &bmdma_addr_ioport_ops, bm,
 255                               "cmd646-bmdma-ioport", 4);
 256         memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport);
 257     }
 258 }
 259
 260 static void cmd646_update_irq(PCIDevice *pd)
 261 {
 262     int pci_level;
 263
 264     pci_level = ((pd->config[MRDMODE] & MRDMODE_INTR_CH0) &&
 265                  !(pd->config[MRDMODE] & MRDMODE_BLK_CH0)) ||
 266         ((pd->config[MRDMODE] & MRDMODE_INTR_CH1) &&
 267          !(pd->config[MRDMODE] & MRDMODE_BLK_CH1));
 268     pci_set_irq(pd, pci_level);
 269 }
 270
 271 /* the PCI irq level is the logical OR of the two channels */
 272 static void cmd646_set_irq(void *opaque, int channel, int level)
 273 {
 274     PCIIDEState *d = opaque;
 275     PCIDevice *pd = PCI_DEVICE(d);
 276     int irq_mask;
 277
 278     irq_mask = MRDMODE_INTR_CH0 << channel;
 279     if (level) {
 280         pd->config[MRDMODE] |= irq_mask;
 281     } else {
 282         pd->config[MRDMODE] &= ~irq_mask;
 283     }
 284     cmd646_update_dma_interrupts(pd);
 285     cmd646_update_irq(pd);
 286 }
 287
 288 static void cmd646_reset(void *opaque)
 289 {
 290     PCIIDEState *d = opaque;
 291     unsigned int i;
 292
 293     for (i = 0; i < 2; i++) {
 294         ide_bus_reset(&d->bus[i]);
 295     }
 296 }
 297
 298 static uint32_t cmd646_pci_config_read(PCIDevice *d,
 299                                        uint32_t address, int len)
 300 {
 301     return pci_default_read_config(d, address, len);
 302 }
 303
 304 static void cmd646_pci_config_write(PCIDevice *d, uint32_t addr, uint32_t val,
 305                                     int l)
 306 {
 307     uint32_t i;
 308
 309     pci_default_write_config(d, addr, val, l);
 310
 311     for (i = addr; i < addr + l; i++) {
 312         switch (i) {
 313         case CFR:
 314         case ARTTIM23:
 315             cmd646_update_udma_interrupts(d);
 316             break;
 317         case MRDMODE:
 318             cmd646_update_dma_interrupts(d);
 319             break;
 320         }
 321     }
 322
 323     cmd646_update_irq(d);
 324 }
 325
 326 /* CMD646 PCI IDE controller */
 327 static void pci_cmd646_ide_realize(PCIDevice *dev, Error **errp)
 328 {
 329     PCIIDEState *d = PCI_IDE(dev);
 330     uint8_t *pci_conf = dev->config;
 331     qemu_irq *irq;
 332     int i;
 333
 334     pci_conf[PCI_CLASS_PROG] = 0x8f;
 335
 336     pci_conf[CNTRL] = CNTRL_EN_CH0; // enable IDE0
 337     if (d->secondary) {
 338         /* XXX: if not enabled, really disable the seconday IDE controller */
 339         pci_conf[CNTRL] |= CNTRL_EN_CH1; /* enable IDE1 */
 340     }
 341
 342     /* Set write-to-clear interrupt bits */
 343     dev->wmask[CFR] = 0x0;
 344     dev->w1cmask[CFR] = CFR_INTR_CH0;
 345     dev->wmask[ARTTIM23] = 0x0;
 346     dev->w1cmask[ARTTIM23] = ARTTIM23_INTR_CH1;
 347     dev->wmask[MRDMODE] = 0x0;
 348     dev->w1cmask[MRDMODE] = MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1;
 349
 350     setup_cmd646_bar(d, 0);
 351     setup_cmd646_bar(d, 1);
 352     pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[0].data);
 353     pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[0].cmd);
 354     pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[1].data);
 355     pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[1].cmd);
 356     bmdma_setup_bar(d);
 357     pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);
 358
 359     /* TODO: RST# value should be 0 */
 360     pci_conf[PCI_INTERRUPT_PIN] = 0x01; // interrupt on pin 1
 361
 362     irq = qemu_allocate_irqs(cmd646_set_irq, d, 2);
 363     for (i = 0; i < 2; i++) {
 364         ide_bus_new(&d->bus[i], sizeof(d->bus[i]), DEVICE(dev), i, 2);
 365         ide_init2(&d->bus[i], irq[i]);
 366
 367         bmdma_init(&d->bus[i], &d->bmdma[i], d);
 368         d->bmdma[i].bus = &d->bus[i];
 369         ide_register_restart_cb(&d->bus[i]);
 370     }
 371
 372     vmstate_register(DEVICE(dev), 0, &vmstate_ide_pci, d);
 373     qemu_register_reset(cmd646_reset, d);
 374 }
 375
 376 static void pci_cmd646_ide_exitfn(PCIDevice *dev)
 377 {
 378     PCIIDEState *d = PCI_IDE(dev);
 379     unsigned i;
 380
 381     for (i = 0; i < 2; ++i) {
 382         memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io);
 383         memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport);
 384     }
 385 }
 386
 387 void pci_cmd646_ide_init(PCIBus *bus, DriveInfo **hd_table,
 388                          int secondary_ide_enabled)
 389 {
 390     PCIDevice *dev;
 391
 392     dev = pci_create(bus, -1, "cmd646-ide");
 393     qdev_prop_set_uint32(&dev->qdev, "secondary", secondary_ide_enabled);
 394     qdev_init_nofail(&dev->qdev);
 395
 396     pci_ide_create_devs(dev, hd_table);
 397 }
 398
 399 static Property cmd646_ide_properties[] = {
 400     DEFINE_PROP_UINT32("secondary", PCIIDEState, secondary, 0),
 401     DEFINE_PROP_END_OF_LIST(),
 402 };
 403
 404 static void cmd646_ide_class_init(ObjectClass *klass, void *data)
 405 {
 406     DeviceClass *dc = DEVICE_CLASS(klass);
 407     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 408
 409     k->realize = pci_cmd646_ide_realize;
 410     k->exit = pci_cmd646_ide_exitfn;
 411     k->vendor_id = PCI_VENDOR_ID_CMD;
 412     k->device_id = PCI_DEVICE_ID_CMD_646;
 413     k->revision = 0x07;
 414     k->class_id = PCI_CLASS_STORAGE_IDE;
 415     k->config_read = cmd646_pci_config_read;
 416     k->config_write = cmd646_pci_config_write;
 417     dc->props = cmd646_ide_properties;
 418     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
 419 }
 420
 421 static const TypeInfo cmd646_ide_info = {
 422     .name          = "cmd646-ide",
 423     .parent        = TYPE_PCI_IDE,
 424     .class_init    = cmd646_ide_class_init,
 425 };
 426
 427 static void cmd646_ide_register_types(void)
 428 {
 429     type_register_static(&cmd646_ide_info);
 430 }
 431
 432 type_init(cmd646_ide_register_types)