hw/pc.c

   1 /*
   2  * QEMU PC System Emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pc.h"
  26 #include "apic.h"
  27 #include "fdc.h"
  28 #include "ide.h"
  29 #include "pci.h"
  30 #include "vmware_vga.h"
  31 #include "monitor.h"
  32 #include "fw_cfg.h"
  33 #include "hpet_emul.h"
  34 #include "smbios.h"
  35 #include "loader.h"
  36 #include "elf.h"
  37 #include "multiboot.h"
  38 #include "mc146818rtc.h"
  39 #include "msix.h"
  40 #include "sysbus.h"
  41 #include "sysemu.h"
  42 #include "blockdev.h"
  43 #include "ui/qemu-spice.h"
  44
  45 /* output Bochs bios info messages */
  46 //#define DEBUG_BIOS
  47
  48 /* debug PC/ISA interrupts */
  49 //#define DEBUG_IRQ
  50
  51 #ifdef DEBUG_IRQ
  52 #define DPRINTF(fmt, ...)                                       \
  53     do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
  54 #else
  55 #define DPRINTF(fmt, ...)
  56 #endif
  57
  58 #define BIOS_FILENAME "bios.bin"
  59
  60 #define PC_MAX_BIOS_SIZE (4 * 1024 * 1024)
  61
  62 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables.  */
  63 #define ACPI_DATA_SIZE       0x10000
  64 #define BIOS_CFG_IOPORT 0x510
  65 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
  66 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
  67 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
  68 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
  69 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
  70
  71 #define MSI_ADDR_BASE 0xfee00000
  72
  73 #define E820_NR_ENTRIES         16
  74
  75 struct e820_entry {
  76     uint64_t address;
  77     uint64_t length;
  78     uint32_t type;
  79 } __attribute((__packed__, __aligned__(4)));
  80
  81 struct e820_table {
  82     uint32_t count;
  83     struct e820_entry entry[E820_NR_ENTRIES];
  84 } __attribute((__packed__, __aligned__(4)));
  85
  86 static struct e820_table e820_table;
  87
  88 void isa_irq_handler(void *opaque, int n, int level)
  89 {
  90     IsaIrqState *isa = (IsaIrqState *)opaque;
  91
  92     DPRINTF("isa_irqs: %s irq %d\n", level? "raise" : "lower", n);
  93     if (n < 16) {
  94         qemu_set_irq(isa->i8259[n], level);
  95     }
  96     if (isa->ioapic)
  97         qemu_set_irq(isa->ioapic[n], level);
  98 };
  99
 100 static void ioport80_write(void *opaque, uint32_t addr, uint32_t data)
 101 {
 102 }
 103
 104 /* MSDOS compatibility mode FPU exception support */
 105 static qemu_irq ferr_irq;
 106
 107 void pc_register_ferr_irq(qemu_irq irq)
 108 {
 109     ferr_irq = irq;
 110 }
 111
 112 /* XXX: add IGNNE support */
 113 void cpu_set_ferr(CPUX86State *s)
 114 {
 115     qemu_irq_raise(ferr_irq);
 116 }
 117
 118 static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data)
 119 {
 120     qemu_irq_lower(ferr_irq);
 121 }
 122
 123 /* TSC handling */
 124 uint64_t cpu_get_tsc(CPUX86State *env)
 125 {
 126     return cpu_get_ticks();
 127 }
 128
 129 /* SMM support */
 130
 131 static cpu_set_smm_t smm_set;
 132 static void *smm_arg;
 133
 134 void cpu_smm_register(cpu_set_smm_t callback, void *arg)
 135 {
 136     assert(smm_set == NULL);
 137     assert(smm_arg == NULL);
 138     smm_set = callback;
 139     smm_arg = arg;
 140 }
 141
 142 void cpu_smm_update(CPUState *env)
 143 {
 144     if (smm_set && smm_arg && env == first_cpu)
 145         smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg);
 146 }
 147
 148
 149 /* IRQ handling */
 150 int cpu_get_pic_interrupt(CPUState *env)
 151 {
 152     int intno;
 153
 154     intno = apic_get_interrupt(env->apic_state);
 155     if (intno >= 0) {
 156         /* set irq request if a PIC irq is still pending */
 157         /* XXX: improve that */
 158         pic_update_irq(isa_pic);
 159         return intno;
 160     }
 161     /* read the irq from the PIC */
 162     if (!apic_accept_pic_intr(env->apic_state)) {
 163         return -1;
 164     }
 165
 166     intno = pic_read_irq(isa_pic);
 167     return intno;
 168 }
 169
 170 static void pic_irq_request(void *opaque, int irq, int level)
 171 {
 172     CPUState *env = first_cpu;
 173
 174     DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
 175     if (env->apic_state) {
 176         while (env) {
 177             if (apic_accept_pic_intr(env->apic_state)) {
 178                 apic_deliver_pic_intr(env->apic_state, level);
 179             }
 180             env = env->next_cpu;
 181         }
 182     } else {
 183         if (level)
 184             cpu_interrupt(env, CPU_INTERRUPT_HARD);
 185         else
 186             cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 187     }
 188 }
 189
 190 /* PC cmos mappings */
 191
 192 #define REG_EQUIPMENT_BYTE          0x14
 193
 194 static int cmos_get_fd_drive_type(int fd0)
 195 {
 196     int val;
 197
 198     switch (fd0) {
 199     case 0:
 200         /* 1.44 Mb 3"5 drive */
 201         val = 4;
 202         break;
 203     case 1:
 204         /* 2.88 Mb 3"5 drive */
 205         val = 5;
 206         break;
 207     case 2:
 208         /* 1.2 Mb 5"5 drive */
 209         val = 2;
 210         break;
 211     default:
 212         val = 0;
 213         break;
 214     }
 215     return val;
 216 }
 217
 218 static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd,
 219                          ISADevice *s)
 220 {
 221     int cylinders, heads, sectors;
 222     bdrv_get_geometry_hint(hd, &cylinders, &heads, &sectors);
 223     rtc_set_memory(s, type_ofs, 47);
 224     rtc_set_memory(s, info_ofs, cylinders);
 225     rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
 226     rtc_set_memory(s, info_ofs + 2, heads);
 227     rtc_set_memory(s, info_ofs + 3, 0xff);
 228     rtc_set_memory(s, info_ofs + 4, 0xff);
 229     rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
 230     rtc_set_memory(s, info_ofs + 6, cylinders);
 231     rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
 232     rtc_set_memory(s, info_ofs + 8, sectors);
 233 }
 234
 235 /* convert boot_device letter to something recognizable by the bios */
 236 static int boot_device2nibble(char boot_device)
 237 {
 238     switch(boot_device) {
 239     case 'a':
 240     case 'b':
 241         return 0x01; /* floppy boot */
 242     case 'c':
 243         return 0x02; /* hard drive boot */
 244     case 'd':
 245         return 0x03; /* CD-ROM boot */
 246     case 'n':
 247         return 0x04; /* Network boot */
 248     }
 249     return 0;
 250 }
 251
 252 static int set_boot_dev(ISADevice *s, const char *boot_device, int fd_bootchk)
 253 {
 254 #define PC_MAX_BOOT_DEVICES 3
 255     int nbds, bds[3] = { 0, };
 256     int i;
 257
 258     nbds = strlen(boot_device);
 259     if (nbds > PC_MAX_BOOT_DEVICES) {
 260         error_report("Too many boot devices for PC");
 261         return(1);
 262     }
 263     for (i = 0; i < nbds; i++) {
 264         bds[i] = boot_device2nibble(boot_device[i]);
 265         if (bds[i] == 0) {
 266             error_report("Invalid boot device for PC: '%c'",
 267                          boot_device[i]);
 268             return(1);
 269         }
 270     }
 271     rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
 272     rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
 273     return(0);
 274 }
 275
 276 static int pc_boot_set(void *opaque, const char *boot_device)
 277 {
 278     return set_boot_dev(opaque, boot_device, 0);
 279 }
 280
 281 typedef struct pc_cmos_init_late_arg {
 282     ISADevice *rtc_state;
 283     BusState *idebus0, *idebus1;
 284 } pc_cmos_init_late_arg;
 285
 286 static void pc_cmos_init_late(void *opaque)
 287 {
 288     pc_cmos_init_late_arg *arg = opaque;
 289     ISADevice *s = arg->rtc_state;
 290     int val;
 291     BlockDriverState *hd_table[4];
 292     int i;
 293
 294     ide_get_bs(hd_table, arg->idebus0);
 295     ide_get_bs(hd_table + 2, arg->idebus1);
 296
 297     rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0));
 298     if (hd_table[0])
 299         cmos_init_hd(0x19, 0x1b, hd_table[0], s);
 300     if (hd_table[1])
 301         cmos_init_hd(0x1a, 0x24, hd_table[1], s);
 302
 303     val = 0;
 304     for (i = 0; i < 4; i++) {
 305         if (hd_table[i]) {
 306             int cylinders, heads, sectors, translation;
 307             /* NOTE: bdrv_get_geometry_hint() returns the physical
 308                 geometry.  It is always such that: 1 <= sects <= 63, 1
 309                 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
 310                 geometry can be different if a translation is done. */
 311             translation = bdrv_get_translation_hint(hd_table[i]);
 312             if (translation == BIOS_ATA_TRANSLATION_AUTO) {
 313                 bdrv_get_geometry_hint(hd_table[i], &cylinders, &heads, &sectors);
 314                 if (cylinders <= 1024 && heads <= 16 && sectors <= 63) {
 315                     /* No translation. */
 316                     translation = 0;
 317                 } else {
 318                     /* LBA translation. */
 319                     translation = 1;
 320                 }
 321             } else {
 322                 translation--;
 323             }
 324             val |= translation << (i * 2);
 325         }
 326     }
 327     rtc_set_memory(s, 0x39, val);
 328
 329     qemu_unregister_reset(pc_cmos_init_late, opaque);
 330 }
 331
 332 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
 333                   const char *boot_device,
 334                   BusState *idebus0, BusState *idebus1,
 335                   FDCtrl *floppy_controller, ISADevice *s)
 336 {
 337     int val;
 338     int fd0, fd1, nb;
 339     static pc_cmos_init_late_arg arg;
 340
 341     /* various important CMOS locations needed by PC/Bochs bios */
 342
 343     /* memory size */
 344     val = 640; /* base memory in K */
 345     rtc_set_memory(s, 0x15, val);
 346     rtc_set_memory(s, 0x16, val >> 8);
 347
 348     val = (ram_size / 1024) - 1024;
 349     if (val > 65535)
 350         val = 65535;
 351     rtc_set_memory(s, 0x17, val);
 352     rtc_set_memory(s, 0x18, val >> 8);
 353     rtc_set_memory(s, 0x30, val);
 354     rtc_set_memory(s, 0x31, val >> 8);
 355
 356     if (above_4g_mem_size) {
 357         rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16);
 358         rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24);
 359         rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32);
 360     }
 361
 362     if (ram_size > (16 * 1024 * 1024))
 363         val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
 364     else
 365         val = 0;
 366     if (val > 65535)
 367         val = 65535;
 368     rtc_set_memory(s, 0x34, val);
 369     rtc_set_memory(s, 0x35, val >> 8);
 370
 371     /* set the number of CPU */
 372     rtc_set_memory(s, 0x5f, smp_cpus - 1);
 373
 374     /* set boot devices, and disable floppy signature check if requested */
 375     if (set_boot_dev(s, boot_device, fd_bootchk)) {
 376         exit(1);
 377     }
 378
 379     /* floppy type */
 380
 381     fd0 = fdctrl_get_drive_type(floppy_controller, 0);
 382     fd1 = fdctrl_get_drive_type(floppy_controller, 1);
 383
 384     val = (cmos_get_fd_drive_type(fd0) << 4) | cmos_get_fd_drive_type(fd1);
 385     rtc_set_memory(s, 0x10, val);
 386
 387     val = 0;
 388     nb = 0;
 389     if (fd0 < 3)
 390         nb++;
 391     if (fd1 < 3)
 392         nb++;
 393     switch (nb) {
 394     case 0:
 395         break;
 396     case 1:
 397         val |= 0x01; /* 1 drive, ready for boot */
 398         break;
 399     case 2:
 400         val |= 0x41; /* 2 drives, ready for boot */
 401         break;
 402     }
 403     val |= 0x02; /* FPU is there */
 404     val |= 0x04; /* PS/2 mouse installed */
 405     rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
 406
 407     /* hard drives */
 408     arg.rtc_state = s;
 409     arg.idebus0 = idebus0;
 410     arg.idebus1 = idebus1;
 411     qemu_register_reset(pc_cmos_init_late, &arg);
 412 }
 413
 414 static void handle_a20_line_change(void *opaque, int irq, int level)
 415 {
 416     CPUState *cpu = opaque;
 417
 418     /* XXX: send to all CPUs ? */
 419     cpu_x86_set_a20(cpu, level);
 420 }
 421
 422 /***********************************************************/
 423 /* Bochs BIOS debug ports */
 424
 425 static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val)
 426 {
 427     static const char shutdown_str[8] = "Shutdown";
 428     static int shutdown_index = 0;
 429
 430     switch(addr) {
 431         /* Bochs BIOS messages */
 432     case 0x400:
 433     case 0x401:
 434         /* used to be panic, now unused */
 435         break;
 436     case 0x402:
 437     case 0x403:
 438 #ifdef DEBUG_BIOS
 439         fprintf(stderr, "%c", val);
 440 #endif
 441         break;
 442     case 0x8900:
 443         /* same as Bochs power off */
 444         if (val == shutdown_str[shutdown_index]) {
 445             shutdown_index++;
 446             if (shutdown_index == 8) {
 447                 shutdown_index = 0;
 448                 qemu_system_shutdown_request();
 449             }
 450         } else {
 451             shutdown_index = 0;
 452         }
 453         break;
 454
 455         /* LGPL'ed VGA BIOS messages */
 456     case 0x501:
 457     case 0x502:
 458         fprintf(stderr, "VGA BIOS panic, line %d\n", val);
 459         exit(1);
 460     case 0x500:
 461     case 0x503:
 462 #ifdef DEBUG_BIOS
 463         fprintf(stderr, "%c", val);
 464 #endif
 465         break;
 466     }
 467 }
 468
 469 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
 470 {
 471     int index = le32_to_cpu(e820_table.count);
 472     struct e820_entry *entry;
 473
 474     if (index >= E820_NR_ENTRIES)
 475         return -EBUSY;
 476     entry = &e820_table.entry[index++];
 477
 478     entry->address = cpu_to_le64(address);
 479     entry->length = cpu_to_le64(length);
 480     entry->type = cpu_to_le32(type);
 481
 482     e820_table.count = cpu_to_le32(index);
 483     return index;
 484 }
 485
 486 static void *bochs_bios_init(void)
 487 {
 488     void *fw_cfg;
 489     uint8_t *smbios_table;
 490     size_t smbios_len;
 491     uint64_t *numa_fw_cfg;
 492     int i, j;
 493
 494     register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL);
 495     register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL);
 496     register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL);
 497     register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL);
 498     register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL);
 499
 500     register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL);
 501     register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL);
 502     register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL);
 503     register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL);
 504
 505     fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
 506
 507     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 508     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 509     fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables,
 510                      acpi_tables_len);
 511     fw_cfg_add_bytes(fw_cfg, FW_CFG_IRQ0_OVERRIDE, &irq0override, 1);
 512
 513     smbios_table = smbios_get_table(&smbios_len);
 514     if (smbios_table)
 515         fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
 516                          smbios_table, smbios_len);
 517     fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, (uint8_t *)&e820_table,
 518                      sizeof(struct e820_table));
 519
 520     fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, (uint8_t *)&hpet_cfg,
 521                      sizeof(struct hpet_fw_config));
 522     /* allocate memory for the NUMA channel: one (64bit) word for the number
 523      * of nodes, one word for each VCPU->node and one word for each node to
 524      * hold the amount of memory.
 525      */
 526     numa_fw_cfg = qemu_mallocz((1 + smp_cpus + nb_numa_nodes) * 8);
 527     numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
 528     for (i = 0; i < smp_cpus; i++) {
 529         for (j = 0; j < nb_numa_nodes; j++) {
 530             if (node_cpumask[j] & (1 << i)) {
 531                 numa_fw_cfg[i + 1] = cpu_to_le64(j);
 532                 break;
 533             }
 534         }
 535     }
 536     for (i = 0; i < nb_numa_nodes; i++) {
 537         numa_fw_cfg[smp_cpus + 1 + i] = cpu_to_le64(node_mem[i]);
 538     }
 539     fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg,
 540                      (1 + smp_cpus + nb_numa_nodes) * 8);
 541
 542     return fw_cfg;
 543 }
 544
 545 static long get_file_size(FILE *f)
 546 {
 547     long where, size;
 548
 549     /* XXX: on Unix systems, using fstat() probably makes more sense */
 550
 551     where = ftell(f);
 552     fseek(f, 0, SEEK_END);
 553     size = ftell(f);
 554     fseek(f, where, SEEK_SET);
 555
 556     return size;
 557 }
 558
 559 static void load_linux(void *fw_cfg,
 560                        const char *kernel_filename,
 561                        const char *initrd_filename,
 562                        const char *kernel_cmdline,
 563                        target_phys_addr_t max_ram_size)
 564 {
 565     uint16_t protocol;
 566     int setup_size, kernel_size, initrd_size = 0, cmdline_size;
 567     uint32_t initrd_max;
 568     uint8_t header[8192], *setup, *kernel, *initrd_data;
 569     target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
 570     FILE *f;
 571     char *vmode;
 572
 573     /* Align to 16 bytes as a paranoia measure */
 574     cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
 575
 576     /* load the kernel header */
 577     f = fopen(kernel_filename, "rb");
 578     if (!f || !(kernel_size = get_file_size(f)) ||
 579         fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
 580         MIN(ARRAY_SIZE(header), kernel_size)) {
 581         fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
 582                 kernel_filename, strerror(errno));
 583         exit(1);
 584     }
 585
 586     /* kernel protocol version */
 587 #if 0
 588     fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
 589 #endif
 590     if (ldl_p(header+0x202) == 0x53726448)
 591         protocol = lduw_p(header+0x206);
 592     else {
 593         /* This looks like a multiboot kernel. If it is, let's stop
 594            treating it like a Linux kernel. */
 595         if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
 596                            kernel_cmdline, kernel_size, header))
 597             return;
 598         protocol = 0;
 599     }
 600
 601     if (protocol < 0x200 || !(header[0x211] & 0x01)) {
 602         /* Low kernel */
 603         real_addr    = 0x90000;
 604         cmdline_addr = 0x9a000 - cmdline_size;
 605         prot_addr    = 0x10000;
 606     } else if (protocol < 0x202) {
 607         /* High but ancient kernel */
 608         real_addr    = 0x90000;
 609         cmdline_addr = 0x9a000 - cmdline_size;
 610         prot_addr    = 0x100000;
 611     } else {
 612         /* High and recent kernel */
 613         real_addr    = 0x10000;
 614         cmdline_addr = 0x20000;
 615         prot_addr    = 0x100000;
 616     }
 617
 618 #if 0
 619     fprintf(stderr,
 620             "qemu: real_addr     = 0x" TARGET_FMT_plx "\n"
 621             "qemu: cmdline_addr  = 0x" TARGET_FMT_plx "\n"
 622             "qemu: prot_addr     = 0x" TARGET_FMT_plx "\n",
 623             real_addr,
 624             cmdline_addr,
 625             prot_addr);
 626 #endif
 627
 628     /* highest address for loading the initrd */
 629     if (protocol >= 0x203)
 630         initrd_max = ldl_p(header+0x22c);
 631     else
 632         initrd_max = 0x37ffffff;
 633
 634     if (initrd_max >= max_ram_size-ACPI_DATA_SIZE)
 635         initrd_max = max_ram_size-ACPI_DATA_SIZE-1;
 636
 637     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
 638     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
 639     fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
 640                      (uint8_t*)strdup(kernel_cmdline),
 641                      strlen(kernel_cmdline)+1);
 642
 643     if (protocol >= 0x202) {
 644         stl_p(header+0x228, cmdline_addr);
 645     } else {
 646         stw_p(header+0x20, 0xA33F);
 647         stw_p(header+0x22, cmdline_addr-real_addr);
 648     }
 649
 650     /* handle vga= parameter */
 651     vmode = strstr(kernel_cmdline, "vga=");
 652     if (vmode) {
 653         unsigned int video_mode;
 654         /* skip "vga=" */
 655         vmode += 4;
 656         if (!strncmp(vmode, "normal", 6)) {
 657             video_mode = 0xffff;
 658         } else if (!strncmp(vmode, "ext", 3)) {
 659             video_mode = 0xfffe;
 660         } else if (!strncmp(vmode, "ask", 3)) {
 661             video_mode = 0xfffd;
 662         } else {
 663             video_mode = strtol(vmode, NULL, 0);
 664         }
 665         stw_p(header+0x1fa, video_mode);
 666     }
 667
 668     /* loader type */
 669     /* High nybble = B reserved for Qemu; low nybble is revision number.
 670        If this code is substantially changed, you may want to consider
 671        incrementing the revision. */
 672     if (protocol >= 0x200)
 673         header[0x210] = 0xB0;
 674
 675     /* heap */
 676     if (protocol >= 0x201) {
 677         header[0x211] |= 0x80;  /* CAN_USE_HEAP */
 678         stw_p(header+0x224, cmdline_addr-real_addr-0x200);
 679     }
 680
 681     /* load initrd */
 682     if (initrd_filename) {
 683         if (protocol < 0x200) {
 684             fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
 685             exit(1);
 686         }
 687
 688         initrd_size = get_image_size(initrd_filename);
 689         if (initrd_size < 0) {
 690             fprintf(stderr, "qemu: error reading initrd %s\n",
 691                     initrd_filename);
 692             exit(1);
 693         }
 694
 695         initrd_addr = (initrd_max-initrd_size) & ~4095;
 696
 697         initrd_data = qemu_malloc(initrd_size);
 698         load_image(initrd_filename, initrd_data);
 699
 700         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
 701         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 702         fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
 703
 704         stl_p(header+0x218, initrd_addr);
 705         stl_p(header+0x21c, initrd_size);
 706     }
 707
 708     /* load kernel and setup */
 709     setup_size = header[0x1f1];
 710     if (setup_size == 0)
 711         setup_size = 4;
 712     setup_size = (setup_size+1)*512;
 713     kernel_size -= setup_size;
 714
 715     setup  = qemu_malloc(setup_size);
 716     kernel = qemu_malloc(kernel_size);
 717     fseek(f, 0, SEEK_SET);
 718     if (fread(setup, 1, setup_size, f) != setup_size) {
 719         fprintf(stderr, "fread() failed\n");
 720         exit(1);
 721     }
 722     if (fread(kernel, 1, kernel_size, f) != kernel_size) {
 723         fprintf(stderr, "fread() failed\n");
 724         exit(1);
 725     }
 726     fclose(f);
 727     memcpy(setup, header, MIN(sizeof(header), setup_size));
 728
 729     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
 730     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 731     fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
 732
 733     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
 734     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
 735     fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
 736
 737     option_rom[nb_option_roms].name = "linuxboot.bin";
 738     option_rom[nb_option_roms].bootindex = 0;
 739     nb_option_roms++;
 740 }
 741
 742 #define NE2000_NB_MAX 6
 743
 744 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
 745                                               0x280, 0x380 };
 746 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
 747
 748 static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
 749 static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
 750
 751 void pc_audio_init (PCIBus *pci_bus, qemu_irq *pic)
 752 {
 753     struct soundhw *c;
 754
 755     for (c = soundhw; c->name; ++c) {
 756         if (c->enabled) {
 757             if (c->isa) {
 758                 c->init.init_isa(pic);
 759             } else {
 760                 if (pci_bus) {
 761                     c->init.init_pci(pci_bus);
 762                 }
 763             }
 764         }
 765     }
 766 }
 767
 768 void pc_init_ne2k_isa(NICInfo *nd)
 769 {
 770     static int nb_ne2k = 0;
 771
 772     if (nb_ne2k == NE2000_NB_MAX)
 773         return;
 774     isa_ne2000_init(ne2000_io[nb_ne2k],
 775                     ne2000_irq[nb_ne2k], nd);
 776     nb_ne2k++;
 777 }
 778
 779 int cpu_is_bsp(CPUState *env)
 780 {
 781     /* We hard-wire the BSP to the first CPU. */
 782     return env->cpu_index == 0;
 783 }
 784
 785 DeviceState *cpu_get_current_apic(void)
 786 {
 787     if (cpu_single_env) {
 788         return cpu_single_env->apic_state;
 789     } else {
 790         return NULL;
 791     }
 792 }
 793
 794 static DeviceState *apic_init(void *env, uint8_t apic_id)
 795 {
 796     DeviceState *dev;
 797     SysBusDevice *d;
 798     static int apic_mapped;
 799
 800     dev = qdev_create(NULL, "apic");
 801     qdev_prop_set_uint8(dev, "id", apic_id);
 802     qdev_prop_set_ptr(dev, "cpu_env", env);
 803     qdev_init_nofail(dev);
 804     d = sysbus_from_qdev(dev);
 805
 806     /* XXX: mapping more APICs at the same memory location */
 807     if (apic_mapped == 0) {
 808         /* NOTE: the APIC is directly connected to the CPU - it is not
 809            on the global memory bus. */
 810         /* XXX: what if the base changes? */
 811         sysbus_mmio_map(d, 0, MSI_ADDR_BASE);
 812         apic_mapped = 1;
 813     }
 814
 815     msix_supported = 1;
 816
 817     return dev;
 818 }
 819
 820 /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
 821    BIOS will read it and start S3 resume at POST Entry */
 822 void pc_cmos_set_s3_resume(void *opaque, int irq, int level)
 823 {
 824     ISADevice *s = opaque;
 825
 826     if (level) {
 827         rtc_set_memory(s, 0xF, 0xFE);
 828     }
 829 }
 830
 831 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
 832 {
 833     CPUState *s = opaque;
 834
 835     if (level) {
 836         cpu_interrupt(s, CPU_INTERRUPT_SMI);
 837     }
 838 }
 839
 840 static void pc_cpu_reset(void *opaque)
 841 {
 842     CPUState *env = opaque;
 843
 844     cpu_reset(env);
 845     env->halted = !cpu_is_bsp(env);
 846 }
 847
 848 static CPUState *pc_new_cpu(const char *cpu_model)
 849 {
 850     CPUState *env;
 851
 852     env = cpu_init(cpu_model);
 853     if (!env) {
 854         fprintf(stderr, "Unable to find x86 CPU definition\n");
 855         exit(1);
 856     }
 857     if ((env->cpuid_features & CPUID_APIC) || smp_cpus > 1) {
 858         env->cpuid_apic_id = env->cpu_index;
 859         env->apic_state = apic_init(env, env->cpuid_apic_id);
 860     }
 861     qemu_register_reset(pc_cpu_reset, env);
 862     pc_cpu_reset(env);
 863     return env;
 864 }
 865
 866 void pc_cpus_init(const char *cpu_model)
 867 {
 868     int i;
 869
 870     /* init CPUs */
 871     if (cpu_model == NULL) {
 872 #ifdef TARGET_X86_64
 873         cpu_model = "qemu64";
 874 #else
 875         cpu_model = "qemu32";
 876 #endif
 877     }
 878
 879     for(i = 0; i < smp_cpus; i++) {
 880         pc_new_cpu(cpu_model);
 881     }
 882 }
 883
 884 void pc_memory_init(ram_addr_t ram_size,
 885                     const char *kernel_filename,
 886                     const char *kernel_cmdline,
 887                     const char *initrd_filename,
 888                     ram_addr_t *below_4g_mem_size_p,
 889                     ram_addr_t *above_4g_mem_size_p)
 890 {
 891     char *filename;
 892     int ret, linux_boot, i;
 893     ram_addr_t ram_addr, bios_offset, option_rom_offset;
 894     ram_addr_t below_4g_mem_size, above_4g_mem_size = 0;
 895     int bios_size, isa_bios_size;
 896     void *fw_cfg;
 897
 898     if (ram_size >= 0xe0000000 ) {
 899         above_4g_mem_size = ram_size - 0xe0000000;
 900         below_4g_mem_size = 0xe0000000;
 901     } else {
 902         below_4g_mem_size = ram_size;
 903     }
 904     *above_4g_mem_size_p = above_4g_mem_size;
 905     *below_4g_mem_size_p = below_4g_mem_size;
 906
 907 #if TARGET_PHYS_ADDR_BITS == 32
 908     if (above_4g_mem_size > 0) {
 909         hw_error("To much RAM for 32-bit physical address");
 910     }
 911 #endif
 912     linux_boot = (kernel_filename != NULL);
 913
 914     /* allocate RAM */
 915     ram_addr = qemu_ram_alloc(NULL, "pc.ram",
 916                               below_4g_mem_size + above_4g_mem_size);
 917     cpu_register_physical_memory(0, 0xa0000, ram_addr);
 918     cpu_register_physical_memory(0x100000,
 919                  below_4g_mem_size - 0x100000,
 920                  ram_addr + 0x100000);
 921 #if TARGET_PHYS_ADDR_BITS > 32
 922     if (above_4g_mem_size > 0) {
 923         cpu_register_physical_memory(0x100000000ULL, above_4g_mem_size,
 924                                      ram_addr + below_4g_mem_size);
 925     }
 926 #endif
 927
 928     /* BIOS load */
 929     if (bios_name == NULL)
 930         bios_name = BIOS_FILENAME;
 931     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 932     if (filename) {
 933         bios_size = get_image_size(filename);
 934     } else {
 935         bios_size = -1;
 936     }
 937     if (bios_size <= 0 ||
 938         (bios_size % 65536) != 0) {
 939         goto bios_error;
 940     }
 941     bios_offset = qemu_ram_alloc(NULL, "pc.bios", bios_size);
 942     ret = rom_add_file_fixed(bios_name, (uint32_t)(-bios_size), -1);
 943     if (ret != 0) {
 944     bios_error:
 945         fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", bios_name);
 946         exit(1);
 947     }
 948     if (filename) {
 949         qemu_free(filename);
 950     }
 951     /* map the last 128KB of the BIOS in ISA space */
 952     isa_bios_size = bios_size;
 953     if (isa_bios_size > (128 * 1024))
 954         isa_bios_size = 128 * 1024;
 955     cpu_register_physical_memory(0x100000 - isa_bios_size,
 956                                  isa_bios_size,
 957                                  (bios_offset + bios_size - isa_bios_size) | IO_MEM_ROM);
 958
 959     option_rom_offset = qemu_ram_alloc(NULL, "pc.rom", PC_ROM_SIZE);
 960     cpu_register_physical_memory(PC_ROM_MIN_VGA, PC_ROM_SIZE, option_rom_offset);
 961
 962     /* map all the bios at the top of memory */
 963     cpu_register_physical_memory((uint32_t)(-bios_size),
 964                                  bios_size, bios_offset | IO_MEM_ROM);
 965
 966     fw_cfg = bochs_bios_init();
 967     rom_set_fw(fw_cfg);
 968
 969     if (linux_boot) {
 970         load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size);
 971     }
 972
 973     for (i = 0; i < nb_option_roms; i++) {
 974         rom_add_option(option_rom[i].name, option_rom[i].bootindex);
 975     }
 976 }
 977
 978 qemu_irq *pc_allocate_cpu_irq(void)
 979 {
 980     return qemu_allocate_irqs(pic_irq_request, NULL, 1);
 981 }
 982
 983 void pc_vga_init(PCIBus *pci_bus)
 984 {
 985     if (cirrus_vga_enabled) {
 986         if (pci_bus) {
 987             pci_cirrus_vga_init(pci_bus);
 988         } else {
 989             isa_cirrus_vga_init();
 990         }
 991     } else if (vmsvga_enabled) {
 992         if (pci_bus)
 993             pci_vmsvga_init(pci_bus);
 994         else
 995             fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);
 996 #ifdef CONFIG_SPICE
 997     } else if (qxl_enabled) {
 998         if (pci_bus)
 999             pci_create_simple(pci_bus, -1, "qxl-vga");
1000         else
1001             fprintf(stderr, "%s: qxl: no PCI bus\n", __FUNCTION__);
1002 #endif
1003     } else if (std_vga_enabled) {
1004         if (pci_bus) {
1005             pci_vga_init(pci_bus);
1006         } else {
1007             isa_vga_init();
1008         }
1009     }
1010 }
1011
1012 static void cpu_request_exit(void *opaque, int irq, int level)
1013 {
1014     CPUState *env = cpu_single_env;
1015
1016     if (env && level) {
1017         cpu_exit(env);
1018     }
1019 }
1020
1021 void pc_basic_device_init(qemu_irq *isa_irq,
1022                           FDCtrl **floppy_controller,
1023                           ISADevice **rtc_state)
1024 {
1025     int i;
1026     DriveInfo *fd[MAX_FD];
1027     PITState *pit;
1028     qemu_irq rtc_irq = NULL;
1029     qemu_irq *a20_line;
1030     ISADevice *i8042;
1031     qemu_irq *cpu_exit_irq;
1032
1033     register_ioport_write(0x80, 1, 1, ioport80_write, NULL);
1034
1035     register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL);
1036
1037     if (!no_hpet) {
1038         DeviceState *hpet = sysbus_create_simple("hpet", HPET_BASE, NULL);
1039
1040         for (i = 0; i < 24; i++) {
1041             sysbus_connect_irq(sysbus_from_qdev(hpet), i, isa_irq[i]);
1042         }
1043         rtc_irq = qdev_get_gpio_in(hpet, 0);
1044     }
1045     *rtc_state = rtc_init(2000, rtc_irq);
1046
1047     qemu_register_boot_set(pc_boot_set, *rtc_state);
1048
1049     pit = pit_init(0x40, isa_reserve_irq(0));
1050     pcspk_init(pit);
1051
1052     for(i = 0; i < MAX_SERIAL_PORTS; i++) {
1053         if (serial_hds[i]) {
1054             serial_isa_init(i, serial_hds[i]);
1055         }
1056     }
1057
1058     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
1059         if (parallel_hds[i]) {
1060             parallel_init(i, parallel_hds[i]);
1061         }
1062     }
1063
1064     a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 1);
1065     i8042 = isa_create_simple("i8042");
1066     i8042_setup_a20_line(i8042, a20_line);
1067     vmmouse_init(i8042);
1068
1069     cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
1070     DMA_init(0, cpu_exit_irq);
1071
1072     for(i = 0; i < MAX_FD; i++) {
1073         fd[i] = drive_get(IF_FLOPPY, 0, i);
1074     }
1075     *floppy_controller = fdctrl_init_isa(fd);
1076 }
1077
1078 void pc_pci_device_init(PCIBus *pci_bus)
1079 {
1080     int max_bus;
1081     int bus;
1082
1083     max_bus = drive_get_max_bus(IF_SCSI);
1084     for (bus = 0; bus <= max_bus; bus++) {
1085         pci_create_simple(pci_bus, -1, "lsi53c895a");
1086     }
1087 }