target-s390x/mmu_helper.c

   1 /*
   2  * S390x MMU related functions
   3  *
   4  * Copyright (c) 2011 Alexander Graf
   5  * Copyright (c) 2015 Thomas Huth, IBM Corporation
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include "qemu/error-report.h"
  19 #include "exec/address-spaces.h"
  20 #include "sysemu/kvm.h"
  21 #include "cpu.h"
  22
  23 /* #define DEBUG_S390 */
  24 /* #define DEBUG_S390_PTE */
  25 /* #define DEBUG_S390_STDOUT */
  26
  27 #ifdef DEBUG_S390
  28 #ifdef DEBUG_S390_STDOUT
  29 #define DPRINTF(fmt, ...) \
  30     do { fprintf(stderr, fmt, ## __VA_ARGS__); \
  31          qemu_log(fmt, ##__VA_ARGS__); } while (0)
  32 #else
  33 #define DPRINTF(fmt, ...) \
  34     do { qemu_log(fmt, ## __VA_ARGS__); } while (0)
  35 #endif
  36 #else
  37 #define DPRINTF(fmt, ...) \
  38     do { } while (0)
  39 #endif
  40
  41 #ifdef DEBUG_S390_PTE
  42 #define PTE_DPRINTF DPRINTF
  43 #else
  44 #define PTE_DPRINTF(fmt, ...) \
  45     do { } while (0)
  46 #endif
  47
  48 /* Fetch/store bits in the translation exception code: */
  49 #define FS_READ  0x800
  50 #define FS_WRITE 0x400
  51
  52 static void trigger_access_exception(CPUS390XState *env, uint32_t type,
  53                                      uint32_t ilen, uint64_t tec)
  54 {
  55     S390CPU *cpu = s390_env_get_cpu(env);
  56
  57     if (kvm_enabled()) {
  58         kvm_s390_access_exception(cpu, type, tec);
  59     } else {
  60         CPUState *cs = CPU(cpu);
  61         stq_phys(cs->as, env->psa + offsetof(LowCore, trans_exc_code), tec);
  62         trigger_pgm_exception(env, type, ilen);
  63     }
  64 }
  65
  66 static void trigger_prot_fault(CPUS390XState *env, target_ulong vaddr,
  67                                uint64_t asc, int rw, bool exc)
  68 {
  69     uint64_t tec;
  70
  71     tec = vaddr | (rw == MMU_DATA_STORE ? FS_WRITE : FS_READ) | 4 | asc >> 46;
  72
  73     DPRINTF("%s: trans_exc_code=%016" PRIx64 "\n", __func__, tec);
  74
  75     if (!exc) {
  76         return;
  77     }
  78
  79     trigger_access_exception(env, PGM_PROTECTION, ILEN_LATER_INC, tec);
  80 }
  81
  82 static void trigger_page_fault(CPUS390XState *env, target_ulong vaddr,
  83                                uint32_t type, uint64_t asc, int rw, bool exc)
  84 {
  85     int ilen = ILEN_LATER;
  86     uint64_t tec;
  87
  88     tec = vaddr | (rw == MMU_DATA_STORE ? FS_WRITE : FS_READ) | asc >> 46;
  89
  90     DPRINTF("%s: vaddr=%016" PRIx64 " bits=%d\n", __func__, vaddr, bits);
  91
  92     if (!exc) {
  93         return;
  94     }
  95
  96     /* Code accesses have an undefined ilc.  */
  97     if (rw == MMU_INST_FETCH) {
  98         ilen = 2;
  99     }
 100
 101     trigger_access_exception(env, type, ilen, tec);
 102 }
 103
 104 /**
 105  * Translate real address to absolute (= physical)
 106  * address by taking care of the prefix mapping.
 107  */
 108 static target_ulong mmu_real2abs(CPUS390XState *env, target_ulong raddr)
 109 {
 110     if (raddr < 0x2000) {
 111         return raddr + env->psa;    /* Map the lowcore. */
 112     } else if (raddr >= env->psa && raddr < env->psa + 0x2000) {
 113         return raddr - env->psa;    /* Map the 0 page. */
 114     }
 115     return raddr;
 116 }
 117
 118 /* Decode page table entry (normal 4KB page) */
 119 static int mmu_translate_pte(CPUS390XState *env, target_ulong vaddr,
 120                              uint64_t asc, uint64_t pt_entry,
 121                              target_ulong *raddr, int *flags, int rw, bool exc)
 122 {
 123     if (pt_entry & _PAGE_INVALID) {
 124         DPRINTF("%s: PTE=0x%" PRIx64 " invalid\n", __func__, pt_entry);
 125         trigger_page_fault(env, vaddr, PGM_PAGE_TRANS, asc, rw, exc);
 126         return -1;
 127     }
 128     if (pt_entry & _PAGE_RES0) {
 129         trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw, exc);
 130         return -1;
 131     }
 132     if (pt_entry & _PAGE_RO) {
 133         *flags &= ~PAGE_WRITE;
 134     }
 135
 136     *raddr = pt_entry & _ASCE_ORIGIN;
 137
 138     PTE_DPRINTF("%s: PTE=0x%" PRIx64 "\n", __func__, pt_entry);
 139
 140     return 0;
 141 }
 142
 143 #define VADDR_PX    0xff000         /* Page index bits */
 144
 145 /* Decode segment table entry */
 146 static int mmu_translate_segment(CPUS390XState *env, target_ulong vaddr,
 147                                  uint64_t asc, uint64_t st_entry,
 148                                  target_ulong *raddr, int *flags, int rw,
 149                                  bool exc)
 150 {
 151     CPUState *cs = CPU(s390_env_get_cpu(env));
 152     uint64_t origin, offs, pt_entry;
 153
 154     if (st_entry & _SEGMENT_ENTRY_RO) {
 155         *flags &= ~PAGE_WRITE;
 156     }
 157
 158     if ((st_entry & _SEGMENT_ENTRY_FC) && (env->cregs[0] & CR0_EDAT)) {
 159         /* Decode EDAT1 segment frame absolute address (1MB page) */
 160         *raddr = (st_entry & 0xfffffffffff00000ULL) | (vaddr & 0xfffff);
 161         PTE_DPRINTF("%s: SEG=0x%" PRIx64 "\n", __func__, st_entry);
 162         return 0;
 163     }
 164
 165     /* Look up 4KB page entry */
 166     origin = st_entry & _SEGMENT_ENTRY_ORIGIN;
 167     offs  = (vaddr & VADDR_PX) >> 9;
 168     pt_entry = ldq_phys(cs->as, origin + offs);
 169     PTE_DPRINTF("%s: 0x%" PRIx64 " + 0x%" PRIx64 " => 0x%016" PRIx64 "\n",
 170                 __func__, origin, offs, pt_entry);
 171     return mmu_translate_pte(env, vaddr, asc, pt_entry, raddr, flags, rw, exc);
 172 }
 173
 174 /* Decode region table entries */
 175 static int mmu_translate_region(CPUS390XState *env, target_ulong vaddr,
 176                                 uint64_t asc, uint64_t entry, int level,
 177                                 target_ulong *raddr, int *flags, int rw,
 178                                 bool exc)
 179 {
 180     CPUState *cs = CPU(s390_env_get_cpu(env));
 181     uint64_t origin, offs, new_entry;
 182     const int pchks[4] = {
 183         PGM_SEGMENT_TRANS, PGM_REG_THIRD_TRANS,
 184         PGM_REG_SEC_TRANS, PGM_REG_FIRST_TRANS
 185     };
 186
 187     PTE_DPRINTF("%s: 0x%" PRIx64 "\n", __func__, entry);
 188
 189     origin = entry & _REGION_ENTRY_ORIGIN;
 190     offs = (vaddr >> (17 + 11 * level / 4)) & 0x3ff8;
 191
 192     new_entry = ldq_phys(cs->as, origin + offs);
 193     PTE_DPRINTF("%s: 0x%" PRIx64 " + 0x%" PRIx64 " => 0x%016" PRIx64 "\n",
 194                 __func__, origin, offs, new_entry);
 195
 196     if ((new_entry & _REGION_ENTRY_INV) != 0) {
 197         DPRINTF("%s: invalid region\n", __func__);
 198         trigger_page_fault(env, vaddr, pchks[level / 4], asc, rw, exc);
 199         return -1;
 200     }
 201
 202     if ((new_entry & _REGION_ENTRY_TYPE_MASK) != level) {
 203         trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw, exc);
 204         return -1;
 205     }
 206
 207     if (level == _ASCE_TYPE_SEGMENT) {
 208         return mmu_translate_segment(env, vaddr, asc, new_entry, raddr, flags,
 209                                      rw, exc);
 210     }
 211
 212     /* Check region table offset and length */
 213     offs = (vaddr >> (28 + 11 * (level - 4) / 4)) & 3;
 214     if (offs < ((new_entry & _REGION_ENTRY_TF) >> 6)
 215         || offs > (new_entry & _REGION_ENTRY_LENGTH)) {
 216         DPRINTF("%s: invalid offset or len (%lx)\n", __func__, new_entry);
 217         trigger_page_fault(env, vaddr, pchks[level / 4 - 1], asc, rw, exc);
 218         return -1;
 219     }
 220
 221     if ((env->cregs[0] & CR0_EDAT) && (new_entry & _REGION_ENTRY_RO)) {
 222         *flags &= ~PAGE_WRITE;
 223     }
 224
 225     /* yet another region */
 226     return mmu_translate_region(env, vaddr, asc, new_entry, level - 4,
 227                                 raddr, flags, rw, exc);
 228 }
 229
 230 static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr,
 231                               uint64_t asc, uint64_t asce, target_ulong *raddr,
 232                               int *flags, int rw, bool exc)
 233 {
 234     int level;
 235     int r;
 236
 237     if (asce & _ASCE_REAL_SPACE) {
 238         /* direct mapping */
 239         *raddr = vaddr;
 240         return 0;
 241     }
 242
 243     level = asce & _ASCE_TYPE_MASK;
 244     switch (level) {
 245     case _ASCE_TYPE_REGION1:
 246         if ((vaddr >> 62) > (asce & _ASCE_TABLE_LENGTH)) {
 247             trigger_page_fault(env, vaddr, PGM_REG_FIRST_TRANS, asc, rw, exc);
 248             return -1;
 249         }
 250         break;
 251     case _ASCE_TYPE_REGION2:
 252         if (vaddr & 0xffe0000000000000ULL) {
 253             DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
 254                     " 0xffe0000000000000ULL\n", __func__, vaddr);
 255             trigger_page_fault(env, vaddr, PGM_ASCE_TYPE, asc, rw, exc);
 256             return -1;
 257         }
 258         if ((vaddr >> 51 & 3) > (asce & _ASCE_TABLE_LENGTH)) {
 259             trigger_page_fault(env, vaddr, PGM_REG_SEC_TRANS, asc, rw, exc);
 260             return -1;
 261         }
 262         break;
 263     case _ASCE_TYPE_REGION3:
 264         if (vaddr & 0xfffffc0000000000ULL) {
 265             DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
 266                     " 0xfffffc0000000000ULL\n", __func__, vaddr);
 267             trigger_page_fault(env, vaddr, PGM_ASCE_TYPE, asc, rw, exc);
 268             return -1;
 269         }
 270         if ((vaddr >> 40 & 3) > (asce & _ASCE_TABLE_LENGTH)) {
 271             trigger_page_fault(env, vaddr, PGM_REG_THIRD_TRANS, asc, rw, exc);
 272             return -1;
 273         }
 274         break;
 275     case _ASCE_TYPE_SEGMENT:
 276         if (vaddr & 0xffffffff80000000ULL) {
 277             DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
 278                     " 0xffffffff80000000ULL\n", __func__, vaddr);
 279             trigger_page_fault(env, vaddr, PGM_ASCE_TYPE, asc, rw, exc);
 280             return -1;
 281         }
 282         if ((vaddr >> 29 & 3) > (asce & _ASCE_TABLE_LENGTH)) {
 283             trigger_page_fault(env, vaddr, PGM_SEGMENT_TRANS, asc, rw, exc);
 284             return -1;
 285         }
 286         break;
 287     }
 288
 289     r = mmu_translate_region(env, vaddr, asc, asce, level, raddr, flags, rw,
 290                              exc);
 291     if (rw == MMU_DATA_STORE && !(*flags & PAGE_WRITE)) {
 292         trigger_prot_fault(env, vaddr, asc, rw, exc);
 293         return -1;
 294     }
 295
 296     return r;
 297 }
 298
 299 /**
 300  * Translate a virtual (logical) address into a physical (absolute) address.
 301  * @param vaddr  the virtual address
 302  * @param rw     0 = read, 1 = write, 2 = code fetch
 303  * @param asc    address space control (one of the PSW_ASC_* modes)
 304  * @param raddr  the translated address is stored to this pointer
 305  * @param flags  the PAGE_READ/WRITE/EXEC flags are stored to this pointer
 306  * @param exc    true = inject a program check if a fault occurred
 307  * @return       0 if the translation was successful, -1 if a fault occurred
 308  */
 309 int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
 310                   target_ulong *raddr, int *flags, bool exc)
 311 {
 312     int r = -1;
 313     uint8_t *sk;
 314
 315     *flags = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 316     vaddr &= TARGET_PAGE_MASK;
 317
 318     if (!(env->psw.mask & PSW_MASK_DAT)) {
 319         *raddr = vaddr;
 320         r = 0;
 321         goto out;
 322     }
 323
 324     switch (asc) {
 325     case PSW_ASC_PRIMARY:
 326         PTE_DPRINTF("%s: asc=primary\n", __func__);
 327         r = mmu_translate_asce(env, vaddr, asc, env->cregs[1], raddr, flags,
 328                                rw, exc);
 329         break;
 330     case PSW_ASC_HOME:
 331         PTE_DPRINTF("%s: asc=home\n", __func__);
 332         r = mmu_translate_asce(env, vaddr, asc, env->cregs[13], raddr, flags,
 333                                rw, exc);
 334         break;
 335     case PSW_ASC_SECONDARY:
 336         PTE_DPRINTF("%s: asc=secondary\n", __func__);
 337         /*
 338          * Instruction: Primary
 339          * Data: Secondary
 340          */
 341         if (rw == MMU_INST_FETCH) {
 342             r = mmu_translate_asce(env, vaddr, PSW_ASC_PRIMARY, env->cregs[1],
 343                                    raddr, flags, rw, exc);
 344             *flags &= ~(PAGE_READ | PAGE_WRITE);
 345         } else {
 346             r = mmu_translate_asce(env, vaddr, PSW_ASC_SECONDARY, env->cregs[7],
 347                                    raddr, flags, rw, exc);
 348             *flags &= ~(PAGE_EXEC);
 349         }
 350         break;
 351     case PSW_ASC_ACCREG:
 352     default:
 353         hw_error("guest switched to unknown asc mode\n");
 354         break;
 355     }
 356
 357  out:
 358     /* Convert real address -> absolute address */
 359     *raddr = mmu_real2abs(env, *raddr);
 360
 361     if (*raddr < ram_size) {
 362         sk = &env->storage_keys[*raddr / TARGET_PAGE_SIZE];
 363         if (*flags & PAGE_READ) {
 364             *sk |= SK_R;
 365         }
 366
 367         if (*flags & PAGE_WRITE) {
 368             *sk |= SK_C;
 369         }
 370     }
 371
 372     return r;
 373 }
 374
 375 /**
 376  * lowprot_enabled: Check whether low-address protection is enabled
 377  */
 378 static bool lowprot_enabled(const CPUS390XState *env)
 379 {
 380     if (!(env->cregs[0] & CR0_LOWPROT)) {
 381         return false;
 382     }
 383     if (!(env->psw.mask & PSW_MASK_DAT)) {
 384         return true;
 385     }
 386
 387     /* Check the private-space control bit */
 388     switch (env->psw.mask & PSW_MASK_ASC) {
 389     case PSW_ASC_PRIMARY:
 390         return !(env->cregs[1] & _ASCE_PRIVATE_SPACE);
 391     case PSW_ASC_SECONDARY:
 392         return !(env->cregs[7] & _ASCE_PRIVATE_SPACE);
 393     case PSW_ASC_HOME:
 394         return !(env->cregs[13] & _ASCE_PRIVATE_SPACE);
 395     default:
 396         /* We don't support access register mode */
 397         error_report("unsupported addressing mode");
 398         exit(1);
 399     }
 400 }
 401
 402 /**
 403  * translate_pages: Translate a set of consecutive logical page addresses
 404  * to absolute addresses
 405  */
 406 static int translate_pages(S390CPU *cpu, vaddr addr, int nr_pages,
 407                            target_ulong *pages, bool is_write)
 408 {
 409     bool lowprot = is_write && lowprot_enabled(&cpu->env);
 410     uint64_t asc = cpu->env.psw.mask & PSW_MASK_ASC;
 411     CPUS390XState *env = &cpu->env;
 412     int ret, i, pflags;
 413
 414     for (i = 0; i < nr_pages; i++) {
 415         /* Low-address protection? */
 416         if (lowprot && (addr < 512 || (addr >= 4096 && addr < 4096 + 512))) {
 417             trigger_access_exception(env, PGM_PROTECTION, ILEN_LATER_INC, 0);
 418             return -EACCES;
 419         }
 420         ret = mmu_translate(env, addr, is_write, asc, &pages[i], &pflags, true);
 421         if (ret) {
 422             return ret;
 423         }
 424         if (!address_space_access_valid(&address_space_memory, pages[i],
 425                                         TARGET_PAGE_SIZE, is_write)) {
 426             program_interrupt(env, PGM_ADDRESSING, 0);
 427             return -EFAULT;
 428         }
 429         addr += TARGET_PAGE_SIZE;
 430     }
 431
 432     return 0;
 433 }
 434
 435 /**
 436  * s390_cpu_virt_mem_rw:
 437  * @laddr:     the logical start address
 438  * @ar:        the access register number
 439  * @hostbuf:   buffer in host memory. NULL = do only checks w/o copying
 440  * @len:       length that should be transferred
 441  * @is_write:  true = write, false = read
 442  * Returns:    0 on success, non-zero if an exception occurred
 443  *
 444  * Copy from/to guest memory using logical addresses. Note that we inject a
 445  * program interrupt in case there is an error while accessing the memory.
 446  */
 447 int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf,
 448                          int len, bool is_write)
 449 {
 450     int currlen, nr_pages, i;
 451     target_ulong *pages;
 452     int ret;
 453
 454     if (kvm_enabled()) {
 455         ret = kvm_s390_mem_op(cpu, laddr, ar, hostbuf, len, is_write);
 456         if (ret >= 0) {
 457             return ret;
 458         }
 459     }
 460
 461     nr_pages = (((laddr & ~TARGET_PAGE_MASK) + len - 1) >> TARGET_PAGE_BITS)
 462                + 1;
 463     pages = g_malloc(nr_pages * sizeof(*pages));
 464
 465     ret = translate_pages(cpu, laddr, nr_pages, pages, is_write);
 466     if (ret == 0 && hostbuf != NULL) {
 467         /* Copy data by stepping through the area page by page */
 468         for (i = 0; i < nr_pages; i++) {
 469             currlen = MIN(len, TARGET_PAGE_SIZE - (laddr % TARGET_PAGE_SIZE));
 470             cpu_physical_memory_rw(pages[i] | (laddr & ~TARGET_PAGE_MASK),
 471                                    hostbuf, currlen, is_write);
 472             laddr += currlen;
 473             hostbuf += currlen;
 474             len -= currlen;
 475         }
 476     }
 477
 478     g_free(pages);
 479     return ret;
 480 }