target-i386/kvm.c

   1 /*
   2  * QEMU KVM support
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  * Copyright IBM, Corp. 2008
   6  *
   7  * Authors:
   8  *  Anthony Liguori   <aliguori@us.ibm.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11  * See the COPYING file in the top-level directory.
  12  *
  13  */
  14
  15 #include <sys/types.h>
  16 #include <sys/ioctl.h>
  17 #include <sys/mman.h>
  18 #include <sys/utsname.h>
  19
  20 #include <linux/kvm.h>
  21
  22 #include "qemu-common.h"
  23 #include "sysemu.h"
  24 #include "kvm.h"
  25 #include "cpu.h"
  26 #include "gdbstub.h"
  27 #include "host-utils.h"
  28 #include "hw/pc.h"
  29 #include "hw/apic.h"
  30 #include "ioport.h"
  31
  32 #ifdef CONFIG_KVM_PARA
  33 #include <linux/kvm_para.h>
  34 #endif
  35 //
  36 //#define DEBUG_KVM
  37
  38 #ifdef DEBUG_KVM
  39 #define DPRINTF(fmt, ...) \
  40     do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
  41 #else
  42 #define DPRINTF(fmt, ...) \
  43     do { } while (0)
  44 #endif
  45
  46 #define MSR_KVM_WALL_CLOCK  0x11
  47 #define MSR_KVM_SYSTEM_TIME 0x12
  48
  49 #ifndef BUS_MCEERR_AR
  50 #define BUS_MCEERR_AR 4
  51 #endif
  52 #ifndef BUS_MCEERR_AO
  53 #define BUS_MCEERR_AO 5
  54 #endif
  55
  56 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
  57     KVM_CAP_INFO(SET_TSS_ADDR),
  58     KVM_CAP_INFO(EXT_CPUID),
  59     KVM_CAP_INFO(MP_STATE),
  60     KVM_CAP_LAST_INFO
  61 };
  62
  63 static bool has_msr_star;
  64 static bool has_msr_hsave_pa;
  65 #if defined(CONFIG_KVM_PARA) && defined(KVM_CAP_ASYNC_PF)
  66 static bool has_msr_async_pf_en;
  67 #endif
  68 static int lm_capable_kernel;
  69
  70 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
  71 {
  72     struct kvm_cpuid2 *cpuid;
  73     int r, size;
  74
  75     size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
  76     cpuid = (struct kvm_cpuid2 *)qemu_mallocz(size);
  77     cpuid->nent = max;
  78     r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
  79     if (r == 0 && cpuid->nent >= max) {
  80         r = -E2BIG;
  81     }
  82     if (r < 0) {
  83         if (r == -E2BIG) {
  84             qemu_free(cpuid);
  85             return NULL;
  86         } else {
  87             fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
  88                     strerror(-r));
  89             exit(1);
  90         }
  91     }
  92     return cpuid;
  93 }
  94
  95 #ifdef CONFIG_KVM_PARA
  96 struct kvm_para_features {
  97     int cap;
  98     int feature;
  99 } para_features[] = {
 100     { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
 101     { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
 102     { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
 103 #ifdef KVM_CAP_ASYNC_PF
 104     { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
 105 #endif
 106     { -1, -1 }
 107 };
 108
 109 static int get_para_features(CPUState *env)
 110 {
 111     int i, features = 0;
 112
 113     for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) {
 114         if (kvm_check_extension(env->kvm_state, para_features[i].cap)) {
 115             features |= (1 << para_features[i].feature);
 116         }
 117     }
 118
 119     return features;
 120 }
 121 #endif
 122
 123
 124 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function,
 125                                       uint32_t index, int reg)
 126 {
 127     struct kvm_cpuid2 *cpuid;
 128     int i, max;
 129     uint32_t ret = 0;
 130     uint32_t cpuid_1_edx;
 131 #ifdef CONFIG_KVM_PARA
 132     int has_kvm_features = 0;
 133 #endif
 134
 135     max = 1;
 136     while ((cpuid = try_get_cpuid(env->kvm_state, max)) == NULL) {
 137         max *= 2;
 138     }
 139
 140     for (i = 0; i < cpuid->nent; ++i) {
 141         if (cpuid->entries[i].function == function &&
 142             cpuid->entries[i].index == index) {
 143 #ifdef CONFIG_KVM_PARA
 144             if (cpuid->entries[i].function == KVM_CPUID_FEATURES) {
 145                 has_kvm_features = 1;
 146             }
 147 #endif
 148             switch (reg) {
 149             case R_EAX:
 150                 ret = cpuid->entries[i].eax;
 151                 break;
 152             case R_EBX:
 153                 ret = cpuid->entries[i].ebx;
 154                 break;
 155             case R_ECX:
 156                 ret = cpuid->entries[i].ecx;
 157                 break;
 158             case R_EDX:
 159                 ret = cpuid->entries[i].edx;
 160                 switch (function) {
 161                 case 1:
 162                     /* KVM before 2.6.30 misreports the following features */
 163                     ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
 164                     break;
 165                 case 0x80000001:
 166                     /* On Intel, kvm returns cpuid according to the Intel spec,
 167                      * so add missing bits according to the AMD spec:
 168                      */
 169                     cpuid_1_edx = kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX);
 170                     ret |= cpuid_1_edx & 0x183f7ff;
 171                     break;
 172                 }
 173                 break;
 174             }
 175         }
 176     }
 177
 178     qemu_free(cpuid);
 179
 180 #ifdef CONFIG_KVM_PARA
 181     /* fallback for older kernels */
 182     if (!has_kvm_features && (function == KVM_CPUID_FEATURES)) {
 183         ret = get_para_features(env);
 184     }
 185 #endif
 186
 187     return ret;
 188 }
 189
 190 typedef struct HWPoisonPage {
 191     ram_addr_t ram_addr;
 192     QLIST_ENTRY(HWPoisonPage) list;
 193 } HWPoisonPage;
 194
 195 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
 196     QLIST_HEAD_INITIALIZER(hwpoison_page_list);
 197
 198 static void kvm_unpoison_all(void *param)
 199 {
 200     HWPoisonPage *page, *next_page;
 201
 202     QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
 203         QLIST_REMOVE(page, list);
 204         qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
 205         qemu_free(page);
 206     }
 207 }
 208
 209 #ifdef KVM_CAP_MCE
 210 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
 211 {
 212     HWPoisonPage *page;
 213
 214     QLIST_FOREACH(page, &hwpoison_page_list, list) {
 215         if (page->ram_addr == ram_addr) {
 216             return;
 217         }
 218     }
 219     page = qemu_malloc(sizeof(HWPoisonPage));
 220     page->ram_addr = ram_addr;
 221     QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
 222 }
 223
 224 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
 225                                      int *max_banks)
 226 {
 227     int r;
 228
 229     r = kvm_check_extension(s, KVM_CAP_MCE);
 230     if (r > 0) {
 231         *max_banks = r;
 232         return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
 233     }
 234     return -ENOSYS;
 235 }
 236
 237 static void kvm_mce_inject(CPUState *env, target_phys_addr_t paddr, int code)
 238 {
 239     uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
 240                       MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
 241     uint64_t mcg_status = MCG_STATUS_MCIP;
 242
 243     if (code == BUS_MCEERR_AR) {
 244         status |= MCI_STATUS_AR | 0x134;
 245         mcg_status |= MCG_STATUS_EIPV;
 246     } else {
 247         status |= 0xc0;
 248         mcg_status |= MCG_STATUS_RIPV;
 249     }
 250     cpu_x86_inject_mce(NULL, env, 9, status, mcg_status, paddr,
 251                        (MCM_ADDR_PHYS << 6) | 0xc,
 252                        cpu_x86_support_mca_broadcast(env) ?
 253                        MCE_INJECT_BROADCAST : 0);
 254 }
 255 #endif /* KVM_CAP_MCE */
 256
 257 static void hardware_memory_error(void)
 258 {
 259     fprintf(stderr, "Hardware memory error!\n");
 260     exit(1);
 261 }
 262
 263 int kvm_arch_on_sigbus_vcpu(CPUState *env, int code, void *addr)
 264 {
 265 #ifdef KVM_CAP_MCE
 266     ram_addr_t ram_addr;
 267     target_phys_addr_t paddr;
 268
 269     if ((env->mcg_cap & MCG_SER_P) && addr
 270         && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
 271         if (qemu_ram_addr_from_host(addr, &ram_addr) ||
 272             !kvm_physical_memory_addr_from_ram(env->kvm_state, ram_addr,
 273                                                &paddr)) {
 274             fprintf(stderr, "Hardware memory error for memory used by "
 275                     "QEMU itself instead of guest system!\n");
 276             /* Hope we are lucky for AO MCE */
 277             if (code == BUS_MCEERR_AO) {
 278                 return 0;
 279             } else {
 280                 hardware_memory_error();
 281             }
 282         }
 283         kvm_hwpoison_page_add(ram_addr);
 284         kvm_mce_inject(env, paddr, code);
 285     } else
 286 #endif /* KVM_CAP_MCE */
 287     {
 288         if (code == BUS_MCEERR_AO) {
 289             return 0;
 290         } else if (code == BUS_MCEERR_AR) {
 291             hardware_memory_error();
 292         } else {
 293             return 1;
 294         }
 295     }
 296     return 0;
 297 }
 298
 299 int kvm_arch_on_sigbus(int code, void *addr)
 300 {
 301 #ifdef KVM_CAP_MCE
 302     if ((first_cpu->mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
 303         ram_addr_t ram_addr;
 304         target_phys_addr_t paddr;
 305
 306         /* Hope we are lucky for AO MCE */
 307         if (qemu_ram_addr_from_host(addr, &ram_addr) ||
 308             !kvm_physical_memory_addr_from_ram(first_cpu->kvm_state, ram_addr,
 309                                                &paddr)) {
 310             fprintf(stderr, "Hardware memory error for memory used by "
 311                     "QEMU itself instead of guest system!: %p\n", addr);
 312             return 0;
 313         }
 314         kvm_hwpoison_page_add(ram_addr);
 315         kvm_mce_inject(first_cpu, paddr, code);
 316     } else
 317 #endif /* KVM_CAP_MCE */
 318     {
 319         if (code == BUS_MCEERR_AO) {
 320             return 0;
 321         } else if (code == BUS_MCEERR_AR) {
 322             hardware_memory_error();
 323         } else {
 324             return 1;
 325         }
 326     }
 327     return 0;
 328 }
 329
 330 static int kvm_inject_mce_oldstyle(CPUState *env)
 331 {
 332 #ifdef KVM_CAP_MCE
 333     if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
 334         unsigned int bank, bank_num = env->mcg_cap & 0xff;
 335         struct kvm_x86_mce mce;
 336
 337         env->exception_injected = -1;
 338
 339         /*
 340          * There must be at least one bank in use if an MCE is pending.
 341          * Find it and use its values for the event injection.
 342          */
 343         for (bank = 0; bank < bank_num; bank++) {
 344             if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
 345                 break;
 346             }
 347         }
 348         assert(bank < bank_num);
 349
 350         mce.bank = bank;
 351         mce.status = env->mce_banks[bank * 4 + 1];
 352         mce.mcg_status = env->mcg_status;
 353         mce.addr = env->mce_banks[bank * 4 + 2];
 354         mce.misc = env->mce_banks[bank * 4 + 3];
 355
 356         return kvm_vcpu_ioctl(env, KVM_X86_SET_MCE, &mce);
 357     }
 358 #endif /* KVM_CAP_MCE */
 359     return 0;
 360 }
 361
 362 static void cpu_update_state(void *opaque, int running, int reason)
 363 {
 364     CPUState *env = opaque;
 365
 366     if (running) {
 367         env->tsc_valid = false;
 368     }
 369 }
 370
 371 int kvm_arch_init_vcpu(CPUState *env)
 372 {
 373     struct {
 374         struct kvm_cpuid2 cpuid;
 375         struct kvm_cpuid_entry2 entries[100];
 376     } __attribute__((packed)) cpuid_data;
 377     uint32_t limit, i, j, cpuid_i;
 378     uint32_t unused;
 379     struct kvm_cpuid_entry2 *c;
 380 #ifdef CONFIG_KVM_PARA
 381     uint32_t signature[3];
 382 #endif
 383
 384     env->cpuid_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX);
 385
 386     i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR;
 387     env->cpuid_ext_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_ECX);
 388     env->cpuid_ext_features |= i;
 389
 390     env->cpuid_ext2_features &= kvm_arch_get_supported_cpuid(env, 0x80000001,
 391                                                              0, R_EDX);
 392     env->cpuid_ext3_features &= kvm_arch_get_supported_cpuid(env, 0x80000001,
 393                                                              0, R_ECX);
 394     env->cpuid_svm_features  &= kvm_arch_get_supported_cpuid(env, 0x8000000A,
 395                                                              0, R_EDX);
 396
 397
 398     cpuid_i = 0;
 399
 400 #ifdef CONFIG_KVM_PARA
 401     /* Paravirtualization CPUIDs */
 402     memcpy(signature, "KVMKVMKVM\0\0\0", 12);
 403     c = &cpuid_data.entries[cpuid_i++];
 404     memset(c, 0, sizeof(*c));
 405     c->function = KVM_CPUID_SIGNATURE;
 406     c->eax = 0;
 407     c->ebx = signature[0];
 408     c->ecx = signature[1];
 409     c->edx = signature[2];
 410
 411     c = &cpuid_data.entries[cpuid_i++];
 412     memset(c, 0, sizeof(*c));
 413     c->function = KVM_CPUID_FEATURES;
 414     c->eax = env->cpuid_kvm_features & kvm_arch_get_supported_cpuid(env,
 415                                                 KVM_CPUID_FEATURES, 0, R_EAX);
 416
 417 #ifdef KVM_CAP_ASYNC_PF
 418     has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF);
 419 #endif
 420
 421 #endif
 422
 423     cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
 424
 425     for (i = 0; i <= limit; i++) {
 426         c = &cpuid_data.entries[cpuid_i++];
 427
 428         switch (i) {
 429         case 2: {
 430             /* Keep reading function 2 till all the input is received */
 431             int times;
 432
 433             c->function = i;
 434             c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
 435                        KVM_CPUID_FLAG_STATE_READ_NEXT;
 436             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 437             times = c->eax & 0xff;
 438
 439             for (j = 1; j < times; ++j) {
 440                 c = &cpuid_data.entries[cpuid_i++];
 441                 c->function = i;
 442                 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
 443                 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 444             }
 445             break;
 446         }
 447         case 4:
 448         case 0xb:
 449         case 0xd:
 450             for (j = 0; ; j++) {
 451                 c->function = i;
 452                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
 453                 c->index = j;
 454                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
 455
 456                 if (i == 4 && c->eax == 0) {
 457                     break;
 458                 }
 459                 if (i == 0xb && !(c->ecx & 0xff00)) {
 460                     break;
 461                 }
 462                 if (i == 0xd && c->eax == 0) {
 463                     break;
 464                 }
 465                 c = &cpuid_data.entries[cpuid_i++];
 466             }
 467             break;
 468         default:
 469             c->function = i;
 470             c->flags = 0;
 471             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 472             break;
 473         }
 474     }
 475     cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
 476
 477     for (i = 0x80000000; i <= limit; i++) {
 478         c = &cpuid_data.entries[cpuid_i++];
 479
 480         c->function = i;
 481         c->flags = 0;
 482         cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 483     }
 484
 485     /* Call Centaur's CPUID instructions they are supported. */
 486     if (env->cpuid_xlevel2 > 0) {
 487         env->cpuid_ext4_features &=
 488             kvm_arch_get_supported_cpuid(env, 0xC0000001, 0, R_EDX);
 489         cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
 490
 491         for (i = 0xC0000000; i <= limit; i++) {
 492             c = &cpuid_data.entries[cpuid_i++];
 493
 494             c->function = i;
 495             c->flags = 0;
 496             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 497         }
 498     }
 499
 500     cpuid_data.cpuid.nent = cpuid_i;
 501
 502 #ifdef KVM_CAP_MCE
 503     if (((env->cpuid_version >> 8)&0xF) >= 6
 504         && (env->cpuid_features&(CPUID_MCE|CPUID_MCA)) == (CPUID_MCE|CPUID_MCA)
 505         && kvm_check_extension(env->kvm_state, KVM_CAP_MCE) > 0) {
 506         uint64_t mcg_cap;
 507         int banks;
 508         int ret;
 509
 510         ret = kvm_get_mce_cap_supported(env->kvm_state, &mcg_cap, &banks);
 511         if (ret < 0) {
 512             fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
 513             return ret;
 514         }
 515
 516         if (banks > MCE_BANKS_DEF) {
 517             banks = MCE_BANKS_DEF;
 518         }
 519         mcg_cap &= MCE_CAP_DEF;
 520         mcg_cap |= banks;
 521         ret = kvm_vcpu_ioctl(env, KVM_X86_SETUP_MCE, &mcg_cap);
 522         if (ret < 0) {
 523             fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
 524             return ret;
 525         }
 526
 527         env->mcg_cap = mcg_cap;
 528     }
 529 #endif
 530
 531     qemu_add_vm_change_state_handler(cpu_update_state, env);
 532
 533     return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
 534 }
 535
 536 void kvm_arch_reset_vcpu(CPUState *env)
 537 {
 538     env->exception_injected = -1;
 539     env->interrupt_injected = -1;
 540     env->xcr0 = 1;
 541     if (kvm_irqchip_in_kernel()) {
 542         env->mp_state = cpu_is_bsp(env) ? KVM_MP_STATE_RUNNABLE :
 543                                           KVM_MP_STATE_UNINITIALIZED;
 544     } else {
 545         env->mp_state = KVM_MP_STATE_RUNNABLE;
 546     }
 547 }
 548
 549 static int kvm_get_supported_msrs(KVMState *s)
 550 {
 551     static int kvm_supported_msrs;
 552     int ret = 0;
 553
 554     /* first time */
 555     if (kvm_supported_msrs == 0) {
 556         struct kvm_msr_list msr_list, *kvm_msr_list;
 557
 558         kvm_supported_msrs = -1;
 559
 560         /* Obtain MSR list from KVM.  These are the MSRs that we must
 561          * save/restore */
 562         msr_list.nmsrs = 0;
 563         ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
 564         if (ret < 0 && ret != -E2BIG) {
 565             return ret;
 566         }
 567         /* Old kernel modules had a bug and could write beyond the provided
 568            memory. Allocate at least a safe amount of 1K. */
 569         kvm_msr_list = qemu_mallocz(MAX(1024, sizeof(msr_list) +
 570                                               msr_list.nmsrs *
 571                                               sizeof(msr_list.indices[0])));
 572
 573         kvm_msr_list->nmsrs = msr_list.nmsrs;
 574         ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
 575         if (ret >= 0) {
 576             int i;
 577
 578             for (i = 0; i < kvm_msr_list->nmsrs; i++) {
 579                 if (kvm_msr_list->indices[i] == MSR_STAR) {
 580                     has_msr_star = true;
 581                     continue;
 582                 }
 583                 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
 584                     has_msr_hsave_pa = true;
 585                     continue;
 586                 }
 587             }
 588         }
 589
 590         qemu_free(kvm_msr_list);
 591     }
 592
 593     return ret;
 594 }
 595
 596 int kvm_arch_init(KVMState *s)
 597 {
 598     uint64_t identity_base = 0xfffbc000;
 599     int ret;
 600     struct utsname utsname;
 601
 602     ret = kvm_get_supported_msrs(s);
 603     if (ret < 0) {
 604         return ret;
 605     }
 606
 607     uname(&utsname);
 608     lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
 609
 610     /*
 611      * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
 612      * In order to use vm86 mode, an EPT identity map and a TSS  are needed.
 613      * Since these must be part of guest physical memory, we need to allocate
 614      * them, both by setting their start addresses in the kernel and by
 615      * creating a corresponding e820 entry. We need 4 pages before the BIOS.
 616      *
 617      * Older KVM versions may not support setting the identity map base. In
 618      * that case we need to stick with the default, i.e. a 256K maximum BIOS
 619      * size.
 620      */
 621 #ifdef KVM_CAP_SET_IDENTITY_MAP_ADDR
 622     if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
 623         /* Allows up to 16M BIOSes. */
 624         identity_base = 0xfeffc000;
 625
 626         ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
 627         if (ret < 0) {
 628             return ret;
 629         }
 630     }
 631 #endif
 632     /* Set TSS base one page after EPT identity map. */
 633     ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
 634     if (ret < 0) {
 635         return ret;
 636     }
 637
 638     /* Tell fw_cfg to notify the BIOS to reserve the range. */
 639     ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
 640     if (ret < 0) {
 641         fprintf(stderr, "e820_add_entry() table is full\n");
 642         return ret;
 643     }
 644     qemu_register_reset(kvm_unpoison_all, NULL);
 645
 646     return 0;
 647 }
 648
 649 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 650 {
 651     lhs->selector = rhs->selector;
 652     lhs->base = rhs->base;
 653     lhs->limit = rhs->limit;
 654     lhs->type = 3;
 655     lhs->present = 1;
 656     lhs->dpl = 3;
 657     lhs->db = 0;
 658     lhs->s = 1;
 659     lhs->l = 0;
 660     lhs->g = 0;
 661     lhs->avl = 0;
 662     lhs->unusable = 0;
 663 }
 664
 665 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 666 {
 667     unsigned flags = rhs->flags;
 668     lhs->selector = rhs->selector;
 669     lhs->base = rhs->base;
 670     lhs->limit = rhs->limit;
 671     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
 672     lhs->present = (flags & DESC_P_MASK) != 0;
 673     lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
 674     lhs->db = (flags >> DESC_B_SHIFT) & 1;
 675     lhs->s = (flags & DESC_S_MASK) != 0;
 676     lhs->l = (flags >> DESC_L_SHIFT) & 1;
 677     lhs->g = (flags & DESC_G_MASK) != 0;
 678     lhs->avl = (flags & DESC_AVL_MASK) != 0;
 679     lhs->unusable = 0;
 680 }
 681
 682 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
 683 {
 684     lhs->selector = rhs->selector;
 685     lhs->base = rhs->base;
 686     lhs->limit = rhs->limit;
 687     lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
 688                  (rhs->present * DESC_P_MASK) |
 689                  (rhs->dpl << DESC_DPL_SHIFT) |
 690                  (rhs->db << DESC_B_SHIFT) |
 691                  (rhs->s * DESC_S_MASK) |
 692                  (rhs->l << DESC_L_SHIFT) |
 693                  (rhs->g * DESC_G_MASK) |
 694                  (rhs->avl * DESC_AVL_MASK);
 695 }
 696
 697 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
 698 {
 699     if (set) {
 700         *kvm_reg = *qemu_reg;
 701     } else {
 702         *qemu_reg = *kvm_reg;
 703     }
 704 }
 705
 706 static int kvm_getput_regs(CPUState *env, int set)
 707 {
 708     struct kvm_regs regs;
 709     int ret = 0;
 710
 711     if (!set) {
 712         ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
 713         if (ret < 0) {
 714             return ret;
 715         }
 716     }
 717
 718     kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
 719     kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
 720     kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
 721     kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
 722     kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
 723     kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
 724     kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
 725     kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
 726 #ifdef TARGET_X86_64
 727     kvm_getput_reg(&regs.r8, &env->regs[8], set);
 728     kvm_getput_reg(&regs.r9, &env->regs[9], set);
 729     kvm_getput_reg(&regs.r10, &env->regs[10], set);
 730     kvm_getput_reg(&regs.r11, &env->regs[11], set);
 731     kvm_getput_reg(&regs.r12, &env->regs[12], set);
 732     kvm_getput_reg(&regs.r13, &env->regs[13], set);
 733     kvm_getput_reg(&regs.r14, &env->regs[14], set);
 734     kvm_getput_reg(&regs.r15, &env->regs[15], set);
 735 #endif
 736
 737     kvm_getput_reg(&regs.rflags, &env->eflags, set);
 738     kvm_getput_reg(&regs.rip, &env->eip, set);
 739
 740     if (set) {
 741         ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
 742     }
 743
 744     return ret;
 745 }
 746
 747 static int kvm_put_fpu(CPUState *env)
 748 {
 749     struct kvm_fpu fpu;
 750     int i;
 751
 752     memset(&fpu, 0, sizeof fpu);
 753     fpu.fsw = env->fpus & ~(7 << 11);
 754     fpu.fsw |= (env->fpstt & 7) << 11;
 755     fpu.fcw = env->fpuc;
 756     for (i = 0; i < 8; ++i) {
 757         fpu.ftwx |= (!env->fptags[i]) << i;
 758     }
 759     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
 760     memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
 761     fpu.mxcsr = env->mxcsr;
 762
 763     return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
 764 }
 765
 766 #ifdef KVM_CAP_XSAVE
 767 #define XSAVE_CWD_RIP     2
 768 #define XSAVE_CWD_RDP     4
 769 #define XSAVE_MXCSR       6
 770 #define XSAVE_ST_SPACE    8
 771 #define XSAVE_XMM_SPACE   40
 772 #define XSAVE_XSTATE_BV   128
 773 #define XSAVE_YMMH_SPACE  144
 774 #endif
 775
 776 static int kvm_put_xsave(CPUState *env)
 777 {
 778 #ifdef KVM_CAP_XSAVE
 779     int i, r;
 780     struct kvm_xsave* xsave;
 781     uint16_t cwd, swd, twd, fop;
 782
 783     if (!kvm_has_xsave()) {
 784         return kvm_put_fpu(env);
 785     }
 786
 787     xsave = qemu_memalign(4096, sizeof(struct kvm_xsave));
 788     memset(xsave, 0, sizeof(struct kvm_xsave));
 789     cwd = swd = twd = fop = 0;
 790     swd = env->fpus & ~(7 << 11);
 791     swd |= (env->fpstt & 7) << 11;
 792     cwd = env->fpuc;
 793     for (i = 0; i < 8; ++i) {
 794         twd |= (!env->fptags[i]) << i;
 795     }
 796     xsave->region[0] = (uint32_t)(swd << 16) + cwd;
 797     xsave->region[1] = (uint32_t)(fop << 16) + twd;
 798     memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
 799             sizeof env->fpregs);
 800     memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs,
 801             sizeof env->xmm_regs);
 802     xsave->region[XSAVE_MXCSR] = env->mxcsr;
 803     *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
 804     memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs,
 805             sizeof env->ymmh_regs);
 806     r = kvm_vcpu_ioctl(env, KVM_SET_XSAVE, xsave);
 807     qemu_free(xsave);
 808     return r;
 809 #else
 810     return kvm_put_fpu(env);
 811 #endif
 812 }
 813
 814 static int kvm_put_xcrs(CPUState *env)
 815 {
 816 #ifdef KVM_CAP_XCRS
 817     struct kvm_xcrs xcrs;
 818
 819     if (!kvm_has_xcrs()) {
 820         return 0;
 821     }
 822
 823     xcrs.nr_xcrs = 1;
 824     xcrs.flags = 0;
 825     xcrs.xcrs[0].xcr = 0;
 826     xcrs.xcrs[0].value = env->xcr0;
 827     return kvm_vcpu_ioctl(env, KVM_SET_XCRS, &xcrs);
 828 #else
 829     return 0;
 830 #endif
 831 }
 832
 833 static int kvm_put_sregs(CPUState *env)
 834 {
 835     struct kvm_sregs sregs;
 836
 837     memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
 838     if (env->interrupt_injected >= 0) {
 839         sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
 840                 (uint64_t)1 << (env->interrupt_injected % 64);
 841     }
 842
 843     if ((env->eflags & VM_MASK)) {
 844         set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
 845         set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
 846         set_v8086_seg(&sregs.es, &env->segs[R_ES]);
 847         set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
 848         set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
 849         set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
 850     } else {
 851         set_seg(&sregs.cs, &env->segs[R_CS]);
 852         set_seg(&sregs.ds, &env->segs[R_DS]);
 853         set_seg(&sregs.es, &env->segs[R_ES]);
 854         set_seg(&sregs.fs, &env->segs[R_FS]);
 855         set_seg(&sregs.gs, &env->segs[R_GS]);
 856         set_seg(&sregs.ss, &env->segs[R_SS]);
 857     }
 858
 859     set_seg(&sregs.tr, &env->tr);
 860     set_seg(&sregs.ldt, &env->ldt);
 861
 862     sregs.idt.limit = env->idt.limit;
 863     sregs.idt.base = env->idt.base;
 864     sregs.gdt.limit = env->gdt.limit;
 865     sregs.gdt.base = env->gdt.base;
 866
 867     sregs.cr0 = env->cr[0];
 868     sregs.cr2 = env->cr[2];
 869     sregs.cr3 = env->cr[3];
 870     sregs.cr4 = env->cr[4];
 871
 872     sregs.cr8 = cpu_get_apic_tpr(env->apic_state);
 873     sregs.apic_base = cpu_get_apic_base(env->apic_state);
 874
 875     sregs.efer = env->efer;
 876
 877     return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
 878 }
 879
 880 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
 881                               uint32_t index, uint64_t value)
 882 {
 883     entry->index = index;
 884     entry->data = value;
 885 }
 886
 887 static int kvm_put_msrs(CPUState *env, int level)
 888 {
 889     struct {
 890         struct kvm_msrs info;
 891         struct kvm_msr_entry entries[100];
 892     } msr_data;
 893     struct kvm_msr_entry *msrs = msr_data.entries;
 894     int n = 0;
 895
 896     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
 897     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
 898     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
 899     kvm_msr_entry_set(&msrs[n++], MSR_PAT, env->pat);
 900     if (has_msr_star) {
 901         kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
 902     }
 903     if (has_msr_hsave_pa) {
 904         kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
 905     }
 906 #ifdef TARGET_X86_64
 907     if (lm_capable_kernel) {
 908         kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
 909         kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
 910         kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
 911         kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
 912     }
 913 #endif
 914     if (level == KVM_PUT_FULL_STATE) {
 915         /*
 916          * KVM is yet unable to synchronize TSC values of multiple VCPUs on
 917          * writeback. Until this is fixed, we only write the offset to SMP
 918          * guests after migration, desynchronizing the VCPUs, but avoiding
 919          * huge jump-backs that would occur without any writeback at all.
 920          */
 921         if (smp_cpus == 1 || env->tsc != 0) {
 922             kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
 923         }
 924     }
 925     /*
 926      * The following paravirtual MSRs have side effects on the guest or are
 927      * too heavy for normal writeback. Limit them to reset or full state
 928      * updates.
 929      */
 930     if (level >= KVM_PUT_RESET_STATE) {
 931         kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
 932                           env->system_time_msr);
 933         kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
 934 #if defined(CONFIG_KVM_PARA) && defined(KVM_CAP_ASYNC_PF)
 935         if (has_msr_async_pf_en) {
 936             kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN,
 937                               env->async_pf_en_msr);
 938         }
 939 #endif
 940     }
 941 #ifdef KVM_CAP_MCE
 942     if (env->mcg_cap) {
 943         int i;
 944
 945         kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
 946         kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl);
 947         for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
 948             kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]);
 949         }
 950     }
 951 #endif
 952
 953     msr_data.info.nmsrs = n;
 954
 955     return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
 956
 957 }
 958
 959
 960 static int kvm_get_fpu(CPUState *env)
 961 {
 962     struct kvm_fpu fpu;
 963     int i, ret;
 964
 965     ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
 966     if (ret < 0) {
 967         return ret;
 968     }
 969
 970     env->fpstt = (fpu.fsw >> 11) & 7;
 971     env->fpus = fpu.fsw;
 972     env->fpuc = fpu.fcw;
 973     for (i = 0; i < 8; ++i) {
 974         env->fptags[i] = !((fpu.ftwx >> i) & 1);
 975     }
 976     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
 977     memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
 978     env->mxcsr = fpu.mxcsr;
 979
 980     return 0;
 981 }
 982
 983 static int kvm_get_xsave(CPUState *env)
 984 {
 985 #ifdef KVM_CAP_XSAVE
 986     struct kvm_xsave* xsave;
 987     int ret, i;
 988     uint16_t cwd, swd, twd, fop;
 989
 990     if (!kvm_has_xsave()) {
 991         return kvm_get_fpu(env);
 992     }
 993
 994     xsave = qemu_memalign(4096, sizeof(struct kvm_xsave));
 995     ret = kvm_vcpu_ioctl(env, KVM_GET_XSAVE, xsave);
 996     if (ret < 0) {
 997         qemu_free(xsave);
 998         return ret;
 999     }
1000
1001     cwd = (uint16_t)xsave->region[0];
1002     swd = (uint16_t)(xsave->region[0] >> 16);
1003     twd = (uint16_t)xsave->region[1];
1004     fop = (uint16_t)(xsave->region[1] >> 16);
1005     env->fpstt = (swd >> 11) & 7;
1006     env->fpus = swd;
1007     env->fpuc = cwd;
1008     for (i = 0; i < 8; ++i) {
1009         env->fptags[i] = !((twd >> i) & 1);
1010     }
1011     env->mxcsr = xsave->region[XSAVE_MXCSR];
1012     memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
1013             sizeof env->fpregs);
1014     memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE],
1015             sizeof env->xmm_regs);
1016     env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
1017     memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE],
1018             sizeof env->ymmh_regs);
1019     qemu_free(xsave);
1020     return 0;
1021 #else
1022     return kvm_get_fpu(env);
1023 #endif
1024 }
1025
1026 static int kvm_get_xcrs(CPUState *env)
1027 {
1028 #ifdef KVM_CAP_XCRS
1029     int i, ret;
1030     struct kvm_xcrs xcrs;
1031
1032     if (!kvm_has_xcrs()) {
1033         return 0;
1034     }
1035
1036     ret = kvm_vcpu_ioctl(env, KVM_GET_XCRS, &xcrs);
1037     if (ret < 0) {
1038         return ret;
1039     }
1040
1041     for (i = 0; i < xcrs.nr_xcrs; i++) {
1042         /* Only support xcr0 now */
1043         if (xcrs.xcrs[0].xcr == 0) {
1044             env->xcr0 = xcrs.xcrs[0].value;
1045             break;
1046         }
1047     }
1048     return 0;
1049 #else
1050     return 0;
1051 #endif
1052 }
1053
1054 static int kvm_get_sregs(CPUState *env)
1055 {
1056     struct kvm_sregs sregs;
1057     uint32_t hflags;
1058     int bit, i, ret;
1059
1060     ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
1061     if (ret < 0) {
1062         return ret;
1063     }
1064
1065     /* There can only be one pending IRQ set in the bitmap at a time, so try
1066        to find it and save its number instead (-1 for none). */
1067     env->interrupt_injected = -1;
1068     for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1069         if (sregs.interrupt_bitmap[i]) {
1070             bit = ctz64(sregs.interrupt_bitmap[i]);
1071             env->interrupt_injected = i * 64 + bit;
1072             break;
1073         }
1074     }
1075
1076     get_seg(&env->segs[R_CS], &sregs.cs);
1077     get_seg(&env->segs[R_DS], &sregs.ds);
1078     get_seg(&env->segs[R_ES], &sregs.es);
1079     get_seg(&env->segs[R_FS], &sregs.fs);
1080     get_seg(&env->segs[R_GS], &sregs.gs);
1081     get_seg(&env->segs[R_SS], &sregs.ss);
1082
1083     get_seg(&env->tr, &sregs.tr);
1084     get_seg(&env->ldt, &sregs.ldt);
1085
1086     env->idt.limit = sregs.idt.limit;
1087     env->idt.base = sregs.idt.base;
1088     env->gdt.limit = sregs.gdt.limit;
1089     env->gdt.base = sregs.gdt.base;
1090
1091     env->cr[0] = sregs.cr0;
1092     env->cr[2] = sregs.cr2;
1093     env->cr[3] = sregs.cr3;
1094     env->cr[4] = sregs.cr4;
1095
1096     cpu_set_apic_base(env->apic_state, sregs.apic_base);
1097
1098     env->efer = sregs.efer;
1099     //cpu_set_apic_tpr(env->apic_state, sregs.cr8);
1100
1101 #define HFLAG_COPY_MASK \
1102     ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1103        HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1104        HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1105        HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1106
1107     hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1108     hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1109     hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1110                 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1111     hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1112     hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
1113                 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
1114
1115     if (env->efer & MSR_EFER_LMA) {
1116         hflags |= HF_LMA_MASK;
1117     }
1118
1119     if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1120         hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1121     } else {
1122         hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1123                     (DESC_B_SHIFT - HF_CS32_SHIFT);
1124         hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1125                     (DESC_B_SHIFT - HF_SS32_SHIFT);
1126         if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1127             !(hflags & HF_CS32_MASK)) {
1128             hflags |= HF_ADDSEG_MASK;
1129         } else {
1130             hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1131                         env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1132         }
1133     }
1134     env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
1135
1136     return 0;
1137 }
1138
1139 static int kvm_get_msrs(CPUState *env)
1140 {
1141     struct {
1142         struct kvm_msrs info;
1143         struct kvm_msr_entry entries[100];
1144     } msr_data;
1145     struct kvm_msr_entry *msrs = msr_data.entries;
1146     int ret, i, n;
1147
1148     n = 0;
1149     msrs[n++].index = MSR_IA32_SYSENTER_CS;
1150     msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1151     msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1152     msrs[n++].index = MSR_PAT;
1153     if (has_msr_star) {
1154         msrs[n++].index = MSR_STAR;
1155     }
1156     if (has_msr_hsave_pa) {
1157         msrs[n++].index = MSR_VM_HSAVE_PA;
1158     }
1159
1160     if (!env->tsc_valid) {
1161         msrs[n++].index = MSR_IA32_TSC;
1162         env->tsc_valid = !vm_running;
1163     }
1164
1165 #ifdef TARGET_X86_64
1166     if (lm_capable_kernel) {
1167         msrs[n++].index = MSR_CSTAR;
1168         msrs[n++].index = MSR_KERNELGSBASE;
1169         msrs[n++].index = MSR_FMASK;
1170         msrs[n++].index = MSR_LSTAR;
1171     }
1172 #endif
1173     msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1174     msrs[n++].index = MSR_KVM_WALL_CLOCK;
1175 #if defined(CONFIG_KVM_PARA) && defined(KVM_CAP_ASYNC_PF)
1176     if (has_msr_async_pf_en) {
1177         msrs[n++].index = MSR_KVM_ASYNC_PF_EN;
1178     }
1179 #endif
1180
1181 #ifdef KVM_CAP_MCE
1182     if (env->mcg_cap) {
1183         msrs[n++].index = MSR_MCG_STATUS;
1184         msrs[n++].index = MSR_MCG_CTL;
1185         for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1186             msrs[n++].index = MSR_MC0_CTL + i;
1187         }
1188     }
1189 #endif
1190
1191     msr_data.info.nmsrs = n;
1192     ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
1193     if (ret < 0) {
1194         return ret;
1195     }
1196
1197     for (i = 0; i < ret; i++) {
1198         switch (msrs[i].index) {
1199         case MSR_IA32_SYSENTER_CS:
1200             env->sysenter_cs = msrs[i].data;
1201             break;
1202         case MSR_IA32_SYSENTER_ESP:
1203             env->sysenter_esp = msrs[i].data;
1204             break;
1205         case MSR_IA32_SYSENTER_EIP:
1206             env->sysenter_eip = msrs[i].data;
1207             break;
1208         case MSR_PAT:
1209             env->pat = msrs[i].data;
1210             break;
1211         case MSR_STAR:
1212             env->star = msrs[i].data;
1213             break;
1214 #ifdef TARGET_X86_64
1215         case MSR_CSTAR:
1216             env->cstar = msrs[i].data;
1217             break;
1218         case MSR_KERNELGSBASE:
1219             env->kernelgsbase = msrs[i].data;
1220             break;
1221         case MSR_FMASK:
1222             env->fmask = msrs[i].data;
1223             break;
1224         case MSR_LSTAR:
1225             env->lstar = msrs[i].data;
1226             break;
1227 #endif
1228         case MSR_IA32_TSC:
1229             env->tsc = msrs[i].data;
1230             break;
1231         case MSR_VM_HSAVE_PA:
1232             env->vm_hsave = msrs[i].data;
1233             break;
1234         case MSR_KVM_SYSTEM_TIME:
1235             env->system_time_msr = msrs[i].data;
1236             break;
1237         case MSR_KVM_WALL_CLOCK:
1238             env->wall_clock_msr = msrs[i].data;
1239             break;
1240 #ifdef KVM_CAP_MCE
1241         case MSR_MCG_STATUS:
1242             env->mcg_status = msrs[i].data;
1243             break;
1244         case MSR_MCG_CTL:
1245             env->mcg_ctl = msrs[i].data;
1246             break;
1247 #endif
1248         default:
1249 #ifdef KVM_CAP_MCE
1250             if (msrs[i].index >= MSR_MC0_CTL &&
1251                 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
1252                 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
1253             }
1254 #endif
1255             break;
1256 #if defined(CONFIG_KVM_PARA) && defined(KVM_CAP_ASYNC_PF)
1257         case MSR_KVM_ASYNC_PF_EN:
1258             env->async_pf_en_msr = msrs[i].data;
1259             break;
1260 #endif
1261         }
1262     }
1263
1264     return 0;
1265 }
1266
1267 static int kvm_put_mp_state(CPUState *env)
1268 {
1269     struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
1270
1271     return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state);
1272 }
1273
1274 static int kvm_get_mp_state(CPUState *env)
1275 {
1276     struct kvm_mp_state mp_state;
1277     int ret;
1278
1279     ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state);
1280     if (ret < 0) {
1281         return ret;
1282     }
1283     env->mp_state = mp_state.mp_state;
1284     if (kvm_irqchip_in_kernel()) {
1285         env->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
1286     }
1287     return 0;
1288 }
1289
1290 static int kvm_put_vcpu_events(CPUState *env, int level)
1291 {
1292 #ifdef KVM_CAP_VCPU_EVENTS
1293     struct kvm_vcpu_events events;
1294
1295     if (!kvm_has_vcpu_events()) {
1296         return 0;
1297     }
1298
1299     events.exception.injected = (env->exception_injected >= 0);
1300     events.exception.nr = env->exception_injected;
1301     events.exception.has_error_code = env->has_error_code;
1302     events.exception.error_code = env->error_code;
1303
1304     events.interrupt.injected = (env->interrupt_injected >= 0);
1305     events.interrupt.nr = env->interrupt_injected;
1306     events.interrupt.soft = env->soft_interrupt;
1307
1308     events.nmi.injected = env->nmi_injected;
1309     events.nmi.pending = env->nmi_pending;
1310     events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
1311
1312     events.sipi_vector = env->sipi_vector;
1313
1314     events.flags = 0;
1315     if (level >= KVM_PUT_RESET_STATE) {
1316         events.flags |=
1317             KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
1318     }
1319
1320     return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events);
1321 #else
1322     return 0;
1323 #endif
1324 }
1325
1326 static int kvm_get_vcpu_events(CPUState *env)
1327 {
1328 #ifdef KVM_CAP_VCPU_EVENTS
1329     struct kvm_vcpu_events events;
1330     int ret;
1331
1332     if (!kvm_has_vcpu_events()) {
1333         return 0;
1334     }
1335
1336     ret = kvm_vcpu_ioctl(env, KVM_GET_VCPU_EVENTS, &events);
1337     if (ret < 0) {
1338        return ret;
1339     }
1340     env->exception_injected =
1341        events.exception.injected ? events.exception.nr : -1;
1342     env->has_error_code = events.exception.has_error_code;
1343     env->error_code = events.exception.error_code;
1344
1345     env->interrupt_injected =
1346         events.interrupt.injected ? events.interrupt.nr : -1;
1347     env->soft_interrupt = events.interrupt.soft;
1348
1349     env->nmi_injected = events.nmi.injected;
1350     env->nmi_pending = events.nmi.pending;
1351     if (events.nmi.masked) {
1352         env->hflags2 |= HF2_NMI_MASK;
1353     } else {
1354         env->hflags2 &= ~HF2_NMI_MASK;
1355     }
1356
1357     env->sipi_vector = events.sipi_vector;
1358 #endif
1359
1360     return 0;
1361 }
1362
1363 static int kvm_guest_debug_workarounds(CPUState *env)
1364 {
1365     int ret = 0;
1366 #ifdef KVM_CAP_SET_GUEST_DEBUG
1367     unsigned long reinject_trap = 0;
1368
1369     if (!kvm_has_vcpu_events()) {
1370         if (env->exception_injected == 1) {
1371             reinject_trap = KVM_GUESTDBG_INJECT_DB;
1372         } else if (env->exception_injected == 3) {
1373             reinject_trap = KVM_GUESTDBG_INJECT_BP;
1374         }
1375         env->exception_injected = -1;
1376     }
1377
1378     /*
1379      * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
1380      * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
1381      * by updating the debug state once again if single-stepping is on.
1382      * Another reason to call kvm_update_guest_debug here is a pending debug
1383      * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
1384      * reinject them via SET_GUEST_DEBUG.
1385      */
1386     if (reinject_trap ||
1387         (!kvm_has_robust_singlestep() && env->singlestep_enabled)) {
1388         ret = kvm_update_guest_debug(env, reinject_trap);
1389     }
1390 #endif /* KVM_CAP_SET_GUEST_DEBUG */
1391     return ret;
1392 }
1393
1394 static int kvm_put_debugregs(CPUState *env)
1395 {
1396 #ifdef KVM_CAP_DEBUGREGS
1397     struct kvm_debugregs dbgregs;
1398     int i;
1399
1400     if (!kvm_has_debugregs()) {
1401         return 0;
1402     }
1403
1404     for (i = 0; i < 4; i++) {
1405         dbgregs.db[i] = env->dr[i];
1406     }
1407     dbgregs.dr6 = env->dr[6];
1408     dbgregs.dr7 = env->dr[7];
1409     dbgregs.flags = 0;
1410
1411     return kvm_vcpu_ioctl(env, KVM_SET_DEBUGREGS, &dbgregs);
1412 #else
1413     return 0;
1414 #endif
1415 }
1416
1417 static int kvm_get_debugregs(CPUState *env)
1418 {
1419 #ifdef KVM_CAP_DEBUGREGS
1420     struct kvm_debugregs dbgregs;
1421     int i, ret;
1422
1423     if (!kvm_has_debugregs()) {
1424         return 0;
1425     }
1426
1427     ret = kvm_vcpu_ioctl(env, KVM_GET_DEBUGREGS, &dbgregs);
1428     if (ret < 0) {
1429         return ret;
1430     }
1431     for (i = 0; i < 4; i++) {
1432         env->dr[i] = dbgregs.db[i];
1433     }
1434     env->dr[4] = env->dr[6] = dbgregs.dr6;
1435     env->dr[5] = env->dr[7] = dbgregs.dr7;
1436 #endif
1437
1438     return 0;
1439 }
1440
1441 int kvm_arch_put_registers(CPUState *env, int level)
1442 {
1443     int ret;
1444
1445     assert(cpu_is_stopped(env) || qemu_cpu_is_self(env));
1446
1447     ret = kvm_getput_regs(env, 1);
1448     if (ret < 0) {
1449         return ret;
1450     }
1451     ret = kvm_put_xsave(env);
1452     if (ret < 0) {
1453         return ret;
1454     }
1455     ret = kvm_put_xcrs(env);
1456     if (ret < 0) {
1457         return ret;
1458     }
1459     ret = kvm_put_sregs(env);
1460     if (ret < 0) {
1461         return ret;
1462     }
1463     /* must be before kvm_put_msrs */
1464     ret = kvm_inject_mce_oldstyle(env);
1465     if (ret < 0) {
1466         return ret;
1467     }
1468     ret = kvm_put_msrs(env, level);
1469     if (ret < 0) {
1470         return ret;
1471     }
1472     if (level >= KVM_PUT_RESET_STATE) {
1473         ret = kvm_put_mp_state(env);
1474         if (ret < 0) {
1475             return ret;
1476         }
1477     }
1478     ret = kvm_put_vcpu_events(env, level);
1479     if (ret < 0) {
1480         return ret;
1481     }
1482     ret = kvm_put_debugregs(env);
1483     if (ret < 0) {
1484         return ret;
1485     }
1486     /* must be last */
1487     ret = kvm_guest_debug_workarounds(env);
1488     if (ret < 0) {
1489         return ret;
1490     }
1491     return 0;
1492 }
1493
1494 int kvm_arch_get_registers(CPUState *env)
1495 {
1496     int ret;
1497
1498     assert(cpu_is_stopped(env) || qemu_cpu_is_self(env));
1499
1500     ret = kvm_getput_regs(env, 0);
1501     if (ret < 0) {
1502         return ret;
1503     }
1504     ret = kvm_get_xsave(env);
1505     if (ret < 0) {
1506         return ret;
1507     }
1508     ret = kvm_get_xcrs(env);
1509     if (ret < 0) {
1510         return ret;
1511     }
1512     ret = kvm_get_sregs(env);
1513     if (ret < 0) {
1514         return ret;
1515     }
1516     ret = kvm_get_msrs(env);
1517     if (ret < 0) {
1518         return ret;
1519     }
1520     ret = kvm_get_mp_state(env);
1521     if (ret < 0) {
1522         return ret;
1523     }
1524     ret = kvm_get_vcpu_events(env);
1525     if (ret < 0) {
1526         return ret;
1527     }
1528     ret = kvm_get_debugregs(env);
1529     if (ret < 0) {
1530         return ret;
1531     }
1532     return 0;
1533 }
1534
1535 void kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
1536 {
1537     int ret;
1538
1539     /* Inject NMI */
1540     if (env->interrupt_request & CPU_INTERRUPT_NMI) {
1541         env->interrupt_request &= ~CPU_INTERRUPT_NMI;
1542         DPRINTF("injected NMI\n");
1543         ret = kvm_vcpu_ioctl(env, KVM_NMI);
1544         if (ret < 0) {
1545             fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
1546                     strerror(-ret));
1547         }
1548     }
1549
1550     if (!kvm_irqchip_in_kernel()) {
1551         /* Force the VCPU out of its inner loop to process the INIT request */
1552         if (env->interrupt_request & CPU_INTERRUPT_INIT) {
1553             env->exit_request = 1;
1554         }
1555
1556         /* Try to inject an interrupt if the guest can accept it */
1557         if (run->ready_for_interrupt_injection &&
1558             (env->interrupt_request & CPU_INTERRUPT_HARD) &&
1559             (env->eflags & IF_MASK)) {
1560             int irq;
1561
1562             env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1563             irq = cpu_get_pic_interrupt(env);
1564             if (irq >= 0) {
1565                 struct kvm_interrupt intr;
1566
1567                 intr.irq = irq;
1568                 DPRINTF("injected interrupt %d\n", irq);
1569                 ret = kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
1570                 if (ret < 0) {
1571                     fprintf(stderr,
1572                             "KVM: injection failed, interrupt lost (%s)\n",
1573                             strerror(-ret));
1574                 }
1575             }
1576         }
1577
1578         /* If we have an interrupt but the guest is not ready to receive an
1579          * interrupt, request an interrupt window exit.  This will
1580          * cause a return to userspace as soon as the guest is ready to
1581          * receive interrupts. */
1582         if ((env->interrupt_request & CPU_INTERRUPT_HARD)) {
1583             run->request_interrupt_window = 1;
1584         } else {
1585             run->request_interrupt_window = 0;
1586         }
1587
1588         DPRINTF("setting tpr\n");
1589         run->cr8 = cpu_get_apic_tpr(env->apic_state);
1590     }
1591 }
1592
1593 void kvm_arch_post_run(CPUState *env, struct kvm_run *run)
1594 {
1595     if (run->if_flag) {
1596         env->eflags |= IF_MASK;
1597     } else {
1598         env->eflags &= ~IF_MASK;
1599     }
1600     cpu_set_apic_tpr(env->apic_state, run->cr8);
1601     cpu_set_apic_base(env->apic_state, run->apic_base);
1602 }
1603
1604 int kvm_arch_process_async_events(CPUState *env)
1605 {
1606     if (env->interrupt_request & CPU_INTERRUPT_MCE) {
1607         /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
1608         assert(env->mcg_cap);
1609
1610         env->interrupt_request &= ~CPU_INTERRUPT_MCE;
1611
1612         kvm_cpu_synchronize_state(env);
1613
1614         if (env->exception_injected == EXCP08_DBLE) {
1615             /* this means triple fault */
1616             qemu_system_reset_request();
1617             env->exit_request = 1;
1618             return 0;
1619         }
1620         env->exception_injected = EXCP12_MCHK;
1621         env->has_error_code = 0;
1622
1623         env->halted = 0;
1624         if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
1625             env->mp_state = KVM_MP_STATE_RUNNABLE;
1626         }
1627     }
1628
1629     if (kvm_irqchip_in_kernel()) {
1630         return 0;
1631     }
1632
1633     if (((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1634          (env->eflags & IF_MASK)) ||
1635         (env->interrupt_request & CPU_INTERRUPT_NMI)) {
1636         env->halted = 0;
1637     }
1638     if (env->interrupt_request & CPU_INTERRUPT_INIT) {
1639         kvm_cpu_synchronize_state(env);
1640         do_cpu_init(env);
1641     }
1642     if (env->interrupt_request & CPU_INTERRUPT_SIPI) {
1643         kvm_cpu_synchronize_state(env);
1644         do_cpu_sipi(env);
1645     }
1646
1647     return env->halted;
1648 }
1649
1650 static int kvm_handle_halt(CPUState *env)
1651 {
1652     if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1653           (env->eflags & IF_MASK)) &&
1654         !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
1655         env->halted = 1;
1656         return EXCP_HLT;
1657     }
1658
1659     return 0;
1660 }
1661
1662 #ifdef KVM_CAP_SET_GUEST_DEBUG
1663 int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1664 {
1665     static const uint8_t int3 = 0xcc;
1666
1667     if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
1668         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1)) {
1669         return -EINVAL;
1670     }
1671     return 0;
1672 }
1673
1674 int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1675 {
1676     uint8_t int3;
1677
1678     if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
1679         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
1680         return -EINVAL;
1681     }
1682     return 0;
1683 }
1684
1685 static struct {
1686     target_ulong addr;
1687     int len;
1688     int type;
1689 } hw_breakpoint[4];
1690
1691 static int nb_hw_breakpoint;
1692
1693 static int find_hw_breakpoint(target_ulong addr, int len, int type)
1694 {
1695     int n;
1696
1697     for (n = 0; n < nb_hw_breakpoint; n++) {
1698         if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
1699             (hw_breakpoint[n].len == len || len == -1)) {
1700             return n;
1701         }
1702     }
1703     return -1;
1704 }
1705
1706 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1707                                   target_ulong len, int type)
1708 {
1709     switch (type) {
1710     case GDB_BREAKPOINT_HW:
1711         len = 1;
1712         break;
1713     case GDB_WATCHPOINT_WRITE:
1714     case GDB_WATCHPOINT_ACCESS:
1715         switch (len) {
1716         case 1:
1717             break;
1718         case 2:
1719         case 4:
1720         case 8:
1721             if (addr & (len - 1)) {
1722                 return -EINVAL;
1723             }
1724             break;
1725         default:
1726             return -EINVAL;
1727         }
1728         break;
1729     default:
1730         return -ENOSYS;
1731     }
1732
1733     if (nb_hw_breakpoint == 4) {
1734         return -ENOBUFS;
1735     }
1736     if (find_hw_breakpoint(addr, len, type) >= 0) {
1737         return -EEXIST;
1738     }
1739     hw_breakpoint[nb_hw_breakpoint].addr = addr;
1740     hw_breakpoint[nb_hw_breakpoint].len = len;
1741     hw_breakpoint[nb_hw_breakpoint].type = type;
1742     nb_hw_breakpoint++;
1743
1744     return 0;
1745 }
1746
1747 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1748                                   target_ulong len, int type)
1749 {
1750     int n;
1751
1752     n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
1753     if (n < 0) {
1754         return -ENOENT;
1755     }
1756     nb_hw_breakpoint--;
1757     hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
1758
1759     return 0;
1760 }
1761
1762 void kvm_arch_remove_all_hw_breakpoints(void)
1763 {
1764     nb_hw_breakpoint = 0;
1765 }
1766
1767 static CPUWatchpoint hw_watchpoint;
1768
1769 static int kvm_handle_debug(struct kvm_debug_exit_arch *arch_info)
1770 {
1771     int ret = 0;
1772     int n;
1773
1774     if (arch_info->exception == 1) {
1775         if (arch_info->dr6 & (1 << 14)) {
1776             if (cpu_single_env->singlestep_enabled) {
1777                 ret = EXCP_DEBUG;
1778             }
1779         } else {
1780             for (n = 0; n < 4; n++) {
1781                 if (arch_info->dr6 & (1 << n)) {
1782                     switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
1783                     case 0x0:
1784                         ret = EXCP_DEBUG;
1785                         break;
1786                     case 0x1:
1787                         ret = EXCP_DEBUG;
1788                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1789                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1790                         hw_watchpoint.flags = BP_MEM_WRITE;
1791                         break;
1792                     case 0x3:
1793                         ret = EXCP_DEBUG;
1794                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1795                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1796                         hw_watchpoint.flags = BP_MEM_ACCESS;
1797                         break;
1798                     }
1799                 }
1800             }
1801         }
1802     } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc)) {
1803         ret = EXCP_DEBUG;
1804     }
1805     if (ret == 0) {
1806         cpu_synchronize_state(cpu_single_env);
1807         assert(cpu_single_env->exception_injected == -1);
1808
1809         /* pass to guest */
1810         cpu_single_env->exception_injected = arch_info->exception;
1811         cpu_single_env->has_error_code = 0;
1812     }
1813
1814     return ret;
1815 }
1816
1817 void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg)
1818 {
1819     const uint8_t type_code[] = {
1820         [GDB_BREAKPOINT_HW] = 0x0,
1821         [GDB_WATCHPOINT_WRITE] = 0x1,
1822         [GDB_WATCHPOINT_ACCESS] = 0x3
1823     };
1824     const uint8_t len_code[] = {
1825         [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
1826     };
1827     int n;
1828
1829     if (kvm_sw_breakpoints_active(env)) {
1830         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1831     }
1832     if (nb_hw_breakpoint > 0) {
1833         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1834         dbg->arch.debugreg[7] = 0x0600;
1835         for (n = 0; n < nb_hw_breakpoint; n++) {
1836             dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
1837             dbg->arch.debugreg[7] |= (2 << (n * 2)) |
1838                 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
1839                 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
1840         }
1841     }
1842 }
1843 #endif /* KVM_CAP_SET_GUEST_DEBUG */
1844
1845 static bool host_supports_vmx(void)
1846 {
1847     uint32_t ecx, unused;
1848
1849     host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
1850     return ecx & CPUID_EXT_VMX;
1851 }
1852
1853 #define VMX_INVALID_GUEST_STATE 0x80000021
1854
1855 int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
1856 {
1857     uint64_t code;
1858     int ret;
1859
1860     switch (run->exit_reason) {
1861     case KVM_EXIT_HLT:
1862         DPRINTF("handle_hlt\n");
1863         ret = kvm_handle_halt(env);
1864         break;
1865     case KVM_EXIT_SET_TPR:
1866         ret = 0;
1867         break;
1868     case KVM_EXIT_FAIL_ENTRY:
1869         code = run->fail_entry.hardware_entry_failure_reason;
1870         fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
1871                 code);
1872         if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
1873             fprintf(stderr,
1874                     "\nIf you're runnning a guest on an Intel machine without "
1875                         "unrestricted mode\n"
1876                     "support, the failure can be most likely due to the guest "
1877                         "entering an invalid\n"
1878                     "state for Intel VT. For example, the guest maybe running "
1879                         "in big real mode\n"
1880                     "which is not supported on less recent Intel processors."
1881                         "\n\n");
1882         }
1883         ret = -1;
1884         break;
1885     case KVM_EXIT_EXCEPTION:
1886         fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
1887                 run->ex.exception, run->ex.error_code);
1888         ret = -1;
1889         break;
1890 #ifdef KVM_CAP_SET_GUEST_DEBUG
1891     case KVM_EXIT_DEBUG:
1892         DPRINTF("kvm_exit_debug\n");
1893         ret = kvm_handle_debug(&run->debug.arch);
1894         break;
1895 #endif /* KVM_CAP_SET_GUEST_DEBUG */
1896     default:
1897         fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
1898         ret = -1;
1899         break;
1900     }
1901
1902     return ret;
1903 }
1904
1905 bool kvm_arch_stop_on_emulation_error(CPUState *env)
1906 {
1907     return !(env->cr[0] & CR0_PE_MASK) ||
1908            ((env->segs[R_CS].selector  & 3) != 3);
1909 }