2 #include "exec/gdbstub.h"
4 #include "qemu/host-utils.h"
5 #include "sysemu/arch_init.h"
6 #include "sysemu/sysemu.h"
7 #include "qemu/bitops.h"
9 #ifndef CONFIG_USER_ONLY
10 static inline int get_phys_addr(CPUARMState
*env
, uint32_t address
,
11 int access_type
, int is_user
,
12 hwaddr
*phys_ptr
, int *prot
,
13 target_ulong
*page_size
);
16 static int vfp_gdb_get_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
20 /* VFP data registers are always little-endian. */
21 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
23 stfq_le_p(buf
, env
->vfp
.regs
[reg
]);
26 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
27 /* Aliases for Q regs. */
30 stfq_le_p(buf
, env
->vfp
.regs
[(reg
- 32) * 2]);
31 stfq_le_p(buf
+ 8, env
->vfp
.regs
[(reg
- 32) * 2 + 1]);
35 switch (reg
- nregs
) {
36 case 0: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSID
]); return 4;
37 case 1: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSCR
]); return 4;
38 case 2: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPEXC
]); return 4;
43 static int vfp_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
47 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
49 env
->vfp
.regs
[reg
] = ldfq_le_p(buf
);
52 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
55 env
->vfp
.regs
[(reg
- 32) * 2] = ldfq_le_p(buf
);
56 env
->vfp
.regs
[(reg
- 32) * 2 + 1] = ldfq_le_p(buf
+ 8);
60 switch (reg
- nregs
) {
61 case 0: env
->vfp
.xregs
[ARM_VFP_FPSID
] = ldl_p(buf
); return 4;
62 case 1: env
->vfp
.xregs
[ARM_VFP_FPSCR
] = ldl_p(buf
); return 4;
63 case 2: env
->vfp
.xregs
[ARM_VFP_FPEXC
] = ldl_p(buf
) & (1 << 30); return 4;
68 static int raw_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
71 if (ri
->type
& ARM_CP_64BIT
) {
72 *value
= CPREG_FIELD64(env
, ri
);
74 *value
= CPREG_FIELD32(env
, ri
);
79 static int raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
82 if (ri
->type
& ARM_CP_64BIT
) {
83 CPREG_FIELD64(env
, ri
) = value
;
85 CPREG_FIELD32(env
, ri
) = value
;
90 static bool read_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
93 /* Raw read of a coprocessor register (as needed for migration, etc)
94 * return true on success, false if the read is impossible for some reason.
96 if (ri
->type
& ARM_CP_CONST
) {
98 } else if (ri
->raw_readfn
) {
99 return (ri
->raw_readfn(env
, ri
, v
) == 0);
100 } else if (ri
->readfn
) {
101 return (ri
->readfn(env
, ri
, v
) == 0);
103 if (ri
->type
& ARM_CP_64BIT
) {
104 *v
= CPREG_FIELD64(env
, ri
);
106 *v
= CPREG_FIELD32(env
, ri
);
112 static bool write_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
115 /* Raw write of a coprocessor register (as needed for migration, etc).
116 * Return true on success, false if the write is impossible for some reason.
117 * Note that constant registers are treated as write-ignored; the
118 * caller should check for success by whether a readback gives the
121 if (ri
->type
& ARM_CP_CONST
) {
123 } else if (ri
->raw_writefn
) {
124 return (ri
->raw_writefn(env
, ri
, v
) == 0);
125 } else if (ri
->writefn
) {
126 return (ri
->writefn(env
, ri
, v
) == 0);
128 if (ri
->type
& ARM_CP_64BIT
) {
129 CPREG_FIELD64(env
, ri
) = v
;
131 CPREG_FIELD32(env
, ri
) = v
;
137 bool write_cpustate_to_list(ARMCPU
*cpu
)
139 /* Write the coprocessor state from cpu->env to the (index,value) list. */
143 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
144 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
145 const ARMCPRegInfo
*ri
;
147 ri
= get_arm_cp_reginfo(cpu
, regidx
);
152 if (ri
->type
& ARM_CP_NO_MIGRATE
) {
155 if (!read_raw_cp_reg(&cpu
->env
, ri
, &v
)) {
159 cpu
->cpreg_values
[i
] = v
;
164 bool write_list_to_cpustate(ARMCPU
*cpu
)
169 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
170 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
171 uint64_t v
= cpu
->cpreg_values
[i
];
173 const ARMCPRegInfo
*ri
;
175 ri
= get_arm_cp_reginfo(cpu
, regidx
);
180 if (ri
->type
& ARM_CP_NO_MIGRATE
) {
183 /* Write value and confirm it reads back as written
184 * (to catch read-only registers and partially read-only
185 * registers where the incoming migration value doesn't match)
187 if (!write_raw_cp_reg(&cpu
->env
, ri
, v
) ||
188 !read_raw_cp_reg(&cpu
->env
, ri
, &readback
) ||
196 static void add_cpreg_to_list(gpointer key
, gpointer opaque
)
198 ARMCPU
*cpu
= opaque
;
200 const ARMCPRegInfo
*ri
;
202 regidx
= *(uint32_t *)key
;
203 ri
= get_arm_cp_reginfo(cpu
, regidx
);
205 if (!(ri
->type
& ARM_CP_NO_MIGRATE
)) {
206 cpu
->cpreg_indexes
[cpu
->cpreg_array_len
] = cpreg_to_kvm_id(regidx
);
207 /* The value array need not be initialized at this point */
208 cpu
->cpreg_array_len
++;
212 static void count_cpreg(gpointer key
, gpointer opaque
)
214 ARMCPU
*cpu
= opaque
;
216 const ARMCPRegInfo
*ri
;
218 regidx
= *(uint32_t *)key
;
219 ri
= get_arm_cp_reginfo(cpu
, regidx
);
221 if (!(ri
->type
& ARM_CP_NO_MIGRATE
)) {
222 cpu
->cpreg_array_len
++;
226 static gint
cpreg_key_compare(gconstpointer a
, gconstpointer b
)
228 uint64_t aidx
= cpreg_to_kvm_id(*(uint32_t *)a
);
229 uint64_t bidx
= cpreg_to_kvm_id(*(uint32_t *)b
);
240 static void cpreg_make_keylist(gpointer key
, gpointer value
, gpointer udata
)
242 GList
**plist
= udata
;
244 *plist
= g_list_prepend(*plist
, key
);
247 void init_cpreg_list(ARMCPU
*cpu
)
249 /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
250 * Note that we require cpreg_tuples[] to be sorted by key ID.
255 g_hash_table_foreach(cpu
->cp_regs
, cpreg_make_keylist
, &keys
);
257 keys
= g_list_sort(keys
, cpreg_key_compare
);
259 cpu
->cpreg_array_len
= 0;
261 g_list_foreach(keys
, count_cpreg
, cpu
);
263 arraylen
= cpu
->cpreg_array_len
;
264 cpu
->cpreg_indexes
= g_new(uint64_t, arraylen
);
265 cpu
->cpreg_values
= g_new(uint64_t, arraylen
);
266 cpu
->cpreg_vmstate_indexes
= g_new(uint64_t, arraylen
);
267 cpu
->cpreg_vmstate_values
= g_new(uint64_t, arraylen
);
268 cpu
->cpreg_vmstate_array_len
= cpu
->cpreg_array_len
;
269 cpu
->cpreg_array_len
= 0;
271 g_list_foreach(keys
, add_cpreg_to_list
, cpu
);
273 assert(cpu
->cpreg_array_len
== arraylen
);
278 static int dacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
280 env
->cp15
.c3
= value
;
281 tlb_flush(env
, 1); /* Flush TLB as domain not tracked in TLB */
285 static int fcse_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
287 if (env
->cp15
.c13_fcse
!= value
) {
288 /* Unlike real hardware the qemu TLB uses virtual addresses,
289 * not modified virtual addresses, so this causes a TLB flush.
292 env
->cp15
.c13_fcse
= value
;
296 static int contextidr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
299 if (env
->cp15
.c13_context
!= value
&& !arm_feature(env
, ARM_FEATURE_MPU
)) {
300 /* For VMSA (when not using the LPAE long descriptor page table
301 * format) this register includes the ASID, so do a TLB flush.
302 * For PMSA it is purely a process ID and no action is needed.
306 env
->cp15
.c13_context
= value
;
310 static int tlbiall_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
313 /* Invalidate all (TLBIALL) */
318 static int tlbimva_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
321 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
322 tlb_flush_page(env
, value
& TARGET_PAGE_MASK
);
326 static int tlbiasid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
329 /* Invalidate by ASID (TLBIASID) */
330 tlb_flush(env
, value
== 0);
334 static int tlbimvaa_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
337 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
338 tlb_flush_page(env
, value
& TARGET_PAGE_MASK
);
342 static const ARMCPRegInfo cp_reginfo
[] = {
343 /* DBGDIDR: just RAZ. In particular this means the "debug architecture
344 * version" bits will read as a reserved value, which should cause
345 * Linux to not try to use the debug hardware.
347 { .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
348 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
349 /* MMU Domain access control / MPU write buffer control */
350 { .name
= "DACR", .cp
= 15,
351 .crn
= 3, .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
352 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c3
),
353 .resetvalue
= 0, .writefn
= dacr_write
, .raw_writefn
= raw_write
, },
354 { .name
= "FCSEIDR", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 0,
355 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c13_fcse
),
356 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
357 { .name
= "CONTEXTIDR", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 1,
358 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c13_fcse
),
359 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
360 /* ??? This covers not just the impdef TLB lockdown registers but also
361 * some v7VMSA registers relating to TEX remap, so it is overly broad.
363 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= CP_ANY
,
364 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
365 /* MMU TLB control. Note that the wildcarding means we cover not just
366 * the unified TLB ops but also the dside/iside/inner-shareable variants.
368 { .name
= "TLBIALL", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
369 .opc1
= CP_ANY
, .opc2
= 0, .access
= PL1_W
, .writefn
= tlbiall_write
,
370 .type
= ARM_CP_NO_MIGRATE
},
371 { .name
= "TLBIMVA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
372 .opc1
= CP_ANY
, .opc2
= 1, .access
= PL1_W
, .writefn
= tlbimva_write
,
373 .type
= ARM_CP_NO_MIGRATE
},
374 { .name
= "TLBIASID", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
375 .opc1
= CP_ANY
, .opc2
= 2, .access
= PL1_W
, .writefn
= tlbiasid_write
,
376 .type
= ARM_CP_NO_MIGRATE
},
377 { .name
= "TLBIMVAA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
378 .opc1
= CP_ANY
, .opc2
= 3, .access
= PL1_W
, .writefn
= tlbimvaa_write
,
379 .type
= ARM_CP_NO_MIGRATE
},
380 /* Cache maintenance ops; some of this space may be overridden later. */
381 { .name
= "CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
382 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
383 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
},
387 static const ARMCPRegInfo not_v6_cp_reginfo
[] = {
388 /* Not all pre-v6 cores implemented this WFI, so this is slightly
391 { .name
= "WFI_v5", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= 2,
392 .access
= PL1_W
, .type
= ARM_CP_WFI
},
396 static const ARMCPRegInfo not_v7_cp_reginfo
[] = {
397 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
398 * is UNPREDICTABLE; we choose to NOP as most implementations do).
400 { .name
= "WFI_v6", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
401 .access
= PL1_W
, .type
= ARM_CP_WFI
},
402 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
403 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
404 * OMAPCP will override this space.
406 { .name
= "DLOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 0,
407 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_data
),
409 { .name
= "ILOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 1,
410 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_insn
),
412 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
413 { .name
= "DUMMY", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= CP_ANY
,
414 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_MIGRATE
,
419 static int cpacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
421 if (env
->cp15
.c1_coproc
!= value
) {
422 env
->cp15
.c1_coproc
= value
;
423 /* ??? Is this safe when called from within a TB? */
429 static const ARMCPRegInfo v6_cp_reginfo
[] = {
430 /* prefetch by MVA in v6, NOP in v7 */
431 { .name
= "MVA_prefetch",
432 .cp
= 15, .crn
= 7, .crm
= 13, .opc1
= 0, .opc2
= 1,
433 .access
= PL1_W
, .type
= ARM_CP_NOP
},
434 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 5, .opc1
= 0, .opc2
= 4,
435 .access
= PL0_W
, .type
= ARM_CP_NOP
},
436 { .name
= "DSB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 4,
437 .access
= PL0_W
, .type
= ARM_CP_NOP
},
438 { .name
= "DMB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 5,
439 .access
= PL0_W
, .type
= ARM_CP_NOP
},
440 { .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 2,
441 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_insn
),
443 /* Watchpoint Fault Address Register : should actually only be present
444 * for 1136, 1176, 11MPCore.
446 { .name
= "WFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
447 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0, },
448 { .name
= "CPACR", .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 2,
449 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_coproc
),
450 .resetvalue
= 0, .writefn
= cpacr_write
},
455 static int pmreg_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
458 /* Generic performance monitor register read function for where
459 * user access may be allowed by PMUSERENR.
461 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
464 *value
= CPREG_FIELD32(env
, ri
);
468 static int pmcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
471 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
474 /* only the DP, X, D and E bits are writable */
475 env
->cp15
.c9_pmcr
&= ~0x39;
476 env
->cp15
.c9_pmcr
|= (value
& 0x39);
480 static int pmcntenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
483 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
487 env
->cp15
.c9_pmcnten
|= value
;
491 static int pmcntenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
494 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
498 env
->cp15
.c9_pmcnten
&= ~value
;
502 static int pmovsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
505 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
508 env
->cp15
.c9_pmovsr
&= ~value
;
512 static int pmxevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
515 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
518 env
->cp15
.c9_pmxevtyper
= value
& 0xff;
522 static int pmuserenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
525 env
->cp15
.c9_pmuserenr
= value
& 1;
529 static int pmintenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
532 /* We have no event counters so only the C bit can be changed */
534 env
->cp15
.c9_pminten
|= value
;
538 static int pmintenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
542 env
->cp15
.c9_pminten
&= ~value
;
546 static int vbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
549 env
->cp15
.c12_vbar
= value
& ~0x1Ful
;
553 static int ccsidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
556 ARMCPU
*cpu
= arm_env_get_cpu(env
);
557 *value
= cpu
->ccsidr
[env
->cp15
.c0_cssel
];
561 static int csselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
564 env
->cp15
.c0_cssel
= value
& 0xf;
568 static const ARMCPRegInfo v7_cp_reginfo
[] = {
569 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
572 { .name
= "DBGDRAR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 0,
573 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
574 { .name
= "DBGDSAR", .cp
= 14, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
575 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
576 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
577 { .name
= "NOP", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
578 .access
= PL1_W
, .type
= ARM_CP_NOP
},
579 /* Performance monitors are implementation defined in v7,
580 * but with an ARM recommended set of registers, which we
581 * follow (although we don't actually implement any counters)
583 * Performance registers fall into three categories:
584 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
585 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
586 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
587 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
588 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
590 { .name
= "PMCNTENSET", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 1,
591 .access
= PL0_RW
, .resetvalue
= 0,
592 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
593 .readfn
= pmreg_read
, .writefn
= pmcntenset_write
,
594 .raw_readfn
= raw_read
, .raw_writefn
= raw_write
},
595 { .name
= "PMCNTENCLR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 2,
596 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
597 .readfn
= pmreg_read
, .writefn
= pmcntenclr_write
,
598 .type
= ARM_CP_NO_MIGRATE
},
599 { .name
= "PMOVSR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 3,
600 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
601 .readfn
= pmreg_read
, .writefn
= pmovsr_write
,
602 .raw_readfn
= raw_read
, .raw_writefn
= raw_write
},
603 /* Unimplemented so WI. Strictly speaking write accesses in PL0 should
606 { .name
= "PMSWINC", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 4,
607 .access
= PL0_W
, .type
= ARM_CP_NOP
},
608 /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
609 * We choose to RAZ/WI. XXX should respect PMUSERENR.
611 { .name
= "PMSELR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 5,
612 .access
= PL0_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
613 /* Unimplemented, RAZ/WI. XXX PMUSERENR */
614 { .name
= "PMCCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 0,
615 .access
= PL0_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
616 { .name
= "PMXEVTYPER", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 1,
618 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmxevtyper
),
619 .readfn
= pmreg_read
, .writefn
= pmxevtyper_write
,
620 .raw_readfn
= raw_read
, .raw_writefn
= raw_write
},
621 /* Unimplemented, RAZ/WI. XXX PMUSERENR */
622 { .name
= "PMXEVCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 2,
623 .access
= PL0_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
624 { .name
= "PMUSERENR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 0,
625 .access
= PL0_R
| PL1_RW
,
626 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmuserenr
),
628 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
629 { .name
= "PMINTENSET", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 1,
631 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
633 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
},
634 { .name
= "PMINTENCLR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 2,
635 .access
= PL1_RW
, .type
= ARM_CP_NO_MIGRATE
,
636 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
637 .resetvalue
= 0, .writefn
= pmintenclr_write
, },
638 { .name
= "VBAR", .cp
= 15, .crn
= 12, .crm
= 0, .opc1
= 0, .opc2
= 0,
639 .access
= PL1_RW
, .writefn
= vbar_write
,
640 .fieldoffset
= offsetof(CPUARMState
, cp15
.c12_vbar
),
642 { .name
= "SCR", .cp
= 15, .crn
= 1, .crm
= 1, .opc1
= 0, .opc2
= 0,
643 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_scr
),
645 { .name
= "CCSIDR", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 0,
646 .access
= PL1_R
, .readfn
= ccsidr_read
, .type
= ARM_CP_NO_MIGRATE
},
647 { .name
= "CSSELR", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 2, .opc2
= 0,
648 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cssel
),
649 .writefn
= csselr_write
, .resetvalue
= 0 },
650 /* Auxiliary ID register: this actually has an IMPDEF value but for now
651 * just RAZ for all cores:
653 { .name
= "AIDR", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 7,
654 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
658 static int teecr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
665 static int teehbr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
668 /* This is a helper function because the user access rights
669 * depend on the value of the TEECR.
671 if (arm_current_pl(env
) == 0 && (env
->teecr
& 1)) {
674 *value
= env
->teehbr
;
678 static int teehbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
681 if (arm_current_pl(env
) == 0 && (env
->teecr
& 1)) {
688 static const ARMCPRegInfo t2ee_cp_reginfo
[] = {
689 { .name
= "TEECR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 6, .opc2
= 0,
690 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, teecr
),
692 .writefn
= teecr_write
},
693 { .name
= "TEEHBR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 6, .opc2
= 0,
694 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, teehbr
),
695 .resetvalue
= 0, .raw_readfn
= raw_read
, .raw_writefn
= raw_write
,
696 .readfn
= teehbr_read
, .writefn
= teehbr_write
},
700 static const ARMCPRegInfo v6k_cp_reginfo
[] = {
701 { .name
= "TPIDRURW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 2,
703 .fieldoffset
= offsetof(CPUARMState
, cp15
.c13_tls1
),
705 { .name
= "TPIDRURO", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 3,
706 .access
= PL0_R
|PL1_W
,
707 .fieldoffset
= offsetof(CPUARMState
, cp15
.c13_tls2
),
709 { .name
= "TPIDRPRW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 4,
711 .fieldoffset
= offsetof(CPUARMState
, cp15
.c13_tls3
),
716 #ifndef CONFIG_USER_ONLY
718 static uint64_t gt_get_countervalue(CPUARMState
*env
)
720 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) / GTIMER_SCALE
;
723 static void gt_recalc_timer(ARMCPU
*cpu
, int timeridx
)
725 ARMGenericTimer
*gt
= &cpu
->env
.cp15
.c14_timer
[timeridx
];
728 /* Timer enabled: calculate and set current ISTATUS, irq, and
729 * reset timer to when ISTATUS next has to change
731 uint64_t count
= gt_get_countervalue(&cpu
->env
);
732 /* Note that this must be unsigned 64 bit arithmetic: */
733 int istatus
= count
>= gt
->cval
;
736 gt
->ctl
= deposit32(gt
->ctl
, 2, 1, istatus
);
737 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
],
738 (istatus
&& !(gt
->ctl
& 2)));
740 /* Next transition is when count rolls back over to zero */
741 nexttick
= UINT64_MAX
;
743 /* Next transition is when we hit cval */
746 /* Note that the desired next expiry time might be beyond the
747 * signed-64-bit range of a QEMUTimer -- in this case we just
748 * set the timer for as far in the future as possible. When the
749 * timer expires we will reset the timer for any remaining period.
751 if (nexttick
> INT64_MAX
/ GTIMER_SCALE
) {
752 nexttick
= INT64_MAX
/ GTIMER_SCALE
;
754 timer_mod(cpu
->gt_timer
[timeridx
], nexttick
);
756 /* Timer disabled: ISTATUS and timer output always clear */
758 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], 0);
759 timer_del(cpu
->gt_timer
[timeridx
]);
763 static int gt_cntfrq_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
766 /* Not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero */
767 if (arm_current_pl(env
) == 0 && !extract32(env
->cp15
.c14_cntkctl
, 0, 2)) {
770 *value
= env
->cp15
.c14_cntfrq
;
774 static void gt_cnt_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
776 ARMCPU
*cpu
= arm_env_get_cpu(env
);
777 int timeridx
= ri
->opc1
& 1;
779 timer_del(cpu
->gt_timer
[timeridx
]);
782 static int gt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
785 int timeridx
= ri
->opc1
& 1;
787 if (arm_current_pl(env
) == 0 &&
788 !extract32(env
->cp15
.c14_cntkctl
, timeridx
, 1)) {
791 *value
= gt_get_countervalue(env
);
795 static int gt_cval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
798 int timeridx
= ri
->opc1
& 1;
800 if (arm_current_pl(env
) == 0 &&
801 !extract32(env
->cp15
.c14_cntkctl
, 9 - timeridx
, 1)) {
804 *value
= env
->cp15
.c14_timer
[timeridx
].cval
;
808 static int gt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
811 int timeridx
= ri
->opc1
& 1;
813 env
->cp15
.c14_timer
[timeridx
].cval
= value
;
814 gt_recalc_timer(arm_env_get_cpu(env
), timeridx
);
817 static int gt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
820 int timeridx
= ri
->crm
& 1;
822 if (arm_current_pl(env
) == 0 &&
823 !extract32(env
->cp15
.c14_cntkctl
, 9 - timeridx
, 1)) {
826 *value
= (uint32_t)(env
->cp15
.c14_timer
[timeridx
].cval
-
827 gt_get_countervalue(env
));
831 static int gt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
834 int timeridx
= ri
->crm
& 1;
836 env
->cp15
.c14_timer
[timeridx
].cval
= gt_get_countervalue(env
) +
837 + sextract64(value
, 0, 32);
838 gt_recalc_timer(arm_env_get_cpu(env
), timeridx
);
842 static int gt_ctl_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
845 int timeridx
= ri
->crm
& 1;
847 if (arm_current_pl(env
) == 0 &&
848 !extract32(env
->cp15
.c14_cntkctl
, 9 - timeridx
, 1)) {
851 *value
= env
->cp15
.c14_timer
[timeridx
].ctl
;
855 static int gt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
858 ARMCPU
*cpu
= arm_env_get_cpu(env
);
859 int timeridx
= ri
->crm
& 1;
860 uint32_t oldval
= env
->cp15
.c14_timer
[timeridx
].ctl
;
862 env
->cp15
.c14_timer
[timeridx
].ctl
= value
& 3;
863 if ((oldval
^ value
) & 1) {
865 gt_recalc_timer(cpu
, timeridx
);
866 } else if ((oldval
& value
) & 2) {
867 /* IMASK toggled: don't need to recalculate,
868 * just set the interrupt line based on ISTATUS
870 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
],
871 (oldval
& 4) && (value
& 2));
876 void arm_gt_ptimer_cb(void *opaque
)
878 ARMCPU
*cpu
= opaque
;
880 gt_recalc_timer(cpu
, GTIMER_PHYS
);
883 void arm_gt_vtimer_cb(void *opaque
)
885 ARMCPU
*cpu
= opaque
;
887 gt_recalc_timer(cpu
, GTIMER_VIRT
);
890 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
891 /* Note that CNTFRQ is purely reads-as-written for the benefit
892 * of software; writing it doesn't actually change the timer frequency.
893 * Our reset value matches the fixed frequency we implement the timer at.
895 { .name
= "CNTFRQ", .cp
= 15, .crn
= 14, .crm
= 0, .opc1
= 0, .opc2
= 0,
896 .access
= PL1_RW
| PL0_R
,
897 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
898 .resetvalue
= (1000 * 1000 * 1000) / GTIMER_SCALE
,
899 .readfn
= gt_cntfrq_read
, .raw_readfn
= raw_read
,
901 /* overall control: mostly access permissions */
902 { .name
= "CNTKCTL", .cp
= 15, .crn
= 14, .crm
= 1, .opc1
= 0, .opc2
= 0,
904 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntkctl
),
907 /* per-timer control */
908 { .name
= "CNTP_CTL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
909 .type
= ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
910 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
912 .readfn
= gt_ctl_read
, .writefn
= gt_ctl_write
,
913 .raw_readfn
= raw_read
, .raw_writefn
= raw_write
,
915 { .name
= "CNTV_CTL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 1,
916 .type
= ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
917 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
919 .readfn
= gt_ctl_read
, .writefn
= gt_ctl_write
,
920 .raw_readfn
= raw_read
, .raw_writefn
= raw_write
,
922 /* TimerValue views: a 32 bit downcounting view of the underlying state */
923 { .name
= "CNTP_TVAL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
924 .type
= ARM_CP_NO_MIGRATE
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
925 .readfn
= gt_tval_read
, .writefn
= gt_tval_write
,
927 { .name
= "CNTV_TVAL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 0,
928 .type
= ARM_CP_NO_MIGRATE
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
929 .readfn
= gt_tval_read
, .writefn
= gt_tval_write
,
931 /* The counter itself */
932 { .name
= "CNTPCT", .cp
= 15, .crm
= 14, .opc1
= 0,
933 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_MIGRATE
| ARM_CP_IO
,
934 .readfn
= gt_cnt_read
, .resetfn
= gt_cnt_reset
,
936 { .name
= "CNTVCT", .cp
= 15, .crm
= 14, .opc1
= 1,
937 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_MIGRATE
| ARM_CP_IO
,
938 .readfn
= gt_cnt_read
, .resetfn
= gt_cnt_reset
,
940 /* Comparison value, indicating when the timer goes off */
941 { .name
= "CNTP_CVAL", .cp
= 15, .crm
= 14, .opc1
= 2,
942 .access
= PL1_RW
| PL0_R
,
943 .type
= ARM_CP_64BIT
| ARM_CP_IO
,
944 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
946 .readfn
= gt_cval_read
, .writefn
= gt_cval_write
,
947 .raw_readfn
= raw_read
, .raw_writefn
= raw_write
,
949 { .name
= "CNTV_CVAL", .cp
= 15, .crm
= 14, .opc1
= 3,
950 .access
= PL1_RW
| PL0_R
,
951 .type
= ARM_CP_64BIT
| ARM_CP_IO
,
952 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
954 .readfn
= gt_cval_read
, .writefn
= gt_cval_write
,
955 .raw_readfn
= raw_read
, .raw_writefn
= raw_write
,
961 /* In user-mode none of the generic timer registers are accessible,
962 * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs,
963 * so instead just don't register any of them.
965 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
971 static int par_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
973 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
974 env
->cp15
.c7_par
= value
;
975 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
976 env
->cp15
.c7_par
= value
& 0xfffff6ff;
978 env
->cp15
.c7_par
= value
& 0xfffff1ff;
983 #ifndef CONFIG_USER_ONLY
984 /* get_phys_addr() isn't present for user-mode-only targets */
986 /* Return true if extended addresses are enabled, ie this is an
987 * LPAE implementation and we are using the long-descriptor translation
988 * table format because the TTBCR EAE bit is set.
990 static inline bool extended_addresses_enabled(CPUARMState
*env
)
992 return arm_feature(env
, ARM_FEATURE_LPAE
)
993 && (env
->cp15
.c2_control
& (1U << 31));
996 static int ats_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
999 target_ulong page_size
;
1001 int ret
, is_user
= ri
->opc2
& 2;
1002 int access_type
= ri
->opc2
& 1;
1005 /* Other states are only available with TrustZone */
1008 ret
= get_phys_addr(env
, value
, access_type
, is_user
,
1009 &phys_addr
, &prot
, &page_size
);
1010 if (extended_addresses_enabled(env
)) {
1011 /* ret is a DFSR/IFSR value for the long descriptor
1012 * translation table format, but with WnR always clear.
1013 * Convert it to a 64-bit PAR.
1015 uint64_t par64
= (1 << 11); /* LPAE bit always set */
1017 par64
|= phys_addr
& ~0xfffULL
;
1018 /* We don't set the ATTR or SH fields in the PAR. */
1021 par64
|= (ret
& 0x3f) << 1; /* FS */
1022 /* Note that S2WLK and FSTAGE are always zero, because we don't
1023 * implement virtualization and therefore there can't be a stage 2
1027 env
->cp15
.c7_par
= par64
;
1028 env
->cp15
.c7_par_hi
= par64
>> 32;
1030 /* ret is a DFSR/IFSR value for the short descriptor
1031 * translation table format (with WnR always clear).
1032 * Convert it to a 32-bit PAR.
1035 /* We do not set any attribute bits in the PAR */
1036 if (page_size
== (1 << 24)
1037 && arm_feature(env
, ARM_FEATURE_V7
)) {
1038 env
->cp15
.c7_par
= (phys_addr
& 0xff000000) | 1 << 1;
1040 env
->cp15
.c7_par
= phys_addr
& 0xfffff000;
1043 env
->cp15
.c7_par
= ((ret
& (10 << 1)) >> 5) |
1044 ((ret
& (12 << 1)) >> 6) |
1045 ((ret
& 0xf) << 1) | 1;
1047 env
->cp15
.c7_par_hi
= 0;
1053 static const ARMCPRegInfo vapa_cp_reginfo
[] = {
1054 { .name
= "PAR", .cp
= 15, .crn
= 7, .crm
= 4, .opc1
= 0, .opc2
= 0,
1055 .access
= PL1_RW
, .resetvalue
= 0,
1056 .fieldoffset
= offsetof(CPUARMState
, cp15
.c7_par
),
1057 .writefn
= par_write
},
1058 #ifndef CONFIG_USER_ONLY
1059 { .name
= "ATS", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= CP_ANY
,
1060 .access
= PL1_W
, .writefn
= ats_write
, .type
= ARM_CP_NO_MIGRATE
},
1065 /* Return basic MPU access permission bits. */
1066 static uint32_t simple_mpu_ap_bits(uint32_t val
)
1073 for (i
= 0; i
< 16; i
+= 2) {
1074 ret
|= (val
>> i
) & mask
;
1080 /* Pad basic MPU access permission bits to extended format. */
1081 static uint32_t extended_mpu_ap_bits(uint32_t val
)
1088 for (i
= 0; i
< 16; i
+= 2) {
1089 ret
|= (val
& mask
) << i
;
1095 static int pmsav5_data_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1098 env
->cp15
.c5_data
= extended_mpu_ap_bits(value
);
1102 static int pmsav5_data_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1105 *value
= simple_mpu_ap_bits(env
->cp15
.c5_data
);
1109 static int pmsav5_insn_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1112 env
->cp15
.c5_insn
= extended_mpu_ap_bits(value
);
1116 static int pmsav5_insn_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1119 *value
= simple_mpu_ap_bits(env
->cp15
.c5_insn
);
1123 static int arm946_prbs_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1129 *value
= env
->cp15
.c6_region
[ri
->crm
];
1133 static int arm946_prbs_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1139 env
->cp15
.c6_region
[ri
->crm
] = value
;
1143 static const ARMCPRegInfo pmsav5_cp_reginfo
[] = {
1144 { .name
= "DATA_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
1145 .access
= PL1_RW
, .type
= ARM_CP_NO_MIGRATE
,
1146 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_data
), .resetvalue
= 0,
1147 .readfn
= pmsav5_data_ap_read
, .writefn
= pmsav5_data_ap_write
, },
1148 { .name
= "INSN_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
1149 .access
= PL1_RW
, .type
= ARM_CP_NO_MIGRATE
,
1150 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_insn
), .resetvalue
= 0,
1151 .readfn
= pmsav5_insn_ap_read
, .writefn
= pmsav5_insn_ap_write
, },
1152 { .name
= "DATA_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 2,
1154 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_data
), .resetvalue
= 0, },
1155 { .name
= "INSN_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 3,
1157 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_insn
), .resetvalue
= 0, },
1158 { .name
= "DCACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
1160 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_data
), .resetvalue
= 0, },
1161 { .name
= "ICACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
1163 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_insn
), .resetvalue
= 0, },
1164 /* Protection region base and size registers */
1165 { .name
= "946_PRBS", .cp
= 15, .crn
= 6, .crm
= CP_ANY
, .opc1
= 0,
1166 .opc2
= CP_ANY
, .access
= PL1_RW
,
1167 .readfn
= arm946_prbs_read
, .writefn
= arm946_prbs_write
, },
1171 static int vmsa_ttbcr_raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1174 int maskshift
= extract32(value
, 0, 3);
1176 if (arm_feature(env
, ARM_FEATURE_LPAE
) && (value
& (1 << 31))) {
1177 value
&= ~((7 << 19) | (3 << 14) | (0xf << 3));
1181 /* Note that we always calculate c2_mask and c2_base_mask, but
1182 * they are only used for short-descriptor tables (ie if EAE is 0);
1183 * for long-descriptor tables the TTBCR fields are used differently
1184 * and the c2_mask and c2_base_mask values are meaningless.
1186 env
->cp15
.c2_control
= value
;
1187 env
->cp15
.c2_mask
= ~(((uint32_t)0xffffffffu
) >> maskshift
);
1188 env
->cp15
.c2_base_mask
= ~((uint32_t)0x3fffu
>> maskshift
);
1192 static int vmsa_ttbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1195 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
1196 /* With LPAE the TTBCR could result in a change of ASID
1197 * via the TTBCR.A1 bit, so do a TLB flush.
1201 return vmsa_ttbcr_raw_write(env
, ri
, value
);
1204 static void vmsa_ttbcr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1206 env
->cp15
.c2_base_mask
= 0xffffc000u
;
1207 env
->cp15
.c2_control
= 0;
1208 env
->cp15
.c2_mask
= 0;
1211 static const ARMCPRegInfo vmsa_cp_reginfo
[] = {
1212 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
1214 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_data
), .resetvalue
= 0, },
1215 { .name
= "IFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
1217 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_insn
), .resetvalue
= 0, },
1218 { .name
= "TTBR0", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
1220 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_base0
), .resetvalue
= 0, },
1221 { .name
= "TTBR1", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
1223 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_base1
), .resetvalue
= 0, },
1224 { .name
= "TTBCR", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
1225 .access
= PL1_RW
, .writefn
= vmsa_ttbcr_write
,
1226 .resetfn
= vmsa_ttbcr_reset
, .raw_writefn
= vmsa_ttbcr_raw_write
,
1227 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_control
) },
1228 { .name
= "DFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 0,
1229 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_data
),
1234 static int omap_ticonfig_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1237 env
->cp15
.c15_ticonfig
= value
& 0xe7;
1238 /* The OS_TYPE bit in this register changes the reported CPUID! */
1239 env
->cp15
.c0_cpuid
= (value
& (1 << 5)) ?
1240 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
1244 static int omap_threadid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1247 env
->cp15
.c15_threadid
= value
& 0xffff;
1251 static int omap_wfi_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1254 /* Wait-for-interrupt (deprecated) */
1255 cpu_interrupt(CPU(arm_env_get_cpu(env
)), CPU_INTERRUPT_HALT
);
1259 static int omap_cachemaint_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1262 /* On OMAP there are registers indicating the max/min index of dcache lines
1263 * containing a dirty line; cache flush operations have to reset these.
1265 env
->cp15
.c15_i_max
= 0x000;
1266 env
->cp15
.c15_i_min
= 0xff0;
1270 static const ARMCPRegInfo omap_cp_reginfo
[] = {
1271 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= CP_ANY
,
1272 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_OVERRIDE
,
1273 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_data
), .resetvalue
= 0, },
1274 { .name
= "", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
1275 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
1276 { .name
= "TICONFIG", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
1278 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ticonfig
), .resetvalue
= 0,
1279 .writefn
= omap_ticonfig_write
},
1280 { .name
= "IMAX", .cp
= 15, .crn
= 15, .crm
= 2, .opc1
= 0, .opc2
= 0,
1282 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_max
), .resetvalue
= 0, },
1283 { .name
= "IMIN", .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 0, .opc2
= 0,
1284 .access
= PL1_RW
, .resetvalue
= 0xff0,
1285 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_min
) },
1286 { .name
= "THREADID", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 0, .opc2
= 0,
1288 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_threadid
), .resetvalue
= 0,
1289 .writefn
= omap_threadid_write
},
1290 { .name
= "TI925T_STATUS", .cp
= 15, .crn
= 15,
1291 .crm
= 8, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
1292 .type
= ARM_CP_NO_MIGRATE
,
1293 .readfn
= arm_cp_read_zero
, .writefn
= omap_wfi_write
, },
1294 /* TODO: Peripheral port remap register:
1295 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
1296 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
1299 { .name
= "OMAP_CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
1300 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
1301 .type
= ARM_CP_OVERRIDE
| ARM_CP_NO_MIGRATE
,
1302 .writefn
= omap_cachemaint_write
},
1303 { .name
= "C9", .cp
= 15, .crn
= 9,
1304 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
,
1305 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
, .resetvalue
= 0 },
1309 static int xscale_cpar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1313 if (env
->cp15
.c15_cpar
!= value
) {
1314 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
1316 env
->cp15
.c15_cpar
= value
;
1321 static const ARMCPRegInfo xscale_cp_reginfo
[] = {
1322 { .name
= "XSCALE_CPAR",
1323 .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
1324 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_cpar
), .resetvalue
= 0,
1325 .writefn
= xscale_cpar_write
, },
1326 { .name
= "XSCALE_AUXCR",
1327 .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 1, .access
= PL1_RW
,
1328 .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_xscaleauxcr
),
1333 static const ARMCPRegInfo dummy_c15_cp_reginfo
[] = {
1334 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
1335 * implementation of this implementation-defined space.
1336 * Ideally this should eventually disappear in favour of actually
1337 * implementing the correct behaviour for all cores.
1339 { .name
= "C15_IMPDEF", .cp
= 15, .crn
= 15,
1340 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
1341 .access
= PL1_RW
, .type
= ARM_CP_CONST
| ARM_CP_NO_MIGRATE
,
1346 static const ARMCPRegInfo cache_dirty_status_cp_reginfo
[] = {
1347 /* Cache status: RAZ because we have no cache so it's always clean */
1348 { .name
= "CDSR", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 6,
1349 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_MIGRATE
,
1354 static const ARMCPRegInfo cache_block_ops_cp_reginfo
[] = {
1355 /* We never have a a block transfer operation in progress */
1356 { .name
= "BXSR", .cp
= 15, .crn
= 7, .crm
= 12, .opc1
= 0, .opc2
= 4,
1357 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_MIGRATE
,
1359 /* The cache ops themselves: these all NOP for QEMU */
1360 { .name
= "IICR", .cp
= 15, .crm
= 5, .opc1
= 0,
1361 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
1362 { .name
= "IDCR", .cp
= 15, .crm
= 6, .opc1
= 0,
1363 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
1364 { .name
= "CDCR", .cp
= 15, .crm
= 12, .opc1
= 0,
1365 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
1366 { .name
= "PIR", .cp
= 15, .crm
= 12, .opc1
= 1,
1367 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
1368 { .name
= "PDR", .cp
= 15, .crm
= 12, .opc1
= 2,
1369 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
1370 { .name
= "CIDCR", .cp
= 15, .crm
= 14, .opc1
= 0,
1371 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
1375 static const ARMCPRegInfo cache_test_clean_cp_reginfo
[] = {
1376 /* The cache test-and-clean instructions always return (1 << 30)
1377 * to indicate that there are no dirty cache lines.
1379 { .name
= "TC_DCACHE", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 3,
1380 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_MIGRATE
,
1381 .resetvalue
= (1 << 30) },
1382 { .name
= "TCI_DCACHE", .cp
= 15, .crn
= 7, .crm
= 14, .opc1
= 0, .opc2
= 3,
1383 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_MIGRATE
,
1384 .resetvalue
= (1 << 30) },
1388 static const ARMCPRegInfo strongarm_cp_reginfo
[] = {
1389 /* Ignore ReadBuffer accesses */
1390 { .name
= "C9_READBUFFER", .cp
= 15, .crn
= 9,
1391 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
1392 .access
= PL1_RW
, .resetvalue
= 0,
1393 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
| ARM_CP_NO_MIGRATE
},
1397 static int mpidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1400 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
1401 uint32_t mpidr
= cs
->cpu_index
;
1402 /* We don't support setting cluster ID ([8..11])
1403 * so these bits always RAZ.
1405 if (arm_feature(env
, ARM_FEATURE_V7MP
)) {
1406 mpidr
|= (1U << 31);
1407 /* Cores which are uniprocessor (non-coherent)
1408 * but still implement the MP extensions set
1409 * bit 30. (For instance, A9UP.) However we do
1410 * not currently model any of those cores.
1417 static const ARMCPRegInfo mpidr_cp_reginfo
[] = {
1418 { .name
= "MPIDR", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 5,
1419 .access
= PL1_R
, .readfn
= mpidr_read
, .type
= ARM_CP_NO_MIGRATE
},
1423 static int par64_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t *value
)
1425 *value
= ((uint64_t)env
->cp15
.c7_par_hi
<< 32) | env
->cp15
.c7_par
;
1429 static int par64_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
1431 env
->cp15
.c7_par_hi
= value
>> 32;
1432 env
->cp15
.c7_par
= value
;
1436 static void par64_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1438 env
->cp15
.c7_par_hi
= 0;
1439 env
->cp15
.c7_par
= 0;
1442 static int ttbr064_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1445 *value
= ((uint64_t)env
->cp15
.c2_base0_hi
<< 32) | env
->cp15
.c2_base0
;
1449 static int ttbr064_raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1452 env
->cp15
.c2_base0_hi
= value
>> 32;
1453 env
->cp15
.c2_base0
= value
;
1457 static int ttbr064_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1460 /* Writes to the 64 bit format TTBRs may change the ASID */
1462 return ttbr064_raw_write(env
, ri
, value
);
1465 static void ttbr064_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1467 env
->cp15
.c2_base0_hi
= 0;
1468 env
->cp15
.c2_base0
= 0;
1471 static int ttbr164_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1474 *value
= ((uint64_t)env
->cp15
.c2_base1_hi
<< 32) | env
->cp15
.c2_base1
;
1478 static int ttbr164_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1481 env
->cp15
.c2_base1_hi
= value
>> 32;
1482 env
->cp15
.c2_base1
= value
;
1486 static void ttbr164_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1488 env
->cp15
.c2_base1_hi
= 0;
1489 env
->cp15
.c2_base1
= 0;
1492 static const ARMCPRegInfo lpae_cp_reginfo
[] = {
1493 /* NOP AMAIR0/1: the override is because these clash with the rather
1494 * broadly specified TLB_LOCKDOWN entry in the generic cp_reginfo.
1496 { .name
= "AMAIR0", .cp
= 15, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 0,
1497 .access
= PL1_RW
, .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
,
1499 { .name
= "AMAIR1", .cp
= 15, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 1,
1500 .access
= PL1_RW
, .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
,
1502 /* 64 bit access versions of the (dummy) debug registers */
1503 { .name
= "DBGDRAR", .cp
= 14, .crm
= 1, .opc1
= 0,
1504 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
1505 { .name
= "DBGDSAR", .cp
= 14, .crm
= 2, .opc1
= 0,
1506 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
1507 { .name
= "PAR", .cp
= 15, .crm
= 7, .opc1
= 0,
1508 .access
= PL1_RW
, .type
= ARM_CP_64BIT
,
1509 .readfn
= par64_read
, .writefn
= par64_write
, .resetfn
= par64_reset
},
1510 { .name
= "TTBR0", .cp
= 15, .crm
= 2, .opc1
= 0,
1511 .access
= PL1_RW
, .type
= ARM_CP_64BIT
, .readfn
= ttbr064_read
,
1512 .writefn
= ttbr064_write
, .raw_writefn
= ttbr064_raw_write
,
1513 .resetfn
= ttbr064_reset
},
1514 { .name
= "TTBR1", .cp
= 15, .crm
= 2, .opc1
= 1,
1515 .access
= PL1_RW
, .type
= ARM_CP_64BIT
, .readfn
= ttbr164_read
,
1516 .writefn
= ttbr164_write
, .resetfn
= ttbr164_reset
},
1520 static int sctlr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
1522 env
->cp15
.c1_sys
= value
;
1523 /* ??? Lots of these bits are not implemented. */
1524 /* This may enable/disable the MMU, so do a TLB flush. */
1529 void register_cp_regs_for_features(ARMCPU
*cpu
)
1531 /* Register all the coprocessor registers based on feature bits */
1532 CPUARMState
*env
= &cpu
->env
;
1533 if (arm_feature(env
, ARM_FEATURE_M
)) {
1534 /* M profile has no coprocessor registers */
1538 define_arm_cp_regs(cpu
, cp_reginfo
);
1539 if (arm_feature(env
, ARM_FEATURE_V6
)) {
1540 /* The ID registers all have impdef reset values */
1541 ARMCPRegInfo v6_idregs
[] = {
1542 { .name
= "ID_PFR0", .cp
= 15, .crn
= 0, .crm
= 1,
1543 .opc1
= 0, .opc2
= 0, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1544 .resetvalue
= cpu
->id_pfr0
},
1545 { .name
= "ID_PFR1", .cp
= 15, .crn
= 0, .crm
= 1,
1546 .opc1
= 0, .opc2
= 1, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1547 .resetvalue
= cpu
->id_pfr1
},
1548 { .name
= "ID_DFR0", .cp
= 15, .crn
= 0, .crm
= 1,
1549 .opc1
= 0, .opc2
= 2, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1550 .resetvalue
= cpu
->id_dfr0
},
1551 { .name
= "ID_AFR0", .cp
= 15, .crn
= 0, .crm
= 1,
1552 .opc1
= 0, .opc2
= 3, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1553 .resetvalue
= cpu
->id_afr0
},
1554 { .name
= "ID_MMFR0", .cp
= 15, .crn
= 0, .crm
= 1,
1555 .opc1
= 0, .opc2
= 4, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1556 .resetvalue
= cpu
->id_mmfr0
},
1557 { .name
= "ID_MMFR1", .cp
= 15, .crn
= 0, .crm
= 1,
1558 .opc1
= 0, .opc2
= 5, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1559 .resetvalue
= cpu
->id_mmfr1
},
1560 { .name
= "ID_MMFR2", .cp
= 15, .crn
= 0, .crm
= 1,
1561 .opc1
= 0, .opc2
= 6, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1562 .resetvalue
= cpu
->id_mmfr2
},
1563 { .name
= "ID_MMFR3", .cp
= 15, .crn
= 0, .crm
= 1,
1564 .opc1
= 0, .opc2
= 7, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1565 .resetvalue
= cpu
->id_mmfr3
},
1566 { .name
= "ID_ISAR0", .cp
= 15, .crn
= 0, .crm
= 2,
1567 .opc1
= 0, .opc2
= 0, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1568 .resetvalue
= cpu
->id_isar0
},
1569 { .name
= "ID_ISAR1", .cp
= 15, .crn
= 0, .crm
= 2,
1570 .opc1
= 0, .opc2
= 1, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1571 .resetvalue
= cpu
->id_isar1
},
1572 { .name
= "ID_ISAR2", .cp
= 15, .crn
= 0, .crm
= 2,
1573 .opc1
= 0, .opc2
= 2, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1574 .resetvalue
= cpu
->id_isar2
},
1575 { .name
= "ID_ISAR3", .cp
= 15, .crn
= 0, .crm
= 2,
1576 .opc1
= 0, .opc2
= 3, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1577 .resetvalue
= cpu
->id_isar3
},
1578 { .name
= "ID_ISAR4", .cp
= 15, .crn
= 0, .crm
= 2,
1579 .opc1
= 0, .opc2
= 4, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1580 .resetvalue
= cpu
->id_isar4
},
1581 { .name
= "ID_ISAR5", .cp
= 15, .crn
= 0, .crm
= 2,
1582 .opc1
= 0, .opc2
= 5, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1583 .resetvalue
= cpu
->id_isar5
},
1584 /* 6..7 are as yet unallocated and must RAZ */
1585 { .name
= "ID_ISAR6", .cp
= 15, .crn
= 0, .crm
= 2,
1586 .opc1
= 0, .opc2
= 6, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1588 { .name
= "ID_ISAR7", .cp
= 15, .crn
= 0, .crm
= 2,
1589 .opc1
= 0, .opc2
= 7, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1593 define_arm_cp_regs(cpu
, v6_idregs
);
1594 define_arm_cp_regs(cpu
, v6_cp_reginfo
);
1596 define_arm_cp_regs(cpu
, not_v6_cp_reginfo
);
1598 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
1599 define_arm_cp_regs(cpu
, v6k_cp_reginfo
);
1601 if (arm_feature(env
, ARM_FEATURE_V7
)) {
1602 /* v7 performance monitor control register: same implementor
1603 * field as main ID register, and we implement no event counters.
1605 ARMCPRegInfo pmcr
= {
1606 .name
= "PMCR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 0,
1607 .access
= PL0_RW
, .resetvalue
= cpu
->midr
& 0xff000000,
1608 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcr
),
1609 .readfn
= pmreg_read
, .writefn
= pmcr_write
,
1610 .raw_readfn
= raw_read
, .raw_writefn
= raw_write
,
1612 ARMCPRegInfo clidr
= {
1613 .name
= "CLIDR", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 1,
1614 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->clidr
1616 define_one_arm_cp_reg(cpu
, &pmcr
);
1617 define_one_arm_cp_reg(cpu
, &clidr
);
1618 define_arm_cp_regs(cpu
, v7_cp_reginfo
);
1620 define_arm_cp_regs(cpu
, not_v7_cp_reginfo
);
1622 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1623 /* These are the MPU registers prior to PMSAv6. Any new
1624 * PMSA core later than the ARM946 will require that we
1625 * implement the PMSAv6 or PMSAv7 registers, which are
1626 * completely different.
1628 assert(!arm_feature(env
, ARM_FEATURE_V6
));
1629 define_arm_cp_regs(cpu
, pmsav5_cp_reginfo
);
1631 define_arm_cp_regs(cpu
, vmsa_cp_reginfo
);
1633 if (arm_feature(env
, ARM_FEATURE_THUMB2EE
)) {
1634 define_arm_cp_regs(cpu
, t2ee_cp_reginfo
);
1636 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
1637 define_arm_cp_regs(cpu
, generic_timer_cp_reginfo
);
1639 if (arm_feature(env
, ARM_FEATURE_VAPA
)) {
1640 define_arm_cp_regs(cpu
, vapa_cp_reginfo
);
1642 if (arm_feature(env
, ARM_FEATURE_CACHE_TEST_CLEAN
)) {
1643 define_arm_cp_regs(cpu
, cache_test_clean_cp_reginfo
);
1645 if (arm_feature(env
, ARM_FEATURE_CACHE_DIRTY_REG
)) {
1646 define_arm_cp_regs(cpu
, cache_dirty_status_cp_reginfo
);
1648 if (arm_feature(env
, ARM_FEATURE_CACHE_BLOCK_OPS
)) {
1649 define_arm_cp_regs(cpu
, cache_block_ops_cp_reginfo
);
1651 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
1652 define_arm_cp_regs(cpu
, omap_cp_reginfo
);
1654 if (arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
1655 define_arm_cp_regs(cpu
, strongarm_cp_reginfo
);
1657 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1658 define_arm_cp_regs(cpu
, xscale_cp_reginfo
);
1660 if (arm_feature(env
, ARM_FEATURE_DUMMY_C15_REGS
)) {
1661 define_arm_cp_regs(cpu
, dummy_c15_cp_reginfo
);
1663 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
1664 define_arm_cp_regs(cpu
, lpae_cp_reginfo
);
1666 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
1667 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
1668 * be read-only (ie write causes UNDEF exception).
1671 ARMCPRegInfo id_cp_reginfo
[] = {
1672 /* Note that the MIDR isn't a simple constant register because
1673 * of the TI925 behaviour where writes to another register can
1674 * cause the MIDR value to change.
1676 * Unimplemented registers in the c15 0 0 0 space default to
1677 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
1678 * and friends override accordingly.
1681 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= CP_ANY
,
1682 .access
= PL1_R
, .resetvalue
= cpu
->midr
,
1683 .writefn
= arm_cp_write_ignore
, .raw_writefn
= raw_write
,
1684 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
1685 .type
= ARM_CP_OVERRIDE
},
1687 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 1,
1688 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
1690 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 2,
1691 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1693 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 3,
1694 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1695 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
1697 .cp
= 15, .crn
= 0, .crm
= 3, .opc1
= 0, .opc2
= CP_ANY
,
1698 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1700 .cp
= 15, .crn
= 0, .crm
= 4, .opc1
= 0, .opc2
= CP_ANY
,
1701 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1703 .cp
= 15, .crn
= 0, .crm
= 5, .opc1
= 0, .opc2
= CP_ANY
,
1704 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1706 .cp
= 15, .crn
= 0, .crm
= 6, .opc1
= 0, .opc2
= CP_ANY
,
1707 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1709 .cp
= 15, .crn
= 0, .crm
= 7, .opc1
= 0, .opc2
= CP_ANY
,
1710 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1713 ARMCPRegInfo crn0_wi_reginfo
= {
1714 .name
= "CRN0_WI", .cp
= 15, .crn
= 0, .crm
= CP_ANY
,
1715 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_W
,
1716 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
1718 if (arm_feature(env
, ARM_FEATURE_OMAPCP
) ||
1719 arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
1721 /* Register the blanket "writes ignored" value first to cover the
1722 * whole space. Then update the specific ID registers to allow write
1723 * access, so that they ignore writes rather than causing them to
1726 define_one_arm_cp_reg(cpu
, &crn0_wi_reginfo
);
1727 for (r
= id_cp_reginfo
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
1731 define_arm_cp_regs(cpu
, id_cp_reginfo
);
1734 if (arm_feature(env
, ARM_FEATURE_MPIDR
)) {
1735 define_arm_cp_regs(cpu
, mpidr_cp_reginfo
);
1738 if (arm_feature(env
, ARM_FEATURE_AUXCR
)) {
1739 ARMCPRegInfo auxcr
= {
1740 .name
= "AUXCR", .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 1,
1741 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
1742 .resetvalue
= cpu
->reset_auxcr
1744 define_one_arm_cp_reg(cpu
, &auxcr
);
1747 /* Generic registers whose values depend on the implementation */
1749 ARMCPRegInfo sctlr
= {
1750 .name
= "SCTLR", .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 0,
1751 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_sys
),
1752 .writefn
= sctlr_write
, .resetvalue
= cpu
->reset_sctlr
,
1753 .raw_writefn
= raw_write
,
1755 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1756 /* Normally we would always end the TB on an SCTLR write, but Linux
1757 * arch/arm/mach-pxa/sleep.S expects two instructions following
1758 * an MMU enable to execute from cache. Imitate this behaviour.
1760 sctlr
.type
|= ARM_CP_SUPPRESS_TB_END
;
1762 define_one_arm_cp_reg(cpu
, &sctlr
);
1766 ARMCPU
*cpu_arm_init(const char *cpu_model
)
1771 oc
= cpu_class_by_name(TYPE_ARM_CPU
, cpu_model
);
1775 cpu
= ARM_CPU(object_new(object_class_get_name(oc
)));
1777 /* TODO this should be set centrally, once possible */
1778 object_property_set_bool(OBJECT(cpu
), true, "realized", NULL
);
1783 void arm_cpu_register_gdb_regs_for_features(ARMCPU
*cpu
)
1785 CPUState
*cs
= CPU(cpu
);
1786 CPUARMState
*env
= &cpu
->env
;
1788 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
1789 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
1790 51, "arm-neon.xml", 0);
1791 } else if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
1792 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
1793 35, "arm-vfp3.xml", 0);
1794 } else if (arm_feature(env
, ARM_FEATURE_VFP
)) {
1795 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
1796 19, "arm-vfp.xml", 0);
1800 /* Sort alphabetically by type name, except for "any". */
1801 static gint
arm_cpu_list_compare(gconstpointer a
, gconstpointer b
)
1803 ObjectClass
*class_a
= (ObjectClass
*)a
;
1804 ObjectClass
*class_b
= (ObjectClass
*)b
;
1805 const char *name_a
, *name_b
;
1807 name_a
= object_class_get_name(class_a
);
1808 name_b
= object_class_get_name(class_b
);
1809 if (strcmp(name_a
, "any-" TYPE_ARM_CPU
) == 0) {
1811 } else if (strcmp(name_b
, "any-" TYPE_ARM_CPU
) == 0) {
1814 return strcmp(name_a
, name_b
);
1818 static void arm_cpu_list_entry(gpointer data
, gpointer user_data
)
1820 ObjectClass
*oc
= data
;
1821 CPUListState
*s
= user_data
;
1822 const char *typename
;
1825 typename
= object_class_get_name(oc
);
1826 name
= g_strndup(typename
, strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
1827 (*s
->cpu_fprintf
)(s
->file
, " %s\n",
1832 void arm_cpu_list(FILE *f
, fprintf_function cpu_fprintf
)
1836 .cpu_fprintf
= cpu_fprintf
,
1840 list
= object_class_get_list(TYPE_ARM_CPU
, false);
1841 list
= g_slist_sort(list
, arm_cpu_list_compare
);
1842 (*cpu_fprintf
)(f
, "Available CPUs:\n");
1843 g_slist_foreach(list
, arm_cpu_list_entry
, &s
);
1846 /* The 'host' CPU type is dynamically registered only if KVM is
1847 * enabled, so we have to special-case it here:
1849 (*cpu_fprintf
)(f
, " host (only available in KVM mode)\n");
1853 static void arm_cpu_add_definition(gpointer data
, gpointer user_data
)
1855 ObjectClass
*oc
= data
;
1856 CpuDefinitionInfoList
**cpu_list
= user_data
;
1857 CpuDefinitionInfoList
*entry
;
1858 CpuDefinitionInfo
*info
;
1859 const char *typename
;
1861 typename
= object_class_get_name(oc
);
1862 info
= g_malloc0(sizeof(*info
));
1863 info
->name
= g_strndup(typename
,
1864 strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
1866 entry
= g_malloc0(sizeof(*entry
));
1867 entry
->value
= info
;
1868 entry
->next
= *cpu_list
;
1872 CpuDefinitionInfoList
*arch_query_cpu_definitions(Error
**errp
)
1874 CpuDefinitionInfoList
*cpu_list
= NULL
;
1877 list
= object_class_get_list(TYPE_ARM_CPU
, false);
1878 g_slist_foreach(list
, arm_cpu_add_definition
, &cpu_list
);
1884 void define_one_arm_cp_reg_with_opaque(ARMCPU
*cpu
,
1885 const ARMCPRegInfo
*r
, void *opaque
)
1887 /* Define implementations of coprocessor registers.
1888 * We store these in a hashtable because typically
1889 * there are less than 150 registers in a space which
1890 * is 16*16*16*8*8 = 262144 in size.
1891 * Wildcarding is supported for the crm, opc1 and opc2 fields.
1892 * If a register is defined twice then the second definition is
1893 * used, so this can be used to define some generic registers and
1894 * then override them with implementation specific variations.
1895 * At least one of the original and the second definition should
1896 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
1897 * against accidental use.
1899 int crm
, opc1
, opc2
;
1900 int crmmin
= (r
->crm
== CP_ANY
) ? 0 : r
->crm
;
1901 int crmmax
= (r
->crm
== CP_ANY
) ? 15 : r
->crm
;
1902 int opc1min
= (r
->opc1
== CP_ANY
) ? 0 : r
->opc1
;
1903 int opc1max
= (r
->opc1
== CP_ANY
) ? 7 : r
->opc1
;
1904 int opc2min
= (r
->opc2
== CP_ANY
) ? 0 : r
->opc2
;
1905 int opc2max
= (r
->opc2
== CP_ANY
) ? 7 : r
->opc2
;
1906 /* 64 bit registers have only CRm and Opc1 fields */
1907 assert(!((r
->type
& ARM_CP_64BIT
) && (r
->opc2
|| r
->crn
)));
1908 /* Check that the register definition has enough info to handle
1909 * reads and writes if they are permitted.
1911 if (!(r
->type
& (ARM_CP_SPECIAL
|ARM_CP_CONST
))) {
1912 if (r
->access
& PL3_R
) {
1913 assert(r
->fieldoffset
|| r
->readfn
);
1915 if (r
->access
& PL3_W
) {
1916 assert(r
->fieldoffset
|| r
->writefn
);
1919 /* Bad type field probably means missing sentinel at end of reg list */
1920 assert(cptype_valid(r
->type
));
1921 for (crm
= crmmin
; crm
<= crmmax
; crm
++) {
1922 for (opc1
= opc1min
; opc1
<= opc1max
; opc1
++) {
1923 for (opc2
= opc2min
; opc2
<= opc2max
; opc2
++) {
1924 uint32_t *key
= g_new(uint32_t, 1);
1925 ARMCPRegInfo
*r2
= g_memdup(r
, sizeof(ARMCPRegInfo
));
1926 int is64
= (r
->type
& ARM_CP_64BIT
) ? 1 : 0;
1927 *key
= ENCODE_CP_REG(r
->cp
, is64
, r
->crn
, crm
, opc1
, opc2
);
1929 r2
->opaque
= opaque
;
1931 /* Make sure reginfo passed to helpers for wildcarded regs
1932 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
1937 /* By convention, for wildcarded registers only the first
1938 * entry is used for migration; the others are marked as
1939 * NO_MIGRATE so we don't try to transfer the register
1940 * multiple times. Special registers (ie NOP/WFI) are
1943 if ((r
->type
& ARM_CP_SPECIAL
) ||
1944 ((r
->crm
== CP_ANY
) && crm
!= 0) ||
1945 ((r
->opc1
== CP_ANY
) && opc1
!= 0) ||
1946 ((r
->opc2
== CP_ANY
) && opc2
!= 0)) {
1947 r2
->type
|= ARM_CP_NO_MIGRATE
;
1950 /* Overriding of an existing definition must be explicitly
1953 if (!(r
->type
& ARM_CP_OVERRIDE
)) {
1954 ARMCPRegInfo
*oldreg
;
1955 oldreg
= g_hash_table_lookup(cpu
->cp_regs
, key
);
1956 if (oldreg
&& !(oldreg
->type
& ARM_CP_OVERRIDE
)) {
1957 fprintf(stderr
, "Register redefined: cp=%d %d bit "
1958 "crn=%d crm=%d opc1=%d opc2=%d, "
1959 "was %s, now %s\n", r2
->cp
, 32 + 32 * is64
,
1960 r2
->crn
, r2
->crm
, r2
->opc1
, r2
->opc2
,
1961 oldreg
->name
, r2
->name
);
1962 g_assert_not_reached();
1965 g_hash_table_insert(cpu
->cp_regs
, key
, r2
);
1971 void define_arm_cp_regs_with_opaque(ARMCPU
*cpu
,
1972 const ARMCPRegInfo
*regs
, void *opaque
)
1974 /* Define a whole list of registers */
1975 const ARMCPRegInfo
*r
;
1976 for (r
= regs
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
1977 define_one_arm_cp_reg_with_opaque(cpu
, r
, opaque
);
1981 const ARMCPRegInfo
*get_arm_cp_reginfo(ARMCPU
*cpu
, uint32_t encoded_cp
)
1983 return g_hash_table_lookup(cpu
->cp_regs
, &encoded_cp
);
1986 int arm_cp_write_ignore(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1989 /* Helper coprocessor write function for write-ignore registers */
1993 int arm_cp_read_zero(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t *value
)
1995 /* Helper coprocessor write function for read-as-zero registers */
2000 static int bad_mode_switch(CPUARMState
*env
, int mode
)
2002 /* Return true if it is not valid for us to switch to
2003 * this CPU mode (ie all the UNPREDICTABLE cases in
2004 * the ARM ARM CPSRWriteByInstr pseudocode).
2007 case ARM_CPU_MODE_USR
:
2008 case ARM_CPU_MODE_SYS
:
2009 case ARM_CPU_MODE_SVC
:
2010 case ARM_CPU_MODE_ABT
:
2011 case ARM_CPU_MODE_UND
:
2012 case ARM_CPU_MODE_IRQ
:
2013 case ARM_CPU_MODE_FIQ
:
2020 uint32_t cpsr_read(CPUARMState
*env
)
2023 ZF
= (env
->ZF
== 0);
2024 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
2025 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
2026 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
2027 | ((env
->condexec_bits
& 0xfc) << 8)
2031 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
)
2033 if (mask
& CPSR_NZCV
) {
2034 env
->ZF
= (~val
) & CPSR_Z
;
2036 env
->CF
= (val
>> 29) & 1;
2037 env
->VF
= (val
<< 3) & 0x80000000;
2040 env
->QF
= ((val
& CPSR_Q
) != 0);
2042 env
->thumb
= ((val
& CPSR_T
) != 0);
2043 if (mask
& CPSR_IT_0_1
) {
2044 env
->condexec_bits
&= ~3;
2045 env
->condexec_bits
|= (val
>> 25) & 3;
2047 if (mask
& CPSR_IT_2_7
) {
2048 env
->condexec_bits
&= 3;
2049 env
->condexec_bits
|= (val
>> 8) & 0xfc;
2051 if (mask
& CPSR_GE
) {
2052 env
->GE
= (val
>> 16) & 0xf;
2055 if ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
) {
2056 if (bad_mode_switch(env
, val
& CPSR_M
)) {
2057 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
2058 * We choose to ignore the attempt and leave the CPSR M field
2063 switch_mode(env
, val
& CPSR_M
);
2066 mask
&= ~CACHED_CPSR_BITS
;
2067 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
2070 /* Sign/zero extend */
2071 uint32_t HELPER(sxtb16
)(uint32_t x
)
2074 res
= (uint16_t)(int8_t)x
;
2075 res
|= (uint32_t)(int8_t)(x
>> 16) << 16;
2079 uint32_t HELPER(uxtb16
)(uint32_t x
)
2082 res
= (uint16_t)(uint8_t)x
;
2083 res
|= (uint32_t)(uint8_t)(x
>> 16) << 16;
2087 uint32_t HELPER(clz
)(uint32_t x
)
2092 int32_t HELPER(sdiv
)(int32_t num
, int32_t den
)
2096 if (num
== INT_MIN
&& den
== -1)
2101 uint32_t HELPER(udiv
)(uint32_t num
, uint32_t den
)
2108 uint32_t HELPER(rbit
)(uint32_t x
)
2110 x
= ((x
& 0xff000000) >> 24)
2111 | ((x
& 0x00ff0000) >> 8)
2112 | ((x
& 0x0000ff00) << 8)
2113 | ((x
& 0x000000ff) << 24);
2114 x
= ((x
& 0xf0f0f0f0) >> 4)
2115 | ((x
& 0x0f0f0f0f) << 4);
2116 x
= ((x
& 0x88888888) >> 3)
2117 | ((x
& 0x44444444) >> 1)
2118 | ((x
& 0x22222222) << 1)
2119 | ((x
& 0x11111111) << 3);
2123 #if defined(CONFIG_USER_ONLY)
2125 void arm_cpu_do_interrupt(CPUState
*cs
)
2127 ARMCPU
*cpu
= ARM_CPU(cs
);
2128 CPUARMState
*env
= &cpu
->env
;
2130 env
->exception_index
= -1;
2133 int cpu_arm_handle_mmu_fault (CPUARMState
*env
, target_ulong address
, int rw
,
2137 env
->exception_index
= EXCP_PREFETCH_ABORT
;
2138 env
->cp15
.c6_insn
= address
;
2140 env
->exception_index
= EXCP_DATA_ABORT
;
2141 env
->cp15
.c6_data
= address
;
2146 /* These should probably raise undefined insn exceptions. */
2147 void HELPER(v7m_msr
)(CPUARMState
*env
, uint32_t reg
, uint32_t val
)
2149 cpu_abort(env
, "v7m_mrs %d\n", reg
);
2152 uint32_t HELPER(v7m_mrs
)(CPUARMState
*env
, uint32_t reg
)
2154 cpu_abort(env
, "v7m_mrs %d\n", reg
);
2158 void switch_mode(CPUARMState
*env
, int mode
)
2160 if (mode
!= ARM_CPU_MODE_USR
)
2161 cpu_abort(env
, "Tried to switch out of user mode\n");
2164 void HELPER(set_r13_banked
)(CPUARMState
*env
, uint32_t mode
, uint32_t val
)
2166 cpu_abort(env
, "banked r13 write\n");
2169 uint32_t HELPER(get_r13_banked
)(CPUARMState
*env
, uint32_t mode
)
2171 cpu_abort(env
, "banked r13 read\n");
2177 /* Map CPU modes onto saved register banks. */
2178 int bank_number(int mode
)
2181 case ARM_CPU_MODE_USR
:
2182 case ARM_CPU_MODE_SYS
:
2184 case ARM_CPU_MODE_SVC
:
2186 case ARM_CPU_MODE_ABT
:
2188 case ARM_CPU_MODE_UND
:
2190 case ARM_CPU_MODE_IRQ
:
2192 case ARM_CPU_MODE_FIQ
:
2195 hw_error("bank number requested for bad CPSR mode value 0x%x\n", mode
);
2198 void switch_mode(CPUARMState
*env
, int mode
)
2203 old_mode
= env
->uncached_cpsr
& CPSR_M
;
2204 if (mode
== old_mode
)
2207 if (old_mode
== ARM_CPU_MODE_FIQ
) {
2208 memcpy (env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
2209 memcpy (env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
2210 } else if (mode
== ARM_CPU_MODE_FIQ
) {
2211 memcpy (env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
2212 memcpy (env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
2215 i
= bank_number(old_mode
);
2216 env
->banked_r13
[i
] = env
->regs
[13];
2217 env
->banked_r14
[i
] = env
->regs
[14];
2218 env
->banked_spsr
[i
] = env
->spsr
;
2220 i
= bank_number(mode
);
2221 env
->regs
[13] = env
->banked_r13
[i
];
2222 env
->regs
[14] = env
->banked_r14
[i
];
2223 env
->spsr
= env
->banked_spsr
[i
];
2226 static void v7m_push(CPUARMState
*env
, uint32_t val
)
2229 stl_phys(env
->regs
[13], val
);
2232 static uint32_t v7m_pop(CPUARMState
*env
)
2235 val
= ldl_phys(env
->regs
[13]);
2240 /* Switch to V7M main or process stack pointer. */
2241 static void switch_v7m_sp(CPUARMState
*env
, int process
)
2244 if (env
->v7m
.current_sp
!= process
) {
2245 tmp
= env
->v7m
.other_sp
;
2246 env
->v7m
.other_sp
= env
->regs
[13];
2247 env
->regs
[13] = tmp
;
2248 env
->v7m
.current_sp
= process
;
2252 static void do_v7m_exception_exit(CPUARMState
*env
)
2257 type
= env
->regs
[15];
2258 if (env
->v7m
.exception
!= 0)
2259 armv7m_nvic_complete_irq(env
->nvic
, env
->v7m
.exception
);
2261 /* Switch to the target stack. */
2262 switch_v7m_sp(env
, (type
& 4) != 0);
2263 /* Pop registers. */
2264 env
->regs
[0] = v7m_pop(env
);
2265 env
->regs
[1] = v7m_pop(env
);
2266 env
->regs
[2] = v7m_pop(env
);
2267 env
->regs
[3] = v7m_pop(env
);
2268 env
->regs
[12] = v7m_pop(env
);
2269 env
->regs
[14] = v7m_pop(env
);
2270 env
->regs
[15] = v7m_pop(env
);
2271 xpsr
= v7m_pop(env
);
2272 xpsr_write(env
, xpsr
, 0xfffffdff);
2273 /* Undo stack alignment. */
2276 /* ??? The exception return type specifies Thread/Handler mode. However
2277 this is also implied by the xPSR value. Not sure what to do
2278 if there is a mismatch. */
2279 /* ??? Likewise for mismatches between the CONTROL register and the stack
2283 /* Exception names for debug logging; note that not all of these
2284 * precisely correspond to architectural exceptions.
2286 static const char * const excnames
[] = {
2287 [EXCP_UDEF
] = "Undefined Instruction",
2289 [EXCP_PREFETCH_ABORT
] = "Prefetch Abort",
2290 [EXCP_DATA_ABORT
] = "Data Abort",
2293 [EXCP_BKPT
] = "Breakpoint",
2294 [EXCP_EXCEPTION_EXIT
] = "QEMU v7M exception exit",
2295 [EXCP_KERNEL_TRAP
] = "QEMU intercept of kernel commpage",
2296 [EXCP_STREX
] = "QEMU intercept of STREX",
2299 static inline void arm_log_exception(int idx
)
2301 if (qemu_loglevel_mask(CPU_LOG_INT
)) {
2302 const char *exc
= NULL
;
2304 if (idx
>= 0 && idx
< ARRAY_SIZE(excnames
)) {
2305 exc
= excnames
[idx
];
2310 qemu_log_mask(CPU_LOG_INT
, "Taking exception %d [%s]\n", idx
, exc
);
2314 void arm_v7m_cpu_do_interrupt(CPUState
*cs
)
2316 ARMCPU
*cpu
= ARM_CPU(cs
);
2317 CPUARMState
*env
= &cpu
->env
;
2318 uint32_t xpsr
= xpsr_read(env
);
2322 arm_log_exception(env
->exception_index
);
2325 if (env
->v7m
.current_sp
)
2327 if (env
->v7m
.exception
== 0)
2330 /* For exceptions we just mark as pending on the NVIC, and let that
2332 /* TODO: Need to escalate if the current priority is higher than the
2333 one we're raising. */
2334 switch (env
->exception_index
) {
2336 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
);
2339 /* The PC already points to the next instruction. */
2340 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SVC
);
2342 case EXCP_PREFETCH_ABORT
:
2343 case EXCP_DATA_ABORT
:
2344 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_MEM
);
2347 if (semihosting_enabled
) {
2349 nr
= arm_lduw_code(env
, env
->regs
[15], env
->bswap_code
) & 0xff;
2352 env
->regs
[0] = do_arm_semihosting(env
);
2353 qemu_log_mask(CPU_LOG_INT
, "...handled as semihosting call\n");
2357 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_DEBUG
);
2360 env
->v7m
.exception
= armv7m_nvic_acknowledge_irq(env
->nvic
);
2362 case EXCP_EXCEPTION_EXIT
:
2363 do_v7m_exception_exit(env
);
2366 cpu_abort(env
, "Unhandled exception 0x%x\n", env
->exception_index
);
2367 return; /* Never happens. Keep compiler happy. */
2370 /* Align stack pointer. */
2371 /* ??? Should only do this if Configuration Control Register
2372 STACKALIGN bit is set. */
2373 if (env
->regs
[13] & 4) {
2377 /* Switch to the handler mode. */
2378 v7m_push(env
, xpsr
);
2379 v7m_push(env
, env
->regs
[15]);
2380 v7m_push(env
, env
->regs
[14]);
2381 v7m_push(env
, env
->regs
[12]);
2382 v7m_push(env
, env
->regs
[3]);
2383 v7m_push(env
, env
->regs
[2]);
2384 v7m_push(env
, env
->regs
[1]);
2385 v7m_push(env
, env
->regs
[0]);
2386 switch_v7m_sp(env
, 0);
2388 env
->condexec_bits
= 0;
2390 addr
= ldl_phys(env
->v7m
.vecbase
+ env
->v7m
.exception
* 4);
2391 env
->regs
[15] = addr
& 0xfffffffe;
2392 env
->thumb
= addr
& 1;
2395 /* Handle a CPU exception. */
2396 void arm_cpu_do_interrupt(CPUState
*cs
)
2398 ARMCPU
*cpu
= ARM_CPU(cs
);
2399 CPUARMState
*env
= &cpu
->env
;
2407 arm_log_exception(env
->exception_index
);
2409 /* TODO: Vectored interrupt controller. */
2410 switch (env
->exception_index
) {
2412 new_mode
= ARM_CPU_MODE_UND
;
2421 if (semihosting_enabled
) {
2422 /* Check for semihosting interrupt. */
2424 mask
= arm_lduw_code(env
, env
->regs
[15] - 2, env
->bswap_code
)
2427 mask
= arm_ldl_code(env
, env
->regs
[15] - 4, env
->bswap_code
)
2430 /* Only intercept calls from privileged modes, to provide some
2431 semblance of security. */
2432 if (((mask
== 0x123456 && !env
->thumb
)
2433 || (mask
== 0xab && env
->thumb
))
2434 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
2435 env
->regs
[0] = do_arm_semihosting(env
);
2436 qemu_log_mask(CPU_LOG_INT
, "...handled as semihosting call\n");
2440 new_mode
= ARM_CPU_MODE_SVC
;
2443 /* The PC already points to the next instruction. */
2447 /* See if this is a semihosting syscall. */
2448 if (env
->thumb
&& semihosting_enabled
) {
2449 mask
= arm_lduw_code(env
, env
->regs
[15], env
->bswap_code
) & 0xff;
2451 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
2453 env
->regs
[0] = do_arm_semihosting(env
);
2454 qemu_log_mask(CPU_LOG_INT
, "...handled as semihosting call\n");
2458 env
->cp15
.c5_insn
= 2;
2459 /* Fall through to prefetch abort. */
2460 case EXCP_PREFETCH_ABORT
:
2461 qemu_log_mask(CPU_LOG_INT
, "...with IFSR 0x%x IFAR 0x%x\n",
2462 env
->cp15
.c5_insn
, env
->cp15
.c6_insn
);
2463 new_mode
= ARM_CPU_MODE_ABT
;
2465 mask
= CPSR_A
| CPSR_I
;
2468 case EXCP_DATA_ABORT
:
2469 qemu_log_mask(CPU_LOG_INT
, "...with DFSR 0x%x DFAR 0x%x\n",
2470 env
->cp15
.c5_data
, env
->cp15
.c6_data
);
2471 new_mode
= ARM_CPU_MODE_ABT
;
2473 mask
= CPSR_A
| CPSR_I
;
2477 new_mode
= ARM_CPU_MODE_IRQ
;
2479 /* Disable IRQ and imprecise data aborts. */
2480 mask
= CPSR_A
| CPSR_I
;
2484 new_mode
= ARM_CPU_MODE_FIQ
;
2486 /* Disable FIQ, IRQ and imprecise data aborts. */
2487 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
2491 cpu_abort(env
, "Unhandled exception 0x%x\n", env
->exception_index
);
2492 return; /* Never happens. Keep compiler happy. */
2495 if (env
->cp15
.c1_sys
& (1 << 13)) {
2496 /* when enabled, base address cannot be remapped. */
2499 /* ARM v7 architectures provide a vector base address register to remap
2500 * the interrupt vector table.
2501 * This register is only followed in non-monitor mode, and has a secure
2502 * and un-secure copy. Since the cpu is always in a un-secure operation
2503 * and is never in monitor mode this feature is always active.
2504 * Note: only bits 31:5 are valid.
2506 addr
+= env
->cp15
.c12_vbar
;
2508 switch_mode (env
, new_mode
);
2509 env
->spsr
= cpsr_read(env
);
2510 /* Clear IT bits. */
2511 env
->condexec_bits
= 0;
2512 /* Switch to the new mode, and to the correct instruction set. */
2513 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
2514 env
->uncached_cpsr
|= mask
;
2515 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
2516 * and we should just guard the thumb mode on V4 */
2517 if (arm_feature(env
, ARM_FEATURE_V4T
)) {
2518 env
->thumb
= (env
->cp15
.c1_sys
& (1 << 30)) != 0;
2520 env
->regs
[14] = env
->regs
[15] + offset
;
2521 env
->regs
[15] = addr
;
2522 cs
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
2525 /* Check section/page access permissions.
2526 Returns the page protection flags, or zero if the access is not
2528 static inline int check_ap(CPUARMState
*env
, int ap
, int domain_prot
,
2529 int access_type
, int is_user
)
2533 if (domain_prot
== 3) {
2534 return PAGE_READ
| PAGE_WRITE
;
2537 if (access_type
== 1)
2540 prot_ro
= PAGE_READ
;
2544 if (access_type
== 1)
2546 switch ((env
->cp15
.c1_sys
>> 8) & 3) {
2548 return is_user
? 0 : PAGE_READ
;
2555 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
2560 return PAGE_READ
| PAGE_WRITE
;
2562 return PAGE_READ
| PAGE_WRITE
;
2563 case 4: /* Reserved. */
2566 return is_user
? 0 : prot_ro
;
2570 if (!arm_feature (env
, ARM_FEATURE_V6K
))
2578 static uint32_t get_level1_table_address(CPUARMState
*env
, uint32_t address
)
2582 if (address
& env
->cp15
.c2_mask
)
2583 table
= env
->cp15
.c2_base1
& 0xffffc000;
2585 table
= env
->cp15
.c2_base0
& env
->cp15
.c2_base_mask
;
2587 table
|= (address
>> 18) & 0x3ffc;
2591 static int get_phys_addr_v5(CPUARMState
*env
, uint32_t address
, int access_type
,
2592 int is_user
, hwaddr
*phys_ptr
,
2593 int *prot
, target_ulong
*page_size
)
2604 /* Pagetable walk. */
2605 /* Lookup l1 descriptor. */
2606 table
= get_level1_table_address(env
, address
);
2607 desc
= ldl_phys(table
);
2609 domain
= (desc
>> 5) & 0x0f;
2610 domain_prot
= (env
->cp15
.c3
>> (domain
* 2)) & 3;
2612 /* Section translation fault. */
2616 if (domain_prot
== 0 || domain_prot
== 2) {
2618 code
= 9; /* Section domain fault. */
2620 code
= 11; /* Page domain fault. */
2625 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
2626 ap
= (desc
>> 10) & 3;
2628 *page_size
= 1024 * 1024;
2630 /* Lookup l2 entry. */
2632 /* Coarse pagetable. */
2633 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
2635 /* Fine pagetable. */
2636 table
= (desc
& 0xfffff000) | ((address
>> 8) & 0xffc);
2638 desc
= ldl_phys(table
);
2640 case 0: /* Page translation fault. */
2643 case 1: /* 64k page. */
2644 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
2645 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
2646 *page_size
= 0x10000;
2648 case 2: /* 4k page. */
2649 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
2650 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
2651 *page_size
= 0x1000;
2653 case 3: /* 1k page. */
2655 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
2656 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
2658 /* Page translation fault. */
2663 phys_addr
= (desc
& 0xfffffc00) | (address
& 0x3ff);
2665 ap
= (desc
>> 4) & 3;
2669 /* Never happens, but compiler isn't smart enough to tell. */
2674 *prot
= check_ap(env
, ap
, domain_prot
, access_type
, is_user
);
2676 /* Access permission fault. */
2680 *phys_ptr
= phys_addr
;
2683 return code
| (domain
<< 4);
2686 static int get_phys_addr_v6(CPUARMState
*env
, uint32_t address
, int access_type
,
2687 int is_user
, hwaddr
*phys_ptr
,
2688 int *prot
, target_ulong
*page_size
)
2701 /* Pagetable walk. */
2702 /* Lookup l1 descriptor. */
2703 table
= get_level1_table_address(env
, address
);
2704 desc
= ldl_phys(table
);
2706 if (type
== 0 || (type
== 3 && !arm_feature(env
, ARM_FEATURE_PXN
))) {
2707 /* Section translation fault, or attempt to use the encoding
2708 * which is Reserved on implementations without PXN.
2713 if ((type
== 1) || !(desc
& (1 << 18))) {
2714 /* Page or Section. */
2715 domain
= (desc
>> 5) & 0x0f;
2717 domain_prot
= (env
->cp15
.c3
>> (domain
* 2)) & 3;
2718 if (domain_prot
== 0 || domain_prot
== 2) {
2720 code
= 9; /* Section domain fault. */
2722 code
= 11; /* Page domain fault. */
2727 if (desc
& (1 << 18)) {
2729 phys_addr
= (desc
& 0xff000000) | (address
& 0x00ffffff);
2730 *page_size
= 0x1000000;
2733 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
2734 *page_size
= 0x100000;
2736 ap
= ((desc
>> 10) & 3) | ((desc
>> 13) & 4);
2737 xn
= desc
& (1 << 4);
2741 if (arm_feature(env
, ARM_FEATURE_PXN
)) {
2742 pxn
= (desc
>> 2) & 1;
2744 /* Lookup l2 entry. */
2745 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
2746 desc
= ldl_phys(table
);
2747 ap
= ((desc
>> 4) & 3) | ((desc
>> 7) & 4);
2749 case 0: /* Page translation fault. */
2752 case 1: /* 64k page. */
2753 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
2754 xn
= desc
& (1 << 15);
2755 *page_size
= 0x10000;
2757 case 2: case 3: /* 4k page. */
2758 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
2760 *page_size
= 0x1000;
2763 /* Never happens, but compiler isn't smart enough to tell. */
2768 if (domain_prot
== 3) {
2769 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
2771 if (pxn
&& !is_user
) {
2774 if (xn
&& access_type
== 2)
2777 /* The simplified model uses AP[0] as an access control bit. */
2778 if ((env
->cp15
.c1_sys
& (1 << 29)) && (ap
& 1) == 0) {
2779 /* Access flag fault. */
2780 code
= (code
== 15) ? 6 : 3;
2783 *prot
= check_ap(env
, ap
, domain_prot
, access_type
, is_user
);
2785 /* Access permission fault. */
2792 *phys_ptr
= phys_addr
;
2795 return code
| (domain
<< 4);
2798 /* Fault type for long-descriptor MMU fault reporting; this corresponds
2799 * to bits [5..2] in the STATUS field in long-format DFSR/IFSR.
2802 translation_fault
= 1,
2804 permission_fault
= 3,
2807 static int get_phys_addr_lpae(CPUARMState
*env
, uint32_t address
,
2808 int access_type
, int is_user
,
2809 hwaddr
*phys_ptr
, int *prot
,
2810 target_ulong
*page_size_ptr
)
2812 /* Read an LPAE long-descriptor translation table. */
2813 MMUFaultType fault_type
= translation_fault
;
2821 uint32_t tableattrs
;
2822 target_ulong page_size
;
2825 /* Determine whether this address is in the region controlled by
2826 * TTBR0 or TTBR1 (or if it is in neither region and should fault).
2827 * This is a Non-secure PL0/1 stage 1 translation, so controlled by
2828 * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
2830 uint32_t t0sz
= extract32(env
->cp15
.c2_control
, 0, 3);
2831 uint32_t t1sz
= extract32(env
->cp15
.c2_control
, 16, 3);
2832 if (t0sz
&& !extract32(address
, 32 - t0sz
, t0sz
)) {
2833 /* there is a ttbr0 region and we are in it (high bits all zero) */
2835 } else if (t1sz
&& !extract32(~address
, 32 - t1sz
, t1sz
)) {
2836 /* there is a ttbr1 region and we are in it (high bits all one) */
2839 /* ttbr0 region is "everything not in the ttbr1 region" */
2842 /* ttbr1 region is "everything not in the ttbr0 region" */
2845 /* in the gap between the two regions, this is a Translation fault */
2846 fault_type
= translation_fault
;
2850 /* Note that QEMU ignores shareability and cacheability attributes,
2851 * so we don't need to do anything with the SH, ORGN, IRGN fields
2852 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
2853 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
2854 * implement any ASID-like capability so we can ignore it (instead
2855 * we will always flush the TLB any time the ASID is changed).
2857 if (ttbr_select
== 0) {
2858 ttbr
= ((uint64_t)env
->cp15
.c2_base0_hi
<< 32) | env
->cp15
.c2_base0
;
2859 epd
= extract32(env
->cp15
.c2_control
, 7, 1);
2862 ttbr
= ((uint64_t)env
->cp15
.c2_base1_hi
<< 32) | env
->cp15
.c2_base1
;
2863 epd
= extract32(env
->cp15
.c2_control
, 23, 1);
2868 /* Translation table walk disabled => Translation fault on TLB miss */
2872 /* If the region is small enough we will skip straight to a 2nd level
2873 * lookup. This affects the number of bits of the address used in
2874 * combination with the TTBR to find the first descriptor. ('n' here
2875 * matches the usage in the ARM ARM sB3.6.6, where bits [39..n] are
2876 * from the TTBR, [n-1..3] from the vaddr, and [2..0] always zero).
2885 /* Clear the vaddr bits which aren't part of the within-region address,
2886 * so that we don't have to special case things when calculating the
2887 * first descriptor address.
2889 address
&= (0xffffffffU
>> tsz
);
2891 /* Now we can extract the actual base address from the TTBR */
2892 descaddr
= extract64(ttbr
, 0, 40);
2893 descaddr
&= ~((1ULL << n
) - 1);
2897 uint64_t descriptor
;
2899 descaddr
|= ((address
>> (9 * (4 - level
))) & 0xff8);
2900 descriptor
= ldq_phys(descaddr
);
2901 if (!(descriptor
& 1) ||
2902 (!(descriptor
& 2) && (level
== 3))) {
2903 /* Invalid, or the Reserved level 3 encoding */
2906 descaddr
= descriptor
& 0xfffffff000ULL
;
2908 if ((descriptor
& 2) && (level
< 3)) {
2909 /* Table entry. The top five bits are attributes which may
2910 * propagate down through lower levels of the table (and
2911 * which are all arranged so that 0 means "no effect", so
2912 * we can gather them up by ORing in the bits at each level).
2914 tableattrs
|= extract64(descriptor
, 59, 5);
2918 /* Block entry at level 1 or 2, or page entry at level 3.
2919 * These are basically the same thing, although the number
2920 * of bits we pull in from the vaddr varies.
2922 page_size
= (1 << (39 - (9 * level
)));
2923 descaddr
|= (address
& (page_size
- 1));
2924 /* Extract attributes from the descriptor and merge with table attrs */
2925 attrs
= extract64(descriptor
, 2, 10)
2926 | (extract64(descriptor
, 52, 12) << 10);
2927 attrs
|= extract32(tableattrs
, 0, 2) << 11; /* XN, PXN */
2928 attrs
|= extract32(tableattrs
, 3, 1) << 5; /* APTable[1] => AP[2] */
2929 /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
2930 * means "force PL1 access only", which means forcing AP[1] to 0.
2932 if (extract32(tableattrs
, 2, 1)) {
2935 /* Since we're always in the Non-secure state, NSTable is ignored. */
2938 /* Here descaddr is the final physical address, and attributes
2941 fault_type
= access_fault
;
2942 if ((attrs
& (1 << 8)) == 0) {
2946 fault_type
= permission_fault
;
2947 if (is_user
&& !(attrs
& (1 << 4))) {
2948 /* Unprivileged access not enabled */
2951 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
2952 if (attrs
& (1 << 12) || (!is_user
&& (attrs
& (1 << 11)))) {
2954 if (access_type
== 2) {
2957 *prot
&= ~PAGE_EXEC
;
2959 if (attrs
& (1 << 5)) {
2960 /* Write access forbidden */
2961 if (access_type
== 1) {
2964 *prot
&= ~PAGE_WRITE
;
2967 *phys_ptr
= descaddr
;
2968 *page_size_ptr
= page_size
;
2972 /* Long-descriptor format IFSR/DFSR value */
2973 return (1 << 9) | (fault_type
<< 2) | level
;
2976 static int get_phys_addr_mpu(CPUARMState
*env
, uint32_t address
,
2977 int access_type
, int is_user
,
2978 hwaddr
*phys_ptr
, int *prot
)
2984 *phys_ptr
= address
;
2985 for (n
= 7; n
>= 0; n
--) {
2986 base
= env
->cp15
.c6_region
[n
];
2987 if ((base
& 1) == 0)
2989 mask
= 1 << ((base
>> 1) & 0x1f);
2990 /* Keep this shift separate from the above to avoid an
2991 (undefined) << 32. */
2992 mask
= (mask
<< 1) - 1;
2993 if (((base
^ address
) & ~mask
) == 0)
2999 if (access_type
== 2) {
3000 mask
= env
->cp15
.c5_insn
;
3002 mask
= env
->cp15
.c5_data
;
3004 mask
= (mask
>> (n
* 4)) & 0xf;
3011 *prot
= PAGE_READ
| PAGE_WRITE
;
3016 *prot
|= PAGE_WRITE
;
3019 *prot
= PAGE_READ
| PAGE_WRITE
;
3030 /* Bad permission. */
3037 /* get_phys_addr - get the physical address for this virtual address
3039 * Find the physical address corresponding to the given virtual address,
3040 * by doing a translation table walk on MMU based systems or using the
3041 * MPU state on MPU based systems.
3043 * Returns 0 if the translation was successful. Otherwise, phys_ptr,
3044 * prot and page_size are not filled in, and the return value provides
3045 * information on why the translation aborted, in the format of a
3046 * DFSR/IFSR fault register, with the following caveats:
3047 * * we honour the short vs long DFSR format differences.
3048 * * the WnR bit is never set (the caller must do this).
3049 * * for MPU based systems we don't bother to return a full FSR format
3053 * @address: virtual address to get physical address for
3054 * @access_type: 0 for read, 1 for write, 2 for execute
3055 * @is_user: 0 for privileged access, 1 for user
3056 * @phys_ptr: set to the physical address corresponding to the virtual address
3057 * @prot: set to the permissions for the page containing phys_ptr
3058 * @page_size: set to the size of the page containing phys_ptr
3060 static inline int get_phys_addr(CPUARMState
*env
, uint32_t address
,
3061 int access_type
, int is_user
,
3062 hwaddr
*phys_ptr
, int *prot
,
3063 target_ulong
*page_size
)
3065 /* Fast Context Switch Extension. */
3066 if (address
< 0x02000000)
3067 address
+= env
->cp15
.c13_fcse
;
3069 if ((env
->cp15
.c1_sys
& 1) == 0) {
3070 /* MMU/MPU disabled. */
3071 *phys_ptr
= address
;
3072 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
3073 *page_size
= TARGET_PAGE_SIZE
;
3075 } else if (arm_feature(env
, ARM_FEATURE_MPU
)) {
3076 *page_size
= TARGET_PAGE_SIZE
;
3077 return get_phys_addr_mpu(env
, address
, access_type
, is_user
, phys_ptr
,
3079 } else if (extended_addresses_enabled(env
)) {
3080 return get_phys_addr_lpae(env
, address
, access_type
, is_user
, phys_ptr
,
3082 } else if (env
->cp15
.c1_sys
& (1 << 23)) {
3083 return get_phys_addr_v6(env
, address
, access_type
, is_user
, phys_ptr
,
3086 return get_phys_addr_v5(env
, address
, access_type
, is_user
, phys_ptr
,
3091 int cpu_arm_handle_mmu_fault (CPUARMState
*env
, target_ulong address
,
3092 int access_type
, int mmu_idx
)
3095 target_ulong page_size
;
3099 is_user
= mmu_idx
== MMU_USER_IDX
;
3100 ret
= get_phys_addr(env
, address
, access_type
, is_user
, &phys_addr
, &prot
,
3103 /* Map a single [sub]page. */
3104 phys_addr
&= ~(hwaddr
)0x3ff;
3105 address
&= ~(uint32_t)0x3ff;
3106 tlb_set_page (env
, address
, phys_addr
, prot
, mmu_idx
, page_size
);
3110 if (access_type
== 2) {
3111 env
->cp15
.c5_insn
= ret
;
3112 env
->cp15
.c6_insn
= address
;
3113 env
->exception_index
= EXCP_PREFETCH_ABORT
;
3115 env
->cp15
.c5_data
= ret
;
3116 if (access_type
== 1 && arm_feature(env
, ARM_FEATURE_V6
))
3117 env
->cp15
.c5_data
|= (1 << 11);
3118 env
->cp15
.c6_data
= address
;
3119 env
->exception_index
= EXCP_DATA_ABORT
;
3124 hwaddr
arm_cpu_get_phys_page_debug(CPUState
*cs
, vaddr addr
)
3126 ARMCPU
*cpu
= ARM_CPU(cs
);
3128 target_ulong page_size
;
3132 ret
= get_phys_addr(&cpu
->env
, addr
, 0, 0, &phys_addr
, &prot
, &page_size
);
3141 void HELPER(set_r13_banked
)(CPUARMState
*env
, uint32_t mode
, uint32_t val
)
3143 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
3144 env
->regs
[13] = val
;
3146 env
->banked_r13
[bank_number(mode
)] = val
;
3150 uint32_t HELPER(get_r13_banked
)(CPUARMState
*env
, uint32_t mode
)
3152 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
3153 return env
->regs
[13];
3155 return env
->banked_r13
[bank_number(mode
)];
3159 uint32_t HELPER(v7m_mrs
)(CPUARMState
*env
, uint32_t reg
)
3163 return xpsr_read(env
) & 0xf8000000;
3165 return xpsr_read(env
) & 0xf80001ff;
3167 return xpsr_read(env
) & 0xff00fc00;
3169 return xpsr_read(env
) & 0xff00fdff;
3171 return xpsr_read(env
) & 0x000001ff;
3173 return xpsr_read(env
) & 0x0700fc00;
3175 return xpsr_read(env
) & 0x0700edff;
3177 return env
->v7m
.current_sp
? env
->v7m
.other_sp
: env
->regs
[13];
3179 return env
->v7m
.current_sp
? env
->regs
[13] : env
->v7m
.other_sp
;
3180 case 16: /* PRIMASK */
3181 return (env
->uncached_cpsr
& CPSR_I
) != 0;
3182 case 17: /* BASEPRI */
3183 case 18: /* BASEPRI_MAX */
3184 return env
->v7m
.basepri
;
3185 case 19: /* FAULTMASK */
3186 return (env
->uncached_cpsr
& CPSR_F
) != 0;
3187 case 20: /* CONTROL */
3188 return env
->v7m
.control
;
3190 /* ??? For debugging only. */
3191 cpu_abort(env
, "Unimplemented system register read (%d)\n", reg
);
3196 void HELPER(v7m_msr
)(CPUARMState
*env
, uint32_t reg
, uint32_t val
)
3200 xpsr_write(env
, val
, 0xf8000000);
3203 xpsr_write(env
, val
, 0xf8000000);
3206 xpsr_write(env
, val
, 0xfe00fc00);
3209 xpsr_write(env
, val
, 0xfe00fc00);
3212 /* IPSR bits are readonly. */
3215 xpsr_write(env
, val
, 0x0600fc00);
3218 xpsr_write(env
, val
, 0x0600fc00);
3221 if (env
->v7m
.current_sp
)
3222 env
->v7m
.other_sp
= val
;
3224 env
->regs
[13] = val
;
3227 if (env
->v7m
.current_sp
)
3228 env
->regs
[13] = val
;
3230 env
->v7m
.other_sp
= val
;
3232 case 16: /* PRIMASK */
3234 env
->uncached_cpsr
|= CPSR_I
;
3236 env
->uncached_cpsr
&= ~CPSR_I
;
3238 case 17: /* BASEPRI */
3239 env
->v7m
.basepri
= val
& 0xff;
3241 case 18: /* BASEPRI_MAX */
3243 if (val
!= 0 && (val
< env
->v7m
.basepri
|| env
->v7m
.basepri
== 0))
3244 env
->v7m
.basepri
= val
;
3246 case 19: /* FAULTMASK */
3248 env
->uncached_cpsr
|= CPSR_F
;
3250 env
->uncached_cpsr
&= ~CPSR_F
;
3252 case 20: /* CONTROL */
3253 env
->v7m
.control
= val
& 3;
3254 switch_v7m_sp(env
, (val
& 2) != 0);
3257 /* ??? For debugging only. */
3258 cpu_abort(env
, "Unimplemented system register write (%d)\n", reg
);
3265 /* Note that signed overflow is undefined in C. The following routines are
3266 careful to use unsigned types where modulo arithmetic is required.
3267 Failure to do so _will_ break on newer gcc. */
3269 /* Signed saturating arithmetic. */
3271 /* Perform 16-bit signed saturating addition. */
3272 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
3277 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
3286 /* Perform 8-bit signed saturating addition. */
3287 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
3292 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
3301 /* Perform 16-bit signed saturating subtraction. */
3302 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
3307 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
3316 /* Perform 8-bit signed saturating subtraction. */
3317 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
3322 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
3331 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
3332 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
3333 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
3334 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
3337 #include "op_addsub.h"
3339 /* Unsigned saturating arithmetic. */
3340 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
3349 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
3357 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
3366 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
3374 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
3375 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
3376 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
3377 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
3380 #include "op_addsub.h"
3382 /* Signed modulo arithmetic. */
3383 #define SARITH16(a, b, n, op) do { \
3385 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
3386 RESULT(sum, n, 16); \
3388 ge |= 3 << (n * 2); \
3391 #define SARITH8(a, b, n, op) do { \
3393 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
3394 RESULT(sum, n, 8); \
3400 #define ADD16(a, b, n) SARITH16(a, b, n, +)
3401 #define SUB16(a, b, n) SARITH16(a, b, n, -)
3402 #define ADD8(a, b, n) SARITH8(a, b, n, +)
3403 #define SUB8(a, b, n) SARITH8(a, b, n, -)
3407 #include "op_addsub.h"
3409 /* Unsigned modulo arithmetic. */
3410 #define ADD16(a, b, n) do { \
3412 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
3413 RESULT(sum, n, 16); \
3414 if ((sum >> 16) == 1) \
3415 ge |= 3 << (n * 2); \
3418 #define ADD8(a, b, n) do { \
3420 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
3421 RESULT(sum, n, 8); \
3422 if ((sum >> 8) == 1) \
3426 #define SUB16(a, b, n) do { \
3428 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
3429 RESULT(sum, n, 16); \
3430 if ((sum >> 16) == 0) \
3431 ge |= 3 << (n * 2); \
3434 #define SUB8(a, b, n) do { \
3436 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
3437 RESULT(sum, n, 8); \
3438 if ((sum >> 8) == 0) \
3445 #include "op_addsub.h"
3447 /* Halved signed arithmetic. */
3448 #define ADD16(a, b, n) \
3449 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
3450 #define SUB16(a, b, n) \
3451 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
3452 #define ADD8(a, b, n) \
3453 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
3454 #define SUB8(a, b, n) \
3455 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
3458 #include "op_addsub.h"
3460 /* Halved unsigned arithmetic. */
3461 #define ADD16(a, b, n) \
3462 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
3463 #define SUB16(a, b, n) \
3464 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
3465 #define ADD8(a, b, n) \
3466 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
3467 #define SUB8(a, b, n) \
3468 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
3471 #include "op_addsub.h"
3473 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
3481 /* Unsigned sum of absolute byte differences. */
3482 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
3485 sum
= do_usad(a
, b
);
3486 sum
+= do_usad(a
>> 8, b
>> 8);
3487 sum
+= do_usad(a
>> 16, b
>>16);
3488 sum
+= do_usad(a
>> 24, b
>> 24);
3492 /* For ARMv6 SEL instruction. */
3493 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
3506 return (a
& mask
) | (b
& ~mask
);
3509 /* VFP support. We follow the convention used for VFP instructions:
3510 Single precision routines have a "s" suffix, double precision a
3513 /* Convert host exception flags to vfp form. */
3514 static inline int vfp_exceptbits_from_host(int host_bits
)
3516 int target_bits
= 0;
3518 if (host_bits
& float_flag_invalid
)
3520 if (host_bits
& float_flag_divbyzero
)
3522 if (host_bits
& float_flag_overflow
)
3524 if (host_bits
& (float_flag_underflow
| float_flag_output_denormal
))
3526 if (host_bits
& float_flag_inexact
)
3527 target_bits
|= 0x10;
3528 if (host_bits
& float_flag_input_denormal
)
3529 target_bits
|= 0x80;
3533 uint32_t HELPER(vfp_get_fpscr
)(CPUARMState
*env
)
3538 fpscr
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & 0xffc8ffff)
3539 | (env
->vfp
.vec_len
<< 16)
3540 | (env
->vfp
.vec_stride
<< 20);
3541 i
= get_float_exception_flags(&env
->vfp
.fp_status
);
3542 i
|= get_float_exception_flags(&env
->vfp
.standard_fp_status
);
3543 fpscr
|= vfp_exceptbits_from_host(i
);
3547 uint32_t vfp_get_fpscr(CPUARMState
*env
)
3549 return HELPER(vfp_get_fpscr
)(env
);
3552 /* Convert vfp exception flags to target form. */
3553 static inline int vfp_exceptbits_to_host(int target_bits
)
3557 if (target_bits
& 1)
3558 host_bits
|= float_flag_invalid
;
3559 if (target_bits
& 2)
3560 host_bits
|= float_flag_divbyzero
;
3561 if (target_bits
& 4)
3562 host_bits
|= float_flag_overflow
;
3563 if (target_bits
& 8)
3564 host_bits
|= float_flag_underflow
;
3565 if (target_bits
& 0x10)
3566 host_bits
|= float_flag_inexact
;
3567 if (target_bits
& 0x80)
3568 host_bits
|= float_flag_input_denormal
;
3572 void HELPER(vfp_set_fpscr
)(CPUARMState
*env
, uint32_t val
)
3577 changed
= env
->vfp
.xregs
[ARM_VFP_FPSCR
];
3578 env
->vfp
.xregs
[ARM_VFP_FPSCR
] = (val
& 0xffc8ffff);
3579 env
->vfp
.vec_len
= (val
>> 16) & 7;
3580 env
->vfp
.vec_stride
= (val
>> 20) & 3;
3583 if (changed
& (3 << 22)) {
3584 i
= (val
>> 22) & 3;
3587 i
= float_round_nearest_even
;
3593 i
= float_round_down
;
3596 i
= float_round_to_zero
;
3599 set_float_rounding_mode(i
, &env
->vfp
.fp_status
);
3601 if (changed
& (1 << 24)) {
3602 set_flush_to_zero((val
& (1 << 24)) != 0, &env
->vfp
.fp_status
);
3603 set_flush_inputs_to_zero((val
& (1 << 24)) != 0, &env
->vfp
.fp_status
);
3605 if (changed
& (1 << 25))
3606 set_default_nan_mode((val
& (1 << 25)) != 0, &env
->vfp
.fp_status
);
3608 i
= vfp_exceptbits_to_host(val
);
3609 set_float_exception_flags(i
, &env
->vfp
.fp_status
);
3610 set_float_exception_flags(0, &env
->vfp
.standard_fp_status
);
3613 void vfp_set_fpscr(CPUARMState
*env
, uint32_t val
)
3615 HELPER(vfp_set_fpscr
)(env
, val
);
3618 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
3620 #define VFP_BINOP(name) \
3621 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
3623 float_status *fpst = fpstp; \
3624 return float32_ ## name(a, b, fpst); \
3626 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
3628 float_status *fpst = fpstp; \
3629 return float64_ ## name(a, b, fpst); \
3637 float32
VFP_HELPER(neg
, s
)(float32 a
)
3639 return float32_chs(a
);
3642 float64
VFP_HELPER(neg
, d
)(float64 a
)
3644 return float64_chs(a
);
3647 float32
VFP_HELPER(abs
, s
)(float32 a
)
3649 return float32_abs(a
);
3652 float64
VFP_HELPER(abs
, d
)(float64 a
)
3654 return float64_abs(a
);
3657 float32
VFP_HELPER(sqrt
, s
)(float32 a
, CPUARMState
*env
)
3659 return float32_sqrt(a
, &env
->vfp
.fp_status
);
3662 float64
VFP_HELPER(sqrt
, d
)(float64 a
, CPUARMState
*env
)
3664 return float64_sqrt(a
, &env
->vfp
.fp_status
);
3667 /* XXX: check quiet/signaling case */
3668 #define DO_VFP_cmp(p, type) \
3669 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
3672 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
3673 case 0: flags = 0x6; break; \
3674 case -1: flags = 0x8; break; \
3675 case 1: flags = 0x2; break; \
3676 default: case 2: flags = 0x3; break; \
3678 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
3679 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
3681 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
3684 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
3685 case 0: flags = 0x6; break; \
3686 case -1: flags = 0x8; break; \
3687 case 1: flags = 0x2; break; \
3688 default: case 2: flags = 0x3; break; \
3690 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
3691 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
3693 DO_VFP_cmp(s
, float32
)
3694 DO_VFP_cmp(d
, float64
)
3697 /* Integer to float and float to integer conversions */
3699 #define CONV_ITOF(name, fsz, sign) \
3700 float##fsz HELPER(name)(uint32_t x, void *fpstp) \
3702 float_status *fpst = fpstp; \
3703 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
3706 #define CONV_FTOI(name, fsz, sign, round) \
3707 uint32_t HELPER(name)(float##fsz x, void *fpstp) \
3709 float_status *fpst = fpstp; \
3710 if (float##fsz##_is_any_nan(x)) { \
3711 float_raise(float_flag_invalid, fpst); \
3714 return float##fsz##_to_##sign##int32##round(x, fpst); \
3717 #define FLOAT_CONVS(name, p, fsz, sign) \
3718 CONV_ITOF(vfp_##name##to##p, fsz, sign) \
3719 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
3720 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
3722 FLOAT_CONVS(si
, s
, 32, )
3723 FLOAT_CONVS(si
, d
, 64, )
3724 FLOAT_CONVS(ui
, s
, 32, u
)
3725 FLOAT_CONVS(ui
, d
, 64, u
)
3731 /* floating point conversion */
3732 float64
VFP_HELPER(fcvtd
, s
)(float32 x
, CPUARMState
*env
)
3734 float64 r
= float32_to_float64(x
, &env
->vfp
.fp_status
);
3735 /* ARM requires that S<->D conversion of any kind of NaN generates
3736 * a quiet NaN by forcing the most significant frac bit to 1.
3738 return float64_maybe_silence_nan(r
);
3741 float32
VFP_HELPER(fcvts
, d
)(float64 x
, CPUARMState
*env
)
3743 float32 r
= float64_to_float32(x
, &env
->vfp
.fp_status
);
3744 /* ARM requires that S<->D conversion of any kind of NaN generates
3745 * a quiet NaN by forcing the most significant frac bit to 1.
3747 return float32_maybe_silence_nan(r
);
3750 /* VFP3 fixed point conversion. */
3751 #define VFP_CONV_FIX(name, p, fsz, itype, sign) \
3752 float##fsz HELPER(vfp_##name##to##p)(uint##fsz##_t x, uint32_t shift, \
3755 float_status *fpst = fpstp; \
3757 tmp = sign##int32_to_##float##fsz((itype##_t)x, fpst); \
3758 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
3760 uint##fsz##_t HELPER(vfp_to##name##p)(float##fsz x, uint32_t shift, \
3763 float_status *fpst = fpstp; \
3765 if (float##fsz##_is_any_nan(x)) { \
3766 float_raise(float_flag_invalid, fpst); \
3769 tmp = float##fsz##_scalbn(x, shift, fpst); \
3770 return float##fsz##_to_##itype##_round_to_zero(tmp, fpst); \
3773 VFP_CONV_FIX(sh
, d
, 64, int16
, )
3774 VFP_CONV_FIX(sl
, d
, 64, int32
, )
3775 VFP_CONV_FIX(uh
, d
, 64, uint16
, u
)
3776 VFP_CONV_FIX(ul
, d
, 64, uint32
, u
)
3777 VFP_CONV_FIX(sh
, s
, 32, int16
, )
3778 VFP_CONV_FIX(sl
, s
, 32, int32
, )
3779 VFP_CONV_FIX(uh
, s
, 32, uint16
, u
)
3780 VFP_CONV_FIX(ul
, s
, 32, uint32
, u
)
3783 /* Half precision conversions. */
3784 static float32
do_fcvt_f16_to_f32(uint32_t a
, CPUARMState
*env
, float_status
*s
)
3786 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
3787 float32 r
= float16_to_float32(make_float16(a
), ieee
, s
);
3789 return float32_maybe_silence_nan(r
);
3794 static uint32_t do_fcvt_f32_to_f16(float32 a
, CPUARMState
*env
, float_status
*s
)
3796 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
3797 float16 r
= float32_to_float16(a
, ieee
, s
);
3799 r
= float16_maybe_silence_nan(r
);
3801 return float16_val(r
);
3804 float32
HELPER(neon_fcvt_f16_to_f32
)(uint32_t a
, CPUARMState
*env
)
3806 return do_fcvt_f16_to_f32(a
, env
, &env
->vfp
.standard_fp_status
);
3809 uint32_t HELPER(neon_fcvt_f32_to_f16
)(float32 a
, CPUARMState
*env
)
3811 return do_fcvt_f32_to_f16(a
, env
, &env
->vfp
.standard_fp_status
);
3814 float32
HELPER(vfp_fcvt_f16_to_f32
)(uint32_t a
, CPUARMState
*env
)
3816 return do_fcvt_f16_to_f32(a
, env
, &env
->vfp
.fp_status
);
3819 uint32_t HELPER(vfp_fcvt_f32_to_f16
)(float32 a
, CPUARMState
*env
)
3821 return do_fcvt_f32_to_f16(a
, env
, &env
->vfp
.fp_status
);
3824 #define float32_two make_float32(0x40000000)
3825 #define float32_three make_float32(0x40400000)
3826 #define float32_one_point_five make_float32(0x3fc00000)
3828 float32
HELPER(recps_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
3830 float_status
*s
= &env
->vfp
.standard_fp_status
;
3831 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
3832 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
3833 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
3834 float_raise(float_flag_input_denormal
, s
);
3838 return float32_sub(float32_two
, float32_mul(a
, b
, s
), s
);
3841 float32
HELPER(rsqrts_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
3843 float_status
*s
= &env
->vfp
.standard_fp_status
;
3845 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
3846 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
3847 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
3848 float_raise(float_flag_input_denormal
, s
);
3850 return float32_one_point_five
;
3852 product
= float32_mul(a
, b
, s
);
3853 return float32_div(float32_sub(float32_three
, product
, s
), float32_two
, s
);
3858 /* Constants 256 and 512 are used in some helpers; we avoid relying on
3859 * int->float conversions at run-time. */
3860 #define float64_256 make_float64(0x4070000000000000LL)
3861 #define float64_512 make_float64(0x4080000000000000LL)
3863 /* The algorithm that must be used to calculate the estimate
3864 * is specified by the ARM ARM.
3866 static float64
recip_estimate(float64 a
, CPUARMState
*env
)
3868 /* These calculations mustn't set any fp exception flags,
3869 * so we use a local copy of the fp_status.
3871 float_status dummy_status
= env
->vfp
.standard_fp_status
;
3872 float_status
*s
= &dummy_status
;
3873 /* q = (int)(a * 512.0) */
3874 float64 q
= float64_mul(float64_512
, a
, s
);
3875 int64_t q_int
= float64_to_int64_round_to_zero(q
, s
);
3877 /* r = 1.0 / (((double)q + 0.5) / 512.0) */
3878 q
= int64_to_float64(q_int
, s
);
3879 q
= float64_add(q
, float64_half
, s
);
3880 q
= float64_div(q
, float64_512
, s
);
3881 q
= float64_div(float64_one
, q
, s
);
3883 /* s = (int)(256.0 * r + 0.5) */
3884 q
= float64_mul(q
, float64_256
, s
);
3885 q
= float64_add(q
, float64_half
, s
);
3886 q_int
= float64_to_int64_round_to_zero(q
, s
);
3888 /* return (double)s / 256.0 */
3889 return float64_div(int64_to_float64(q_int
, s
), float64_256
, s
);
3892 float32
HELPER(recpe_f32
)(float32 a
, CPUARMState
*env
)
3894 float_status
*s
= &env
->vfp
.standard_fp_status
;
3896 uint32_t val32
= float32_val(a
);
3899 int a_exp
= (val32
& 0x7f800000) >> 23;
3900 int sign
= val32
& 0x80000000;
3902 if (float32_is_any_nan(a
)) {
3903 if (float32_is_signaling_nan(a
)) {
3904 float_raise(float_flag_invalid
, s
);
3906 return float32_default_nan
;
3907 } else if (float32_is_infinity(a
)) {
3908 return float32_set_sign(float32_zero
, float32_is_neg(a
));
3909 } else if (float32_is_zero_or_denormal(a
)) {
3910 if (!float32_is_zero(a
)) {
3911 float_raise(float_flag_input_denormal
, s
);
3913 float_raise(float_flag_divbyzero
, s
);
3914 return float32_set_sign(float32_infinity
, float32_is_neg(a
));
3915 } else if (a_exp
>= 253) {
3916 float_raise(float_flag_underflow
, s
);
3917 return float32_set_sign(float32_zero
, float32_is_neg(a
));
3920 f64
= make_float64((0x3feULL
<< 52)
3921 | ((int64_t)(val32
& 0x7fffff) << 29));
3923 result_exp
= 253 - a_exp
;
3925 f64
= recip_estimate(f64
, env
);
3928 | ((result_exp
& 0xff) << 23)
3929 | ((float64_val(f64
) >> 29) & 0x7fffff);
3930 return make_float32(val32
);
3933 /* The algorithm that must be used to calculate the estimate
3934 * is specified by the ARM ARM.
3936 static float64
recip_sqrt_estimate(float64 a
, CPUARMState
*env
)
3938 /* These calculations mustn't set any fp exception flags,
3939 * so we use a local copy of the fp_status.
3941 float_status dummy_status
= env
->vfp
.standard_fp_status
;
3942 float_status
*s
= &dummy_status
;
3946 if (float64_lt(a
, float64_half
, s
)) {
3947 /* range 0.25 <= a < 0.5 */
3949 /* a in units of 1/512 rounded down */
3950 /* q0 = (int)(a * 512.0); */
3951 q
= float64_mul(float64_512
, a
, s
);
3952 q_int
= float64_to_int64_round_to_zero(q
, s
);
3954 /* reciprocal root r */
3955 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
3956 q
= int64_to_float64(q_int
, s
);
3957 q
= float64_add(q
, float64_half
, s
);
3958 q
= float64_div(q
, float64_512
, s
);
3959 q
= float64_sqrt(q
, s
);
3960 q
= float64_div(float64_one
, q
, s
);
3962 /* range 0.5 <= a < 1.0 */
3964 /* a in units of 1/256 rounded down */
3965 /* q1 = (int)(a * 256.0); */
3966 q
= float64_mul(float64_256
, a
, s
);
3967 int64_t q_int
= float64_to_int64_round_to_zero(q
, s
);
3969 /* reciprocal root r */
3970 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
3971 q
= int64_to_float64(q_int
, s
);
3972 q
= float64_add(q
, float64_half
, s
);
3973 q
= float64_div(q
, float64_256
, s
);
3974 q
= float64_sqrt(q
, s
);
3975 q
= float64_div(float64_one
, q
, s
);
3977 /* r in units of 1/256 rounded to nearest */
3978 /* s = (int)(256.0 * r + 0.5); */
3980 q
= float64_mul(q
, float64_256
,s
);
3981 q
= float64_add(q
, float64_half
, s
);
3982 q_int
= float64_to_int64_round_to_zero(q
, s
);
3984 /* return (double)s / 256.0;*/
3985 return float64_div(int64_to_float64(q_int
, s
), float64_256
, s
);
3988 float32
HELPER(rsqrte_f32
)(float32 a
, CPUARMState
*env
)
3990 float_status
*s
= &env
->vfp
.standard_fp_status
;
3996 val
= float32_val(a
);
3998 if (float32_is_any_nan(a
)) {
3999 if (float32_is_signaling_nan(a
)) {
4000 float_raise(float_flag_invalid
, s
);
4002 return float32_default_nan
;
4003 } else if (float32_is_zero_or_denormal(a
)) {
4004 if (!float32_is_zero(a
)) {
4005 float_raise(float_flag_input_denormal
, s
);
4007 float_raise(float_flag_divbyzero
, s
);
4008 return float32_set_sign(float32_infinity
, float32_is_neg(a
));
4009 } else if (float32_is_neg(a
)) {
4010 float_raise(float_flag_invalid
, s
);
4011 return float32_default_nan
;
4012 } else if (float32_is_infinity(a
)) {
4013 return float32_zero
;
4016 /* Normalize to a double-precision value between 0.25 and 1.0,
4017 * preserving the parity of the exponent. */
4018 if ((val
& 0x800000) == 0) {
4019 f64
= make_float64(((uint64_t)(val
& 0x80000000) << 32)
4021 | ((uint64_t)(val
& 0x7fffff) << 29));
4023 f64
= make_float64(((uint64_t)(val
& 0x80000000) << 32)
4025 | ((uint64_t)(val
& 0x7fffff) << 29));
4028 result_exp
= (380 - ((val
& 0x7f800000) >> 23)) / 2;
4030 f64
= recip_sqrt_estimate(f64
, env
);
4032 val64
= float64_val(f64
);
4034 val
= ((result_exp
& 0xff) << 23)
4035 | ((val64
>> 29) & 0x7fffff);
4036 return make_float32(val
);
4039 uint32_t HELPER(recpe_u32
)(uint32_t a
, CPUARMState
*env
)
4043 if ((a
& 0x80000000) == 0) {
4047 f64
= make_float64((0x3feULL
<< 52)
4048 | ((int64_t)(a
& 0x7fffffff) << 21));
4050 f64
= recip_estimate (f64
, env
);
4052 return 0x80000000 | ((float64_val(f64
) >> 21) & 0x7fffffff);
4055 uint32_t HELPER(rsqrte_u32
)(uint32_t a
, CPUARMState
*env
)
4059 if ((a
& 0xc0000000) == 0) {
4063 if (a
& 0x80000000) {
4064 f64
= make_float64((0x3feULL
<< 52)
4065 | ((uint64_t)(a
& 0x7fffffff) << 21));
4066 } else { /* bits 31-30 == '01' */
4067 f64
= make_float64((0x3fdULL
<< 52)
4068 | ((uint64_t)(a
& 0x3fffffff) << 22));
4071 f64
= recip_sqrt_estimate(f64
, env
);
4073 return 0x80000000 | ((float64_val(f64
) >> 21) & 0x7fffffff);
4076 /* VFPv4 fused multiply-accumulate */
4077 float32
VFP_HELPER(muladd
, s
)(float32 a
, float32 b
, float32 c
, void *fpstp
)
4079 float_status
*fpst
= fpstp
;
4080 return float32_muladd(a
, b
, c
, 0, fpst
);
4083 float64
VFP_HELPER(muladd
, d
)(float64 a
, float64 b
, float64 c
, void *fpstp
)
4085 float_status
*fpst
= fpstp
;
4086 return float64_muladd(a
, b
, c
, 0, fpst
);
4089 /* ARMv8 VMAXNM/VMINNM */
4090 float32
VFP_HELPER(maxnm
, s
)(float32 a
, float32 b
, void *fpstp
)
4092 float_status
*fpst
= fpstp
;
4093 return float32_maxnum(a
, b
, fpst
);
4096 float64
VFP_HELPER(maxnm
, d
)(float64 a
, float64 b
, void *fpstp
)
4098 float_status
*fpst
= fpstp
;
4099 return float64_maxnum(a
, b
, fpst
);
4102 float32
VFP_HELPER(minnm
, s
)(float32 a
, float32 b
, void *fpstp
)
4104 float_status
*fpst
= fpstp
;
4105 return float32_minnum(a
, b
, fpst
);
4108 float64
VFP_HELPER(minnm
, d
)(float64 a
, float64 b
, void *fpstp
)
4110 float_status
*fpst
= fpstp
;
4111 return float64_minnum(a
, b
, fpst
);