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change all other clock references to use nanosecond resolution accessors
[qemu.git] / hw / usb-ohci.c
blobd2b14f7b4fc68386c277b467a31deec58a75f9b1
1 /*
2 * QEMU USB OHCI Emulation
3 * Copyright (c) 2004 Gianni Tedesco
4 * Copyright (c) 2006 CodeSourcery
5 * Copyright (c) 2006 Openedhand Ltd.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 *
20 * TODO:
21 * o Isochronous transfers
22 * o Allocate bandwidth in frames properly
23 * o Disable timers when nothing needs to be done, or remove timer usage
24 * all together.
25 * o Handle unrecoverable errors properly
26 * o BIOS work to boot from USB storage
27 */
28
29 #include "hw.h"
30 #include "qemu-timer.h"
31 #include "usb.h"
32 #include "pci.h"
33 #include "usb-ohci.h"
34 #include "sysbus.h"
35 #include "qdev-addr.h"
36
37 //#define DEBUG_OHCI
38 /* Dump packet contents. */
39 //#define DEBUG_PACKET
40 //#define DEBUG_ISOCH
41 /* This causes frames to occur 1000x slower */
42 //#define OHCI_TIME_WARP 1
43
44 #ifdef DEBUG_OHCI
45 #define DPRINTF printf
46 #else
47 #define DPRINTF(...)
48 #endif
49
50 /* Number of Downstream Ports on the root hub. */
51
52 #define OHCI_MAX_PORTS 15
53
54 static int64_t usb_frame_time;
55 static int64_t usb_bit_time;
56
57 typedef struct OHCIPort {
58 USBPort port;
59 uint32_t ctrl;
60 } OHCIPort;
61
62 typedef struct {
63 USBBus bus;
64 qemu_irq irq;
65 int mem;
66 int num_ports;
67 const char *name;
68
69 QEMUTimer *eof_timer;
70 int64_t sof_time;
71
72 /* OHCI state */
73 /* Control partition */
74 uint32_t ctl, status;
75 uint32_t intr_status;
76 uint32_t intr;
77
78 /* memory pointer partition */
79 uint32_t hcca;
80 uint32_t ctrl_head, ctrl_cur;
81 uint32_t bulk_head, bulk_cur;
82 uint32_t per_cur;
83 uint32_t done;
84 int done_count;
85
86 /* Frame counter partition */
87 uint32_t fsmps:15;
88 uint32_t fit:1;
89 uint32_t fi:14;
90 uint32_t frt:1;
91 uint16_t frame_number;
92 uint16_t padding;
93 uint32_t pstart;
94 uint32_t lst;
95
96 /* Root Hub partition */
97 uint32_t rhdesc_a, rhdesc_b;
98 uint32_t rhstatus;
99 OHCIPort rhport[OHCI_MAX_PORTS];
100
101 /* PXA27x Non-OHCI events */
102 uint32_t hstatus;
103 uint32_t hmask;
104 uint32_t hreset;
105 uint32_t htest;
106
107 /* SM501 local memory offset */
108 target_phys_addr_t localmem_base;
109
110 /* Active packets. */
111 uint32_t old_ctl;
112 USBPacket usb_packet;
113 uint8_t usb_buf[8192];
114 uint32_t async_td;
115 int async_complete;
116
117 } OHCIState;
118
119 /* Host Controller Communications Area */
120 struct ohci_hcca {
121 uint32_t intr[32];
122 uint16_t frame, pad;
123 uint32_t done;
124 };
125
126 static void ohci_bus_stop(OHCIState *ohci);
127
128 /* Bitfields for the first word of an Endpoint Desciptor. */
129 #define OHCI_ED_FA_SHIFT 0
130 #define OHCI_ED_FA_MASK (0x7f<<OHCI_ED_FA_SHIFT)
131 #define OHCI_ED_EN_SHIFT 7
132 #define OHCI_ED_EN_MASK (0xf<<OHCI_ED_EN_SHIFT)
133 #define OHCI_ED_D_SHIFT 11
134 #define OHCI_ED_D_MASK (3<<OHCI_ED_D_SHIFT)
135 #define OHCI_ED_S (1<<13)
136 #define OHCI_ED_K (1<<14)
137 #define OHCI_ED_F (1<<15)
138 #define OHCI_ED_MPS_SHIFT 16
139 #define OHCI_ED_MPS_MASK (0x7ff<<OHCI_ED_MPS_SHIFT)
140
141 /* Flags in the head field of an Endpoint Desciptor. */
142 #define OHCI_ED_H 1
143 #define OHCI_ED_C 2
144
145 /* Bitfields for the first word of a Transfer Desciptor. */
146 #define OHCI_TD_R (1<<18)
147 #define OHCI_TD_DP_SHIFT 19
148 #define OHCI_TD_DP_MASK (3<<OHCI_TD_DP_SHIFT)
149 #define OHCI_TD_DI_SHIFT 21
150 #define OHCI_TD_DI_MASK (7<<OHCI_TD_DI_SHIFT)
151 #define OHCI_TD_T0 (1<<24)
152 #define OHCI_TD_T1 (1<<24)
153 #define OHCI_TD_EC_SHIFT 26
154 #define OHCI_TD_EC_MASK (3<<OHCI_TD_EC_SHIFT)
155 #define OHCI_TD_CC_SHIFT 28
156 #define OHCI_TD_CC_MASK (0xf<<OHCI_TD_CC_SHIFT)
157
158 /* Bitfields for the first word of an Isochronous Transfer Desciptor. */
159 /* CC & DI - same as in the General Transfer Desciptor */
160 #define OHCI_TD_SF_SHIFT 0
161 #define OHCI_TD_SF_MASK (0xffff<<OHCI_TD_SF_SHIFT)
162 #define OHCI_TD_FC_SHIFT 24
163 #define OHCI_TD_FC_MASK (7<<OHCI_TD_FC_SHIFT)
164
165 /* Isochronous Transfer Desciptor - Offset / PacketStatusWord */
166 #define OHCI_TD_PSW_CC_SHIFT 12
167 #define OHCI_TD_PSW_CC_MASK (0xf<<OHCI_TD_PSW_CC_SHIFT)
168 #define OHCI_TD_PSW_SIZE_SHIFT 0
169 #define OHCI_TD_PSW_SIZE_MASK (0xfff<<OHCI_TD_PSW_SIZE_SHIFT)
170
171 #define OHCI_PAGE_MASK 0xfffff000
172 #define OHCI_OFFSET_MASK 0xfff
173
174 #define OHCI_DPTR_MASK 0xfffffff0
175
176 #define OHCI_BM(val, field) \
177 (((val) & OHCI_##field##_MASK) >> OHCI_##field##_SHIFT)
178
179 #define OHCI_SET_BM(val, field, newval) do { \
180 val &= ~OHCI_##field##_MASK; \
181 val |= ((newval) << OHCI_##field##_SHIFT) & OHCI_##field##_MASK; \
182 } while(0)
183
184 /* endpoint descriptor */
185 struct ohci_ed {
186 uint32_t flags;
187 uint32_t tail;
188 uint32_t head;
189 uint32_t next;
190 };
191
192 /* General transfer descriptor */
193 struct ohci_td {
194 uint32_t flags;
195 uint32_t cbp;
196 uint32_t next;
197 uint32_t be;
198 };
199
200 /* Isochronous transfer descriptor */
201 struct ohci_iso_td {
202 uint32_t flags;
203 uint32_t bp;
204 uint32_t next;
205 uint32_t be;
206 uint16_t offset[8];
207 };
208
209 #define USB_HZ 12000000
210
211 /* OHCI Local stuff */
212 #define OHCI_CTL_CBSR ((1<<0)|(1<<1))
213 #define OHCI_CTL_PLE (1<<2)
214 #define OHCI_CTL_IE (1<<3)
215 #define OHCI_CTL_CLE (1<<4)
216 #define OHCI_CTL_BLE (1<<5)
217 #define OHCI_CTL_HCFS ((1<<6)|(1<<7))
218 #define OHCI_USB_RESET 0x00
219 #define OHCI_USB_RESUME 0x40
220 #define OHCI_USB_OPERATIONAL 0x80
221 #define OHCI_USB_SUSPEND 0xc0
222 #define OHCI_CTL_IR (1<<8)
223 #define OHCI_CTL_RWC (1<<9)
224 #define OHCI_CTL_RWE (1<<10)
225
226 #define OHCI_STATUS_HCR (1<<0)
227 #define OHCI_STATUS_CLF (1<<1)
228 #define OHCI_STATUS_BLF (1<<2)
229 #define OHCI_STATUS_OCR (1<<3)
230 #define OHCI_STATUS_SOC ((1<<6)|(1<<7))
231
232 #define OHCI_INTR_SO (1<<0) /* Scheduling overrun */
233 #define OHCI_INTR_WD (1<<1) /* HcDoneHead writeback */
234 #define OHCI_INTR_SF (1<<2) /* Start of frame */
235 #define OHCI_INTR_RD (1<<3) /* Resume detect */
236 #define OHCI_INTR_UE (1<<4) /* Unrecoverable error */
237 #define OHCI_INTR_FNO (1<<5) /* Frame number overflow */
238 #define OHCI_INTR_RHSC (1<<6) /* Root hub status change */
239 #define OHCI_INTR_OC (1<<30) /* Ownership change */
240 #define OHCI_INTR_MIE (1<<31) /* Master Interrupt Enable */
241
242 #define OHCI_HCCA_SIZE 0x100
243 #define OHCI_HCCA_MASK 0xffffff00
244
245 #define OHCI_EDPTR_MASK 0xfffffff0
246
247 #define OHCI_FMI_FI 0x00003fff
248 #define OHCI_FMI_FSMPS 0xffff0000
249 #define OHCI_FMI_FIT 0x80000000
250
251 #define OHCI_FR_RT (1<<31)
252
253 #define OHCI_LS_THRESH 0x628
254
255 #define OHCI_RHA_RW_MASK 0x00000000 /* Mask of supported features. */
256 #define OHCI_RHA_PSM (1<<8)
257 #define OHCI_RHA_NPS (1<<9)
258 #define OHCI_RHA_DT (1<<10)
259 #define OHCI_RHA_OCPM (1<<11)
260 #define OHCI_RHA_NOCP (1<<12)
261 #define OHCI_RHA_POTPGT_MASK 0xff000000
262
263 #define OHCI_RHS_LPS (1<<0)
264 #define OHCI_RHS_OCI (1<<1)
265 #define OHCI_RHS_DRWE (1<<15)
266 #define OHCI_RHS_LPSC (1<<16)
267 #define OHCI_RHS_OCIC (1<<17)
268 #define OHCI_RHS_CRWE (1<<31)
269
270 #define OHCI_PORT_CCS (1<<0)
271 #define OHCI_PORT_PES (1<<1)
272 #define OHCI_PORT_PSS (1<<2)
273 #define OHCI_PORT_POCI (1<<3)
274 #define OHCI_PORT_PRS (1<<4)
275 #define OHCI_PORT_PPS (1<<8)
276 #define OHCI_PORT_LSDA (1<<9)
277 #define OHCI_PORT_CSC (1<<16)
278 #define OHCI_PORT_PESC (1<<17)
279 #define OHCI_PORT_PSSC (1<<18)
280 #define OHCI_PORT_OCIC (1<<19)
281 #define OHCI_PORT_PRSC (1<<20)
282 #define OHCI_PORT_WTC (OHCI_PORT_CSC|OHCI_PORT_PESC|OHCI_PORT_PSSC \
283 |OHCI_PORT_OCIC|OHCI_PORT_PRSC)
284
285 #define OHCI_TD_DIR_SETUP 0x0
286 #define OHCI_TD_DIR_OUT 0x1
287 #define OHCI_TD_DIR_IN 0x2
288 #define OHCI_TD_DIR_RESERVED 0x3
289
290 #define OHCI_CC_NOERROR 0x0
291 #define OHCI_CC_CRC 0x1
292 #define OHCI_CC_BITSTUFFING 0x2
293 #define OHCI_CC_DATATOGGLEMISMATCH 0x3
294 #define OHCI_CC_STALL 0x4
295 #define OHCI_CC_DEVICENOTRESPONDING 0x5
296 #define OHCI_CC_PIDCHECKFAILURE 0x6
297 #define OHCI_CC_UNDEXPETEDPID 0x7
298 #define OHCI_CC_DATAOVERRUN 0x8
299 #define OHCI_CC_DATAUNDERRUN 0x9
300 #define OHCI_CC_BUFFEROVERRUN 0xc
301 #define OHCI_CC_BUFFERUNDERRUN 0xd
302
303 #define OHCI_HRESET_FSBIR (1 << 0)
304
305 /* Update IRQ levels */
306 static inline void ohci_intr_update(OHCIState *ohci)
307 {
308 int level = 0;
309
310 if ((ohci->intr & OHCI_INTR_MIE) &&
311 (ohci->intr_status & ohci->intr))
312 level = 1;
313
314 qemu_set_irq(ohci->irq, level);
315 }
316
317 /* Set an interrupt */
318 static inline void ohci_set_interrupt(OHCIState *ohci, uint32_t intr)
319 {
320 ohci->intr_status |= intr;
321 ohci_intr_update(ohci);
322 }
323
324 /* Attach or detach a device on a root hub port. */
325 static void ohci_attach(USBPort *port1)
326 {
327 OHCIState *s = port1->opaque;
328 OHCIPort *port = &s->rhport[port1->index];
329
330 /* set connect status */
331 port->ctrl |= OHCI_PORT_CCS | OHCI_PORT_CSC;
332
333 /* update speed */
334 if (port->port.dev->speed == USB_SPEED_LOW) {
335 port->ctrl |= OHCI_PORT_LSDA;
336 } else {
337 port->ctrl &= ~OHCI_PORT_LSDA;
338 }
339
340 /* notify of remote-wakeup */
341 if ((s->ctl & OHCI_CTL_HCFS) == OHCI_USB_SUSPEND) {
342 ohci_set_interrupt(s, OHCI_INTR_RD);
343 }
344
345 DPRINTF("usb-ohci: Attached port %d\n", port1->index);
346 }
347
348 static void ohci_detach(USBPort *port1)
349 {
350 OHCIState *s = port1->opaque;
351 OHCIPort *port = &s->rhport[port1->index];
352 uint32_t old_state = port->ctrl;
353
354 /* set connect status */
355 if (port->ctrl & OHCI_PORT_CCS) {
356 port->ctrl &= ~OHCI_PORT_CCS;
357 port->ctrl |= OHCI_PORT_CSC;
358 }
359 /* disable port */
360 if (port->ctrl & OHCI_PORT_PES) {
361 port->ctrl &= ~OHCI_PORT_PES;
362 port->ctrl |= OHCI_PORT_PESC;
363 }
364 DPRINTF("usb-ohci: Detached port %d\n", port1->index);
365
366 if (old_state != port->ctrl)
367 ohci_set_interrupt(s, OHCI_INTR_RHSC);
368 }
369
370 /* Reset the controller */
371 static void ohci_reset(void *opaque)
372 {
373 OHCIState *ohci = opaque;
374 OHCIPort *port;
375 int i;
376
377 ohci_bus_stop(ohci);
378 ohci->ctl = 0;
379 ohci->old_ctl = 0;
380 ohci->status = 0;
381 ohci->intr_status = 0;
382 ohci->intr = OHCI_INTR_MIE;
383
384 ohci->hcca = 0;
385 ohci->ctrl_head = ohci->ctrl_cur = 0;
386 ohci->bulk_head = ohci->bulk_cur = 0;
387 ohci->per_cur = 0;
388 ohci->done = 0;
389 ohci->done_count = 7;
390
391 /* FSMPS is marked TBD in OCHI 1.0, what gives ffs?
392 * I took the value linux sets ...
393 */
394 ohci->fsmps = 0x2778;
395 ohci->fi = 0x2edf;
396 ohci->fit = 0;
397 ohci->frt = 0;
398 ohci->frame_number = 0;
399 ohci->pstart = 0;
400 ohci->lst = OHCI_LS_THRESH;
401
402 ohci->rhdesc_a = OHCI_RHA_NPS | ohci->num_ports;
403 ohci->rhdesc_b = 0x0; /* Impl. specific */
404 ohci->rhstatus = 0;
405
406 for (i = 0; i < ohci->num_ports; i++)
407 {
408 port = &ohci->rhport[i];
409 port->ctrl = 0;
410 if (port->port.dev) {
411 usb_attach(&port->port, port->port.dev);
412 }
413 }
414 if (ohci->async_td) {
415 usb_cancel_packet(&ohci->usb_packet);
416 ohci->async_td = 0;
417 }
418 DPRINTF("usb-ohci: Reset %s\n", ohci->name);
419 }
420
421 /* Get an array of dwords from main memory */
422 static inline int get_dwords(OHCIState *ohci,
423 uint32_t addr, uint32_t *buf, int num)
424 {
425 int i;
426
427 addr += ohci->localmem_base;
428
429 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
430 cpu_physical_memory_rw(addr, (uint8_t *)buf, sizeof(*buf), 0);
431 *buf = le32_to_cpu(*buf);
432 }
433
434 return 1;
435 }
436
437 /* Put an array of dwords in to main memory */
438 static inline int put_dwords(OHCIState *ohci,
439 uint32_t addr, uint32_t *buf, int num)
440 {
441 int i;
442
443 addr += ohci->localmem_base;
444
445 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
446 uint32_t tmp = cpu_to_le32(*buf);
447 cpu_physical_memory_rw(addr, (uint8_t *)&tmp, sizeof(tmp), 1);
448 }
449
450 return 1;
451 }
452
453 /* Get an array of words from main memory */
454 static inline int get_words(OHCIState *ohci,
455 uint32_t addr, uint16_t *buf, int num)
456 {
457 int i;
458
459 addr += ohci->localmem_base;
460
461 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
462 cpu_physical_memory_rw(addr, (uint8_t *)buf, sizeof(*buf), 0);
463 *buf = le16_to_cpu(*buf);
464 }
465
466 return 1;
467 }
468
469 /* Put an array of words in to main memory */
470 static inline int put_words(OHCIState *ohci,
471 uint32_t addr, uint16_t *buf, int num)
472 {
473 int i;
474
475 addr += ohci->localmem_base;
476
477 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
478 uint16_t tmp = cpu_to_le16(*buf);
479 cpu_physical_memory_rw(addr, (uint8_t *)&tmp, sizeof(tmp), 1);
480 }
481
482 return 1;
483 }
484
485 static inline int ohci_read_ed(OHCIState *ohci,
486 uint32_t addr, struct ohci_ed *ed)
487 {
488 return get_dwords(ohci, addr, (uint32_t *)ed, sizeof(*ed) >> 2);
489 }
490
491 static inline int ohci_read_td(OHCIState *ohci,
492 uint32_t addr, struct ohci_td *td)
493 {
494 return get_dwords(ohci, addr, (uint32_t *)td, sizeof(*td) >> 2);
495 }
496
497 static inline int ohci_read_iso_td(OHCIState *ohci,
498 uint32_t addr, struct ohci_iso_td *td)
499 {
500 return (get_dwords(ohci, addr, (uint32_t *)td, 4) &&
501 get_words(ohci, addr + 16, td->offset, 8));
502 }
503
504 static inline int ohci_read_hcca(OHCIState *ohci,
505 uint32_t addr, struct ohci_hcca *hcca)
506 {
507 cpu_physical_memory_rw(addr + ohci->localmem_base,
508 (uint8_t *)hcca, sizeof(*hcca), 0);
509 return 1;
510 }
511
512 static inline int ohci_put_ed(OHCIState *ohci,
513 uint32_t addr, struct ohci_ed *ed)
514 {
515 return put_dwords(ohci, addr, (uint32_t *)ed, sizeof(*ed) >> 2);
516 }
517
518 static inline int ohci_put_td(OHCIState *ohci,
519 uint32_t addr, struct ohci_td *td)
520 {
521 return put_dwords(ohci, addr, (uint32_t *)td, sizeof(*td) >> 2);
522 }
523
524 static inline int ohci_put_iso_td(OHCIState *ohci,
525 uint32_t addr, struct ohci_iso_td *td)
526 {
527 return (put_dwords(ohci, addr, (uint32_t *)td, 4) &&
528 put_words(ohci, addr + 16, td->offset, 8));
529 }
530
531 static inline int ohci_put_hcca(OHCIState *ohci,
532 uint32_t addr, struct ohci_hcca *hcca)
533 {
534 cpu_physical_memory_rw(addr + ohci->localmem_base,
535 (uint8_t *)hcca, sizeof(*hcca), 1);
536 return 1;
537 }
538
539 /* Read/Write the contents of a TD from/to main memory. */
540 static void ohci_copy_td(OHCIState *ohci, struct ohci_td *td,
541 uint8_t *buf, int len, int write)
542 {
543 uint32_t ptr;
544 uint32_t n;
545
546 ptr = td->cbp;
547 n = 0x1000 - (ptr & 0xfff);
548 if (n > len)
549 n = len;
550 cpu_physical_memory_rw(ptr + ohci->localmem_base, buf, n, write);
551 if (n == len)
552 return;
553 ptr = td->be & ~0xfffu;
554 buf += n;
555 cpu_physical_memory_rw(ptr + ohci->localmem_base, buf, len - n, write);
556 }
557
558 /* Read/Write the contents of an ISO TD from/to main memory. */
559 static void ohci_copy_iso_td(OHCIState *ohci,
560 uint32_t start_addr, uint32_t end_addr,
561 uint8_t *buf, int len, int write)
562 {
563 uint32_t ptr;
564 uint32_t n;
565
566 ptr = start_addr;
567 n = 0x1000 - (ptr & 0xfff);
568 if (n > len)
569 n = len;
570 cpu_physical_memory_rw(ptr + ohci->localmem_base, buf, n, write);
571 if (n == len)
572 return;
573 ptr = end_addr & ~0xfffu;
574 buf += n;
575 cpu_physical_memory_rw(ptr + ohci->localmem_base, buf, len - n, write);
576 }
577
578 static void ohci_process_lists(OHCIState *ohci, int completion);
579
580 static void ohci_async_complete_packet(USBPacket *packet, void *opaque)
581 {
582 OHCIState *ohci = opaque;
583 #ifdef DEBUG_PACKET
584 DPRINTF("Async packet complete\n");
585 #endif
586 ohci->async_complete = 1;
587 ohci_process_lists(ohci, 1);
588 }
589
590 #define USUB(a, b) ((int16_t)((uint16_t)(a) - (uint16_t)(b)))
591
592 static int ohci_service_iso_td(OHCIState *ohci, struct ohci_ed *ed,
593 int completion)
594 {
595 int dir;
596 size_t len = 0;
597 #ifdef DEBUG_ISOCH
598 const char *str = NULL;
599 #endif
600 int pid;
601 int ret;
602 int i;
603 USBDevice *dev;
604 struct ohci_iso_td iso_td;
605 uint32_t addr;
606 uint16_t starting_frame;
607 int16_t relative_frame_number;
608 int frame_count;
609 uint32_t start_offset, next_offset, end_offset = 0;
610 uint32_t start_addr, end_addr;
611
612 addr = ed->head & OHCI_DPTR_MASK;
613
614 if (!ohci_read_iso_td(ohci, addr, &iso_td)) {
615 printf("usb-ohci: ISO_TD read error at %x\n", addr);
616 return 0;
617 }
618
619 starting_frame = OHCI_BM(iso_td.flags, TD_SF);
620 frame_count = OHCI_BM(iso_td.flags, TD_FC);
621 relative_frame_number = USUB(ohci->frame_number, starting_frame);
622
623 #ifdef DEBUG_ISOCH
624 printf("--- ISO_TD ED head 0x%.8x tailp 0x%.8x\n"
625 "0x%.8x 0x%.8x 0x%.8x 0x%.8x\n"
626 "0x%.8x 0x%.8x 0x%.8x 0x%.8x\n"
627 "0x%.8x 0x%.8x 0x%.8x 0x%.8x\n"
628 "frame_number 0x%.8x starting_frame 0x%.8x\n"
629 "frame_count 0x%.8x relative %d\n"
630 "di 0x%.8x cc 0x%.8x\n",
631 ed->head & OHCI_DPTR_MASK, ed->tail & OHCI_DPTR_MASK,
632 iso_td.flags, iso_td.bp, iso_td.next, iso_td.be,
633 iso_td.offset[0], iso_td.offset[1], iso_td.offset[2], iso_td.offset[3],
634 iso_td.offset[4], iso_td.offset[5], iso_td.offset[6], iso_td.offset[7],
635 ohci->frame_number, starting_frame,
636 frame_count, relative_frame_number,
637 OHCI_BM(iso_td.flags, TD_DI), OHCI_BM(iso_td.flags, TD_CC));
638 #endif
639
640 if (relative_frame_number < 0) {
641 DPRINTF("usb-ohci: ISO_TD R=%d < 0\n", relative_frame_number);
642 return 1;
643 } else if (relative_frame_number > frame_count) {
644 /* ISO TD expired - retire the TD to the Done Queue and continue with
645 the next ISO TD of the same ED */
646 DPRINTF("usb-ohci: ISO_TD R=%d > FC=%d\n", relative_frame_number,
647 frame_count);
648 OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_DATAOVERRUN);
649 ed->head &= ~OHCI_DPTR_MASK;
650 ed->head |= (iso_td.next & OHCI_DPTR_MASK);
651 iso_td.next = ohci->done;
652 ohci->done = addr;
653 i = OHCI_BM(iso_td.flags, TD_DI);
654 if (i < ohci->done_count)
655 ohci->done_count = i;
656 ohci_put_iso_td(ohci, addr, &iso_td);
657 return 0;
658 }
659
660 dir = OHCI_BM(ed->flags, ED_D);
661 switch (dir) {
662 case OHCI_TD_DIR_IN:
663 #ifdef DEBUG_ISOCH
664 str = "in";
665 #endif
666 pid = USB_TOKEN_IN;
667 break;
668 case OHCI_TD_DIR_OUT:
669 #ifdef DEBUG_ISOCH
670 str = "out";
671 #endif
672 pid = USB_TOKEN_OUT;
673 break;
674 case OHCI_TD_DIR_SETUP:
675 #ifdef DEBUG_ISOCH
676 str = "setup";
677 #endif
678 pid = USB_TOKEN_SETUP;
679 break;
680 default:
681 printf("usb-ohci: Bad direction %d\n", dir);
682 return 1;
683 }
684
685 if (!iso_td.bp || !iso_td.be) {
686 printf("usb-ohci: ISO_TD bp 0x%.8x be 0x%.8x\n", iso_td.bp, iso_td.be);
687 return 1;
688 }
689
690 start_offset = iso_td.offset[relative_frame_number];
691 next_offset = iso_td.offset[relative_frame_number + 1];
692
693 if (!(OHCI_BM(start_offset, TD_PSW_CC) & 0xe) ||
694 ((relative_frame_number < frame_count) &&
695 !(OHCI_BM(next_offset, TD_PSW_CC) & 0xe))) {
696 printf("usb-ohci: ISO_TD cc != not accessed 0x%.8x 0x%.8x\n",
697 start_offset, next_offset);
698 return 1;
699 }
700
701 if ((relative_frame_number < frame_count) && (start_offset > next_offset)) {
702 printf("usb-ohci: ISO_TD start_offset=0x%.8x > next_offset=0x%.8x\n",
703 start_offset, next_offset);
704 return 1;
705 }
706
707 if ((start_offset & 0x1000) == 0) {
708 start_addr = (iso_td.bp & OHCI_PAGE_MASK) |
709 (start_offset & OHCI_OFFSET_MASK);
710 } else {
711 start_addr = (iso_td.be & OHCI_PAGE_MASK) |
712 (start_offset & OHCI_OFFSET_MASK);
713 }
714
715 if (relative_frame_number < frame_count) {
716 end_offset = next_offset - 1;
717 if ((end_offset & 0x1000) == 0) {
718 end_addr = (iso_td.bp & OHCI_PAGE_MASK) |
719 (end_offset & OHCI_OFFSET_MASK);
720 } else {
721 end_addr = (iso_td.be & OHCI_PAGE_MASK) |
722 (end_offset & OHCI_OFFSET_MASK);
723 }
724 } else {
725 /* Last packet in the ISO TD */
726 end_addr = iso_td.be;
727 }
728
729 if ((start_addr & OHCI_PAGE_MASK) != (end_addr & OHCI_PAGE_MASK)) {
730 len = (end_addr & OHCI_OFFSET_MASK) + 0x1001
731 - (start_addr & OHCI_OFFSET_MASK);
732 } else {
733 len = end_addr - start_addr + 1;
734 }
735
736 if (len && dir != OHCI_TD_DIR_IN) {
737 ohci_copy_iso_td(ohci, start_addr, end_addr, ohci->usb_buf, len, 0);
738 }
739
740 if (completion) {
741 ret = ohci->usb_packet.len;
742 } else {
743 ret = USB_RET_NODEV;
744 for (i = 0; i < ohci->num_ports; i++) {
745 dev = ohci->rhport[i].port.dev;
746 if ((ohci->rhport[i].ctrl & OHCI_PORT_PES) == 0)
747 continue;
748 ohci->usb_packet.pid = pid;
749 ohci->usb_packet.devaddr = OHCI_BM(ed->flags, ED_FA);
750 ohci->usb_packet.devep = OHCI_BM(ed->flags, ED_EN);
751 ohci->usb_packet.data = ohci->usb_buf;
752 ohci->usb_packet.len = len;
753 ohci->usb_packet.complete_cb = ohci_async_complete_packet;
754 ohci->usb_packet.complete_opaque = ohci;
755 ret = dev->info->handle_packet(dev, &ohci->usb_packet);
756 if (ret != USB_RET_NODEV)
757 break;
758 }
759
760 if (ret == USB_RET_ASYNC) {
761 return 1;
762 }
763 }
764
765 #ifdef DEBUG_ISOCH
766 printf("so 0x%.8x eo 0x%.8x\nsa 0x%.8x ea 0x%.8x\ndir %s len %zu ret %d\n",
767 start_offset, end_offset, start_addr, end_addr, str, len, ret);
768 #endif
769
770 /* Writeback */
771 if (dir == OHCI_TD_DIR_IN && ret >= 0 && ret <= len) {
772 /* IN transfer succeeded */
773 ohci_copy_iso_td(ohci, start_addr, end_addr, ohci->usb_buf, ret, 1);
774 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
775 OHCI_CC_NOERROR);
776 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, ret);
777 } else if (dir == OHCI_TD_DIR_OUT && ret == len) {
778 /* OUT transfer succeeded */
779 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
780 OHCI_CC_NOERROR);
781 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, 0);
782 } else {
783 if (ret > (ssize_t) len) {
784 printf("usb-ohci: DataOverrun %d > %zu\n", ret, len);
785 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
786 OHCI_CC_DATAOVERRUN);
787 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE,
788 len);
789 } else if (ret >= 0) {
790 printf("usb-ohci: DataUnderrun %d\n", ret);
791 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
792 OHCI_CC_DATAUNDERRUN);
793 } else {
794 switch (ret) {
795 case USB_RET_NODEV:
796 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
797 OHCI_CC_DEVICENOTRESPONDING);
798 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE,
799 0);
800 break;
801 case USB_RET_NAK:
802 case USB_RET_STALL:
803 printf("usb-ohci: got NAK/STALL %d\n", ret);
804 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
805 OHCI_CC_STALL);
806 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE,
807 0);
808 break;
809 default:
810 printf("usb-ohci: Bad device response %d\n", ret);
811 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
812 OHCI_CC_UNDEXPETEDPID);
813 break;
814 }
815 }
816 }
817
818 if (relative_frame_number == frame_count) {
819 /* Last data packet of ISO TD - retire the TD to the Done Queue */
820 OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_NOERROR);
821 ed->head &= ~OHCI_DPTR_MASK;
822 ed->head |= (iso_td.next & OHCI_DPTR_MASK);
823 iso_td.next = ohci->done;
824 ohci->done = addr;
825 i = OHCI_BM(iso_td.flags, TD_DI);
826 if (i < ohci->done_count)
827 ohci->done_count = i;
828 }
829 ohci_put_iso_td(ohci, addr, &iso_td);
830 return 1;
831 }
832
833 /* Service a transport descriptor.
834 Returns nonzero to terminate processing of this endpoint. */
835
836 static int ohci_service_td(OHCIState *ohci, struct ohci_ed *ed)
837 {
838 int dir;
839 size_t len = 0;
840 #ifdef DEBUG_PACKET
841 const char *str = NULL;
842 #endif
843 int pid;
844 int ret;
845 int i;
846 USBDevice *dev;
847 struct ohci_td td;
848 uint32_t addr;
849 int flag_r;
850 int completion;
851
852 addr = ed->head & OHCI_DPTR_MASK;
853 /* See if this TD has already been submitted to the device. */
854 completion = (addr == ohci->async_td);
855 if (completion && !ohci->async_complete) {
856 #ifdef DEBUG_PACKET
857 DPRINTF("Skipping async TD\n");
858 #endif
859 return 1;
860 }
861 if (!ohci_read_td(ohci, addr, &td)) {
862 fprintf(stderr, "usb-ohci: TD read error at %x\n", addr);
863 return 0;
864 }
865
866 dir = OHCI_BM(ed->flags, ED_D);
867 switch (dir) {
868 case OHCI_TD_DIR_OUT:
869 case OHCI_TD_DIR_IN:
870 /* Same value. */
871 break;
872 default:
873 dir = OHCI_BM(td.flags, TD_DP);
874 break;
875 }
876
877 switch (dir) {
878 case OHCI_TD_DIR_IN:
879 #ifdef DEBUG_PACKET
880 str = "in";
881 #endif
882 pid = USB_TOKEN_IN;
883 break;
884 case OHCI_TD_DIR_OUT:
885 #ifdef DEBUG_PACKET
886 str = "out";
887 #endif
888 pid = USB_TOKEN_OUT;
889 break;
890 case OHCI_TD_DIR_SETUP:
891 #ifdef DEBUG_PACKET
892 str = "setup";
893 #endif
894 pid = USB_TOKEN_SETUP;
895 break;
896 default:
897 fprintf(stderr, "usb-ohci: Bad direction\n");
898 return 1;
899 }
900 if (td.cbp && td.be) {
901 if ((td.cbp & 0xfffff000) != (td.be & 0xfffff000)) {
902 len = (td.be & 0xfff) + 0x1001 - (td.cbp & 0xfff);
903 } else {
904 len = (td.be - td.cbp) + 1;
905 }
906
907 if (len && dir != OHCI_TD_DIR_IN && !completion) {
908 ohci_copy_td(ohci, &td, ohci->usb_buf, len, 0);
909 }
910 }
911
912 flag_r = (td.flags & OHCI_TD_R) != 0;
913 #ifdef DEBUG_PACKET
914 DPRINTF(" TD @ 0x%.8x %" PRId64 " bytes %s r=%d cbp=0x%.8x be=0x%.8x\n",
915 addr, (int64_t)len, str, flag_r, td.cbp, td.be);
916
917 if (len > 0 && dir != OHCI_TD_DIR_IN) {
918 DPRINTF(" data:");
919 for (i = 0; i < len; i++)
920 printf(" %.2x", ohci->usb_buf[i]);
921 DPRINTF("\n");
922 }
923 #endif
924 if (completion) {
925 ret = ohci->usb_packet.len;
926 ohci->async_td = 0;
927 ohci->async_complete = 0;
928 } else {
929 ret = USB_RET_NODEV;
930 for (i = 0; i < ohci->num_ports; i++) {
931 dev = ohci->rhport[i].port.dev;
932 if ((ohci->rhport[i].ctrl & OHCI_PORT_PES) == 0)
933 continue;
934
935 if (ohci->async_td) {
936 /* ??? The hardware should allow one active packet per
937 endpoint. We only allow one active packet per controller.
938 This should be sufficient as long as devices respond in a
939 timely manner.
940 */
941 #ifdef DEBUG_PACKET
942 DPRINTF("Too many pending packets\n");
943 #endif
944 return 1;
945 }
946 ohci->usb_packet.pid = pid;
947 ohci->usb_packet.devaddr = OHCI_BM(ed->flags, ED_FA);
948 ohci->usb_packet.devep = OHCI_BM(ed->flags, ED_EN);
949 ohci->usb_packet.data = ohci->usb_buf;
950 ohci->usb_packet.len = len;
951 ohci->usb_packet.complete_cb = ohci_async_complete_packet;
952 ohci->usb_packet.complete_opaque = ohci;
953 ret = dev->info->handle_packet(dev, &ohci->usb_packet);
954 if (ret != USB_RET_NODEV)
955 break;
956 }
957 #ifdef DEBUG_PACKET
958 DPRINTF("ret=%d\n", ret);
959 #endif
960 if (ret == USB_RET_ASYNC) {
961 ohci->async_td = addr;
962 return 1;
963 }
964 }
965 if (ret >= 0) {
966 if (dir == OHCI_TD_DIR_IN) {
967 ohci_copy_td(ohci, &td, ohci->usb_buf, ret, 1);
968 #ifdef DEBUG_PACKET
969 DPRINTF(" data:");
970 for (i = 0; i < ret; i++)
971 printf(" %.2x", ohci->usb_buf[i]);
972 DPRINTF("\n");
973 #endif
974 } else {
975 ret = len;
976 }
977 }
978
979 /* Writeback */
980 if (ret == len || (dir == OHCI_TD_DIR_IN && ret >= 0 && flag_r)) {
981 /* Transmission succeeded. */
982 if (ret == len) {
983 td.cbp = 0;
984 } else {
985 td.cbp += ret;
986 if ((td.cbp & 0xfff) + ret > 0xfff) {
987 td.cbp &= 0xfff;
988 td.cbp |= td.be & ~0xfff;
989 }
990 }
991 td.flags |= OHCI_TD_T1;
992 td.flags ^= OHCI_TD_T0;
993 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_NOERROR);
994 OHCI_SET_BM(td.flags, TD_EC, 0);
995
996 ed->head &= ~OHCI_ED_C;
997 if (td.flags & OHCI_TD_T0)
998 ed->head |= OHCI_ED_C;
999 } else {
1000 if (ret >= 0) {
1001 DPRINTF("usb-ohci: Underrun\n");
1002 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAUNDERRUN);
1003 } else {
1004 switch (ret) {
1005 case USB_RET_NODEV:
1006 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DEVICENOTRESPONDING);
1007 case USB_RET_NAK:
1008 DPRINTF("usb-ohci: got NAK\n");
1009 return 1;
1010 case USB_RET_STALL:
1011 DPRINTF("usb-ohci: got STALL\n");
1012 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_STALL);
1013 break;
1014 case USB_RET_BABBLE:
1015 DPRINTF("usb-ohci: got BABBLE\n");
1016 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAOVERRUN);
1017 break;
1018 default:
1019 fprintf(stderr, "usb-ohci: Bad device response %d\n", ret);
1020 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_UNDEXPETEDPID);
1021 OHCI_SET_BM(td.flags, TD_EC, 3);
1022 break;
1023 }
1024 }
1025 ed->head |= OHCI_ED_H;
1026 }
1027
1028 /* Retire this TD */
1029 ed->head &= ~OHCI_DPTR_MASK;
1030 ed->head |= td.next & OHCI_DPTR_MASK;
1031 td.next = ohci->done;
1032 ohci->done = addr;
1033 i = OHCI_BM(td.flags, TD_DI);
1034 if (i < ohci->done_count)
1035 ohci->done_count = i;
1036 ohci_put_td(ohci, addr, &td);
1037 return OHCI_BM(td.flags, TD_CC) != OHCI_CC_NOERROR;
1038 }
1039
1040 /* Service an endpoint list. Returns nonzero if active TD were found. */
1041 static int ohci_service_ed_list(OHCIState *ohci, uint32_t head, int completion)
1042 {
1043 struct ohci_ed ed;
1044 uint32_t next_ed;
1045 uint32_t cur;
1046 int active;
1047
1048 active = 0;
1049
1050 if (head == 0)
1051 return 0;
1052
1053 for (cur = head; cur; cur = next_ed) {
1054 if (!ohci_read_ed(ohci, cur, &ed)) {
1055 fprintf(stderr, "usb-ohci: ED read error at %x\n", cur);
1056 return 0;
1057 }
1058
1059 next_ed = ed.next & OHCI_DPTR_MASK;
1060
1061 if ((ed.head & OHCI_ED_H) || (ed.flags & OHCI_ED_K)) {
1062 uint32_t addr;
1063 /* Cancel pending packets for ED that have been paused. */
1064 addr = ed.head & OHCI_DPTR_MASK;
1065 if (ohci->async_td && addr == ohci->async_td) {
1066 usb_cancel_packet(&ohci->usb_packet);
1067 ohci->async_td = 0;
1068 }
1069 continue;
1070 }
1071
1072 while ((ed.head & OHCI_DPTR_MASK) != ed.tail) {
1073 #ifdef DEBUG_PACKET
1074 DPRINTF("ED @ 0x%.8x fa=%u en=%u d=%u s=%u k=%u f=%u mps=%u "
1075 "h=%u c=%u\n head=0x%.8x tailp=0x%.8x next=0x%.8x\n", cur,
1076 OHCI_BM(ed.flags, ED_FA), OHCI_BM(ed.flags, ED_EN),
1077 OHCI_BM(ed.flags, ED_D), (ed.flags & OHCI_ED_S)!= 0,
1078 (ed.flags & OHCI_ED_K) != 0, (ed.flags & OHCI_ED_F) != 0,
1079 OHCI_BM(ed.flags, ED_MPS), (ed.head & OHCI_ED_H) != 0,
1080 (ed.head & OHCI_ED_C) != 0, ed.head & OHCI_DPTR_MASK,
1081 ed.tail & OHCI_DPTR_MASK, ed.next & OHCI_DPTR_MASK);
1082 #endif
1083 active = 1;
1084
1085 if ((ed.flags & OHCI_ED_F) == 0) {
1086 if (ohci_service_td(ohci, &ed))
1087 break;
1088 } else {
1089 /* Handle isochronous endpoints */
1090 if (ohci_service_iso_td(ohci, &ed, completion))
1091 break;
1092 }
1093 }
1094
1095 ohci_put_ed(ohci, cur, &ed);
1096 }
1097
1098 return active;
1099 }
1100
1101 /* Generate a SOF event, and set a timer for EOF */
1102 static void ohci_sof(OHCIState *ohci)
1103 {
1104 ohci->sof_time = qemu_get_clock_ns(vm_clock);
1105 qemu_mod_timer(ohci->eof_timer, ohci->sof_time + usb_frame_time);
1106 ohci_set_interrupt(ohci, OHCI_INTR_SF);
1107 }
1108
1109 /* Process Control and Bulk lists. */
1110 static void ohci_process_lists(OHCIState *ohci, int completion)
1111 {
1112 if ((ohci->ctl & OHCI_CTL_CLE) && (ohci->status & OHCI_STATUS_CLF)) {
1113 if (ohci->ctrl_cur && ohci->ctrl_cur != ohci->ctrl_head) {
1114 DPRINTF("usb-ohci: head %x, cur %x\n",
1115 ohci->ctrl_head, ohci->ctrl_cur);
1116 }
1117 if (!ohci_service_ed_list(ohci, ohci->ctrl_head, completion)) {
1118 ohci->ctrl_cur = 0;
1119 ohci->status &= ~OHCI_STATUS_CLF;
1120 }
1121 }
1122
1123 if ((ohci->ctl & OHCI_CTL_BLE) && (ohci->status & OHCI_STATUS_BLF)) {
1124 if (!ohci_service_ed_list(ohci, ohci->bulk_head, completion)) {
1125 ohci->bulk_cur = 0;
1126 ohci->status &= ~OHCI_STATUS_BLF;
1127 }
1128 }
1129 }
1130
1131 /* Do frame processing on frame boundary */
1132 static void ohci_frame_boundary(void *opaque)
1133 {
1134 OHCIState *ohci = opaque;
1135 struct ohci_hcca hcca;
1136
1137 ohci_read_hcca(ohci, ohci->hcca, &hcca);
1138
1139 /* Process all the lists at the end of the frame */
1140 if (ohci->ctl & OHCI_CTL_PLE) {
1141 int n;
1142
1143 n = ohci->frame_number & 0x1f;
1144 ohci_service_ed_list(ohci, le32_to_cpu(hcca.intr[n]), 0);
1145 }
1146
1147 /* Cancel all pending packets if either of the lists has been disabled. */
1148 if (ohci->async_td &&
1149 ohci->old_ctl & (~ohci->ctl) & (OHCI_CTL_BLE | OHCI_CTL_CLE)) {
1150 usb_cancel_packet(&ohci->usb_packet);
1151 ohci->async_td = 0;
1152 }
1153 ohci->old_ctl = ohci->ctl;
1154 ohci_process_lists(ohci, 0);
1155
1156 /* Frame boundary, so do EOF stuf here */
1157 ohci->frt = ohci->fit;
1158
1159 /* Increment frame number and take care of endianness. */
1160 ohci->frame_number = (ohci->frame_number + 1) & 0xffff;
1161 hcca.frame = cpu_to_le16(ohci->frame_number);
1162
1163 if (ohci->done_count == 0 && !(ohci->intr_status & OHCI_INTR_WD)) {
1164 if (!ohci->done)
1165 abort();
1166 if (ohci->intr & ohci->intr_status)
1167 ohci->done |= 1;
1168 hcca.done = cpu_to_le32(ohci->done);
1169 ohci->done = 0;
1170 ohci->done_count = 7;
1171 ohci_set_interrupt(ohci, OHCI_INTR_WD);
1172 }
1173
1174 if (ohci->done_count != 7 && ohci->done_count != 0)
1175 ohci->done_count--;
1176
1177 /* Do SOF stuff here */
1178 ohci_sof(ohci);
1179
1180 /* Writeback HCCA */
1181 ohci_put_hcca(ohci, ohci->hcca, &hcca);
1182 }
1183
1184 /* Start sending SOF tokens across the USB bus, lists are processed in
1185 * next frame
1186 */
1187 static int ohci_bus_start(OHCIState *ohci)
1188 {
1189 ohci->eof_timer = qemu_new_timer_ns(vm_clock,
1190 ohci_frame_boundary,
1191 ohci);
1192
1193 if (ohci->eof_timer == NULL) {
1194 fprintf(stderr, "usb-ohci: %s: qemu_new_timer_ns failed\n", ohci->name);
1195 /* TODO: Signal unrecoverable error */
1196 return 0;
1197 }
1198
1199 DPRINTF("usb-ohci: %s: USB Operational\n", ohci->name);
1200
1201 ohci_sof(ohci);
1202
1203 return 1;
1204 }
1205
1206 /* Stop sending SOF tokens on the bus */
1207 static void ohci_bus_stop(OHCIState *ohci)
1208 {
1209 if (ohci->eof_timer)
1210 qemu_del_timer(ohci->eof_timer);
1211 ohci->eof_timer = NULL;
1212 }
1213
1214 /* Sets a flag in a port status register but only set it if the port is
1215 * connected, if not set ConnectStatusChange flag. If flag is enabled
1216 * return 1.
1217 */
1218 static int ohci_port_set_if_connected(OHCIState *ohci, int i, uint32_t val)
1219 {
1220 int ret = 1;
1221
1222 /* writing a 0 has no effect */
1223 if (val == 0)
1224 return 0;
1225
1226 /* If CurrentConnectStatus is cleared we set
1227 * ConnectStatusChange
1228 */
1229 if (!(ohci->rhport[i].ctrl & OHCI_PORT_CCS)) {
1230 ohci->rhport[i].ctrl |= OHCI_PORT_CSC;
1231 if (ohci->rhstatus & OHCI_RHS_DRWE) {
1232 /* TODO: CSC is a wakeup event */
1233 }
1234 return 0;
1235 }
1236
1237 if (ohci->rhport[i].ctrl & val)
1238 ret = 0;
1239
1240 /* set the bit */
1241 ohci->rhport[i].ctrl |= val;
1242
1243 return ret;
1244 }
1245
1246 /* Set the frame interval - frame interval toggle is manipulated by the hcd only */
1247 static void ohci_set_frame_interval(OHCIState *ohci, uint16_t val)
1248 {
1249 val &= OHCI_FMI_FI;
1250
1251 if (val != ohci->fi) {
1252 DPRINTF("usb-ohci: %s: FrameInterval = 0x%x (%u)\n",
1253 ohci->name, ohci->fi, ohci->fi);
1254 }
1255
1256 ohci->fi = val;
1257 }
1258
1259 static void ohci_port_power(OHCIState *ohci, int i, int p)
1260 {
1261 if (p) {
1262 ohci->rhport[i].ctrl |= OHCI_PORT_PPS;
1263 } else {
1264 ohci->rhport[i].ctrl &= ~(OHCI_PORT_PPS|
1265 OHCI_PORT_CCS|
1266 OHCI_PORT_PSS|
1267 OHCI_PORT_PRS);
1268 }
1269 }
1270
1271 /* Set HcControlRegister */
1272 static void ohci_set_ctl(OHCIState *ohci, uint32_t val)
1273 {
1274 uint32_t old_state;
1275 uint32_t new_state;
1276
1277 old_state = ohci->ctl & OHCI_CTL_HCFS;
1278 ohci->ctl = val;
1279 new_state = ohci->ctl & OHCI_CTL_HCFS;
1280
1281 /* no state change */
1282 if (old_state == new_state)
1283 return;
1284
1285 switch (new_state) {
1286 case OHCI_USB_OPERATIONAL:
1287 ohci_bus_start(ohci);
1288 break;
1289 case OHCI_USB_SUSPEND:
1290 ohci_bus_stop(ohci);
1291 DPRINTF("usb-ohci: %s: USB Suspended\n", ohci->name);
1292 break;
1293 case OHCI_USB_RESUME:
1294 DPRINTF("usb-ohci: %s: USB Resume\n", ohci->name);
1295 break;
1296 case OHCI_USB_RESET:
1297 ohci_reset(ohci);
1298 DPRINTF("usb-ohci: %s: USB Reset\n", ohci->name);
1299 break;
1300 }
1301 }
1302
1303 static uint32_t ohci_get_frame_remaining(OHCIState *ohci)
1304 {
1305 uint16_t fr;
1306 int64_t tks;
1307
1308 if ((ohci->ctl & OHCI_CTL_HCFS) != OHCI_USB_OPERATIONAL)
1309 return (ohci->frt << 31);
1310
1311 /* Being in USB operational state guarnatees sof_time was
1312 * set already.
1313 */
1314 tks = qemu_get_clock_ns(vm_clock) - ohci->sof_time;
1315
1316 /* avoid muldiv if possible */
1317 if (tks >= usb_frame_time)
1318 return (ohci->frt << 31);
1319
1320 tks = muldiv64(1, tks, usb_bit_time);
1321 fr = (uint16_t)(ohci->fi - tks);
1322
1323 return (ohci->frt << 31) | fr;
1324 }
1325
1326
1327 /* Set root hub status */
1328 static void ohci_set_hub_status(OHCIState *ohci, uint32_t val)
1329 {
1330 uint32_t old_state;
1331
1332 old_state = ohci->rhstatus;
1333
1334 /* write 1 to clear OCIC */
1335 if (val & OHCI_RHS_OCIC)
1336 ohci->rhstatus &= ~OHCI_RHS_OCIC;
1337
1338 if (val & OHCI_RHS_LPS) {
1339 int i;
1340
1341 for (i = 0; i < ohci->num_ports; i++)
1342 ohci_port_power(ohci, i, 0);
1343 DPRINTF("usb-ohci: powered down all ports\n");
1344 }
1345
1346 if (val & OHCI_RHS_LPSC) {
1347 int i;
1348
1349 for (i = 0; i < ohci->num_ports; i++)
1350 ohci_port_power(ohci, i, 1);
1351 DPRINTF("usb-ohci: powered up all ports\n");
1352 }
1353
1354 if (val & OHCI_RHS_DRWE)
1355 ohci->rhstatus |= OHCI_RHS_DRWE;
1356
1357 if (val & OHCI_RHS_CRWE)
1358 ohci->rhstatus &= ~OHCI_RHS_DRWE;
1359
1360 if (old_state != ohci->rhstatus)
1361 ohci_set_interrupt(ohci, OHCI_INTR_RHSC);
1362 }
1363
1364 /* Set root hub port status */
1365 static void ohci_port_set_status(OHCIState *ohci, int portnum, uint32_t val)
1366 {
1367 uint32_t old_state;
1368 OHCIPort *port;
1369
1370 port = &ohci->rhport[portnum];
1371 old_state = port->ctrl;
1372
1373 /* Write to clear CSC, PESC, PSSC, OCIC, PRSC */
1374 if (val & OHCI_PORT_WTC)
1375 port->ctrl &= ~(val & OHCI_PORT_WTC);
1376
1377 if (val & OHCI_PORT_CCS)
1378 port->ctrl &= ~OHCI_PORT_PES;
1379
1380 ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PES);
1381
1382 if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PSS)) {
1383 DPRINTF("usb-ohci: port %d: SUSPEND\n", portnum);
1384 }
1385
1386 if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PRS)) {
1387 DPRINTF("usb-ohci: port %d: RESET\n", portnum);
1388 usb_send_msg(port->port.dev, USB_MSG_RESET);
1389 port->ctrl &= ~OHCI_PORT_PRS;
1390 /* ??? Should this also set OHCI_PORT_PESC. */
1391 port->ctrl |= OHCI_PORT_PES | OHCI_PORT_PRSC;
1392 }
1393
1394 /* Invert order here to ensure in ambiguous case, device is
1395 * powered up...
1396 */
1397 if (val & OHCI_PORT_LSDA)
1398 ohci_port_power(ohci, portnum, 0);
1399 if (val & OHCI_PORT_PPS)
1400 ohci_port_power(ohci, portnum, 1);
1401
1402 if (old_state != port->ctrl)
1403 ohci_set_interrupt(ohci, OHCI_INTR_RHSC);
1404
1405 return;
1406 }
1407
1408 static uint32_t ohci_mem_read(void *ptr, target_phys_addr_t addr)
1409 {
1410 OHCIState *ohci = ptr;
1411 uint32_t retval;
1412
1413 addr &= 0xff;
1414
1415 /* Only aligned reads are allowed on OHCI */
1416 if (addr & 3) {
1417 fprintf(stderr, "usb-ohci: Mis-aligned read\n");
1418 return 0xffffffff;
1419 } else if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) {
1420 /* HcRhPortStatus */
1421 retval = ohci->rhport[(addr - 0x54) >> 2].ctrl | OHCI_PORT_PPS;
1422 } else {
1423 switch (addr >> 2) {
1424 case 0: /* HcRevision */
1425 retval = 0x10;
1426 break;
1427
1428 case 1: /* HcControl */
1429 retval = ohci->ctl;
1430 break;
1431
1432 case 2: /* HcCommandStatus */
1433 retval = ohci->status;
1434 break;
1435
1436 case 3: /* HcInterruptStatus */
1437 retval = ohci->intr_status;
1438 break;
1439
1440 case 4: /* HcInterruptEnable */
1441 case 5: /* HcInterruptDisable */
1442 retval = ohci->intr;
1443 break;
1444
1445 case 6: /* HcHCCA */
1446 retval = ohci->hcca;
1447 break;
1448
1449 case 7: /* HcPeriodCurrentED */
1450 retval = ohci->per_cur;
1451 break;
1452
1453 case 8: /* HcControlHeadED */
1454 retval = ohci->ctrl_head;
1455 break;
1456
1457 case 9: /* HcControlCurrentED */
1458 retval = ohci->ctrl_cur;
1459 break;
1460
1461 case 10: /* HcBulkHeadED */
1462 retval = ohci->bulk_head;
1463 break;
1464
1465 case 11: /* HcBulkCurrentED */
1466 retval = ohci->bulk_cur;
1467 break;
1468
1469 case 12: /* HcDoneHead */
1470 retval = ohci->done;
1471 break;
1472
1473 case 13: /* HcFmInterretval */
1474 retval = (ohci->fit << 31) | (ohci->fsmps << 16) | (ohci->fi);
1475 break;
1476
1477 case 14: /* HcFmRemaining */
1478 retval = ohci_get_frame_remaining(ohci);
1479 break;
1480
1481 case 15: /* HcFmNumber */
1482 retval = ohci->frame_number;
1483 break;
1484
1485 case 16: /* HcPeriodicStart */
1486 retval = ohci->pstart;
1487 break;
1488
1489 case 17: /* HcLSThreshold */
1490 retval = ohci->lst;
1491 break;
1492
1493 case 18: /* HcRhDescriptorA */
1494 retval = ohci->rhdesc_a;
1495 break;
1496
1497 case 19: /* HcRhDescriptorB */
1498 retval = ohci->rhdesc_b;
1499 break;
1500
1501 case 20: /* HcRhStatus */
1502 retval = ohci->rhstatus;
1503 break;
1504
1505 /* PXA27x specific registers */
1506 case 24: /* HcStatus */
1507 retval = ohci->hstatus & ohci->hmask;
1508 break;
1509
1510 case 25: /* HcHReset */
1511 retval = ohci->hreset;
1512 break;
1513
1514 case 26: /* HcHInterruptEnable */
1515 retval = ohci->hmask;
1516 break;
1517
1518 case 27: /* HcHInterruptTest */
1519 retval = ohci->htest;
1520 break;
1521
1522 default:
1523 fprintf(stderr, "ohci_read: Bad offset %x\n", (int)addr);
1524 retval = 0xffffffff;
1525 }
1526 }
1527
1528 return retval;
1529 }
1530
1531 static void ohci_mem_write(void *ptr, target_phys_addr_t addr, uint32_t val)
1532 {
1533 OHCIState *ohci = ptr;
1534
1535 addr &= 0xff;
1536
1537 /* Only aligned reads are allowed on OHCI */
1538 if (addr & 3) {
1539 fprintf(stderr, "usb-ohci: Mis-aligned write\n");
1540 return;
1541 }
1542
1543 if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) {
1544 /* HcRhPortStatus */
1545 ohci_port_set_status(ohci, (addr - 0x54) >> 2, val);
1546 return;
1547 }
1548
1549 switch (addr >> 2) {
1550 case 1: /* HcControl */
1551 ohci_set_ctl(ohci, val);
1552 break;
1553
1554 case 2: /* HcCommandStatus */
1555 /* SOC is read-only */
1556 val = (val & ~OHCI_STATUS_SOC);
1557
1558 /* Bits written as '0' remain unchanged in the register */
1559 ohci->status |= val;
1560
1561 if (ohci->status & OHCI_STATUS_HCR)
1562 ohci_reset(ohci);
1563 break;
1564
1565 case 3: /* HcInterruptStatus */
1566 ohci->intr_status &= ~val;
1567 ohci_intr_update(ohci);
1568 break;
1569
1570 case 4: /* HcInterruptEnable */
1571 ohci->intr |= val;
1572 ohci_intr_update(ohci);
1573 break;
1574
1575 case 5: /* HcInterruptDisable */
1576 ohci->intr &= ~val;
1577 ohci_intr_update(ohci);
1578 break;
1579
1580 case 6: /* HcHCCA */
1581 ohci->hcca = val & OHCI_HCCA_MASK;
1582 break;
1583
1584 case 8: /* HcControlHeadED */
1585 ohci->ctrl_head = val & OHCI_EDPTR_MASK;
1586 break;
1587
1588 case 9: /* HcControlCurrentED */
1589 ohci->ctrl_cur = val & OHCI_EDPTR_MASK;
1590 break;
1591
1592 case 10: /* HcBulkHeadED */
1593 ohci->bulk_head = val & OHCI_EDPTR_MASK;
1594 break;
1595
1596 case 11: /* HcBulkCurrentED */
1597 ohci->bulk_cur = val & OHCI_EDPTR_MASK;
1598 break;
1599
1600 case 13: /* HcFmInterval */
1601 ohci->fsmps = (val & OHCI_FMI_FSMPS) >> 16;
1602 ohci->fit = (val & OHCI_FMI_FIT) >> 31;
1603 ohci_set_frame_interval(ohci, val);
1604 break;
1605
1606 case 15: /* HcFmNumber */
1607 break;
1608
1609 case 16: /* HcPeriodicStart */
1610 ohci->pstart = val & 0xffff;
1611 break;
1612
1613 case 17: /* HcLSThreshold */
1614 ohci->lst = val & 0xffff;
1615 break;
1616
1617 case 18: /* HcRhDescriptorA */
1618 ohci->rhdesc_a &= ~OHCI_RHA_RW_MASK;
1619 ohci->rhdesc_a |= val & OHCI_RHA_RW_MASK;
1620 break;
1621
1622 case 19: /* HcRhDescriptorB */
1623 break;
1624
1625 case 20: /* HcRhStatus */
1626 ohci_set_hub_status(ohci, val);
1627 break;
1628
1629 /* PXA27x specific registers */
1630 case 24: /* HcStatus */
1631 ohci->hstatus &= ~(val & ohci->hmask);
1632
1633 case 25: /* HcHReset */
1634 ohci->hreset = val & ~OHCI_HRESET_FSBIR;
1635 if (val & OHCI_HRESET_FSBIR)
1636 ohci_reset(ohci);
1637 break;
1638
1639 case 26: /* HcHInterruptEnable */
1640 ohci->hmask = val;
1641 break;
1642
1643 case 27: /* HcHInterruptTest */
1644 ohci->htest = val;
1645 break;
1646
1647 default:
1648 fprintf(stderr, "ohci_write: Bad offset %x\n", (int)addr);
1649 break;
1650 }
1651 }
1652
1653 /* Only dword reads are defined on OHCI register space */
1654 static CPUReadMemoryFunc * const ohci_readfn[3]={
1655 ohci_mem_read,
1656 ohci_mem_read,
1657 ohci_mem_read
1658 };
1659
1660 /* Only dword writes are defined on OHCI register space */
1661 static CPUWriteMemoryFunc * const ohci_writefn[3]={
1662 ohci_mem_write,
1663 ohci_mem_write,
1664 ohci_mem_write
1665 };
1666
1667 static USBPortOps ohci_port_ops = {
1668 .attach = ohci_attach,
1669 .detach = ohci_detach,
1670 };
1671
1672 static void usb_ohci_init(OHCIState *ohci, DeviceState *dev,
1673 int num_ports, uint32_t localmem_base)
1674 {
1675 int i;
1676
1677 if (usb_frame_time == 0) {
1678 #ifdef OHCI_TIME_WARP
1679 usb_frame_time = get_ticks_per_sec();
1680 usb_bit_time = muldiv64(1, get_ticks_per_sec(), USB_HZ/1000);
1681 #else
1682 usb_frame_time = muldiv64(1, get_ticks_per_sec(), 1000);
1683 if (get_ticks_per_sec() >= USB_HZ) {
1684 usb_bit_time = muldiv64(1, get_ticks_per_sec(), USB_HZ);
1685 } else {
1686 usb_bit_time = 1;
1687 }
1688 #endif
1689 DPRINTF("usb-ohci: usb_bit_time=%" PRId64 " usb_frame_time=%" PRId64 "\n",
1690 usb_frame_time, usb_bit_time);
1691 }
1692
1693 ohci->mem = cpu_register_io_memory(ohci_readfn, ohci_writefn, ohci,
1694 DEVICE_LITTLE_ENDIAN);
1695 ohci->localmem_base = localmem_base;
1696
1697 ohci->name = dev->info->name;
1698
1699 usb_bus_new(&ohci->bus, dev);
1700 ohci->num_ports = num_ports;
1701 for (i = 0; i < num_ports; i++) {
1702 usb_register_port(&ohci->bus, &ohci->rhport[i].port, ohci, i, &ohci_port_ops,
1703 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL);
1704 usb_port_location(&ohci->rhport[i].port, NULL, i+1);
1705 }
1706
1707 ohci->async_td = 0;
1708 qemu_register_reset(ohci_reset, ohci);
1709 }
1710
1711 typedef struct {
1712 PCIDevice pci_dev;
1713 OHCIState state;
1714 } OHCIPCIState;
1715
1716 static void ohci_mapfunc(PCIDevice *pci_dev, int i,
1717 pcibus_t addr, pcibus_t size, int type)
1718 {
1719 OHCIPCIState *ohci = DO_UPCAST(OHCIPCIState, pci_dev, pci_dev);
1720 cpu_register_physical_memory(addr, size, ohci->state.mem);
1721 }
1722
1723 static int usb_ohci_initfn_pci(struct PCIDevice *dev)
1724 {
1725 OHCIPCIState *ohci = DO_UPCAST(OHCIPCIState, pci_dev, dev);
1726 int num_ports = 3;
1727
1728 pci_config_set_vendor_id(ohci->pci_dev.config, PCI_VENDOR_ID_APPLE);
1729 pci_config_set_device_id(ohci->pci_dev.config,
1730 PCI_DEVICE_ID_APPLE_IPID_USB);
1731 ohci->pci_dev.config[PCI_CLASS_PROG] = 0x10; /* OHCI */
1732 pci_config_set_class(ohci->pci_dev.config, PCI_CLASS_SERIAL_USB);
1733 /* TODO: RST# value should be 0. */
1734 ohci->pci_dev.config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */
1735
1736 usb_ohci_init(&ohci->state, &dev->qdev, num_ports, 0);
1737 ohci->state.irq = ohci->pci_dev.irq[0];
1738
1739 /* TODO: avoid cast below by using dev */
1740 pci_register_bar(&ohci->pci_dev, 0, 256,
1741 PCI_BASE_ADDRESS_SPACE_MEMORY, ohci_mapfunc);
1742 return 0;
1743 }
1744
1745 void usb_ohci_init_pci(struct PCIBus *bus, int devfn)
1746 {
1747 pci_create_simple(bus, devfn, "pci-ohci");
1748 }
1749
1750 typedef struct {
1751 SysBusDevice busdev;
1752 OHCIState ohci;
1753 uint32_t num_ports;
1754 target_phys_addr_t dma_offset;
1755 } OHCISysBusState;
1756
1757 static int ohci_init_pxa(SysBusDevice *dev)
1758 {
1759 OHCISysBusState *s = FROM_SYSBUS(OHCISysBusState, dev);
1760
1761 usb_ohci_init(&s->ohci, &dev->qdev, s->num_ports, s->dma_offset);
1762 sysbus_init_irq(dev, &s->ohci.irq);
1763 sysbus_init_mmio(dev, 0x1000, s->ohci.mem);
1764
1765 return 0;
1766 }
1767
1768 static PCIDeviceInfo ohci_pci_info = {
1769 .qdev.name = "pci-ohci",
1770 .qdev.desc = "Apple USB Controller",
1771 .qdev.size = sizeof(OHCIPCIState),
1772 .init = usb_ohci_initfn_pci,
1773 };
1774
1775 static SysBusDeviceInfo ohci_sysbus_info = {
1776 .init = ohci_init_pxa,
1777 .qdev.name = "sysbus-ohci",
1778 .qdev.desc = "OHCI USB Controller",
1779 .qdev.size = sizeof(OHCISysBusState),
1780 .qdev.props = (Property[]) {
1781 DEFINE_PROP_UINT32("num-ports", OHCISysBusState, num_ports, 3),
1782 DEFINE_PROP_TADDR("dma-offset", OHCISysBusState, dma_offset, 3),
1783 DEFINE_PROP_END_OF_LIST(),
1784 }
1785 };
1786
1787 static void ohci_register(void)
1788 {
1789 pci_qdev_register(&ohci_pci_info);
1790 sysbus_register_withprop(&ohci_sysbus_info);
1791 }
1792 device_init(ohci_register);
QEmu