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arm_gic: Fix read of GICD_ICFGR
[qemu.git] / target-i386 / kvm.c
blobddedc735ff21790df0e2d3bd0e14d1774a74f174
1 /*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15 #include <sys/types.h>
16 #include <sys/ioctl.h>
17 #include <sys/mman.h>
18 #include <sys/utsname.h>
19
20 #include <linux/kvm.h>
21 #include <linux/kvm_para.h>
22
23 #include "qemu-common.h"
24 #include "sysemu/sysemu.h"
25 #include "sysemu/kvm.h"
26 #include "kvm_i386.h"
27 #include "cpu.h"
28 #include "exec/gdbstub.h"
29 #include "qemu/host-utils.h"
30 #include "qemu/config-file.h"
31 #include "hw/i386/pc.h"
32 #include "hw/i386/apic.h"
33 #include "hw/i386/apic_internal.h"
34 #include "hw/i386/apic-msidef.h"
35 #include "exec/ioport.h"
36 #include <asm/hyperv.h>
37 #include "hw/pci/pci.h"
38 #include "migration/migration.h"
39 #include "qapi/qmp/qerror.h"
40
41 //#define DEBUG_KVM
42
43 #ifdef DEBUG_KVM
44 #define DPRINTF(fmt, ...) \
45 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
46 #else
47 #define DPRINTF(fmt, ...) \
48 do { } while (0)
49 #endif
50
51 #define MSR_KVM_WALL_CLOCK 0x11
52 #define MSR_KVM_SYSTEM_TIME 0x12
53
54 #ifndef BUS_MCEERR_AR
55 #define BUS_MCEERR_AR 4
56 #endif
57 #ifndef BUS_MCEERR_AO
58 #define BUS_MCEERR_AO 5
59 #endif
60
61 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
62 KVM_CAP_INFO(SET_TSS_ADDR),
63 KVM_CAP_INFO(EXT_CPUID),
64 KVM_CAP_INFO(MP_STATE),
65 KVM_CAP_LAST_INFO
66 };
67
68 static bool has_msr_star;
69 static bool has_msr_hsave_pa;
70 static bool has_msr_tsc_adjust;
71 static bool has_msr_tsc_deadline;
72 static bool has_msr_feature_control;
73 static bool has_msr_async_pf_en;
74 static bool has_msr_pv_eoi_en;
75 static bool has_msr_misc_enable;
76 static bool has_msr_bndcfgs;
77 static bool has_msr_kvm_steal_time;
78 static int lm_capable_kernel;
79 static bool has_msr_hv_hypercall;
80 static bool has_msr_hv_vapic;
81 static bool has_msr_hv_tsc;
82 static bool has_msr_mtrr;
83
84 static bool has_msr_architectural_pmu;
85 static uint32_t num_architectural_pmu_counters;
86
87 bool kvm_allows_irq0_override(void)
88 {
89 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
90 }
91
92 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
93 {
94 struct kvm_cpuid2 *cpuid;
95 int r, size;
96
97 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
98 cpuid = (struct kvm_cpuid2 *)g_malloc0(size);
99 cpuid->nent = max;
100 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
101 if (r == 0 && cpuid->nent >= max) {
102 r = -E2BIG;
103 }
104 if (r < 0) {
105 if (r == -E2BIG) {
106 g_free(cpuid);
107 return NULL;
108 } else {
109 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
110 strerror(-r));
111 exit(1);
112 }
113 }
114 return cpuid;
115 }
116
117 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
118 * for all entries.
119 */
120 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
121 {
122 struct kvm_cpuid2 *cpuid;
123 int max = 1;
124 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
125 max *= 2;
126 }
127 return cpuid;
128 }
129
130 static const struct kvm_para_features {
131 int cap;
132 int feature;
133 } para_features[] = {
134 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
135 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
136 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
137 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
138 };
139
140 static int get_para_features(KVMState *s)
141 {
142 int i, features = 0;
143
144 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
145 if (kvm_check_extension(s, para_features[i].cap)) {
146 features |= (1 << para_features[i].feature);
147 }
148 }
149
150 return features;
151 }
152
153
154 /* Returns the value for a specific register on the cpuid entry
155 */
156 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
157 {
158 uint32_t ret = 0;
159 switch (reg) {
160 case R_EAX:
161 ret = entry->eax;
162 break;
163 case R_EBX:
164 ret = entry->ebx;
165 break;
166 case R_ECX:
167 ret = entry->ecx;
168 break;
169 case R_EDX:
170 ret = entry->edx;
171 break;
172 }
173 return ret;
174 }
175
176 /* Find matching entry for function/index on kvm_cpuid2 struct
177 */
178 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
179 uint32_t function,
180 uint32_t index)
181 {
182 int i;
183 for (i = 0; i < cpuid->nent; ++i) {
184 if (cpuid->entries[i].function == function &&
185 cpuid->entries[i].index == index) {
186 return &cpuid->entries[i];
187 }
188 }
189 /* not found: */
190 return NULL;
191 }
192
193 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
194 uint32_t index, int reg)
195 {
196 struct kvm_cpuid2 *cpuid;
197 uint32_t ret = 0;
198 uint32_t cpuid_1_edx;
199 bool found = false;
200
201 cpuid = get_supported_cpuid(s);
202
203 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
204 if (entry) {
205 found = true;
206 ret = cpuid_entry_get_reg(entry, reg);
207 }
208
209 /* Fixups for the data returned by KVM, below */
210
211 if (function == 1 && reg == R_EDX) {
212 /* KVM before 2.6.30 misreports the following features */
213 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
214 } else if (function == 1 && reg == R_ECX) {
215 /* We can set the hypervisor flag, even if KVM does not return it on
216 * GET_SUPPORTED_CPUID
217 */
218 ret |= CPUID_EXT_HYPERVISOR;
219 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
220 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
221 * and the irqchip is in the kernel.
222 */
223 if (kvm_irqchip_in_kernel() &&
224 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
225 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
226 }
227
228 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
229 * without the in-kernel irqchip
230 */
231 if (!kvm_irqchip_in_kernel()) {
232 ret &= ~CPUID_EXT_X2APIC;
233 }
234 } else if (function == 0x80000001 && reg == R_EDX) {
235 /* On Intel, kvm returns cpuid according to the Intel spec,
236 * so add missing bits according to the AMD spec:
237 */
238 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
239 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
240 }
241
242 g_free(cpuid);
243
244 /* fallback for older kernels */
245 if ((function == KVM_CPUID_FEATURES) && !found) {
246 ret = get_para_features(s);
247 }
248
249 return ret;
250 }
251
252 typedef struct HWPoisonPage {
253 ram_addr_t ram_addr;
254 QLIST_ENTRY(HWPoisonPage) list;
255 } HWPoisonPage;
256
257 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
258 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
259
260 static void kvm_unpoison_all(void *param)
261 {
262 HWPoisonPage *page, *next_page;
263
264 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
265 QLIST_REMOVE(page, list);
266 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
267 g_free(page);
268 }
269 }
270
271 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
272 {
273 HWPoisonPage *page;
274
275 QLIST_FOREACH(page, &hwpoison_page_list, list) {
276 if (page->ram_addr == ram_addr) {
277 return;
278 }
279 }
280 page = g_malloc(sizeof(HWPoisonPage));
281 page->ram_addr = ram_addr;
282 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
283 }
284
285 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
286 int *max_banks)
287 {
288 int r;
289
290 r = kvm_check_extension(s, KVM_CAP_MCE);
291 if (r > 0) {
292 *max_banks = r;
293 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
294 }
295 return -ENOSYS;
296 }
297
298 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
299 {
300 CPUX86State *env = &cpu->env;
301 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
302 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
303 uint64_t mcg_status = MCG_STATUS_MCIP;
304
305 if (code == BUS_MCEERR_AR) {
306 status |= MCI_STATUS_AR | 0x134;
307 mcg_status |= MCG_STATUS_EIPV;
308 } else {
309 status |= 0xc0;
310 mcg_status |= MCG_STATUS_RIPV;
311 }
312 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
313 (MCM_ADDR_PHYS << 6) | 0xc,
314 cpu_x86_support_mca_broadcast(env) ?
315 MCE_INJECT_BROADCAST : 0);
316 }
317
318 static void hardware_memory_error(void)
319 {
320 fprintf(stderr, "Hardware memory error!\n");
321 exit(1);
322 }
323
324 int kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
325 {
326 X86CPU *cpu = X86_CPU(c);
327 CPUX86State *env = &cpu->env;
328 ram_addr_t ram_addr;
329 hwaddr paddr;
330
331 if ((env->mcg_cap & MCG_SER_P) && addr
332 && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
333 if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL ||
334 !kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
335 fprintf(stderr, "Hardware memory error for memory used by "
336 "QEMU itself instead of guest system!\n");
337 /* Hope we are lucky for AO MCE */
338 if (code == BUS_MCEERR_AO) {
339 return 0;
340 } else {
341 hardware_memory_error();
342 }
343 }
344 kvm_hwpoison_page_add(ram_addr);
345 kvm_mce_inject(cpu, paddr, code);
346 } else {
347 if (code == BUS_MCEERR_AO) {
348 return 0;
349 } else if (code == BUS_MCEERR_AR) {
350 hardware_memory_error();
351 } else {
352 return 1;
353 }
354 }
355 return 0;
356 }
357
358 int kvm_arch_on_sigbus(int code, void *addr)
359 {
360 X86CPU *cpu = X86_CPU(first_cpu);
361
362 if ((cpu->env.mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
363 ram_addr_t ram_addr;
364 hwaddr paddr;
365
366 /* Hope we are lucky for AO MCE */
367 if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL ||
368 !kvm_physical_memory_addr_from_host(first_cpu->kvm_state,
369 addr, &paddr)) {
370 fprintf(stderr, "Hardware memory error for memory used by "
371 "QEMU itself instead of guest system!: %p\n", addr);
372 return 0;
373 }
374 kvm_hwpoison_page_add(ram_addr);
375 kvm_mce_inject(X86_CPU(first_cpu), paddr, code);
376 } else {
377 if (code == BUS_MCEERR_AO) {
378 return 0;
379 } else if (code == BUS_MCEERR_AR) {
380 hardware_memory_error();
381 } else {
382 return 1;
383 }
384 }
385 return 0;
386 }
387
388 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
389 {
390 CPUX86State *env = &cpu->env;
391
392 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
393 unsigned int bank, bank_num = env->mcg_cap & 0xff;
394 struct kvm_x86_mce mce;
395
396 env->exception_injected = -1;
397
398 /*
399 * There must be at least one bank in use if an MCE is pending.
400 * Find it and use its values for the event injection.
401 */
402 for (bank = 0; bank < bank_num; bank++) {
403 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
404 break;
405 }
406 }
407 assert(bank < bank_num);
408
409 mce.bank = bank;
410 mce.status = env->mce_banks[bank * 4 + 1];
411 mce.mcg_status = env->mcg_status;
412 mce.addr = env->mce_banks[bank * 4 + 2];
413 mce.misc = env->mce_banks[bank * 4 + 3];
414
415 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
416 }
417 return 0;
418 }
419
420 static void cpu_update_state(void *opaque, int running, RunState state)
421 {
422 CPUX86State *env = opaque;
423
424 if (running) {
425 env->tsc_valid = false;
426 }
427 }
428
429 unsigned long kvm_arch_vcpu_id(CPUState *cs)
430 {
431 X86CPU *cpu = X86_CPU(cs);
432 return cpu->env.cpuid_apic_id;
433 }
434
435 #ifndef KVM_CPUID_SIGNATURE_NEXT
436 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
437 #endif
438
439 static bool hyperv_hypercall_available(X86CPU *cpu)
440 {
441 return cpu->hyperv_vapic ||
442 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
443 }
444
445 static bool hyperv_enabled(X86CPU *cpu)
446 {
447 CPUState *cs = CPU(cpu);
448 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
449 (hyperv_hypercall_available(cpu) ||
450 cpu->hyperv_time ||
451 cpu->hyperv_relaxed_timing);
452 }
453
454 static Error *invtsc_mig_blocker;
455
456 #define KVM_MAX_CPUID_ENTRIES 100
457
458 int kvm_arch_init_vcpu(CPUState *cs)
459 {
460 struct {
461 struct kvm_cpuid2 cpuid;
462 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
463 } QEMU_PACKED cpuid_data;
464 X86CPU *cpu = X86_CPU(cs);
465 CPUX86State *env = &cpu->env;
466 uint32_t limit, i, j, cpuid_i;
467 uint32_t unused;
468 struct kvm_cpuid_entry2 *c;
469 uint32_t signature[3];
470 int kvm_base = KVM_CPUID_SIGNATURE;
471 int r;
472
473 memset(&cpuid_data, 0, sizeof(cpuid_data));
474
475 cpuid_i = 0;
476
477 /* Paravirtualization CPUIDs */
478 if (hyperv_enabled(cpu)) {
479 c = &cpuid_data.entries[cpuid_i++];
480 c->function = HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
481 memcpy(signature, "Microsoft Hv", 12);
482 c->eax = HYPERV_CPUID_MIN;
483 c->ebx = signature[0];
484 c->ecx = signature[1];
485 c->edx = signature[2];
486
487 c = &cpuid_data.entries[cpuid_i++];
488 c->function = HYPERV_CPUID_INTERFACE;
489 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
490 c->eax = signature[0];
491 c->ebx = 0;
492 c->ecx = 0;
493 c->edx = 0;
494
495 c = &cpuid_data.entries[cpuid_i++];
496 c->function = HYPERV_CPUID_VERSION;
497 c->eax = 0x00001bbc;
498 c->ebx = 0x00060001;
499
500 c = &cpuid_data.entries[cpuid_i++];
501 c->function = HYPERV_CPUID_FEATURES;
502 if (cpu->hyperv_relaxed_timing) {
503 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
504 }
505 if (cpu->hyperv_vapic) {
506 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
507 c->eax |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
508 has_msr_hv_vapic = true;
509 }
510 if (cpu->hyperv_time &&
511 kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) {
512 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
513 c->eax |= HV_X64_MSR_TIME_REF_COUNT_AVAILABLE;
514 c->eax |= 0x200;
515 has_msr_hv_tsc = true;
516 }
517 c = &cpuid_data.entries[cpuid_i++];
518 c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
519 if (cpu->hyperv_relaxed_timing) {
520 c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
521 }
522 if (has_msr_hv_vapic) {
523 c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
524 }
525 c->ebx = cpu->hyperv_spinlock_attempts;
526
527 c = &cpuid_data.entries[cpuid_i++];
528 c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
529 c->eax = 0x40;
530 c->ebx = 0x40;
531
532 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
533 has_msr_hv_hypercall = true;
534 }
535
536 if (cpu->expose_kvm) {
537 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
538 c = &cpuid_data.entries[cpuid_i++];
539 c->function = KVM_CPUID_SIGNATURE | kvm_base;
540 c->eax = KVM_CPUID_FEATURES | kvm_base;
541 c->ebx = signature[0];
542 c->ecx = signature[1];
543 c->edx = signature[2];
544
545 c = &cpuid_data.entries[cpuid_i++];
546 c->function = KVM_CPUID_FEATURES | kvm_base;
547 c->eax = env->features[FEAT_KVM];
548
549 has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF);
550
551 has_msr_pv_eoi_en = c->eax & (1 << KVM_FEATURE_PV_EOI);
552
553 has_msr_kvm_steal_time = c->eax & (1 << KVM_FEATURE_STEAL_TIME);
554 }
555
556 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
557
558 for (i = 0; i <= limit; i++) {
559 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
560 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
561 abort();
562 }
563 c = &cpuid_data.entries[cpuid_i++];
564
565 switch (i) {
566 case 2: {
567 /* Keep reading function 2 till all the input is received */
568 int times;
569
570 c->function = i;
571 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
572 KVM_CPUID_FLAG_STATE_READ_NEXT;
573 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
574 times = c->eax & 0xff;
575
576 for (j = 1; j < times; ++j) {
577 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
578 fprintf(stderr, "cpuid_data is full, no space for "
579 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
580 abort();
581 }
582 c = &cpuid_data.entries[cpuid_i++];
583 c->function = i;
584 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
585 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
586 }
587 break;
588 }
589 case 4:
590 case 0xb:
591 case 0xd:
592 for (j = 0; ; j++) {
593 if (i == 0xd && j == 64) {
594 break;
595 }
596 c->function = i;
597 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
598 c->index = j;
599 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
600
601 if (i == 4 && c->eax == 0) {
602 break;
603 }
604 if (i == 0xb && !(c->ecx & 0xff00)) {
605 break;
606 }
607 if (i == 0xd && c->eax == 0) {
608 continue;
609 }
610 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
611 fprintf(stderr, "cpuid_data is full, no space for "
612 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
613 abort();
614 }
615 c = &cpuid_data.entries[cpuid_i++];
616 }
617 break;
618 default:
619 c->function = i;
620 c->flags = 0;
621 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
622 break;
623 }
624 }
625
626 if (limit >= 0x0a) {
627 uint32_t ver;
628
629 cpu_x86_cpuid(env, 0x0a, 0, &ver, &unused, &unused, &unused);
630 if ((ver & 0xff) > 0) {
631 has_msr_architectural_pmu = true;
632 num_architectural_pmu_counters = (ver & 0xff00) >> 8;
633
634 /* Shouldn't be more than 32, since that's the number of bits
635 * available in EBX to tell us _which_ counters are available.
636 * Play it safe.
637 */
638 if (num_architectural_pmu_counters > MAX_GP_COUNTERS) {
639 num_architectural_pmu_counters = MAX_GP_COUNTERS;
640 }
641 }
642 }
643
644 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
645
646 for (i = 0x80000000; i <= limit; i++) {
647 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
648 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
649 abort();
650 }
651 c = &cpuid_data.entries[cpuid_i++];
652
653 c->function = i;
654 c->flags = 0;
655 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
656 }
657
658 /* Call Centaur's CPUID instructions they are supported. */
659 if (env->cpuid_xlevel2 > 0) {
660 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
661
662 for (i = 0xC0000000; i <= limit; i++) {
663 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
664 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
665 abort();
666 }
667 c = &cpuid_data.entries[cpuid_i++];
668
669 c->function = i;
670 c->flags = 0;
671 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
672 }
673 }
674
675 cpuid_data.cpuid.nent = cpuid_i;
676
677 if (((env->cpuid_version >> 8)&0xF) >= 6
678 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
679 (CPUID_MCE | CPUID_MCA)
680 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
681 uint64_t mcg_cap;
682 int banks;
683 int ret;
684
685 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
686 if (ret < 0) {
687 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
688 return ret;
689 }
690
691 if (banks > MCE_BANKS_DEF) {
692 banks = MCE_BANKS_DEF;
693 }
694 mcg_cap &= MCE_CAP_DEF;
695 mcg_cap |= banks;
696 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &mcg_cap);
697 if (ret < 0) {
698 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
699 return ret;
700 }
701
702 env->mcg_cap = mcg_cap;
703 }
704
705 qemu_add_vm_change_state_handler(cpu_update_state, env);
706
707 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
708 if (c) {
709 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
710 !!(c->ecx & CPUID_EXT_SMX);
711 }
712
713 c = cpuid_find_entry(&cpuid_data.cpuid, 0x80000007, 0);
714 if (c && (c->edx & 1<<8) && invtsc_mig_blocker == NULL) {
715 /* for migration */
716 error_setg(&invtsc_mig_blocker,
717 "State blocked by non-migratable CPU device"
718 " (invtsc flag)");
719 migrate_add_blocker(invtsc_mig_blocker);
720 /* for savevm */
721 vmstate_x86_cpu.unmigratable = 1;
722 }
723
724 cpuid_data.cpuid.padding = 0;
725 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
726 if (r) {
727 return r;
728 }
729
730 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL);
731 if (r && env->tsc_khz) {
732 r = kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz);
733 if (r < 0) {
734 fprintf(stderr, "KVM_SET_TSC_KHZ failed\n");
735 return r;
736 }
737 }
738
739 if (kvm_has_xsave()) {
740 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
741 }
742
743 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
744 has_msr_mtrr = true;
745 }
746
747 return 0;
748 }
749
750 void kvm_arch_reset_vcpu(X86CPU *cpu)
751 {
752 CPUX86State *env = &cpu->env;
753
754 env->exception_injected = -1;
755 env->interrupt_injected = -1;
756 env->xcr0 = 1;
757 if (kvm_irqchip_in_kernel()) {
758 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
759 KVM_MP_STATE_UNINITIALIZED;
760 } else {
761 env->mp_state = KVM_MP_STATE_RUNNABLE;
762 }
763 }
764
765 void kvm_arch_do_init_vcpu(X86CPU *cpu)
766 {
767 CPUX86State *env = &cpu->env;
768
769 /* APs get directly into wait-for-SIPI state. */
770 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
771 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
772 }
773 }
774
775 static int kvm_get_supported_msrs(KVMState *s)
776 {
777 static int kvm_supported_msrs;
778 int ret = 0;
779
780 /* first time */
781 if (kvm_supported_msrs == 0) {
782 struct kvm_msr_list msr_list, *kvm_msr_list;
783
784 kvm_supported_msrs = -1;
785
786 /* Obtain MSR list from KVM. These are the MSRs that we must
787 * save/restore */
788 msr_list.nmsrs = 0;
789 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
790 if (ret < 0 && ret != -E2BIG) {
791 return ret;
792 }
793 /* Old kernel modules had a bug and could write beyond the provided
794 memory. Allocate at least a safe amount of 1K. */
795 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
796 msr_list.nmsrs *
797 sizeof(msr_list.indices[0])));
798
799 kvm_msr_list->nmsrs = msr_list.nmsrs;
800 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
801 if (ret >= 0) {
802 int i;
803
804 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
805 if (kvm_msr_list->indices[i] == MSR_STAR) {
806 has_msr_star = true;
807 continue;
808 }
809 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
810 has_msr_hsave_pa = true;
811 continue;
812 }
813 if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) {
814 has_msr_tsc_adjust = true;
815 continue;
816 }
817 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
818 has_msr_tsc_deadline = true;
819 continue;
820 }
821 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
822 has_msr_misc_enable = true;
823 continue;
824 }
825 if (kvm_msr_list->indices[i] == MSR_IA32_BNDCFGS) {
826 has_msr_bndcfgs = true;
827 continue;
828 }
829 }
830 }
831
832 g_free(kvm_msr_list);
833 }
834
835 return ret;
836 }
837
838 int kvm_arch_init(KVMState *s)
839 {
840 uint64_t identity_base = 0xfffbc000;
841 uint64_t shadow_mem;
842 int ret;
843 struct utsname utsname;
844
845 ret = kvm_get_supported_msrs(s);
846 if (ret < 0) {
847 return ret;
848 }
849
850 uname(&utsname);
851 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
852
853 /*
854 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
855 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
856 * Since these must be part of guest physical memory, we need to allocate
857 * them, both by setting their start addresses in the kernel and by
858 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
859 *
860 * Older KVM versions may not support setting the identity map base. In
861 * that case we need to stick with the default, i.e. a 256K maximum BIOS
862 * size.
863 */
864 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
865 /* Allows up to 16M BIOSes. */
866 identity_base = 0xfeffc000;
867
868 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
869 if (ret < 0) {
870 return ret;
871 }
872 }
873
874 /* Set TSS base one page after EPT identity map. */
875 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
876 if (ret < 0) {
877 return ret;
878 }
879
880 /* Tell fw_cfg to notify the BIOS to reserve the range. */
881 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
882 if (ret < 0) {
883 fprintf(stderr, "e820_add_entry() table is full\n");
884 return ret;
885 }
886 qemu_register_reset(kvm_unpoison_all, NULL);
887
888 shadow_mem = qemu_opt_get_size(qemu_get_machine_opts(),
889 "kvm_shadow_mem", -1);
890 if (shadow_mem != -1) {
891 shadow_mem /= 4096;
892 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
893 if (ret < 0) {
894 return ret;
895 }
896 }
897 return 0;
898 }
899
900 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
901 {
902 lhs->selector = rhs->selector;
903 lhs->base = rhs->base;
904 lhs->limit = rhs->limit;
905 lhs->type = 3;
906 lhs->present = 1;
907 lhs->dpl = 3;
908 lhs->db = 0;
909 lhs->s = 1;
910 lhs->l = 0;
911 lhs->g = 0;
912 lhs->avl = 0;
913 lhs->unusable = 0;
914 }
915
916 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
917 {
918 unsigned flags = rhs->flags;
919 lhs->selector = rhs->selector;
920 lhs->base = rhs->base;
921 lhs->limit = rhs->limit;
922 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
923 lhs->present = (flags & DESC_P_MASK) != 0;
924 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
925 lhs->db = (flags >> DESC_B_SHIFT) & 1;
926 lhs->s = (flags & DESC_S_MASK) != 0;
927 lhs->l = (flags >> DESC_L_SHIFT) & 1;
928 lhs->g = (flags & DESC_G_MASK) != 0;
929 lhs->avl = (flags & DESC_AVL_MASK) != 0;
930 lhs->unusable = 0;
931 lhs->padding = 0;
932 }
933
934 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
935 {
936 lhs->selector = rhs->selector;
937 lhs->base = rhs->base;
938 lhs->limit = rhs->limit;
939 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
940 (rhs->present * DESC_P_MASK) |
941 (rhs->dpl << DESC_DPL_SHIFT) |
942 (rhs->db << DESC_B_SHIFT) |
943 (rhs->s * DESC_S_MASK) |
944 (rhs->l << DESC_L_SHIFT) |
945 (rhs->g * DESC_G_MASK) |
946 (rhs->avl * DESC_AVL_MASK);
947 }
948
949 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
950 {
951 if (set) {
952 *kvm_reg = *qemu_reg;
953 } else {
954 *qemu_reg = *kvm_reg;
955 }
956 }
957
958 static int kvm_getput_regs(X86CPU *cpu, int set)
959 {
960 CPUX86State *env = &cpu->env;
961 struct kvm_regs regs;
962 int ret = 0;
963
964 if (!set) {
965 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
966 if (ret < 0) {
967 return ret;
968 }
969 }
970
971 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
972 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
973 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
974 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
975 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
976 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
977 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
978 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
979 #ifdef TARGET_X86_64
980 kvm_getput_reg(&regs.r8, &env->regs[8], set);
981 kvm_getput_reg(&regs.r9, &env->regs[9], set);
982 kvm_getput_reg(&regs.r10, &env->regs[10], set);
983 kvm_getput_reg(&regs.r11, &env->regs[11], set);
984 kvm_getput_reg(&regs.r12, &env->regs[12], set);
985 kvm_getput_reg(&regs.r13, &env->regs[13], set);
986 kvm_getput_reg(&regs.r14, &env->regs[14], set);
987 kvm_getput_reg(&regs.r15, &env->regs[15], set);
988 #endif
989
990 kvm_getput_reg(&regs.rflags, &env->eflags, set);
991 kvm_getput_reg(&regs.rip, &env->eip, set);
992
993 if (set) {
994 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
995 }
996
997 return ret;
998 }
999
1000 static int kvm_put_fpu(X86CPU *cpu)
1001 {
1002 CPUX86State *env = &cpu->env;
1003 struct kvm_fpu fpu;
1004 int i;
1005
1006 memset(&fpu, 0, sizeof fpu);
1007 fpu.fsw = env->fpus & ~(7 << 11);
1008 fpu.fsw |= (env->fpstt & 7) << 11;
1009 fpu.fcw = env->fpuc;
1010 fpu.last_opcode = env->fpop;
1011 fpu.last_ip = env->fpip;
1012 fpu.last_dp = env->fpdp;
1013 for (i = 0; i < 8; ++i) {
1014 fpu.ftwx |= (!env->fptags[i]) << i;
1015 }
1016 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
1017 memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
1018 fpu.mxcsr = env->mxcsr;
1019
1020 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
1021 }
1022
1023 #define XSAVE_FCW_FSW 0
1024 #define XSAVE_FTW_FOP 1
1025 #define XSAVE_CWD_RIP 2
1026 #define XSAVE_CWD_RDP 4
1027 #define XSAVE_MXCSR 6
1028 #define XSAVE_ST_SPACE 8
1029 #define XSAVE_XMM_SPACE 40
1030 #define XSAVE_XSTATE_BV 128
1031 #define XSAVE_YMMH_SPACE 144
1032 #define XSAVE_BNDREGS 240
1033 #define XSAVE_BNDCSR 256
1034
1035 static int kvm_put_xsave(X86CPU *cpu)
1036 {
1037 CPUX86State *env = &cpu->env;
1038 struct kvm_xsave* xsave = env->kvm_xsave_buf;
1039 uint16_t cwd, swd, twd;
1040 int i, r;
1041
1042 if (!kvm_has_xsave()) {
1043 return kvm_put_fpu(cpu);
1044 }
1045
1046 memset(xsave, 0, sizeof(struct kvm_xsave));
1047 twd = 0;
1048 swd = env->fpus & ~(7 << 11);
1049 swd |= (env->fpstt & 7) << 11;
1050 cwd = env->fpuc;
1051 for (i = 0; i < 8; ++i) {
1052 twd |= (!env->fptags[i]) << i;
1053 }
1054 xsave->region[XSAVE_FCW_FSW] = (uint32_t)(swd << 16) + cwd;
1055 xsave->region[XSAVE_FTW_FOP] = (uint32_t)(env->fpop << 16) + twd;
1056 memcpy(&xsave->region[XSAVE_CWD_RIP], &env->fpip, sizeof(env->fpip));
1057 memcpy(&xsave->region[XSAVE_CWD_RDP], &env->fpdp, sizeof(env->fpdp));
1058 memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
1059 sizeof env->fpregs);
1060 memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs,
1061 sizeof env->xmm_regs);
1062 xsave->region[XSAVE_MXCSR] = env->mxcsr;
1063 *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
1064 memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs,
1065 sizeof env->ymmh_regs);
1066 memcpy(&xsave->region[XSAVE_BNDREGS], env->bnd_regs,
1067 sizeof env->bnd_regs);
1068 memcpy(&xsave->region[XSAVE_BNDCSR], &env->bndcs_regs,
1069 sizeof(env->bndcs_regs));
1070 r = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
1071 return r;
1072 }
1073
1074 static int kvm_put_xcrs(X86CPU *cpu)
1075 {
1076 CPUX86State *env = &cpu->env;
1077 struct kvm_xcrs xcrs;
1078
1079 if (!kvm_has_xcrs()) {
1080 return 0;
1081 }
1082
1083 xcrs.nr_xcrs = 1;
1084 xcrs.flags = 0;
1085 xcrs.xcrs[0].xcr = 0;
1086 xcrs.xcrs[0].value = env->xcr0;
1087 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
1088 }
1089
1090 static int kvm_put_sregs(X86CPU *cpu)
1091 {
1092 CPUX86State *env = &cpu->env;
1093 struct kvm_sregs sregs;
1094
1095 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1096 if (env->interrupt_injected >= 0) {
1097 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1098 (uint64_t)1 << (env->interrupt_injected % 64);
1099 }
1100
1101 if ((env->eflags & VM_MASK)) {
1102 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1103 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1104 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1105 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1106 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1107 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
1108 } else {
1109 set_seg(&sregs.cs, &env->segs[R_CS]);
1110 set_seg(&sregs.ds, &env->segs[R_DS]);
1111 set_seg(&sregs.es, &env->segs[R_ES]);
1112 set_seg(&sregs.fs, &env->segs[R_FS]);
1113 set_seg(&sregs.gs, &env->segs[R_GS]);
1114 set_seg(&sregs.ss, &env->segs[R_SS]);
1115 }
1116
1117 set_seg(&sregs.tr, &env->tr);
1118 set_seg(&sregs.ldt, &env->ldt);
1119
1120 sregs.idt.limit = env->idt.limit;
1121 sregs.idt.base = env->idt.base;
1122 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
1123 sregs.gdt.limit = env->gdt.limit;
1124 sregs.gdt.base = env->gdt.base;
1125 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
1126
1127 sregs.cr0 = env->cr[0];
1128 sregs.cr2 = env->cr[2];
1129 sregs.cr3 = env->cr[3];
1130 sregs.cr4 = env->cr[4];
1131
1132 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1133 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
1134
1135 sregs.efer = env->efer;
1136
1137 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
1138 }
1139
1140 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
1141 uint32_t index, uint64_t value)
1142 {
1143 entry->index = index;
1144 entry->data = value;
1145 }
1146
1147 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1148 {
1149 CPUX86State *env = &cpu->env;
1150 struct {
1151 struct kvm_msrs info;
1152 struct kvm_msr_entry entries[1];
1153 } msr_data;
1154 struct kvm_msr_entry *msrs = msr_data.entries;
1155
1156 if (!has_msr_tsc_deadline) {
1157 return 0;
1158 }
1159
1160 kvm_msr_entry_set(&msrs[0], MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1161
1162 msr_data.info.nmsrs = 1;
1163
1164 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1165 }
1166
1167 /*
1168 * Provide a separate write service for the feature control MSR in order to
1169 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1170 * before writing any other state because forcibly leaving nested mode
1171 * invalidates the VCPU state.
1172 */
1173 static int kvm_put_msr_feature_control(X86CPU *cpu)
1174 {
1175 struct {
1176 struct kvm_msrs info;
1177 struct kvm_msr_entry entry;
1178 } msr_data;
1179
1180 kvm_msr_entry_set(&msr_data.entry, MSR_IA32_FEATURE_CONTROL,
1181 cpu->env.msr_ia32_feature_control);
1182 msr_data.info.nmsrs = 1;
1183 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1184 }
1185
1186 static int kvm_put_msrs(X86CPU *cpu, int level)
1187 {
1188 CPUX86State *env = &cpu->env;
1189 struct {
1190 struct kvm_msrs info;
1191 struct kvm_msr_entry entries[150];
1192 } msr_data;
1193 struct kvm_msr_entry *msrs = msr_data.entries;
1194 int n = 0, i;
1195
1196 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1197 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1198 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1199 kvm_msr_entry_set(&msrs[n++], MSR_PAT, env->pat);
1200 if (has_msr_star) {
1201 kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
1202 }
1203 if (has_msr_hsave_pa) {
1204 kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
1205 }
1206 if (has_msr_tsc_adjust) {
1207 kvm_msr_entry_set(&msrs[n++], MSR_TSC_ADJUST, env->tsc_adjust);
1208 }
1209 if (has_msr_misc_enable) {
1210 kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE,
1211 env->msr_ia32_misc_enable);
1212 }
1213 if (has_msr_bndcfgs) {
1214 kvm_msr_entry_set(&msrs[n++], MSR_IA32_BNDCFGS, env->msr_bndcfgs);
1215 }
1216 #ifdef TARGET_X86_64
1217 if (lm_capable_kernel) {
1218 kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
1219 kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
1220 kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
1221 kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
1222 }
1223 #endif
1224 /*
1225 * The following MSRs have side effects on the guest or are too heavy
1226 * for normal writeback. Limit them to reset or full state updates.
1227 */
1228 if (level >= KVM_PUT_RESET_STATE) {
1229 kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
1230 kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
1231 env->system_time_msr);
1232 kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1233 if (has_msr_async_pf_en) {
1234 kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN,
1235 env->async_pf_en_msr);
1236 }
1237 if (has_msr_pv_eoi_en) {
1238 kvm_msr_entry_set(&msrs[n++], MSR_KVM_PV_EOI_EN,
1239 env->pv_eoi_en_msr);
1240 }
1241 if (has_msr_kvm_steal_time) {
1242 kvm_msr_entry_set(&msrs[n++], MSR_KVM_STEAL_TIME,
1243 env->steal_time_msr);
1244 }
1245 if (has_msr_architectural_pmu) {
1246 /* Stop the counter. */
1247 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1248 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL, 0);
1249
1250 /* Set the counter values. */
1251 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1252 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR0 + i,
1253 env->msr_fixed_counters[i]);
1254 }
1255 for (i = 0; i < num_architectural_pmu_counters; i++) {
1256 kvm_msr_entry_set(&msrs[n++], MSR_P6_PERFCTR0 + i,
1257 env->msr_gp_counters[i]);
1258 kvm_msr_entry_set(&msrs[n++], MSR_P6_EVNTSEL0 + i,
1259 env->msr_gp_evtsel[i]);
1260 }
1261 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_STATUS,
1262 env->msr_global_status);
1263 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1264 env->msr_global_ovf_ctrl);
1265
1266 /* Now start the PMU. */
1267 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL,
1268 env->msr_fixed_ctr_ctrl);
1269 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL,
1270 env->msr_global_ctrl);
1271 }
1272 if (has_msr_hv_hypercall) {
1273 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_GUEST_OS_ID,
1274 env->msr_hv_guest_os_id);
1275 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_HYPERCALL,
1276 env->msr_hv_hypercall);
1277 }
1278 if (has_msr_hv_vapic) {
1279 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_APIC_ASSIST_PAGE,
1280 env->msr_hv_vapic);
1281 }
1282 if (has_msr_hv_tsc) {
1283 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_REFERENCE_TSC,
1284 env->msr_hv_tsc);
1285 }
1286 if (has_msr_mtrr) {
1287 kvm_msr_entry_set(&msrs[n++], MSR_MTRRdefType, env->mtrr_deftype);
1288 kvm_msr_entry_set(&msrs[n++],
1289 MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
1290 kvm_msr_entry_set(&msrs[n++],
1291 MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
1292 kvm_msr_entry_set(&msrs[n++],
1293 MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
1294 kvm_msr_entry_set(&msrs[n++],
1295 MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
1296 kvm_msr_entry_set(&msrs[n++],
1297 MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
1298 kvm_msr_entry_set(&msrs[n++],
1299 MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
1300 kvm_msr_entry_set(&msrs[n++],
1301 MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
1302 kvm_msr_entry_set(&msrs[n++],
1303 MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
1304 kvm_msr_entry_set(&msrs[n++],
1305 MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
1306 kvm_msr_entry_set(&msrs[n++],
1307 MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
1308 kvm_msr_entry_set(&msrs[n++],
1309 MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
1310 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
1311 kvm_msr_entry_set(&msrs[n++],
1312 MSR_MTRRphysBase(i), env->mtrr_var[i].base);
1313 kvm_msr_entry_set(&msrs[n++],
1314 MSR_MTRRphysMask(i), env->mtrr_var[i].mask);
1315 }
1316 }
1317
1318 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1319 * kvm_put_msr_feature_control. */
1320 }
1321 if (env->mcg_cap) {
1322 int i;
1323
1324 kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
1325 kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl);
1326 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1327 kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]);
1328 }
1329 }
1330
1331 msr_data.info.nmsrs = n;
1332
1333 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1334
1335 }
1336
1337
1338 static int kvm_get_fpu(X86CPU *cpu)
1339 {
1340 CPUX86State *env = &cpu->env;
1341 struct kvm_fpu fpu;
1342 int i, ret;
1343
1344 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
1345 if (ret < 0) {
1346 return ret;
1347 }
1348
1349 env->fpstt = (fpu.fsw >> 11) & 7;
1350 env->fpus = fpu.fsw;
1351 env->fpuc = fpu.fcw;
1352 env->fpop = fpu.last_opcode;
1353 env->fpip = fpu.last_ip;
1354 env->fpdp = fpu.last_dp;
1355 for (i = 0; i < 8; ++i) {
1356 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1357 }
1358 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1359 memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
1360 env->mxcsr = fpu.mxcsr;
1361
1362 return 0;
1363 }
1364
1365 static int kvm_get_xsave(X86CPU *cpu)
1366 {
1367 CPUX86State *env = &cpu->env;
1368 struct kvm_xsave* xsave = env->kvm_xsave_buf;
1369 int ret, i;
1370 uint16_t cwd, swd, twd;
1371
1372 if (!kvm_has_xsave()) {
1373 return kvm_get_fpu(cpu);
1374 }
1375
1376 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
1377 if (ret < 0) {
1378 return ret;
1379 }
1380
1381 cwd = (uint16_t)xsave->region[XSAVE_FCW_FSW];
1382 swd = (uint16_t)(xsave->region[XSAVE_FCW_FSW] >> 16);
1383 twd = (uint16_t)xsave->region[XSAVE_FTW_FOP];
1384 env->fpop = (uint16_t)(xsave->region[XSAVE_FTW_FOP] >> 16);
1385 env->fpstt = (swd >> 11) & 7;
1386 env->fpus = swd;
1387 env->fpuc = cwd;
1388 for (i = 0; i < 8; ++i) {
1389 env->fptags[i] = !((twd >> i) & 1);
1390 }
1391 memcpy(&env->fpip, &xsave->region[XSAVE_CWD_RIP], sizeof(env->fpip));
1392 memcpy(&env->fpdp, &xsave->region[XSAVE_CWD_RDP], sizeof(env->fpdp));
1393 env->mxcsr = xsave->region[XSAVE_MXCSR];
1394 memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
1395 sizeof env->fpregs);
1396 memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE],
1397 sizeof env->xmm_regs);
1398 env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
1399 memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE],
1400 sizeof env->ymmh_regs);
1401 memcpy(env->bnd_regs, &xsave->region[XSAVE_BNDREGS],
1402 sizeof env->bnd_regs);
1403 memcpy(&env->bndcs_regs, &xsave->region[XSAVE_BNDCSR],
1404 sizeof(env->bndcs_regs));
1405 return 0;
1406 }
1407
1408 static int kvm_get_xcrs(X86CPU *cpu)
1409 {
1410 CPUX86State *env = &cpu->env;
1411 int i, ret;
1412 struct kvm_xcrs xcrs;
1413
1414 if (!kvm_has_xcrs()) {
1415 return 0;
1416 }
1417
1418 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
1419 if (ret < 0) {
1420 return ret;
1421 }
1422
1423 for (i = 0; i < xcrs.nr_xcrs; i++) {
1424 /* Only support xcr0 now */
1425 if (xcrs.xcrs[i].xcr == 0) {
1426 env->xcr0 = xcrs.xcrs[i].value;
1427 break;
1428 }
1429 }
1430 return 0;
1431 }
1432
1433 static int kvm_get_sregs(X86CPU *cpu)
1434 {
1435 CPUX86State *env = &cpu->env;
1436 struct kvm_sregs sregs;
1437 uint32_t hflags;
1438 int bit, i, ret;
1439
1440 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1441 if (ret < 0) {
1442 return ret;
1443 }
1444
1445 /* There can only be one pending IRQ set in the bitmap at a time, so try
1446 to find it and save its number instead (-1 for none). */
1447 env->interrupt_injected = -1;
1448 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1449 if (sregs.interrupt_bitmap[i]) {
1450 bit = ctz64(sregs.interrupt_bitmap[i]);
1451 env->interrupt_injected = i * 64 + bit;
1452 break;
1453 }
1454 }
1455
1456 get_seg(&env->segs[R_CS], &sregs.cs);
1457 get_seg(&env->segs[R_DS], &sregs.ds);
1458 get_seg(&env->segs[R_ES], &sregs.es);
1459 get_seg(&env->segs[R_FS], &sregs.fs);
1460 get_seg(&env->segs[R_GS], &sregs.gs);
1461 get_seg(&env->segs[R_SS], &sregs.ss);
1462
1463 get_seg(&env->tr, &sregs.tr);
1464 get_seg(&env->ldt, &sregs.ldt);
1465
1466 env->idt.limit = sregs.idt.limit;
1467 env->idt.base = sregs.idt.base;
1468 env->gdt.limit = sregs.gdt.limit;
1469 env->gdt.base = sregs.gdt.base;
1470
1471 env->cr[0] = sregs.cr0;
1472 env->cr[2] = sregs.cr2;
1473 env->cr[3] = sregs.cr3;
1474 env->cr[4] = sregs.cr4;
1475
1476 env->efer = sregs.efer;
1477
1478 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1479
1480 #define HFLAG_COPY_MASK \
1481 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1482 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1483 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1484 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1485
1486 hflags = (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1487 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1488 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1489 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1490 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1491 hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
1492 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
1493
1494 if (env->efer & MSR_EFER_LMA) {
1495 hflags |= HF_LMA_MASK;
1496 }
1497
1498 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1499 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1500 } else {
1501 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1502 (DESC_B_SHIFT - HF_CS32_SHIFT);
1503 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1504 (DESC_B_SHIFT - HF_SS32_SHIFT);
1505 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1506 !(hflags & HF_CS32_MASK)) {
1507 hflags |= HF_ADDSEG_MASK;
1508 } else {
1509 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1510 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1511 }
1512 }
1513 env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
1514
1515 return 0;
1516 }
1517
1518 static int kvm_get_msrs(X86CPU *cpu)
1519 {
1520 CPUX86State *env = &cpu->env;
1521 struct {
1522 struct kvm_msrs info;
1523 struct kvm_msr_entry entries[150];
1524 } msr_data;
1525 struct kvm_msr_entry *msrs = msr_data.entries;
1526 int ret, i, n;
1527
1528 n = 0;
1529 msrs[n++].index = MSR_IA32_SYSENTER_CS;
1530 msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1531 msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1532 msrs[n++].index = MSR_PAT;
1533 if (has_msr_star) {
1534 msrs[n++].index = MSR_STAR;
1535 }
1536 if (has_msr_hsave_pa) {
1537 msrs[n++].index = MSR_VM_HSAVE_PA;
1538 }
1539 if (has_msr_tsc_adjust) {
1540 msrs[n++].index = MSR_TSC_ADJUST;
1541 }
1542 if (has_msr_tsc_deadline) {
1543 msrs[n++].index = MSR_IA32_TSCDEADLINE;
1544 }
1545 if (has_msr_misc_enable) {
1546 msrs[n++].index = MSR_IA32_MISC_ENABLE;
1547 }
1548 if (has_msr_feature_control) {
1549 msrs[n++].index = MSR_IA32_FEATURE_CONTROL;
1550 }
1551 if (has_msr_bndcfgs) {
1552 msrs[n++].index = MSR_IA32_BNDCFGS;
1553 }
1554
1555 if (!env->tsc_valid) {
1556 msrs[n++].index = MSR_IA32_TSC;
1557 env->tsc_valid = !runstate_is_running();
1558 }
1559
1560 #ifdef TARGET_X86_64
1561 if (lm_capable_kernel) {
1562 msrs[n++].index = MSR_CSTAR;
1563 msrs[n++].index = MSR_KERNELGSBASE;
1564 msrs[n++].index = MSR_FMASK;
1565 msrs[n++].index = MSR_LSTAR;
1566 }
1567 #endif
1568 msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1569 msrs[n++].index = MSR_KVM_WALL_CLOCK;
1570 if (has_msr_async_pf_en) {
1571 msrs[n++].index = MSR_KVM_ASYNC_PF_EN;
1572 }
1573 if (has_msr_pv_eoi_en) {
1574 msrs[n++].index = MSR_KVM_PV_EOI_EN;
1575 }
1576 if (has_msr_kvm_steal_time) {
1577 msrs[n++].index = MSR_KVM_STEAL_TIME;
1578 }
1579 if (has_msr_architectural_pmu) {
1580 msrs[n++].index = MSR_CORE_PERF_FIXED_CTR_CTRL;
1581 msrs[n++].index = MSR_CORE_PERF_GLOBAL_CTRL;
1582 msrs[n++].index = MSR_CORE_PERF_GLOBAL_STATUS;
1583 msrs[n++].index = MSR_CORE_PERF_GLOBAL_OVF_CTRL;
1584 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1585 msrs[n++].index = MSR_CORE_PERF_FIXED_CTR0 + i;
1586 }
1587 for (i = 0; i < num_architectural_pmu_counters; i++) {
1588 msrs[n++].index = MSR_P6_PERFCTR0 + i;
1589 msrs[n++].index = MSR_P6_EVNTSEL0 + i;
1590 }
1591 }
1592
1593 if (env->mcg_cap) {
1594 msrs[n++].index = MSR_MCG_STATUS;
1595 msrs[n++].index = MSR_MCG_CTL;
1596 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1597 msrs[n++].index = MSR_MC0_CTL + i;
1598 }
1599 }
1600
1601 if (has_msr_hv_hypercall) {
1602 msrs[n++].index = HV_X64_MSR_HYPERCALL;
1603 msrs[n++].index = HV_X64_MSR_GUEST_OS_ID;
1604 }
1605 if (has_msr_hv_vapic) {
1606 msrs[n++].index = HV_X64_MSR_APIC_ASSIST_PAGE;
1607 }
1608 if (has_msr_hv_tsc) {
1609 msrs[n++].index = HV_X64_MSR_REFERENCE_TSC;
1610 }
1611 if (has_msr_mtrr) {
1612 msrs[n++].index = MSR_MTRRdefType;
1613 msrs[n++].index = MSR_MTRRfix64K_00000;
1614 msrs[n++].index = MSR_MTRRfix16K_80000;
1615 msrs[n++].index = MSR_MTRRfix16K_A0000;
1616 msrs[n++].index = MSR_MTRRfix4K_C0000;
1617 msrs[n++].index = MSR_MTRRfix4K_C8000;
1618 msrs[n++].index = MSR_MTRRfix4K_D0000;
1619 msrs[n++].index = MSR_MTRRfix4K_D8000;
1620 msrs[n++].index = MSR_MTRRfix4K_E0000;
1621 msrs[n++].index = MSR_MTRRfix4K_E8000;
1622 msrs[n++].index = MSR_MTRRfix4K_F0000;
1623 msrs[n++].index = MSR_MTRRfix4K_F8000;
1624 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
1625 msrs[n++].index = MSR_MTRRphysBase(i);
1626 msrs[n++].index = MSR_MTRRphysMask(i);
1627 }
1628 }
1629
1630 msr_data.info.nmsrs = n;
1631 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
1632 if (ret < 0) {
1633 return ret;
1634 }
1635
1636 for (i = 0; i < ret; i++) {
1637 uint32_t index = msrs[i].index;
1638 switch (index) {
1639 case MSR_IA32_SYSENTER_CS:
1640 env->sysenter_cs = msrs[i].data;
1641 break;
1642 case MSR_IA32_SYSENTER_ESP:
1643 env->sysenter_esp = msrs[i].data;
1644 break;
1645 case MSR_IA32_SYSENTER_EIP:
1646 env->sysenter_eip = msrs[i].data;
1647 break;
1648 case MSR_PAT:
1649 env->pat = msrs[i].data;
1650 break;
1651 case MSR_STAR:
1652 env->star = msrs[i].data;
1653 break;
1654 #ifdef TARGET_X86_64
1655 case MSR_CSTAR:
1656 env->cstar = msrs[i].data;
1657 break;
1658 case MSR_KERNELGSBASE:
1659 env->kernelgsbase = msrs[i].data;
1660 break;
1661 case MSR_FMASK:
1662 env->fmask = msrs[i].data;
1663 break;
1664 case MSR_LSTAR:
1665 env->lstar = msrs[i].data;
1666 break;
1667 #endif
1668 case MSR_IA32_TSC:
1669 env->tsc = msrs[i].data;
1670 break;
1671 case MSR_TSC_ADJUST:
1672 env->tsc_adjust = msrs[i].data;
1673 break;
1674 case MSR_IA32_TSCDEADLINE:
1675 env->tsc_deadline = msrs[i].data;
1676 break;
1677 case MSR_VM_HSAVE_PA:
1678 env->vm_hsave = msrs[i].data;
1679 break;
1680 case MSR_KVM_SYSTEM_TIME:
1681 env->system_time_msr = msrs[i].data;
1682 break;
1683 case MSR_KVM_WALL_CLOCK:
1684 env->wall_clock_msr = msrs[i].data;
1685 break;
1686 case MSR_MCG_STATUS:
1687 env->mcg_status = msrs[i].data;
1688 break;
1689 case MSR_MCG_CTL:
1690 env->mcg_ctl = msrs[i].data;
1691 break;
1692 case MSR_IA32_MISC_ENABLE:
1693 env->msr_ia32_misc_enable = msrs[i].data;
1694 break;
1695 case MSR_IA32_FEATURE_CONTROL:
1696 env->msr_ia32_feature_control = msrs[i].data;
1697 break;
1698 case MSR_IA32_BNDCFGS:
1699 env->msr_bndcfgs = msrs[i].data;
1700 break;
1701 default:
1702 if (msrs[i].index >= MSR_MC0_CTL &&
1703 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
1704 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
1705 }
1706 break;
1707 case MSR_KVM_ASYNC_PF_EN:
1708 env->async_pf_en_msr = msrs[i].data;
1709 break;
1710 case MSR_KVM_PV_EOI_EN:
1711 env->pv_eoi_en_msr = msrs[i].data;
1712 break;
1713 case MSR_KVM_STEAL_TIME:
1714 env->steal_time_msr = msrs[i].data;
1715 break;
1716 case MSR_CORE_PERF_FIXED_CTR_CTRL:
1717 env->msr_fixed_ctr_ctrl = msrs[i].data;
1718 break;
1719 case MSR_CORE_PERF_GLOBAL_CTRL:
1720 env->msr_global_ctrl = msrs[i].data;
1721 break;
1722 case MSR_CORE_PERF_GLOBAL_STATUS:
1723 env->msr_global_status = msrs[i].data;
1724 break;
1725 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
1726 env->msr_global_ovf_ctrl = msrs[i].data;
1727 break;
1728 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
1729 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
1730 break;
1731 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
1732 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
1733 break;
1734 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
1735 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
1736 break;
1737 case HV_X64_MSR_HYPERCALL:
1738 env->msr_hv_hypercall = msrs[i].data;
1739 break;
1740 case HV_X64_MSR_GUEST_OS_ID:
1741 env->msr_hv_guest_os_id = msrs[i].data;
1742 break;
1743 case HV_X64_MSR_APIC_ASSIST_PAGE:
1744 env->msr_hv_vapic = msrs[i].data;
1745 break;
1746 case HV_X64_MSR_REFERENCE_TSC:
1747 env->msr_hv_tsc = msrs[i].data;
1748 break;
1749 case MSR_MTRRdefType:
1750 env->mtrr_deftype = msrs[i].data;
1751 break;
1752 case MSR_MTRRfix64K_00000:
1753 env->mtrr_fixed[0] = msrs[i].data;
1754 break;
1755 case MSR_MTRRfix16K_80000:
1756 env->mtrr_fixed[1] = msrs[i].data;
1757 break;
1758 case MSR_MTRRfix16K_A0000:
1759 env->mtrr_fixed[2] = msrs[i].data;
1760 break;
1761 case MSR_MTRRfix4K_C0000:
1762 env->mtrr_fixed[3] = msrs[i].data;
1763 break;
1764 case MSR_MTRRfix4K_C8000:
1765 env->mtrr_fixed[4] = msrs[i].data;
1766 break;
1767 case MSR_MTRRfix4K_D0000:
1768 env->mtrr_fixed[5] = msrs[i].data;
1769 break;
1770 case MSR_MTRRfix4K_D8000:
1771 env->mtrr_fixed[6] = msrs[i].data;
1772 break;
1773 case MSR_MTRRfix4K_E0000:
1774 env->mtrr_fixed[7] = msrs[i].data;
1775 break;
1776 case MSR_MTRRfix4K_E8000:
1777 env->mtrr_fixed[8] = msrs[i].data;
1778 break;
1779 case MSR_MTRRfix4K_F0000:
1780 env->mtrr_fixed[9] = msrs[i].data;
1781 break;
1782 case MSR_MTRRfix4K_F8000:
1783 env->mtrr_fixed[10] = msrs[i].data;
1784 break;
1785 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
1786 if (index & 1) {
1787 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data;
1788 } else {
1789 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
1790 }
1791 break;
1792 }
1793 }
1794
1795 return 0;
1796 }
1797
1798 static int kvm_put_mp_state(X86CPU *cpu)
1799 {
1800 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
1801
1802 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
1803 }
1804
1805 static int kvm_get_mp_state(X86CPU *cpu)
1806 {
1807 CPUState *cs = CPU(cpu);
1808 CPUX86State *env = &cpu->env;
1809 struct kvm_mp_state mp_state;
1810 int ret;
1811
1812 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
1813 if (ret < 0) {
1814 return ret;
1815 }
1816 env->mp_state = mp_state.mp_state;
1817 if (kvm_irqchip_in_kernel()) {
1818 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
1819 }
1820 return 0;
1821 }
1822
1823 static int kvm_get_apic(X86CPU *cpu)
1824 {
1825 DeviceState *apic = cpu->apic_state;
1826 struct kvm_lapic_state kapic;
1827 int ret;
1828
1829 if (apic && kvm_irqchip_in_kernel()) {
1830 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
1831 if (ret < 0) {
1832 return ret;
1833 }
1834
1835 kvm_get_apic_state(apic, &kapic);
1836 }
1837 return 0;
1838 }
1839
1840 static int kvm_put_apic(X86CPU *cpu)
1841 {
1842 DeviceState *apic = cpu->apic_state;
1843 struct kvm_lapic_state kapic;
1844
1845 if (apic && kvm_irqchip_in_kernel()) {
1846 kvm_put_apic_state(apic, &kapic);
1847
1848 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_LAPIC, &kapic);
1849 }
1850 return 0;
1851 }
1852
1853 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
1854 {
1855 CPUX86State *env = &cpu->env;
1856 struct kvm_vcpu_events events;
1857
1858 if (!kvm_has_vcpu_events()) {
1859 return 0;
1860 }
1861
1862 events.exception.injected = (env->exception_injected >= 0);
1863 events.exception.nr = env->exception_injected;
1864 events.exception.has_error_code = env->has_error_code;
1865 events.exception.error_code = env->error_code;
1866 events.exception.pad = 0;
1867
1868 events.interrupt.injected = (env->interrupt_injected >= 0);
1869 events.interrupt.nr = env->interrupt_injected;
1870 events.interrupt.soft = env->soft_interrupt;
1871
1872 events.nmi.injected = env->nmi_injected;
1873 events.nmi.pending = env->nmi_pending;
1874 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
1875 events.nmi.pad = 0;
1876
1877 events.sipi_vector = env->sipi_vector;
1878
1879 events.flags = 0;
1880 if (level >= KVM_PUT_RESET_STATE) {
1881 events.flags |=
1882 KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
1883 }
1884
1885 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
1886 }
1887
1888 static int kvm_get_vcpu_events(X86CPU *cpu)
1889 {
1890 CPUX86State *env = &cpu->env;
1891 struct kvm_vcpu_events events;
1892 int ret;
1893
1894 if (!kvm_has_vcpu_events()) {
1895 return 0;
1896 }
1897
1898 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
1899 if (ret < 0) {
1900 return ret;
1901 }
1902 env->exception_injected =
1903 events.exception.injected ? events.exception.nr : -1;
1904 env->has_error_code = events.exception.has_error_code;
1905 env->error_code = events.exception.error_code;
1906
1907 env->interrupt_injected =
1908 events.interrupt.injected ? events.interrupt.nr : -1;
1909 env->soft_interrupt = events.interrupt.soft;
1910
1911 env->nmi_injected = events.nmi.injected;
1912 env->nmi_pending = events.nmi.pending;
1913 if (events.nmi.masked) {
1914 env->hflags2 |= HF2_NMI_MASK;
1915 } else {
1916 env->hflags2 &= ~HF2_NMI_MASK;
1917 }
1918
1919 env->sipi_vector = events.sipi_vector;
1920
1921 return 0;
1922 }
1923
1924 static int kvm_guest_debug_workarounds(X86CPU *cpu)
1925 {
1926 CPUState *cs = CPU(cpu);
1927 CPUX86State *env = &cpu->env;
1928 int ret = 0;
1929 unsigned long reinject_trap = 0;
1930
1931 if (!kvm_has_vcpu_events()) {
1932 if (env->exception_injected == 1) {
1933 reinject_trap = KVM_GUESTDBG_INJECT_DB;
1934 } else if (env->exception_injected == 3) {
1935 reinject_trap = KVM_GUESTDBG_INJECT_BP;
1936 }
1937 env->exception_injected = -1;
1938 }
1939
1940 /*
1941 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
1942 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
1943 * by updating the debug state once again if single-stepping is on.
1944 * Another reason to call kvm_update_guest_debug here is a pending debug
1945 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
1946 * reinject them via SET_GUEST_DEBUG.
1947 */
1948 if (reinject_trap ||
1949 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
1950 ret = kvm_update_guest_debug(cs, reinject_trap);
1951 }
1952 return ret;
1953 }
1954
1955 static int kvm_put_debugregs(X86CPU *cpu)
1956 {
1957 CPUX86State *env = &cpu->env;
1958 struct kvm_debugregs dbgregs;
1959 int i;
1960
1961 if (!kvm_has_debugregs()) {
1962 return 0;
1963 }
1964
1965 for (i = 0; i < 4; i++) {
1966 dbgregs.db[i] = env->dr[i];
1967 }
1968 dbgregs.dr6 = env->dr[6];
1969 dbgregs.dr7 = env->dr[7];
1970 dbgregs.flags = 0;
1971
1972 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
1973 }
1974
1975 static int kvm_get_debugregs(X86CPU *cpu)
1976 {
1977 CPUX86State *env = &cpu->env;
1978 struct kvm_debugregs dbgregs;
1979 int i, ret;
1980
1981 if (!kvm_has_debugregs()) {
1982 return 0;
1983 }
1984
1985 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
1986 if (ret < 0) {
1987 return ret;
1988 }
1989 for (i = 0; i < 4; i++) {
1990 env->dr[i] = dbgregs.db[i];
1991 }
1992 env->dr[4] = env->dr[6] = dbgregs.dr6;
1993 env->dr[5] = env->dr[7] = dbgregs.dr7;
1994
1995 return 0;
1996 }
1997
1998 int kvm_arch_put_registers(CPUState *cpu, int level)
1999 {
2000 X86CPU *x86_cpu = X86_CPU(cpu);
2001 int ret;
2002
2003 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
2004
2005 if (level >= KVM_PUT_RESET_STATE && has_msr_feature_control) {
2006 ret = kvm_put_msr_feature_control(x86_cpu);
2007 if (ret < 0) {
2008 return ret;
2009 }
2010 }
2011
2012 ret = kvm_getput_regs(x86_cpu, 1);
2013 if (ret < 0) {
2014 return ret;
2015 }
2016 ret = kvm_put_xsave(x86_cpu);
2017 if (ret < 0) {
2018 return ret;
2019 }
2020 ret = kvm_put_xcrs(x86_cpu);
2021 if (ret < 0) {
2022 return ret;
2023 }
2024 ret = kvm_put_sregs(x86_cpu);
2025 if (ret < 0) {
2026 return ret;
2027 }
2028 /* must be before kvm_put_msrs */
2029 ret = kvm_inject_mce_oldstyle(x86_cpu);
2030 if (ret < 0) {
2031 return ret;
2032 }
2033 ret = kvm_put_msrs(x86_cpu, level);
2034 if (ret < 0) {
2035 return ret;
2036 }
2037 if (level >= KVM_PUT_RESET_STATE) {
2038 ret = kvm_put_mp_state(x86_cpu);
2039 if (ret < 0) {
2040 return ret;
2041 }
2042 ret = kvm_put_apic(x86_cpu);
2043 if (ret < 0) {
2044 return ret;
2045 }
2046 }
2047
2048 ret = kvm_put_tscdeadline_msr(x86_cpu);
2049 if (ret < 0) {
2050 return ret;
2051 }
2052
2053 ret = kvm_put_vcpu_events(x86_cpu, level);
2054 if (ret < 0) {
2055 return ret;
2056 }
2057 ret = kvm_put_debugregs(x86_cpu);
2058 if (ret < 0) {
2059 return ret;
2060 }
2061 /* must be last */
2062 ret = kvm_guest_debug_workarounds(x86_cpu);
2063 if (ret < 0) {
2064 return ret;
2065 }
2066 return 0;
2067 }
2068
2069 int kvm_arch_get_registers(CPUState *cs)
2070 {
2071 X86CPU *cpu = X86_CPU(cs);
2072 int ret;
2073
2074 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
2075
2076 ret = kvm_getput_regs(cpu, 0);
2077 if (ret < 0) {
2078 return ret;
2079 }
2080 ret = kvm_get_xsave(cpu);
2081 if (ret < 0) {
2082 return ret;
2083 }
2084 ret = kvm_get_xcrs(cpu);
2085 if (ret < 0) {
2086 return ret;
2087 }
2088 ret = kvm_get_sregs(cpu);
2089 if (ret < 0) {
2090 return ret;
2091 }
2092 ret = kvm_get_msrs(cpu);
2093 if (ret < 0) {
2094 return ret;
2095 }
2096 ret = kvm_get_mp_state(cpu);
2097 if (ret < 0) {
2098 return ret;
2099 }
2100 ret = kvm_get_apic(cpu);
2101 if (ret < 0) {
2102 return ret;
2103 }
2104 ret = kvm_get_vcpu_events(cpu);
2105 if (ret < 0) {
2106 return ret;
2107 }
2108 ret = kvm_get_debugregs(cpu);
2109 if (ret < 0) {
2110 return ret;
2111 }
2112 return 0;
2113 }
2114
2115 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
2116 {
2117 X86CPU *x86_cpu = X86_CPU(cpu);
2118 CPUX86State *env = &x86_cpu->env;
2119 int ret;
2120
2121 /* Inject NMI */
2122 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
2123 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
2124 DPRINTF("injected NMI\n");
2125 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
2126 if (ret < 0) {
2127 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
2128 strerror(-ret));
2129 }
2130 }
2131
2132 /* Force the VCPU out of its inner loop to process any INIT requests
2133 * or (for userspace APIC, but it is cheap to combine the checks here)
2134 * pending TPR access reports.
2135 */
2136 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
2137 cpu->exit_request = 1;
2138 }
2139
2140 if (!kvm_irqchip_in_kernel()) {
2141 /* Try to inject an interrupt if the guest can accept it */
2142 if (run->ready_for_interrupt_injection &&
2143 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
2144 (env->eflags & IF_MASK)) {
2145 int irq;
2146
2147 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
2148 irq = cpu_get_pic_interrupt(env);
2149 if (irq >= 0) {
2150 struct kvm_interrupt intr;
2151
2152 intr.irq = irq;
2153 DPRINTF("injected interrupt %d\n", irq);
2154 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
2155 if (ret < 0) {
2156 fprintf(stderr,
2157 "KVM: injection failed, interrupt lost (%s)\n",
2158 strerror(-ret));
2159 }
2160 }
2161 }
2162
2163 /* If we have an interrupt but the guest is not ready to receive an
2164 * interrupt, request an interrupt window exit. This will
2165 * cause a return to userspace as soon as the guest is ready to
2166 * receive interrupts. */
2167 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
2168 run->request_interrupt_window = 1;
2169 } else {
2170 run->request_interrupt_window = 0;
2171 }
2172
2173 DPRINTF("setting tpr\n");
2174 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
2175 }
2176 }
2177
2178 void kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
2179 {
2180 X86CPU *x86_cpu = X86_CPU(cpu);
2181 CPUX86State *env = &x86_cpu->env;
2182
2183 if (run->if_flag) {
2184 env->eflags |= IF_MASK;
2185 } else {
2186 env->eflags &= ~IF_MASK;
2187 }
2188 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
2189 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
2190 }
2191
2192 int kvm_arch_process_async_events(CPUState *cs)
2193 {
2194 X86CPU *cpu = X86_CPU(cs);
2195 CPUX86State *env = &cpu->env;
2196
2197 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
2198 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2199 assert(env->mcg_cap);
2200
2201 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
2202
2203 kvm_cpu_synchronize_state(cs);
2204
2205 if (env->exception_injected == EXCP08_DBLE) {
2206 /* this means triple fault */
2207 qemu_system_reset_request();
2208 cs->exit_request = 1;
2209 return 0;
2210 }
2211 env->exception_injected = EXCP12_MCHK;
2212 env->has_error_code = 0;
2213
2214 cs->halted = 0;
2215 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
2216 env->mp_state = KVM_MP_STATE_RUNNABLE;
2217 }
2218 }
2219
2220 if (cs->interrupt_request & CPU_INTERRUPT_INIT) {
2221 kvm_cpu_synchronize_state(cs);
2222 do_cpu_init(cpu);
2223 }
2224
2225 if (kvm_irqchip_in_kernel()) {
2226 return 0;
2227 }
2228
2229 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2230 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
2231 apic_poll_irq(cpu->apic_state);
2232 }
2233 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2234 (env->eflags & IF_MASK)) ||
2235 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2236 cs->halted = 0;
2237 }
2238 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
2239 kvm_cpu_synchronize_state(cs);
2240 do_cpu_sipi(cpu);
2241 }
2242 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
2243 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
2244 kvm_cpu_synchronize_state(cs);
2245 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
2246 env->tpr_access_type);
2247 }
2248
2249 return cs->halted;
2250 }
2251
2252 static int kvm_handle_halt(X86CPU *cpu)
2253 {
2254 CPUState *cs = CPU(cpu);
2255 CPUX86State *env = &cpu->env;
2256
2257 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2258 (env->eflags & IF_MASK)) &&
2259 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2260 cs->halted = 1;
2261 return EXCP_HLT;
2262 }
2263
2264 return 0;
2265 }
2266
2267 static int kvm_handle_tpr_access(X86CPU *cpu)
2268 {
2269 CPUState *cs = CPU(cpu);
2270 struct kvm_run *run = cs->kvm_run;
2271
2272 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
2273 run->tpr_access.is_write ? TPR_ACCESS_WRITE
2274 : TPR_ACCESS_READ);
2275 return 1;
2276 }
2277
2278 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2279 {
2280 static const uint8_t int3 = 0xcc;
2281
2282 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
2283 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
2284 return -EINVAL;
2285 }
2286 return 0;
2287 }
2288
2289 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2290 {
2291 uint8_t int3;
2292
2293 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
2294 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
2295 return -EINVAL;
2296 }
2297 return 0;
2298 }
2299
2300 static struct {
2301 target_ulong addr;
2302 int len;
2303 int type;
2304 } hw_breakpoint[4];
2305
2306 static int nb_hw_breakpoint;
2307
2308 static int find_hw_breakpoint(target_ulong addr, int len, int type)
2309 {
2310 int n;
2311
2312 for (n = 0; n < nb_hw_breakpoint; n++) {
2313 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
2314 (hw_breakpoint[n].len == len || len == -1)) {
2315 return n;
2316 }
2317 }
2318 return -1;
2319 }
2320
2321 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
2322 target_ulong len, int type)
2323 {
2324 switch (type) {
2325 case GDB_BREAKPOINT_HW:
2326 len = 1;
2327 break;
2328 case GDB_WATCHPOINT_WRITE:
2329 case GDB_WATCHPOINT_ACCESS:
2330 switch (len) {
2331 case 1:
2332 break;
2333 case 2:
2334 case 4:
2335 case 8:
2336 if (addr & (len - 1)) {
2337 return -EINVAL;
2338 }
2339 break;
2340 default:
2341 return -EINVAL;
2342 }
2343 break;
2344 default:
2345 return -ENOSYS;
2346 }
2347
2348 if (nb_hw_breakpoint == 4) {
2349 return -ENOBUFS;
2350 }
2351 if (find_hw_breakpoint(addr, len, type) >= 0) {
2352 return -EEXIST;
2353 }
2354 hw_breakpoint[nb_hw_breakpoint].addr = addr;
2355 hw_breakpoint[nb_hw_breakpoint].len = len;
2356 hw_breakpoint[nb_hw_breakpoint].type = type;
2357 nb_hw_breakpoint++;
2358
2359 return 0;
2360 }
2361
2362 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
2363 target_ulong len, int type)
2364 {
2365 int n;
2366
2367 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
2368 if (n < 0) {
2369 return -ENOENT;
2370 }
2371 nb_hw_breakpoint--;
2372 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
2373
2374 return 0;
2375 }
2376
2377 void kvm_arch_remove_all_hw_breakpoints(void)
2378 {
2379 nb_hw_breakpoint = 0;
2380 }
2381
2382 static CPUWatchpoint hw_watchpoint;
2383
2384 static int kvm_handle_debug(X86CPU *cpu,
2385 struct kvm_debug_exit_arch *arch_info)
2386 {
2387 CPUState *cs = CPU(cpu);
2388 CPUX86State *env = &cpu->env;
2389 int ret = 0;
2390 int n;
2391
2392 if (arch_info->exception == 1) {
2393 if (arch_info->dr6 & (1 << 14)) {
2394 if (cs->singlestep_enabled) {
2395 ret = EXCP_DEBUG;
2396 }
2397 } else {
2398 for (n = 0; n < 4; n++) {
2399 if (arch_info->dr6 & (1 << n)) {
2400 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
2401 case 0x0:
2402 ret = EXCP_DEBUG;
2403 break;
2404 case 0x1:
2405 ret = EXCP_DEBUG;
2406 cs->watchpoint_hit = &hw_watchpoint;
2407 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2408 hw_watchpoint.flags = BP_MEM_WRITE;
2409 break;
2410 case 0x3:
2411 ret = EXCP_DEBUG;
2412 cs->watchpoint_hit = &hw_watchpoint;
2413 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2414 hw_watchpoint.flags = BP_MEM_ACCESS;
2415 break;
2416 }
2417 }
2418 }
2419 }
2420 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
2421 ret = EXCP_DEBUG;
2422 }
2423 if (ret == 0) {
2424 cpu_synchronize_state(cs);
2425 assert(env->exception_injected == -1);
2426
2427 /* pass to guest */
2428 env->exception_injected = arch_info->exception;
2429 env->has_error_code = 0;
2430 }
2431
2432 return ret;
2433 }
2434
2435 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
2436 {
2437 const uint8_t type_code[] = {
2438 [GDB_BREAKPOINT_HW] = 0x0,
2439 [GDB_WATCHPOINT_WRITE] = 0x1,
2440 [GDB_WATCHPOINT_ACCESS] = 0x3
2441 };
2442 const uint8_t len_code[] = {
2443 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
2444 };
2445 int n;
2446
2447 if (kvm_sw_breakpoints_active(cpu)) {
2448 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
2449 }
2450 if (nb_hw_breakpoint > 0) {
2451 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
2452 dbg->arch.debugreg[7] = 0x0600;
2453 for (n = 0; n < nb_hw_breakpoint; n++) {
2454 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
2455 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
2456 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
2457 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
2458 }
2459 }
2460 }
2461
2462 static bool host_supports_vmx(void)
2463 {
2464 uint32_t ecx, unused;
2465
2466 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
2467 return ecx & CPUID_EXT_VMX;
2468 }
2469
2470 #define VMX_INVALID_GUEST_STATE 0x80000021
2471
2472 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2473 {
2474 X86CPU *cpu = X86_CPU(cs);
2475 uint64_t code;
2476 int ret;
2477
2478 switch (run->exit_reason) {
2479 case KVM_EXIT_HLT:
2480 DPRINTF("handle_hlt\n");
2481 ret = kvm_handle_halt(cpu);
2482 break;
2483 case KVM_EXIT_SET_TPR:
2484 ret = 0;
2485 break;
2486 case KVM_EXIT_TPR_ACCESS:
2487 ret = kvm_handle_tpr_access(cpu);
2488 break;
2489 case KVM_EXIT_FAIL_ENTRY:
2490 code = run->fail_entry.hardware_entry_failure_reason;
2491 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
2492 code);
2493 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
2494 fprintf(stderr,
2495 "\nIf you're running a guest on an Intel machine without "
2496 "unrestricted mode\n"
2497 "support, the failure can be most likely due to the guest "
2498 "entering an invalid\n"
2499 "state for Intel VT. For example, the guest maybe running "
2500 "in big real mode\n"
2501 "which is not supported on less recent Intel processors."
2502 "\n\n");
2503 }
2504 ret = -1;
2505 break;
2506 case KVM_EXIT_EXCEPTION:
2507 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
2508 run->ex.exception, run->ex.error_code);
2509 ret = -1;
2510 break;
2511 case KVM_EXIT_DEBUG:
2512 DPRINTF("kvm_exit_debug\n");
2513 ret = kvm_handle_debug(cpu, &run->debug.arch);
2514 break;
2515 default:
2516 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
2517 ret = -1;
2518 break;
2519 }
2520
2521 return ret;
2522 }
2523
2524 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
2525 {
2526 X86CPU *cpu = X86_CPU(cs);
2527 CPUX86State *env = &cpu->env;
2528
2529 kvm_cpu_synchronize_state(cs);
2530 return !(env->cr[0] & CR0_PE_MASK) ||
2531 ((env->segs[R_CS].selector & 3) != 3);
2532 }
2533
2534 void kvm_arch_init_irq_routing(KVMState *s)
2535 {
2536 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
2537 /* If kernel can't do irq routing, interrupt source
2538 * override 0->2 cannot be set up as required by HPET.
2539 * So we have to disable it.
2540 */
2541 no_hpet = 1;
2542 }
2543 /* We know at this point that we're using the in-kernel
2544 * irqchip, so we can use irqfds, and on x86 we know
2545 * we can use msi via irqfd and GSI routing.
2546 */
2547 kvm_irqfds_allowed = true;
2548 kvm_msi_via_irqfd_allowed = true;
2549 kvm_gsi_routing_allowed = true;
2550 }
2551
2552 /* Classic KVM device assignment interface. Will remain x86 only. */
2553 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
2554 uint32_t flags, uint32_t *dev_id)
2555 {
2556 struct kvm_assigned_pci_dev dev_data = {
2557 .segnr = dev_addr->domain,
2558 .busnr = dev_addr->bus,
2559 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
2560 .flags = flags,
2561 };
2562 int ret;
2563
2564 dev_data.assigned_dev_id =
2565 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
2566
2567 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
2568 if (ret < 0) {
2569 return ret;
2570 }
2571
2572 *dev_id = dev_data.assigned_dev_id;
2573
2574 return 0;
2575 }
2576
2577 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
2578 {
2579 struct kvm_assigned_pci_dev dev_data = {
2580 .assigned_dev_id = dev_id,
2581 };
2582
2583 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
2584 }
2585
2586 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
2587 uint32_t irq_type, uint32_t guest_irq)
2588 {
2589 struct kvm_assigned_irq assigned_irq = {
2590 .assigned_dev_id = dev_id,
2591 .guest_irq = guest_irq,
2592 .flags = irq_type,
2593 };
2594
2595 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
2596 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
2597 } else {
2598 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
2599 }
2600 }
2601
2602 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
2603 uint32_t guest_irq)
2604 {
2605 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
2606 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
2607
2608 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
2609 }
2610
2611 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
2612 {
2613 struct kvm_assigned_pci_dev dev_data = {
2614 .assigned_dev_id = dev_id,
2615 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
2616 };
2617
2618 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
2619 }
2620
2621 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
2622 uint32_t type)
2623 {
2624 struct kvm_assigned_irq assigned_irq = {
2625 .assigned_dev_id = dev_id,
2626 .flags = type,
2627 };
2628
2629 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
2630 }
2631
2632 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
2633 {
2634 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
2635 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
2636 }
2637
2638 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
2639 {
2640 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
2641 KVM_DEV_IRQ_GUEST_MSI, virq);
2642 }
2643
2644 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
2645 {
2646 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
2647 KVM_DEV_IRQ_HOST_MSI);
2648 }
2649
2650 bool kvm_device_msix_supported(KVMState *s)
2651 {
2652 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
2653 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
2654 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
2655 }
2656
2657 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
2658 uint32_t nr_vectors)
2659 {
2660 struct kvm_assigned_msix_nr msix_nr = {
2661 .assigned_dev_id = dev_id,
2662 .entry_nr = nr_vectors,
2663 };
2664
2665 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
2666 }
2667
2668 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
2669 int virq)
2670 {
2671 struct kvm_assigned_msix_entry msix_entry = {
2672 .assigned_dev_id = dev_id,
2673 .gsi = virq,
2674 .entry = vector,
2675 };
2676
2677 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
2678 }
2679
2680 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
2681 {
2682 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
2683 KVM_DEV_IRQ_GUEST_MSIX, 0);
2684 }
2685
2686 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
2687 {
2688 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
2689 KVM_DEV_IRQ_HOST_MSIX);
2690 }
QEmu