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sdl: Fix termination in -no-shutdown mode
[qemu.git] / hw / strongarm.c
blob0e03d61a1f4d8dcab24d004139842ddbdbc04b33
1 /*
2 * StrongARM SA-1100/SA-1110 emulation
3 *
4 * Copyright (C) 2011 Dmitry Eremin-Solenikov
5 *
6 * Largely based on StrongARM emulation:
7 * Copyright (c) 2006 Openedhand Ltd.
8 * Written by Andrzej Zaborowski <balrog@zabor.org>
9 *
10 * UART code based on QEMU 16550A UART emulation
11 * Copyright (c) 2003-2004 Fabrice Bellard
12 * Copyright (c) 2008 Citrix Systems, Inc.
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, see <http://www.gnu.org/licenses/>.
25 */
26 #include "sysbus.h"
27 #include "strongarm.h"
28 #include "qemu-error.h"
29 #include "arm-misc.h"
30 #include "sysemu.h"
31 #include "ssi.h"
32
33 //#define DEBUG
34
35 /*
36 TODO
37 - Implement cp15, c14 ?
38 - Implement cp15, c15 !!! (idle used in L)
39 - Implement idle mode handling/DIM
40 - Implement sleep mode/Wake sources
41 - Implement reset control
42 - Implement memory control regs
43 - PCMCIA handling
44 - Maybe support MBGNT/MBREQ
45 - DMA channels
46 - GPCLK
47 - IrDA
48 - MCP
49 - Enhance UART with modem signals
50 */
51
52 #ifdef DEBUG
53 # define DPRINTF(format, ...) printf(format , ## __VA_ARGS__)
54 #else
55 # define DPRINTF(format, ...) do { } while (0)
56 #endif
57
58 static struct {
59 target_phys_addr_t io_base;
60 int irq;
61 } sa_serial[] = {
62 { 0x80010000, SA_PIC_UART1 },
63 { 0x80030000, SA_PIC_UART2 },
64 { 0x80050000, SA_PIC_UART3 },
65 { 0, 0 }
66 };
67
68 /* Interrupt Controller */
69 typedef struct {
70 SysBusDevice busdev;
71 qemu_irq irq;
72 qemu_irq fiq;
73
74 uint32_t pending;
75 uint32_t enabled;
76 uint32_t is_fiq;
77 uint32_t int_idle;
78 } StrongARMPICState;
79
80 #define ICIP 0x00
81 #define ICMR 0x04
82 #define ICLR 0x08
83 #define ICFP 0x10
84 #define ICPR 0x20
85 #define ICCR 0x0c
86
87 #define SA_PIC_SRCS 32
88
89
90 static void strongarm_pic_update(void *opaque)
91 {
92 StrongARMPICState *s = opaque;
93
94 /* FIXME: reflect DIM */
95 qemu_set_irq(s->fiq, s->pending & s->enabled & s->is_fiq);
96 qemu_set_irq(s->irq, s->pending & s->enabled & ~s->is_fiq);
97 }
98
99 static void strongarm_pic_set_irq(void *opaque, int irq, int level)
100 {
101 StrongARMPICState *s = opaque;
102
103 if (level) {
104 s->pending |= 1 << irq;
105 } else {
106 s->pending &= ~(1 << irq);
107 }
108
109 strongarm_pic_update(s);
110 }
111
112 static uint32_t strongarm_pic_mem_read(void *opaque, target_phys_addr_t offset)
113 {
114 StrongARMPICState *s = opaque;
115
116 switch (offset) {
117 case ICIP:
118 return s->pending & ~s->is_fiq & s->enabled;
119 case ICMR:
120 return s->enabled;
121 case ICLR:
122 return s->is_fiq;
123 case ICCR:
124 return s->int_idle == 0;
125 case ICFP:
126 return s->pending & s->is_fiq & s->enabled;
127 case ICPR:
128 return s->pending;
129 default:
130 printf("%s: Bad register offset 0x" TARGET_FMT_plx "\n",
131 __func__, offset);
132 return 0;
133 }
134 }
135
136 static void strongarm_pic_mem_write(void *opaque, target_phys_addr_t offset,
137 uint32_t value)
138 {
139 StrongARMPICState *s = opaque;
140
141 switch (offset) {
142 case ICMR:
143 s->enabled = value;
144 break;
145 case ICLR:
146 s->is_fiq = value;
147 break;
148 case ICCR:
149 s->int_idle = (value & 1) ? 0 : ~0;
150 break;
151 default:
152 printf("%s: Bad register offset 0x" TARGET_FMT_plx "\n",
153 __func__, offset);
154 break;
155 }
156 strongarm_pic_update(s);
157 }
158
159 static CPUReadMemoryFunc * const strongarm_pic_readfn[] = {
160 strongarm_pic_mem_read,
161 strongarm_pic_mem_read,
162 strongarm_pic_mem_read,
163 };
164
165 static CPUWriteMemoryFunc * const strongarm_pic_writefn[] = {
166 strongarm_pic_mem_write,
167 strongarm_pic_mem_write,
168 strongarm_pic_mem_write,
169 };
170
171 static int strongarm_pic_initfn(SysBusDevice *dev)
172 {
173 StrongARMPICState *s = FROM_SYSBUS(StrongARMPICState, dev);
174 int iomemtype;
175
176 qdev_init_gpio_in(&dev->qdev, strongarm_pic_set_irq, SA_PIC_SRCS);
177 iomemtype = cpu_register_io_memory(strongarm_pic_readfn,
178 strongarm_pic_writefn, s, DEVICE_NATIVE_ENDIAN);
179 sysbus_init_mmio(dev, 0x1000, iomemtype);
180 sysbus_init_irq(dev, &s->irq);
181 sysbus_init_irq(dev, &s->fiq);
182
183 return 0;
184 }
185
186 static int strongarm_pic_post_load(void *opaque, int version_id)
187 {
188 strongarm_pic_update(opaque);
189 return 0;
190 }
191
192 static VMStateDescription vmstate_strongarm_pic_regs = {
193 .name = "strongarm_pic",
194 .version_id = 0,
195 .minimum_version_id = 0,
196 .minimum_version_id_old = 0,
197 .post_load = strongarm_pic_post_load,
198 .fields = (VMStateField[]) {
199 VMSTATE_UINT32(pending, StrongARMPICState),
200 VMSTATE_UINT32(enabled, StrongARMPICState),
201 VMSTATE_UINT32(is_fiq, StrongARMPICState),
202 VMSTATE_UINT32(int_idle, StrongARMPICState),
203 VMSTATE_END_OF_LIST(),
204 },
205 };
206
207 static SysBusDeviceInfo strongarm_pic_info = {
208 .init = strongarm_pic_initfn,
209 .qdev.name = "strongarm_pic",
210 .qdev.desc = "StrongARM PIC",
211 .qdev.size = sizeof(StrongARMPICState),
212 .qdev.vmsd = &vmstate_strongarm_pic_regs,
213 };
214
215 /* Real-Time Clock */
216 #define RTAR 0x00 /* RTC Alarm register */
217 #define RCNR 0x04 /* RTC Counter register */
218 #define RTTR 0x08 /* RTC Timer Trim register */
219 #define RTSR 0x10 /* RTC Status register */
220
221 #define RTSR_AL (1 << 0) /* RTC Alarm detected */
222 #define RTSR_HZ (1 << 1) /* RTC 1Hz detected */
223 #define RTSR_ALE (1 << 2) /* RTC Alarm enable */
224 #define RTSR_HZE (1 << 3) /* RTC 1Hz enable */
225
226 /* 16 LSB of RTTR are clockdiv for internal trim logic,
227 * trim delete isn't emulated, so
228 * f = 32 768 / (RTTR_trim + 1) */
229
230 typedef struct {
231 SysBusDevice busdev;
232 uint32_t rttr;
233 uint32_t rtsr;
234 uint32_t rtar;
235 uint32_t last_rcnr;
236 int64_t last_hz;
237 QEMUTimer *rtc_alarm;
238 QEMUTimer *rtc_hz;
239 qemu_irq rtc_irq;
240 qemu_irq rtc_hz_irq;
241 } StrongARMRTCState;
242
243 static inline void strongarm_rtc_int_update(StrongARMRTCState *s)
244 {
245 qemu_set_irq(s->rtc_irq, s->rtsr & RTSR_AL);
246 qemu_set_irq(s->rtc_hz_irq, s->rtsr & RTSR_HZ);
247 }
248
249 static void strongarm_rtc_hzupdate(StrongARMRTCState *s)
250 {
251 int64_t rt = qemu_get_clock_ms(rt_clock);
252 s->last_rcnr += ((rt - s->last_hz) << 15) /
253 (1000 * ((s->rttr & 0xffff) + 1));
254 s->last_hz = rt;
255 }
256
257 static inline void strongarm_rtc_timer_update(StrongARMRTCState *s)
258 {
259 if ((s->rtsr & RTSR_HZE) && !(s->rtsr & RTSR_HZ)) {
260 qemu_mod_timer(s->rtc_hz, s->last_hz + 1000);
261 } else {
262 qemu_del_timer(s->rtc_hz);
263 }
264
265 if ((s->rtsr & RTSR_ALE) && !(s->rtsr & RTSR_AL)) {
266 qemu_mod_timer(s->rtc_alarm, s->last_hz +
267 (((s->rtar - s->last_rcnr) * 1000 *
268 ((s->rttr & 0xffff) + 1)) >> 15));
269 } else {
270 qemu_del_timer(s->rtc_alarm);
271 }
272 }
273
274 static inline void strongarm_rtc_alarm_tick(void *opaque)
275 {
276 StrongARMRTCState *s = opaque;
277 s->rtsr |= RTSR_AL;
278 strongarm_rtc_timer_update(s);
279 strongarm_rtc_int_update(s);
280 }
281
282 static inline void strongarm_rtc_hz_tick(void *opaque)
283 {
284 StrongARMRTCState *s = opaque;
285 s->rtsr |= RTSR_HZ;
286 strongarm_rtc_timer_update(s);
287 strongarm_rtc_int_update(s);
288 }
289
290 static uint32_t strongarm_rtc_read(void *opaque, target_phys_addr_t addr)
291 {
292 StrongARMRTCState *s = opaque;
293
294 switch (addr) {
295 case RTTR:
296 return s->rttr;
297 case RTSR:
298 return s->rtsr;
299 case RTAR:
300 return s->rtar;
301 case RCNR:
302 return s->last_rcnr +
303 ((qemu_get_clock_ms(rt_clock) - s->last_hz) << 15) /
304 (1000 * ((s->rttr & 0xffff) + 1));
305 default:
306 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
307 return 0;
308 }
309 }
310
311 static void strongarm_rtc_write(void *opaque, target_phys_addr_t addr,
312 uint32_t value)
313 {
314 StrongARMRTCState *s = opaque;
315 uint32_t old_rtsr;
316
317 switch (addr) {
318 case RTTR:
319 strongarm_rtc_hzupdate(s);
320 s->rttr = value;
321 strongarm_rtc_timer_update(s);
322 break;
323
324 case RTSR:
325 old_rtsr = s->rtsr;
326 s->rtsr = (value & (RTSR_ALE | RTSR_HZE)) |
327 (s->rtsr & ~(value & (RTSR_AL | RTSR_HZ)));
328
329 if (s->rtsr != old_rtsr) {
330 strongarm_rtc_timer_update(s);
331 }
332
333 strongarm_rtc_int_update(s);
334 break;
335
336 case RTAR:
337 s->rtar = value;
338 strongarm_rtc_timer_update(s);
339 break;
340
341 case RCNR:
342 strongarm_rtc_hzupdate(s);
343 s->last_rcnr = value;
344 strongarm_rtc_timer_update(s);
345 break;
346
347 default:
348 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
349 }
350 }
351
352 static CPUReadMemoryFunc * const strongarm_rtc_readfn[] = {
353 strongarm_rtc_read,
354 strongarm_rtc_read,
355 strongarm_rtc_read,
356 };
357
358 static CPUWriteMemoryFunc * const strongarm_rtc_writefn[] = {
359 strongarm_rtc_write,
360 strongarm_rtc_write,
361 strongarm_rtc_write,
362 };
363
364 static int strongarm_rtc_init(SysBusDevice *dev)
365 {
366 StrongARMRTCState *s = FROM_SYSBUS(StrongARMRTCState, dev);
367 struct tm tm;
368 int iomemtype;
369
370 s->rttr = 0x0;
371 s->rtsr = 0;
372
373 qemu_get_timedate(&tm, 0);
374
375 s->last_rcnr = (uint32_t) mktimegm(&tm);
376 s->last_hz = qemu_get_clock_ms(rt_clock);
377
378 s->rtc_alarm = qemu_new_timer_ms(rt_clock, strongarm_rtc_alarm_tick, s);
379 s->rtc_hz = qemu_new_timer_ms(rt_clock, strongarm_rtc_hz_tick, s);
380
381 sysbus_init_irq(dev, &s->rtc_irq);
382 sysbus_init_irq(dev, &s->rtc_hz_irq);
383
384 iomemtype = cpu_register_io_memory(strongarm_rtc_readfn,
385 strongarm_rtc_writefn, s, DEVICE_NATIVE_ENDIAN);
386 sysbus_init_mmio(dev, 0x10000, iomemtype);
387
388 return 0;
389 }
390
391 static void strongarm_rtc_pre_save(void *opaque)
392 {
393 StrongARMRTCState *s = opaque;
394
395 strongarm_rtc_hzupdate(s);
396 }
397
398 static int strongarm_rtc_post_load(void *opaque, int version_id)
399 {
400 StrongARMRTCState *s = opaque;
401
402 strongarm_rtc_timer_update(s);
403 strongarm_rtc_int_update(s);
404
405 return 0;
406 }
407
408 static const VMStateDescription vmstate_strongarm_rtc_regs = {
409 .name = "strongarm-rtc",
410 .version_id = 0,
411 .minimum_version_id = 0,
412 .minimum_version_id_old = 0,
413 .pre_save = strongarm_rtc_pre_save,
414 .post_load = strongarm_rtc_post_load,
415 .fields = (VMStateField[]) {
416 VMSTATE_UINT32(rttr, StrongARMRTCState),
417 VMSTATE_UINT32(rtsr, StrongARMRTCState),
418 VMSTATE_UINT32(rtar, StrongARMRTCState),
419 VMSTATE_UINT32(last_rcnr, StrongARMRTCState),
420 VMSTATE_INT64(last_hz, StrongARMRTCState),
421 VMSTATE_END_OF_LIST(),
422 },
423 };
424
425 static SysBusDeviceInfo strongarm_rtc_sysbus_info = {
426 .init = strongarm_rtc_init,
427 .qdev.name = "strongarm-rtc",
428 .qdev.desc = "StrongARM RTC Controller",
429 .qdev.size = sizeof(StrongARMRTCState),
430 .qdev.vmsd = &vmstate_strongarm_rtc_regs,
431 };
432
433 /* GPIO */
434 #define GPLR 0x00
435 #define GPDR 0x04
436 #define GPSR 0x08
437 #define GPCR 0x0c
438 #define GRER 0x10
439 #define GFER 0x14
440 #define GEDR 0x18
441 #define GAFR 0x1c
442
443 typedef struct StrongARMGPIOInfo StrongARMGPIOInfo;
444 struct StrongARMGPIOInfo {
445 SysBusDevice busdev;
446 qemu_irq handler[28];
447 qemu_irq irqs[11];
448 qemu_irq irqX;
449
450 uint32_t ilevel;
451 uint32_t olevel;
452 uint32_t dir;
453 uint32_t rising;
454 uint32_t falling;
455 uint32_t status;
456 uint32_t gpsr;
457 uint32_t gafr;
458
459 uint32_t prev_level;
460 };
461
462
463 static void strongarm_gpio_irq_update(StrongARMGPIOInfo *s)
464 {
465 int i;
466 for (i = 0; i < 11; i++) {
467 qemu_set_irq(s->irqs[i], s->status & (1 << i));
468 }
469
470 qemu_set_irq(s->irqX, (s->status & ~0x7ff));
471 }
472
473 static void strongarm_gpio_set(void *opaque, int line, int level)
474 {
475 StrongARMGPIOInfo *s = opaque;
476 uint32_t mask;
477
478 mask = 1 << line;
479
480 if (level) {
481 s->status |= s->rising & mask &
482 ~s->ilevel & ~s->dir;
483 s->ilevel |= mask;
484 } else {
485 s->status |= s->falling & mask &
486 s->ilevel & ~s->dir;
487 s->ilevel &= ~mask;
488 }
489
490 if (s->status & mask) {
491 strongarm_gpio_irq_update(s);
492 }
493 }
494
495 static void strongarm_gpio_handler_update(StrongARMGPIOInfo *s)
496 {
497 uint32_t level, diff;
498 int bit;
499
500 level = s->olevel & s->dir;
501
502 for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
503 bit = ffs(diff) - 1;
504 qemu_set_irq(s->handler[bit], (level >> bit) & 1);
505 }
506
507 s->prev_level = level;
508 }
509
510 static uint32_t strongarm_gpio_read(void *opaque, target_phys_addr_t offset)
511 {
512 StrongARMGPIOInfo *s = opaque;
513
514 switch (offset) {
515 case GPDR: /* GPIO Pin-Direction registers */
516 return s->dir;
517
518 case GPSR: /* GPIO Pin-Output Set registers */
519 DPRINTF("%s: Read from a write-only register 0x" TARGET_FMT_plx "\n",
520 __func__, offset);
521 return s->gpsr; /* Return last written value. */
522
523 case GPCR: /* GPIO Pin-Output Clear registers */
524 DPRINTF("%s: Read from a write-only register 0x" TARGET_FMT_plx "\n",
525 __func__, offset);
526 return 31337; /* Specified as unpredictable in the docs. */
527
528 case GRER: /* GPIO Rising-Edge Detect Enable registers */
529 return s->rising;
530
531 case GFER: /* GPIO Falling-Edge Detect Enable registers */
532 return s->falling;
533
534 case GAFR: /* GPIO Alternate Function registers */
535 return s->gafr;
536
537 case GPLR: /* GPIO Pin-Level registers */
538 return (s->olevel & s->dir) |
539 (s->ilevel & ~s->dir);
540
541 case GEDR: /* GPIO Edge Detect Status registers */
542 return s->status;
543
544 default:
545 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
546 }
547
548 return 0;
549 }
550
551 static void strongarm_gpio_write(void *opaque,
552 target_phys_addr_t offset, uint32_t value)
553 {
554 StrongARMGPIOInfo *s = opaque;
555
556 switch (offset) {
557 case GPDR: /* GPIO Pin-Direction registers */
558 s->dir = value;
559 strongarm_gpio_handler_update(s);
560 break;
561
562 case GPSR: /* GPIO Pin-Output Set registers */
563 s->olevel |= value;
564 strongarm_gpio_handler_update(s);
565 s->gpsr = value;
566 break;
567
568 case GPCR: /* GPIO Pin-Output Clear registers */
569 s->olevel &= ~value;
570 strongarm_gpio_handler_update(s);
571 break;
572
573 case GRER: /* GPIO Rising-Edge Detect Enable registers */
574 s->rising = value;
575 break;
576
577 case GFER: /* GPIO Falling-Edge Detect Enable registers */
578 s->falling = value;
579 break;
580
581 case GAFR: /* GPIO Alternate Function registers */
582 s->gafr = value;
583 break;
584
585 case GEDR: /* GPIO Edge Detect Status registers */
586 s->status &= ~value;
587 strongarm_gpio_irq_update(s);
588 break;
589
590 default:
591 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
592 }
593 }
594
595 static CPUReadMemoryFunc * const strongarm_gpio_readfn[] = {
596 strongarm_gpio_read,
597 strongarm_gpio_read,
598 strongarm_gpio_read
599 };
600
601 static CPUWriteMemoryFunc * const strongarm_gpio_writefn[] = {
602 strongarm_gpio_write,
603 strongarm_gpio_write,
604 strongarm_gpio_write
605 };
606
607 static DeviceState *strongarm_gpio_init(target_phys_addr_t base,
608 DeviceState *pic)
609 {
610 DeviceState *dev;
611 int i;
612
613 dev = qdev_create(NULL, "strongarm-gpio");
614 qdev_init_nofail(dev);
615
616 sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
617 for (i = 0; i < 12; i++)
618 sysbus_connect_irq(sysbus_from_qdev(dev), i,
619 qdev_get_gpio_in(pic, SA_PIC_GPIO0_EDGE + i));
620
621 return dev;
622 }
623
624 static int strongarm_gpio_initfn(SysBusDevice *dev)
625 {
626 int iomemtype;
627 StrongARMGPIOInfo *s;
628 int i;
629
630 s = FROM_SYSBUS(StrongARMGPIOInfo, dev);
631
632 qdev_init_gpio_in(&dev->qdev, strongarm_gpio_set, 28);
633 qdev_init_gpio_out(&dev->qdev, s->handler, 28);
634
635 iomemtype = cpu_register_io_memory(strongarm_gpio_readfn,
636 strongarm_gpio_writefn, s, DEVICE_NATIVE_ENDIAN);
637
638 sysbus_init_mmio(dev, 0x1000, iomemtype);
639 for (i = 0; i < 11; i++) {
640 sysbus_init_irq(dev, &s->irqs[i]);
641 }
642 sysbus_init_irq(dev, &s->irqX);
643
644 return 0;
645 }
646
647 static const VMStateDescription vmstate_strongarm_gpio_regs = {
648 .name = "strongarm-gpio",
649 .version_id = 0,
650 .minimum_version_id = 0,
651 .minimum_version_id_old = 0,
652 .fields = (VMStateField[]) {
653 VMSTATE_UINT32(ilevel, StrongARMGPIOInfo),
654 VMSTATE_UINT32(olevel, StrongARMGPIOInfo),
655 VMSTATE_UINT32(dir, StrongARMGPIOInfo),
656 VMSTATE_UINT32(rising, StrongARMGPIOInfo),
657 VMSTATE_UINT32(falling, StrongARMGPIOInfo),
658 VMSTATE_UINT32(status, StrongARMGPIOInfo),
659 VMSTATE_UINT32(gafr, StrongARMGPIOInfo),
660 VMSTATE_END_OF_LIST(),
661 },
662 };
663
664 static SysBusDeviceInfo strongarm_gpio_info = {
665 .init = strongarm_gpio_initfn,
666 .qdev.name = "strongarm-gpio",
667 .qdev.desc = "StrongARM GPIO controller",
668 .qdev.size = sizeof(StrongARMGPIOInfo),
669 };
670
671 /* Peripheral Pin Controller */
672 #define PPDR 0x00
673 #define PPSR 0x04
674 #define PPAR 0x08
675 #define PSDR 0x0c
676 #define PPFR 0x10
677
678 typedef struct StrongARMPPCInfo StrongARMPPCInfo;
679 struct StrongARMPPCInfo {
680 SysBusDevice busdev;
681 qemu_irq handler[28];
682
683 uint32_t ilevel;
684 uint32_t olevel;
685 uint32_t dir;
686 uint32_t ppar;
687 uint32_t psdr;
688 uint32_t ppfr;
689
690 uint32_t prev_level;
691 };
692
693 static void strongarm_ppc_set(void *opaque, int line, int level)
694 {
695 StrongARMPPCInfo *s = opaque;
696
697 if (level) {
698 s->ilevel |= 1 << line;
699 } else {
700 s->ilevel &= ~(1 << line);
701 }
702 }
703
704 static void strongarm_ppc_handler_update(StrongARMPPCInfo *s)
705 {
706 uint32_t level, diff;
707 int bit;
708
709 level = s->olevel & s->dir;
710
711 for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
712 bit = ffs(diff) - 1;
713 qemu_set_irq(s->handler[bit], (level >> bit) & 1);
714 }
715
716 s->prev_level = level;
717 }
718
719 static uint32_t strongarm_ppc_read(void *opaque, target_phys_addr_t offset)
720 {
721 StrongARMPPCInfo *s = opaque;
722
723 switch (offset) {
724 case PPDR: /* PPC Pin Direction registers */
725 return s->dir | ~0x3fffff;
726
727 case PPSR: /* PPC Pin State registers */
728 return (s->olevel & s->dir) |
729 (s->ilevel & ~s->dir) |
730 ~0x3fffff;
731
732 case PPAR:
733 return s->ppar | ~0x41000;
734
735 case PSDR:
736 return s->psdr;
737
738 case PPFR:
739 return s->ppfr | ~0x7f001;
740
741 default:
742 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
743 }
744
745 return 0;
746 }
747
748 static void strongarm_ppc_write(void *opaque,
749 target_phys_addr_t offset, uint32_t value)
750 {
751 StrongARMPPCInfo *s = opaque;
752
753 switch (offset) {
754 case PPDR: /* PPC Pin Direction registers */
755 s->dir = value & 0x3fffff;
756 strongarm_ppc_handler_update(s);
757 break;
758
759 case PPSR: /* PPC Pin State registers */
760 s->olevel = value & s->dir & 0x3fffff;
761 strongarm_ppc_handler_update(s);
762 break;
763
764 case PPAR:
765 s->ppar = value & 0x41000;
766 break;
767
768 case PSDR:
769 s->psdr = value & 0x3fffff;
770 break;
771
772 case PPFR:
773 s->ppfr = value & 0x7f001;
774 break;
775
776 default:
777 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
778 }
779 }
780
781 static CPUReadMemoryFunc * const strongarm_ppc_readfn[] = {
782 strongarm_ppc_read,
783 strongarm_ppc_read,
784 strongarm_ppc_read
785 };
786
787 static CPUWriteMemoryFunc * const strongarm_ppc_writefn[] = {
788 strongarm_ppc_write,
789 strongarm_ppc_write,
790 strongarm_ppc_write
791 };
792
793 static int strongarm_ppc_init(SysBusDevice *dev)
794 {
795 int iomemtype;
796 StrongARMPPCInfo *s;
797
798 s = FROM_SYSBUS(StrongARMPPCInfo, dev);
799
800 qdev_init_gpio_in(&dev->qdev, strongarm_ppc_set, 22);
801 qdev_init_gpio_out(&dev->qdev, s->handler, 22);
802
803 iomemtype = cpu_register_io_memory(strongarm_ppc_readfn,
804 strongarm_ppc_writefn, s, DEVICE_NATIVE_ENDIAN);
805
806 sysbus_init_mmio(dev, 0x1000, iomemtype);
807
808 return 0;
809 }
810
811 static const VMStateDescription vmstate_strongarm_ppc_regs = {
812 .name = "strongarm-ppc",
813 .version_id = 0,
814 .minimum_version_id = 0,
815 .minimum_version_id_old = 0,
816 .fields = (VMStateField[]) {
817 VMSTATE_UINT32(ilevel, StrongARMPPCInfo),
818 VMSTATE_UINT32(olevel, StrongARMPPCInfo),
819 VMSTATE_UINT32(dir, StrongARMPPCInfo),
820 VMSTATE_UINT32(ppar, StrongARMPPCInfo),
821 VMSTATE_UINT32(psdr, StrongARMPPCInfo),
822 VMSTATE_UINT32(ppfr, StrongARMPPCInfo),
823 VMSTATE_END_OF_LIST(),
824 },
825 };
826
827 static SysBusDeviceInfo strongarm_ppc_info = {
828 .init = strongarm_ppc_init,
829 .qdev.name = "strongarm-ppc",
830 .qdev.desc = "StrongARM PPC controller",
831 .qdev.size = sizeof(StrongARMPPCInfo),
832 };
833
834 /* UART Ports */
835 #define UTCR0 0x00
836 #define UTCR1 0x04
837 #define UTCR2 0x08
838 #define UTCR3 0x0c
839 #define UTDR 0x14
840 #define UTSR0 0x1c
841 #define UTSR1 0x20
842
843 #define UTCR0_PE (1 << 0) /* Parity enable */
844 #define UTCR0_OES (1 << 1) /* Even parity */
845 #define UTCR0_SBS (1 << 2) /* 2 stop bits */
846 #define UTCR0_DSS (1 << 3) /* 8-bit data */
847
848 #define UTCR3_RXE (1 << 0) /* Rx enable */
849 #define UTCR3_TXE (1 << 1) /* Tx enable */
850 #define UTCR3_BRK (1 << 2) /* Force Break */
851 #define UTCR3_RIE (1 << 3) /* Rx int enable */
852 #define UTCR3_TIE (1 << 4) /* Tx int enable */
853 #define UTCR3_LBM (1 << 5) /* Loopback */
854
855 #define UTSR0_TFS (1 << 0) /* Tx FIFO nearly empty */
856 #define UTSR0_RFS (1 << 1) /* Rx FIFO nearly full */
857 #define UTSR0_RID (1 << 2) /* Receiver Idle */
858 #define UTSR0_RBB (1 << 3) /* Receiver begin break */
859 #define UTSR0_REB (1 << 4) /* Receiver end break */
860 #define UTSR0_EIF (1 << 5) /* Error in FIFO */
861
862 #define UTSR1_RNE (1 << 1) /* Receive FIFO not empty */
863 #define UTSR1_TNF (1 << 2) /* Transmit FIFO not full */
864 #define UTSR1_PRE (1 << 3) /* Parity error */
865 #define UTSR1_FRE (1 << 4) /* Frame error */
866 #define UTSR1_ROR (1 << 5) /* Receive Over Run */
867
868 #define RX_FIFO_PRE (1 << 8)
869 #define RX_FIFO_FRE (1 << 9)
870 #define RX_FIFO_ROR (1 << 10)
871
872 typedef struct {
873 SysBusDevice busdev;
874 CharDriverState *chr;
875 qemu_irq irq;
876
877 uint8_t utcr0;
878 uint16_t brd;
879 uint8_t utcr3;
880 uint8_t utsr0;
881 uint8_t utsr1;
882
883 uint8_t tx_fifo[8];
884 uint8_t tx_start;
885 uint8_t tx_len;
886 uint16_t rx_fifo[12]; /* value + error flags in high bits */
887 uint8_t rx_start;
888 uint8_t rx_len;
889
890 uint64_t char_transmit_time; /* time to transmit a char in ticks*/
891 bool wait_break_end;
892 QEMUTimer *rx_timeout_timer;
893 QEMUTimer *tx_timer;
894 } StrongARMUARTState;
895
896 static void strongarm_uart_update_status(StrongARMUARTState *s)
897 {
898 uint16_t utsr1 = 0;
899
900 if (s->tx_len != 8) {
901 utsr1 |= UTSR1_TNF;
902 }
903
904 if (s->rx_len != 0) {
905 uint16_t ent = s->rx_fifo[s->rx_start];
906
907 utsr1 |= UTSR1_RNE;
908 if (ent & RX_FIFO_PRE) {
909 s->utsr1 |= UTSR1_PRE;
910 }
911 if (ent & RX_FIFO_FRE) {
912 s->utsr1 |= UTSR1_FRE;
913 }
914 if (ent & RX_FIFO_ROR) {
915 s->utsr1 |= UTSR1_ROR;
916 }
917 }
918
919 s->utsr1 = utsr1;
920 }
921
922 static void strongarm_uart_update_int_status(StrongARMUARTState *s)
923 {
924 uint16_t utsr0 = s->utsr0 &
925 (UTSR0_REB | UTSR0_RBB | UTSR0_RID);
926 int i;
927
928 if ((s->utcr3 & UTCR3_TXE) &&
929 (s->utcr3 & UTCR3_TIE) &&
930 s->tx_len <= 4) {
931 utsr0 |= UTSR0_TFS;
932 }
933
934 if ((s->utcr3 & UTCR3_RXE) &&
935 (s->utcr3 & UTCR3_RIE) &&
936 s->rx_len > 4) {
937 utsr0 |= UTSR0_RFS;
938 }
939
940 for (i = 0; i < s->rx_len && i < 4; i++)
941 if (s->rx_fifo[(s->rx_start + i) % 12] & ~0xff) {
942 utsr0 |= UTSR0_EIF;
943 break;
944 }
945
946 s->utsr0 = utsr0;
947 qemu_set_irq(s->irq, utsr0);
948 }
949
950 static void strongarm_uart_update_parameters(StrongARMUARTState *s)
951 {
952 int speed, parity, data_bits, stop_bits, frame_size;
953 QEMUSerialSetParams ssp;
954
955 /* Start bit. */
956 frame_size = 1;
957 if (s->utcr0 & UTCR0_PE) {
958 /* Parity bit. */
959 frame_size++;
960 if (s->utcr0 & UTCR0_OES) {
961 parity = 'E';
962 } else {
963 parity = 'O';
964 }
965 } else {
966 parity = 'N';
967 }
968 if (s->utcr0 & UTCR0_SBS) {
969 stop_bits = 2;
970 } else {
971 stop_bits = 1;
972 }
973
974 data_bits = (s->utcr0 & UTCR0_DSS) ? 8 : 7;
975 frame_size += data_bits + stop_bits;
976 speed = 3686400 / 16 / (s->brd + 1);
977 ssp.speed = speed;
978 ssp.parity = parity;
979 ssp.data_bits = data_bits;
980 ssp.stop_bits = stop_bits;
981 s->char_transmit_time = (get_ticks_per_sec() / speed) * frame_size;
982 if (s->chr) {
983 qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
984 }
985
986 DPRINTF(stderr, "%s speed=%d parity=%c data=%d stop=%d\n", s->chr->label,
987 speed, parity, data_bits, stop_bits);
988 }
989
990 static void strongarm_uart_rx_to(void *opaque)
991 {
992 StrongARMUARTState *s = opaque;
993
994 if (s->rx_len) {
995 s->utsr0 |= UTSR0_RID;
996 strongarm_uart_update_int_status(s);
997 }
998 }
999
1000 static void strongarm_uart_rx_push(StrongARMUARTState *s, uint16_t c)
1001 {
1002 if ((s->utcr3 & UTCR3_RXE) == 0) {
1003 /* rx disabled */
1004 return;
1005 }
1006
1007 if (s->wait_break_end) {
1008 s->utsr0 |= UTSR0_REB;
1009 s->wait_break_end = false;
1010 }
1011
1012 if (s->rx_len < 12) {
1013 s->rx_fifo[(s->rx_start + s->rx_len) % 12] = c;
1014 s->rx_len++;
1015 } else
1016 s->rx_fifo[(s->rx_start + 11) % 12] |= RX_FIFO_ROR;
1017 }
1018
1019 static int strongarm_uart_can_receive(void *opaque)
1020 {
1021 StrongARMUARTState *s = opaque;
1022
1023 if (s->rx_len == 12) {
1024 return 0;
1025 }
1026 /* It's best not to get more than 2/3 of RX FIFO, so advertise that much */
1027 if (s->rx_len < 8) {
1028 return 8 - s->rx_len;
1029 }
1030 return 1;
1031 }
1032
1033 static void strongarm_uart_receive(void *opaque, const uint8_t *buf, int size)
1034 {
1035 StrongARMUARTState *s = opaque;
1036 int i;
1037
1038 for (i = 0; i < size; i++) {
1039 strongarm_uart_rx_push(s, buf[i]);
1040 }
1041
1042 /* call the timeout receive callback in 3 char transmit time */
1043 qemu_mod_timer(s->rx_timeout_timer,
1044 qemu_get_clock_ns(vm_clock) + s->char_transmit_time * 3);
1045
1046 strongarm_uart_update_status(s);
1047 strongarm_uart_update_int_status(s);
1048 }
1049
1050 static void strongarm_uart_event(void *opaque, int event)
1051 {
1052 StrongARMUARTState *s = opaque;
1053 if (event == CHR_EVENT_BREAK) {
1054 s->utsr0 |= UTSR0_RBB;
1055 strongarm_uart_rx_push(s, RX_FIFO_FRE);
1056 s->wait_break_end = true;
1057 strongarm_uart_update_status(s);
1058 strongarm_uart_update_int_status(s);
1059 }
1060 }
1061
1062 static void strongarm_uart_tx(void *opaque)
1063 {
1064 StrongARMUARTState *s = opaque;
1065 uint64_t new_xmit_ts = qemu_get_clock_ns(vm_clock);
1066
1067 if (s->utcr3 & UTCR3_LBM) /* loopback */ {
1068 strongarm_uart_receive(s, &s->tx_fifo[s->tx_start], 1);
1069 } else if (s->chr) {
1070 qemu_chr_write(s->chr, &s->tx_fifo[s->tx_start], 1);
1071 }
1072
1073 s->tx_start = (s->tx_start + 1) % 8;
1074 s->tx_len--;
1075 if (s->tx_len) {
1076 qemu_mod_timer(s->tx_timer, new_xmit_ts + s->char_transmit_time);
1077 }
1078 strongarm_uart_update_status(s);
1079 strongarm_uart_update_int_status(s);
1080 }
1081
1082 static uint32_t strongarm_uart_read(void *opaque, target_phys_addr_t addr)
1083 {
1084 StrongARMUARTState *s = opaque;
1085 uint16_t ret;
1086
1087 switch (addr) {
1088 case UTCR0:
1089 return s->utcr0;
1090
1091 case UTCR1:
1092 return s->brd >> 8;
1093
1094 case UTCR2:
1095 return s->brd & 0xff;
1096
1097 case UTCR3:
1098 return s->utcr3;
1099
1100 case UTDR:
1101 if (s->rx_len != 0) {
1102 ret = s->rx_fifo[s->rx_start];
1103 s->rx_start = (s->rx_start + 1) % 12;
1104 s->rx_len--;
1105 strongarm_uart_update_status(s);
1106 strongarm_uart_update_int_status(s);
1107 return ret;
1108 }
1109 return 0;
1110
1111 case UTSR0:
1112 return s->utsr0;
1113
1114 case UTSR1:
1115 return s->utsr1;
1116
1117 default:
1118 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1119 return 0;
1120 }
1121 }
1122
1123 static void strongarm_uart_write(void *opaque, target_phys_addr_t addr,
1124 uint32_t value)
1125 {
1126 StrongARMUARTState *s = opaque;
1127
1128 switch (addr) {
1129 case UTCR0:
1130 s->utcr0 = value & 0x7f;
1131 strongarm_uart_update_parameters(s);
1132 break;
1133
1134 case UTCR1:
1135 s->brd = (s->brd & 0xff) | ((value & 0xf) << 8);
1136 strongarm_uart_update_parameters(s);
1137 break;
1138
1139 case UTCR2:
1140 s->brd = (s->brd & 0xf00) | (value & 0xff);
1141 strongarm_uart_update_parameters(s);
1142 break;
1143
1144 case UTCR3:
1145 s->utcr3 = value & 0x3f;
1146 if ((s->utcr3 & UTCR3_RXE) == 0) {
1147 s->rx_len = 0;
1148 }
1149 if ((s->utcr3 & UTCR3_TXE) == 0) {
1150 s->tx_len = 0;
1151 }
1152 strongarm_uart_update_status(s);
1153 strongarm_uart_update_int_status(s);
1154 break;
1155
1156 case UTDR:
1157 if ((s->utcr3 & UTCR3_TXE) && s->tx_len != 8) {
1158 s->tx_fifo[(s->tx_start + s->tx_len) % 8] = value;
1159 s->tx_len++;
1160 strongarm_uart_update_status(s);
1161 strongarm_uart_update_int_status(s);
1162 if (s->tx_len == 1) {
1163 strongarm_uart_tx(s);
1164 }
1165 }
1166 break;
1167
1168 case UTSR0:
1169 s->utsr0 = s->utsr0 & ~(value &
1170 (UTSR0_REB | UTSR0_RBB | UTSR0_RID));
1171 strongarm_uart_update_int_status(s);
1172 break;
1173
1174 default:
1175 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1176 }
1177 }
1178
1179 static CPUReadMemoryFunc * const strongarm_uart_readfn[] = {
1180 strongarm_uart_read,
1181 strongarm_uart_read,
1182 strongarm_uart_read,
1183 };
1184
1185 static CPUWriteMemoryFunc * const strongarm_uart_writefn[] = {
1186 strongarm_uart_write,
1187 strongarm_uart_write,
1188 strongarm_uart_write,
1189 };
1190
1191 static int strongarm_uart_init(SysBusDevice *dev)
1192 {
1193 StrongARMUARTState *s = FROM_SYSBUS(StrongARMUARTState, dev);
1194 int iomemtype;
1195
1196 iomemtype = cpu_register_io_memory(strongarm_uart_readfn,
1197 strongarm_uart_writefn, s, DEVICE_NATIVE_ENDIAN);
1198 sysbus_init_mmio(dev, 0x10000, iomemtype);
1199 sysbus_init_irq(dev, &s->irq);
1200
1201 s->rx_timeout_timer = qemu_new_timer_ns(vm_clock, strongarm_uart_rx_to, s);
1202 s->tx_timer = qemu_new_timer_ns(vm_clock, strongarm_uart_tx, s);
1203
1204 if (s->chr) {
1205 qemu_chr_add_handlers(s->chr,
1206 strongarm_uart_can_receive,
1207 strongarm_uart_receive,
1208 strongarm_uart_event,
1209 s);
1210 }
1211
1212 return 0;
1213 }
1214
1215 static void strongarm_uart_reset(DeviceState *dev)
1216 {
1217 StrongARMUARTState *s = DO_UPCAST(StrongARMUARTState, busdev.qdev, dev);
1218
1219 s->utcr0 = UTCR0_DSS; /* 8 data, no parity */
1220 s->brd = 23; /* 9600 */
1221 /* enable send & recv - this actually violates spec */
1222 s->utcr3 = UTCR3_TXE | UTCR3_RXE;
1223
1224 s->rx_len = s->tx_len = 0;
1225
1226 strongarm_uart_update_parameters(s);
1227 strongarm_uart_update_status(s);
1228 strongarm_uart_update_int_status(s);
1229 }
1230
1231 static int strongarm_uart_post_load(void *opaque, int version_id)
1232 {
1233 StrongARMUARTState *s = opaque;
1234
1235 strongarm_uart_update_parameters(s);
1236 strongarm_uart_update_status(s);
1237 strongarm_uart_update_int_status(s);
1238
1239 /* tx and restart timer */
1240 if (s->tx_len) {
1241 strongarm_uart_tx(s);
1242 }
1243
1244 /* restart rx timeout timer */
1245 if (s->rx_len) {
1246 qemu_mod_timer(s->rx_timeout_timer,
1247 qemu_get_clock_ns(vm_clock) + s->char_transmit_time * 3);
1248 }
1249
1250 return 0;
1251 }
1252
1253 static const VMStateDescription vmstate_strongarm_uart_regs = {
1254 .name = "strongarm-uart",
1255 .version_id = 0,
1256 .minimum_version_id = 0,
1257 .minimum_version_id_old = 0,
1258 .post_load = strongarm_uart_post_load,
1259 .fields = (VMStateField[]) {
1260 VMSTATE_UINT8(utcr0, StrongARMUARTState),
1261 VMSTATE_UINT16(brd, StrongARMUARTState),
1262 VMSTATE_UINT8(utcr3, StrongARMUARTState),
1263 VMSTATE_UINT8(utsr0, StrongARMUARTState),
1264 VMSTATE_UINT8_ARRAY(tx_fifo, StrongARMUARTState, 8),
1265 VMSTATE_UINT8(tx_start, StrongARMUARTState),
1266 VMSTATE_UINT8(tx_len, StrongARMUARTState),
1267 VMSTATE_UINT16_ARRAY(rx_fifo, StrongARMUARTState, 12),
1268 VMSTATE_UINT8(rx_start, StrongARMUARTState),
1269 VMSTATE_UINT8(rx_len, StrongARMUARTState),
1270 VMSTATE_BOOL(wait_break_end, StrongARMUARTState),
1271 VMSTATE_END_OF_LIST(),
1272 },
1273 };
1274
1275 static SysBusDeviceInfo strongarm_uart_info = {
1276 .init = strongarm_uart_init,
1277 .qdev.name = "strongarm-uart",
1278 .qdev.desc = "StrongARM UART controller",
1279 .qdev.size = sizeof(StrongARMUARTState),
1280 .qdev.reset = strongarm_uart_reset,
1281 .qdev.vmsd = &vmstate_strongarm_uart_regs,
1282 .qdev.props = (Property[]) {
1283 DEFINE_PROP_CHR("chardev", StrongARMUARTState, chr),
1284 DEFINE_PROP_END_OF_LIST(),
1285 }
1286 };
1287
1288 /* Synchronous Serial Ports */
1289 typedef struct {
1290 SysBusDevice busdev;
1291 qemu_irq irq;
1292 SSIBus *bus;
1293
1294 uint16_t sscr[2];
1295 uint16_t sssr;
1296
1297 uint16_t rx_fifo[8];
1298 uint8_t rx_level;
1299 uint8_t rx_start;
1300 } StrongARMSSPState;
1301
1302 #define SSCR0 0x60 /* SSP Control register 0 */
1303 #define SSCR1 0x64 /* SSP Control register 1 */
1304 #define SSDR 0x6c /* SSP Data register */
1305 #define SSSR 0x74 /* SSP Status register */
1306
1307 /* Bitfields for above registers */
1308 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00)
1309 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10)
1310 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20)
1311 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30)
1312 #define SSCR0_SSE (1 << 7)
1313 #define SSCR0_DSS(x) (((x) & 0xf) + 1)
1314 #define SSCR1_RIE (1 << 0)
1315 #define SSCR1_TIE (1 << 1)
1316 #define SSCR1_LBM (1 << 2)
1317 #define SSSR_TNF (1 << 2)
1318 #define SSSR_RNE (1 << 3)
1319 #define SSSR_TFS (1 << 5)
1320 #define SSSR_RFS (1 << 6)
1321 #define SSSR_ROR (1 << 7)
1322 #define SSSR_RW 0x0080
1323
1324 static void strongarm_ssp_int_update(StrongARMSSPState *s)
1325 {
1326 int level = 0;
1327
1328 level |= (s->sssr & SSSR_ROR);
1329 level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE);
1330 level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE);
1331 qemu_set_irq(s->irq, level);
1332 }
1333
1334 static void strongarm_ssp_fifo_update(StrongARMSSPState *s)
1335 {
1336 s->sssr &= ~SSSR_TFS;
1337 s->sssr &= ~SSSR_TNF;
1338 if (s->sscr[0] & SSCR0_SSE) {
1339 if (s->rx_level >= 4) {
1340 s->sssr |= SSSR_RFS;
1341 } else {
1342 s->sssr &= ~SSSR_RFS;
1343 }
1344 if (s->rx_level) {
1345 s->sssr |= SSSR_RNE;
1346 } else {
1347 s->sssr &= ~SSSR_RNE;
1348 }
1349 /* TX FIFO is never filled, so it is always in underrun
1350 condition if SSP is enabled */
1351 s->sssr |= SSSR_TFS;
1352 s->sssr |= SSSR_TNF;
1353 }
1354
1355 strongarm_ssp_int_update(s);
1356 }
1357
1358 static uint32_t strongarm_ssp_read(void *opaque, target_phys_addr_t addr)
1359 {
1360 StrongARMSSPState *s = opaque;
1361 uint32_t retval;
1362
1363 switch (addr) {
1364 case SSCR0:
1365 return s->sscr[0];
1366 case SSCR1:
1367 return s->sscr[1];
1368 case SSSR:
1369 return s->sssr;
1370 case SSDR:
1371 if (~s->sscr[0] & SSCR0_SSE) {
1372 return 0xffffffff;
1373 }
1374 if (s->rx_level < 1) {
1375 printf("%s: SSP Rx Underrun\n", __func__);
1376 return 0xffffffff;
1377 }
1378 s->rx_level--;
1379 retval = s->rx_fifo[s->rx_start++];
1380 s->rx_start &= 0x7;
1381 strongarm_ssp_fifo_update(s);
1382 return retval;
1383 default:
1384 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1385 break;
1386 }
1387 return 0;
1388 }
1389
1390 static void strongarm_ssp_write(void *opaque, target_phys_addr_t addr,
1391 uint32_t value)
1392 {
1393 StrongARMSSPState *s = opaque;
1394
1395 switch (addr) {
1396 case SSCR0:
1397 s->sscr[0] = value & 0xffbf;
1398 if ((s->sscr[0] & SSCR0_SSE) && SSCR0_DSS(value) < 4) {
1399 printf("%s: Wrong data size: %i bits\n", __func__,
1400 SSCR0_DSS(value));
1401 }
1402 if (!(value & SSCR0_SSE)) {
1403 s->sssr = 0;
1404 s->rx_level = 0;
1405 }
1406 strongarm_ssp_fifo_update(s);
1407 break;
1408
1409 case SSCR1:
1410 s->sscr[1] = value & 0x2f;
1411 if (value & SSCR1_LBM) {
1412 printf("%s: Attempt to use SSP LBM mode\n", __func__);
1413 }
1414 strongarm_ssp_fifo_update(s);
1415 break;
1416
1417 case SSSR:
1418 s->sssr &= ~(value & SSSR_RW);
1419 strongarm_ssp_int_update(s);
1420 break;
1421
1422 case SSDR:
1423 if (SSCR0_UWIRE(s->sscr[0])) {
1424 value &= 0xff;
1425 } else
1426 /* Note how 32bits overflow does no harm here */
1427 value &= (1 << SSCR0_DSS(s->sscr[0])) - 1;
1428
1429 /* Data goes from here to the Tx FIFO and is shifted out from
1430 * there directly to the slave, no need to buffer it.
1431 */
1432 if (s->sscr[0] & SSCR0_SSE) {
1433 uint32_t readval;
1434 if (s->sscr[1] & SSCR1_LBM) {
1435 readval = value;
1436 } else {
1437 readval = ssi_transfer(s->bus, value);
1438 }
1439
1440 if (s->rx_level < 0x08) {
1441 s->rx_fifo[(s->rx_start + s->rx_level++) & 0x7] = readval;
1442 } else {
1443 s->sssr |= SSSR_ROR;
1444 }
1445 }
1446 strongarm_ssp_fifo_update(s);
1447 break;
1448
1449 default:
1450 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1451 break;
1452 }
1453 }
1454
1455 static CPUReadMemoryFunc * const strongarm_ssp_readfn[] = {
1456 strongarm_ssp_read,
1457 strongarm_ssp_read,
1458 strongarm_ssp_read,
1459 };
1460
1461 static CPUWriteMemoryFunc * const strongarm_ssp_writefn[] = {
1462 strongarm_ssp_write,
1463 strongarm_ssp_write,
1464 strongarm_ssp_write,
1465 };
1466
1467 static int strongarm_ssp_post_load(void *opaque, int version_id)
1468 {
1469 StrongARMSSPState *s = opaque;
1470
1471 strongarm_ssp_fifo_update(s);
1472
1473 return 0;
1474 }
1475
1476 static int strongarm_ssp_init(SysBusDevice *dev)
1477 {
1478 int iomemtype;
1479 StrongARMSSPState *s = FROM_SYSBUS(StrongARMSSPState, dev);
1480
1481 sysbus_init_irq(dev, &s->irq);
1482
1483 iomemtype = cpu_register_io_memory(strongarm_ssp_readfn,
1484 strongarm_ssp_writefn, s,
1485 DEVICE_NATIVE_ENDIAN);
1486 sysbus_init_mmio(dev, 0x1000, iomemtype);
1487
1488 s->bus = ssi_create_bus(&dev->qdev, "ssi");
1489 return 0;
1490 }
1491
1492 static void strongarm_ssp_reset(DeviceState *dev)
1493 {
1494 StrongARMSSPState *s = DO_UPCAST(StrongARMSSPState, busdev.qdev, dev);
1495 s->sssr = 0x03; /* 3 bit data, SPI, disabled */
1496 s->rx_start = 0;
1497 s->rx_level = 0;
1498 }
1499
1500 static const VMStateDescription vmstate_strongarm_ssp_regs = {
1501 .name = "strongarm-ssp",
1502 .version_id = 0,
1503 .minimum_version_id = 0,
1504 .minimum_version_id_old = 0,
1505 .post_load = strongarm_ssp_post_load,
1506 .fields = (VMStateField[]) {
1507 VMSTATE_UINT16_ARRAY(sscr, StrongARMSSPState, 2),
1508 VMSTATE_UINT16(sssr, StrongARMSSPState),
1509 VMSTATE_UINT16_ARRAY(rx_fifo, StrongARMSSPState, 8),
1510 VMSTATE_UINT8(rx_start, StrongARMSSPState),
1511 VMSTATE_UINT8(rx_level, StrongARMSSPState),
1512 VMSTATE_END_OF_LIST(),
1513 },
1514 };
1515
1516 static SysBusDeviceInfo strongarm_ssp_info = {
1517 .init = strongarm_ssp_init,
1518 .qdev.name = "strongarm-ssp",
1519 .qdev.desc = "StrongARM SSP controller",
1520 .qdev.size = sizeof(StrongARMSSPState),
1521 .qdev.reset = strongarm_ssp_reset,
1522 .qdev.vmsd = &vmstate_strongarm_ssp_regs,
1523 };
1524
1525 /* Main CPU functions */
1526 StrongARMState *sa1110_init(unsigned int sdram_size, const char *rev)
1527 {
1528 StrongARMState *s;
1529 qemu_irq *pic;
1530 int i;
1531
1532 s = qemu_mallocz(sizeof(StrongARMState));
1533
1534 if (!rev) {
1535 rev = "sa1110-b5";
1536 }
1537
1538 if (strncmp(rev, "sa1110", 6)) {
1539 error_report("Machine requires a SA1110 processor.");
1540 exit(1);
1541 }
1542
1543 s->env = cpu_init(rev);
1544
1545 if (!s->env) {
1546 error_report("Unable to find CPU definition");
1547 exit(1);
1548 }
1549
1550 cpu_register_physical_memory(SA_SDCS0,
1551 sdram_size, qemu_ram_alloc(NULL, "strongarm.sdram",
1552 sdram_size) | IO_MEM_RAM);
1553
1554 pic = arm_pic_init_cpu(s->env);
1555 s->pic = sysbus_create_varargs("strongarm_pic", 0x90050000,
1556 pic[ARM_PIC_CPU_IRQ], pic[ARM_PIC_CPU_FIQ], NULL);
1557
1558 sysbus_create_varargs("pxa25x-timer", 0x90000000,
1559 qdev_get_gpio_in(s->pic, SA_PIC_OSTC0),
1560 qdev_get_gpio_in(s->pic, SA_PIC_OSTC1),
1561 qdev_get_gpio_in(s->pic, SA_PIC_OSTC2),
1562 qdev_get_gpio_in(s->pic, SA_PIC_OSTC3),
1563 NULL);
1564
1565 sysbus_create_simple("strongarm-rtc", 0x90010000,
1566 qdev_get_gpio_in(s->pic, SA_PIC_RTC_ALARM));
1567
1568 s->gpio = strongarm_gpio_init(0x90040000, s->pic);
1569
1570 s->ppc = sysbus_create_varargs("strongarm-ppc", 0x90060000, NULL);
1571
1572 for (i = 0; sa_serial[i].io_base; i++) {
1573 DeviceState *dev = qdev_create(NULL, "strongarm-uart");
1574 qdev_prop_set_chr(dev, "chardev", serial_hds[i]);
1575 qdev_init_nofail(dev);
1576 sysbus_mmio_map(sysbus_from_qdev(dev), 0,
1577 sa_serial[i].io_base);
1578 sysbus_connect_irq(sysbus_from_qdev(dev), 0,
1579 qdev_get_gpio_in(s->pic, sa_serial[i].irq));
1580 }
1581
1582 s->ssp = sysbus_create_varargs("strongarm-ssp", 0x80070000,
1583 qdev_get_gpio_in(s->pic, SA_PIC_SSP), NULL);
1584 s->ssp_bus = (SSIBus *)qdev_get_child_bus(s->ssp, "ssi");
1585
1586 return s;
1587 }
1588
1589 static void strongarm_register_devices(void)
1590 {
1591 sysbus_register_withprop(&strongarm_pic_info);
1592 sysbus_register_withprop(&strongarm_rtc_sysbus_info);
1593 sysbus_register_withprop(&strongarm_gpio_info);
1594 sysbus_register_withprop(&strongarm_ppc_info);
1595 sysbus_register_withprop(&strongarm_uart_info);
1596 sysbus_register_withprop(&strongarm_ssp_info);
1597 }
1598 device_init(strongarm_register_devices)
QEmu