target-arm/helper.c

   1 #include "cpu.h"
   2 #include "internals.h"
   3 #include "exec/gdbstub.h"
   4 #include "exec/helper-proto.h"
   5 #include "qemu/host-utils.h"
   6 #include "sysemu/arch_init.h"
   7 #include "sysemu/sysemu.h"
   8 #include "qemu/bitops.h"
   9 #include "qemu/crc32c.h"
  10 #include "exec/cpu_ldst.h"
  11 #include "arm_ldst.h"
  12 #include <zlib.h> /* For crc32 */
  13
  14 #ifndef CONFIG_USER_ONLY
  15 static inline int get_phys_addr(CPUARMState *env, target_ulong address,
  16                                 int access_type, int is_user,
  17                                 hwaddr *phys_ptr, int *prot,
  18                                 target_ulong *page_size);
  19
  20 /* Definitions for the PMCCNTR and PMCR registers */
  21 #define PMCRD   0x8
  22 #define PMCRC   0x4
  23 #define PMCRE   0x1
  24 #endif
  25
  26 static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
  27 {
  28     int nregs;
  29
  30     /* VFP data registers are always little-endian.  */
  31     nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
  32     if (reg < nregs) {
  33         stfq_le_p(buf, env->vfp.regs[reg]);
  34         return 8;
  35     }
  36     if (arm_feature(env, ARM_FEATURE_NEON)) {
  37         /* Aliases for Q regs.  */
  38         nregs += 16;
  39         if (reg < nregs) {
  40             stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
  41             stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
  42             return 16;
  43         }
  44     }
  45     switch (reg - nregs) {
  46     case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
  47     case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
  48     case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
  49     }
  50     return 0;
  51 }
  52
  53 static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
  54 {
  55     int nregs;
  56
  57     nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
  58     if (reg < nregs) {
  59         env->vfp.regs[reg] = ldfq_le_p(buf);
  60         return 8;
  61     }
  62     if (arm_feature(env, ARM_FEATURE_NEON)) {
  63         nregs += 16;
  64         if (reg < nregs) {
  65             env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
  66             env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
  67             return 16;
  68         }
  69     }
  70     switch (reg - nregs) {
  71     case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
  72     case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
  73     case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
  74     }
  75     return 0;
  76 }
  77
  78 static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
  79 {
  80     switch (reg) {
  81     case 0 ... 31:
  82         /* 128 bit FP register */
  83         stfq_le_p(buf, env->vfp.regs[reg * 2]);
  84         stfq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]);
  85         return 16;
  86     case 32:
  87         /* FPSR */
  88         stl_p(buf, vfp_get_fpsr(env));
  89         return 4;
  90     case 33:
  91         /* FPCR */
  92         stl_p(buf, vfp_get_fpcr(env));
  93         return 4;
  94     default:
  95         return 0;
  96     }
  97 }
  98
  99 static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
 100 {
 101     switch (reg) {
 102     case 0 ... 31:
 103         /* 128 bit FP register */
 104         env->vfp.regs[reg * 2] = ldfq_le_p(buf);
 105         env->vfp.regs[reg * 2 + 1] = ldfq_le_p(buf + 8);
 106         return 16;
 107     case 32:
 108         /* FPSR */
 109         vfp_set_fpsr(env, ldl_p(buf));
 110         return 4;
 111     case 33:
 112         /* FPCR */
 113         vfp_set_fpcr(env, ldl_p(buf));
 114         return 4;
 115     default:
 116         return 0;
 117     }
 118 }
 119
 120 static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri)
 121 {
 122     if (cpreg_field_is_64bit(ri)) {
 123         return CPREG_FIELD64(env, ri);
 124     } else {
 125         return CPREG_FIELD32(env, ri);
 126     }
 127 }
 128
 129 static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
 130                       uint64_t value)
 131 {
 132     if (cpreg_field_is_64bit(ri)) {
 133         CPREG_FIELD64(env, ri) = value;
 134     } else {
 135         CPREG_FIELD32(env, ri) = value;
 136     }
 137 }
 138
 139 static uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri)
 140 {
 141     /* Raw read of a coprocessor register (as needed for migration, etc). */
 142     if (ri->type & ARM_CP_CONST) {
 143         return ri->resetvalue;
 144     } else if (ri->raw_readfn) {
 145         return ri->raw_readfn(env, ri);
 146     } else if (ri->readfn) {
 147         return ri->readfn(env, ri);
 148     } else {
 149         return raw_read(env, ri);
 150     }
 151 }
 152
 153 static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
 154                              uint64_t v)
 155 {
 156     /* Raw write of a coprocessor register (as needed for migration, etc).
 157      * Note that constant registers are treated as write-ignored; the
 158      * caller should check for success by whether a readback gives the
 159      * value written.
 160      */
 161     if (ri->type & ARM_CP_CONST) {
 162         return;
 163     } else if (ri->raw_writefn) {
 164         ri->raw_writefn(env, ri, v);
 165     } else if (ri->writefn) {
 166         ri->writefn(env, ri, v);
 167     } else {
 168         raw_write(env, ri, v);
 169     }
 170 }
 171
 172 bool write_cpustate_to_list(ARMCPU *cpu)
 173 {
 174     /* Write the coprocessor state from cpu->env to the (index,value) list. */
 175     int i;
 176     bool ok = true;
 177
 178     for (i = 0; i < cpu->cpreg_array_len; i++) {
 179         uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
 180         const ARMCPRegInfo *ri;
 181
 182         ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 183         if (!ri) {
 184             ok = false;
 185             continue;
 186         }
 187         if (ri->type & ARM_CP_NO_MIGRATE) {
 188             continue;
 189         }
 190         cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri);
 191     }
 192     return ok;
 193 }
 194
 195 bool write_list_to_cpustate(ARMCPU *cpu)
 196 {
 197     int i;
 198     bool ok = true;
 199
 200     for (i = 0; i < cpu->cpreg_array_len; i++) {
 201         uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
 202         uint64_t v = cpu->cpreg_values[i];
 203         const ARMCPRegInfo *ri;
 204
 205         ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 206         if (!ri) {
 207             ok = false;
 208             continue;
 209         }
 210         if (ri->type & ARM_CP_NO_MIGRATE) {
 211             continue;
 212         }
 213         /* Write value and confirm it reads back as written
 214          * (to catch read-only registers and partially read-only
 215          * registers where the incoming migration value doesn't match)
 216          */
 217         write_raw_cp_reg(&cpu->env, ri, v);
 218         if (read_raw_cp_reg(&cpu->env, ri) != v) {
 219             ok = false;
 220         }
 221     }
 222     return ok;
 223 }
 224
 225 static void add_cpreg_to_list(gpointer key, gpointer opaque)
 226 {
 227     ARMCPU *cpu = opaque;
 228     uint64_t regidx;
 229     const ARMCPRegInfo *ri;
 230
 231     regidx = *(uint32_t *)key;
 232     ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 233
 234     if (!(ri->type & ARM_CP_NO_MIGRATE)) {
 235         cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
 236         /* The value array need not be initialized at this point */
 237         cpu->cpreg_array_len++;
 238     }
 239 }
 240
 241 static void count_cpreg(gpointer key, gpointer opaque)
 242 {
 243     ARMCPU *cpu = opaque;
 244     uint64_t regidx;
 245     const ARMCPRegInfo *ri;
 246
 247     regidx = *(uint32_t *)key;
 248     ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 249
 250     if (!(ri->type & ARM_CP_NO_MIGRATE)) {
 251         cpu->cpreg_array_len++;
 252     }
 253 }
 254
 255 static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
 256 {
 257     uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a);
 258     uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b);
 259
 260     if (aidx > bidx) {
 261         return 1;
 262     }
 263     if (aidx < bidx) {
 264         return -1;
 265     }
 266     return 0;
 267 }
 268
 269 static void cpreg_make_keylist(gpointer key, gpointer value, gpointer udata)
 270 {
 271     GList **plist = udata;
 272
 273     *plist = g_list_prepend(*plist, key);
 274 }
 275
 276 void init_cpreg_list(ARMCPU *cpu)
 277 {
 278     /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
 279      * Note that we require cpreg_tuples[] to be sorted by key ID.
 280      */
 281     GList *keys = NULL;
 282     int arraylen;
 283
 284     g_hash_table_foreach(cpu->cp_regs, cpreg_make_keylist, &keys);
 285
 286     keys = g_list_sort(keys, cpreg_key_compare);
 287
 288     cpu->cpreg_array_len = 0;
 289
 290     g_list_foreach(keys, count_cpreg, cpu);
 291
 292     arraylen = cpu->cpreg_array_len;
 293     cpu->cpreg_indexes = g_new(uint64_t, arraylen);
 294     cpu->cpreg_values = g_new(uint64_t, arraylen);
 295     cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen);
 296     cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen);
 297     cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
 298     cpu->cpreg_array_len = 0;
 299
 300     g_list_foreach(keys, add_cpreg_to_list, cpu);
 301
 302     assert(cpu->cpreg_array_len == arraylen);
 303
 304     g_list_free(keys);
 305 }
 306
 307 /* Return true if extended addresses are enabled.
 308  * This is always the case if our translation regime is 64 bit,
 309  * but depends on TTBCR.EAE for 32 bit.
 310  */
 311 static inline bool extended_addresses_enabled(CPUARMState *env)
 312 {
 313     return arm_el_is_aa64(env, 1)
 314         || ((arm_feature(env, ARM_FEATURE_LPAE)
 315              && (env->cp15.c2_control & TTBCR_EAE)));
 316 }
 317
 318 static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 319 {
 320     ARMCPU *cpu = arm_env_get_cpu(env);
 321
 322     raw_write(env, ri, value);
 323     tlb_flush(CPU(cpu), 1); /* Flush TLB as domain not tracked in TLB */
 324 }
 325
 326 static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 327 {
 328     ARMCPU *cpu = arm_env_get_cpu(env);
 329
 330     if (raw_read(env, ri) != value) {
 331         /* Unlike real hardware the qemu TLB uses virtual addresses,
 332          * not modified virtual addresses, so this causes a TLB flush.
 333          */
 334         tlb_flush(CPU(cpu), 1);
 335         raw_write(env, ri, value);
 336     }
 337 }
 338
 339 static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 340                              uint64_t value)
 341 {
 342     ARMCPU *cpu = arm_env_get_cpu(env);
 343
 344     if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_MPU)
 345         && !extended_addresses_enabled(env)) {
 346         /* For VMSA (when not using the LPAE long descriptor page table
 347          * format) this register includes the ASID, so do a TLB flush.
 348          * For PMSA it is purely a process ID and no action is needed.
 349          */
 350         tlb_flush(CPU(cpu), 1);
 351     }
 352     raw_write(env, ri, value);
 353 }
 354
 355 static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
 356                           uint64_t value)
 357 {
 358     /* Invalidate all (TLBIALL) */
 359     ARMCPU *cpu = arm_env_get_cpu(env);
 360
 361     tlb_flush(CPU(cpu), 1);
 362 }
 363
 364 static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
 365                           uint64_t value)
 366 {
 367     /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
 368     ARMCPU *cpu = arm_env_get_cpu(env);
 369
 370     tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
 371 }
 372
 373 static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
 374                            uint64_t value)
 375 {
 376     /* Invalidate by ASID (TLBIASID) */
 377     ARMCPU *cpu = arm_env_get_cpu(env);
 378
 379     tlb_flush(CPU(cpu), value == 0);
 380 }
 381
 382 static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
 383                            uint64_t value)
 384 {
 385     /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
 386     ARMCPU *cpu = arm_env_get_cpu(env);
 387
 388     tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
 389 }
 390
 391 static const ARMCPRegInfo cp_reginfo[] = {
 392     /* DBGDIDR: just RAZ. In particular this means the "debug architecture
 393      * version" bits will read as a reserved value, which should cause
 394      * Linux to not try to use the debug hardware.
 395      */
 396     { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
 397       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
 398     { .name = "FCSEIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 0,
 399       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
 400       .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
 401     { .name = "CONTEXTIDR", .state = ARM_CP_STATE_BOTH,
 402       .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
 403       .access = PL1_RW,
 404       .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el1),
 405       .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
 406     REGINFO_SENTINEL
 407 };
 408
 409 static const ARMCPRegInfo not_v8_cp_reginfo[] = {
 410     /* NB: Some of these registers exist in v8 but with more precise
 411      * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
 412      */
 413     /* MMU Domain access control / MPU write buffer control */
 414     { .name = "DACR", .cp = 15,
 415       .crn = 3, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
 416       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3),
 417       .resetvalue = 0, .writefn = dacr_write, .raw_writefn = raw_write, },
 418     /* ??? This covers not just the impdef TLB lockdown registers but also
 419      * some v7VMSA registers relating to TEX remap, so it is overly broad.
 420      */
 421     { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = CP_ANY,
 422       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
 423     /* MMU TLB control. Note that the wildcarding means we cover not just
 424      * the unified TLB ops but also the dside/iside/inner-shareable variants.
 425      */
 426     { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
 427       .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write,
 428       .type = ARM_CP_NO_MIGRATE },
 429     { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY,
 430       .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write,
 431       .type = ARM_CP_NO_MIGRATE },
 432     { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY,
 433       .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write,
 434       .type = ARM_CP_NO_MIGRATE },
 435     { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY,
 436       .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write,
 437       .type = ARM_CP_NO_MIGRATE },
 438     /* Cache maintenance ops; some of this space may be overridden later. */
 439     { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
 440       .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
 441       .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
 442     REGINFO_SENTINEL
 443 };
 444
 445 static const ARMCPRegInfo not_v6_cp_reginfo[] = {
 446     /* Not all pre-v6 cores implemented this WFI, so this is slightly
 447      * over-broad.
 448      */
 449     { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
 450       .access = PL1_W, .type = ARM_CP_WFI },
 451     REGINFO_SENTINEL
 452 };
 453
 454 static const ARMCPRegInfo not_v7_cp_reginfo[] = {
 455     /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
 456      * is UNPREDICTABLE; we choose to NOP as most implementations do).
 457      */
 458     { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
 459       .access = PL1_W, .type = ARM_CP_WFI },
 460     /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
 461      * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
 462      * OMAPCP will override this space.
 463      */
 464     { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0,
 465       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data),
 466       .resetvalue = 0 },
 467     { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1,
 468       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn),
 469       .resetvalue = 0 },
 470     /* v6 doesn't have the cache ID registers but Linux reads them anyway */
 471     { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
 472       .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
 473       .resetvalue = 0 },
 474     REGINFO_SENTINEL
 475 };
 476
 477 static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 478                         uint64_t value)
 479 {
 480     uint32_t mask = 0;
 481
 482     /* In ARMv8 most bits of CPACR_EL1 are RES0. */
 483     if (!arm_feature(env, ARM_FEATURE_V8)) {
 484         /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
 485          * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
 486          * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
 487          */
 488         if (arm_feature(env, ARM_FEATURE_VFP)) {
 489             /* VFP coprocessor: cp10 & cp11 [23:20] */
 490             mask |= (1 << 31) | (1 << 30) | (0xf << 20);
 491
 492             if (!arm_feature(env, ARM_FEATURE_NEON)) {
 493                 /* ASEDIS [31] bit is RAO/WI */
 494                 value |= (1 << 31);
 495             }
 496
 497             /* VFPv3 and upwards with NEON implement 32 double precision
 498              * registers (D0-D31).
 499              */
 500             if (!arm_feature(env, ARM_FEATURE_NEON) ||
 501                     !arm_feature(env, ARM_FEATURE_VFP3)) {
 502                 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
 503                 value |= (1 << 30);
 504             }
 505         }
 506         value &= mask;
 507     }
 508     env->cp15.c1_coproc = value;
 509 }
 510
 511 static const ARMCPRegInfo v6_cp_reginfo[] = {
 512     /* prefetch by MVA in v6, NOP in v7 */
 513     { .name = "MVA_prefetch",
 514       .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
 515       .access = PL1_W, .type = ARM_CP_NOP },
 516     { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
 517       .access = PL0_W, .type = ARM_CP_NOP },
 518     { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
 519       .access = PL0_W, .type = ARM_CP_NOP },
 520     { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
 521       .access = PL0_W, .type = ARM_CP_NOP },
 522     { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
 523       .access = PL1_RW,
 524       .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[1]),
 525       .resetvalue = 0, },
 526     /* Watchpoint Fault Address Register : should actually only be present
 527      * for 1136, 1176, 11MPCore.
 528      */
 529     { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 530       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
 531     { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
 532       .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2,
 533       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_coproc),
 534       .resetvalue = 0, .writefn = cpacr_write },
 535     REGINFO_SENTINEL
 536 };
 537
 538 static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri)
 539 {
 540     /* Performance monitor registers user accessibility is controlled
 541      * by PMUSERENR.
 542      */
 543     if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
 544         return CP_ACCESS_TRAP;
 545     }
 546     return CP_ACCESS_OK;
 547 }
 548
 549 #ifndef CONFIG_USER_ONLY
 550 static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 551                        uint64_t value)
 552 {
 553     /* Don't computer the number of ticks in user mode */
 554     uint32_t temp_ticks;
 555
 556     temp_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) *
 557                   get_ticks_per_sec() / 1000000;
 558
 559     if (env->cp15.c9_pmcr & PMCRE) {
 560         /* If the counter is enabled */
 561         if (env->cp15.c9_pmcr & PMCRD) {
 562             /* Increment once every 64 processor clock cycles */
 563             env->cp15.c15_ccnt = (temp_ticks/64) - env->cp15.c15_ccnt;
 564         } else {
 565             env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
 566         }
 567     }
 568
 569     if (value & PMCRC) {
 570         /* The counter has been reset */
 571         env->cp15.c15_ccnt = 0;
 572     }
 573
 574     /* only the DP, X, D and E bits are writable */
 575     env->cp15.c9_pmcr &= ~0x39;
 576     env->cp15.c9_pmcr |= (value & 0x39);
 577
 578     if (env->cp15.c9_pmcr & PMCRE) {
 579         if (env->cp15.c9_pmcr & PMCRD) {
 580             /* Increment once every 64 processor clock cycles */
 581             temp_ticks /= 64;
 582         }
 583         env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
 584     }
 585 }
 586
 587 static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 588 {
 589     uint32_t total_ticks;
 590
 591     if (!(env->cp15.c9_pmcr & PMCRE)) {
 592         /* Counter is disabled, do not change value */
 593         return env->cp15.c15_ccnt;
 594     }
 595
 596     total_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) *
 597                   get_ticks_per_sec() / 1000000;
 598
 599     if (env->cp15.c9_pmcr & PMCRD) {
 600         /* Increment once every 64 processor clock cycles */
 601         total_ticks /= 64;
 602     }
 603     return total_ticks - env->cp15.c15_ccnt;
 604 }
 605
 606 static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 607                         uint64_t value)
 608 {
 609     uint32_t total_ticks;
 610
 611     if (!(env->cp15.c9_pmcr & PMCRE)) {
 612         /* Counter is disabled, set the absolute value */
 613         env->cp15.c15_ccnt = value;
 614         return;
 615     }
 616
 617     total_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) *
 618                   get_ticks_per_sec() / 1000000;
 619
 620     if (env->cp15.c9_pmcr & PMCRD) {
 621         /* Increment once every 64 processor clock cycles */
 622         total_ticks /= 64;
 623     }
 624     env->cp15.c15_ccnt = total_ticks - value;
 625 }
 626 #endif
 627
 628 static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
 629                             uint64_t value)
 630 {
 631     value &= (1 << 31);
 632     env->cp15.c9_pmcnten |= value;
 633 }
 634
 635 static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 636                              uint64_t value)
 637 {
 638     value &= (1 << 31);
 639     env->cp15.c9_pmcnten &= ~value;
 640 }
 641
 642 static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 643                          uint64_t value)
 644 {
 645     env->cp15.c9_pmovsr &= ~value;
 646 }
 647
 648 static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
 649                              uint64_t value)
 650 {
 651     env->cp15.c9_pmxevtyper = value & 0xff;
 652 }
 653
 654 static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 655                             uint64_t value)
 656 {
 657     env->cp15.c9_pmuserenr = value & 1;
 658 }
 659
 660 static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
 661                              uint64_t value)
 662 {
 663     /* We have no event counters so only the C bit can be changed */
 664     value &= (1 << 31);
 665     env->cp15.c9_pminten |= value;
 666 }
 667
 668 static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 669                              uint64_t value)
 670 {
 671     value &= (1 << 31);
 672     env->cp15.c9_pminten &= ~value;
 673 }
 674
 675 static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
 676                        uint64_t value)
 677 {
 678     /* Note that even though the AArch64 view of this register has bits
 679      * [10:0] all RES0 we can only mask the bottom 5, to comply with the
 680      * architectural requirements for bits which are RES0 only in some
 681      * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
 682      * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
 683      */
 684     raw_write(env, ri, value & ~0x1FULL);
 685 }
 686
 687 static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 688 {
 689     ARMCPU *cpu = arm_env_get_cpu(env);
 690     return cpu->ccsidr[env->cp15.c0_cssel];
 691 }
 692
 693 static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 694                          uint64_t value)
 695 {
 696     raw_write(env, ri, value & 0xf);
 697 }
 698
 699 static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 700 {
 701     CPUState *cs = ENV_GET_CPU(env);
 702     uint64_t ret = 0;
 703
 704     if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
 705         ret |= CPSR_I;
 706     }
 707     if (cs->interrupt_request & CPU_INTERRUPT_FIQ) {
 708         ret |= CPSR_F;
 709     }
 710     /* External aborts are not possible in QEMU so A bit is always clear */
 711     return ret;
 712 }
 713
 714 static const ARMCPRegInfo v7_cp_reginfo[] = {
 715     /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
 716      * debug components
 717      */
 718     { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
 719       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
 720     { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
 721       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
 722     /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
 723     { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
 724       .access = PL1_W, .type = ARM_CP_NOP },
 725     /* Performance monitors are implementation defined in v7,
 726      * but with an ARM recommended set of registers, which we
 727      * follow (although we don't actually implement any counters)
 728      *
 729      * Performance registers fall into three categories:
 730      *  (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
 731      *  (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
 732      *  (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
 733      * For the cases controlled by PMUSERENR we must set .access to PL0_RW
 734      * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
 735      */
 736     { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
 737       .access = PL0_RW, .resetvalue = 0,
 738       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
 739       .writefn = pmcntenset_write,
 740       .accessfn = pmreg_access,
 741       .raw_writefn = raw_write },
 742     { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
 743       .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
 744       .accessfn = pmreg_access,
 745       .writefn = pmcntenclr_write,
 746       .type = ARM_CP_NO_MIGRATE },
 747     { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
 748       .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
 749       .accessfn = pmreg_access,
 750       .writefn = pmovsr_write,
 751       .raw_writefn = raw_write },
 752     /* Unimplemented so WI. */
 753     { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
 754       .access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP },
 755     /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
 756      * We choose to RAZ/WI.
 757      */
 758     { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
 759       .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
 760       .accessfn = pmreg_access },
 761 #ifndef CONFIG_USER_ONLY
 762     { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
 763       .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO,
 764       .readfn = pmccntr_read, .writefn = pmccntr_write,
 765       .accessfn = pmreg_access },
 766 #endif
 767     { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
 768       .access = PL0_RW,
 769       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
 770       .accessfn = pmreg_access, .writefn = pmxevtyper_write,
 771       .raw_writefn = raw_write },
 772     /* Unimplemented, RAZ/WI. */
 773     { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
 774       .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
 775       .accessfn = pmreg_access },
 776     { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
 777       .access = PL0_R | PL1_RW,
 778       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
 779       .resetvalue = 0,
 780       .writefn = pmuserenr_write, .raw_writefn = raw_write },
 781     { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
 782       .access = PL1_RW,
 783       .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
 784       .resetvalue = 0,
 785       .writefn = pmintenset_write, .raw_writefn = raw_write },
 786     { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
 787       .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
 788       .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
 789       .resetvalue = 0, .writefn = pmintenclr_write, },
 790     { .name = "VBAR", .state = ARM_CP_STATE_BOTH,
 791       .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
 792       .access = PL1_RW, .writefn = vbar_write,
 793       .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[1]),
 794       .resetvalue = 0 },
 795     { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
 796       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr),
 797       .resetvalue = 0, },
 798     { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
 799       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
 800       .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE },
 801     { .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
 802       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
 803       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c0_cssel),
 804       .writefn = csselr_write, .resetvalue = 0 },
 805     /* Auxiliary ID register: this actually has an IMPDEF value but for now
 806      * just RAZ for all cores:
 807      */
 808     { .name = "AIDR", .state = ARM_CP_STATE_BOTH,
 809       .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7,
 810       .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
 811     /* Auxiliary fault status registers: these also are IMPDEF, and we
 812      * choose to RAZ/WI for all cores.
 813      */
 814     { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH,
 815       .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0,
 816       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 817     { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH,
 818       .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1,
 819       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 820     /* MAIR can just read-as-written because we don't implement caches
 821      * and so don't need to care about memory attributes.
 822      */
 823     { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64,
 824       .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0,
 825       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el1),
 826       .resetvalue = 0 },
 827     /* For non-long-descriptor page tables these are PRRR and NMRR;
 828      * regardless they still act as reads-as-written for QEMU.
 829      * The override is necessary because of the overly-broad TLB_LOCKDOWN
 830      * definition.
 831      */
 832     { .name = "MAIR0", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE,
 833       .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW,
 834       .fieldoffset = offsetoflow32(CPUARMState, cp15.mair_el1),
 835       .resetfn = arm_cp_reset_ignore },
 836     { .name = "MAIR1", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE,
 837       .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW,
 838       .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el1),
 839       .resetfn = arm_cp_reset_ignore },
 840     { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH,
 841       .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0,
 842       .type = ARM_CP_NO_MIGRATE, .access = PL1_R, .readfn = isr_read },
 843     REGINFO_SENTINEL
 844 };
 845
 846 static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 847                         uint64_t value)
 848 {
 849     value &= 1;
 850     env->teecr = value;
 851 }
 852
 853 static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri)
 854 {
 855     if (arm_current_pl(env) == 0 && (env->teecr & 1)) {
 856         return CP_ACCESS_TRAP;
 857     }
 858     return CP_ACCESS_OK;
 859 }
 860
 861 static const ARMCPRegInfo t2ee_cp_reginfo[] = {
 862     { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
 863       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
 864       .resetvalue = 0,
 865       .writefn = teecr_write },
 866     { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
 867       .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
 868       .accessfn = teehbr_access, .resetvalue = 0 },
 869     REGINFO_SENTINEL
 870 };
 871
 872 static const ARMCPRegInfo v6k_cp_reginfo[] = {
 873     { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64,
 874       .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0,
 875       .access = PL0_RW,
 876       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el0), .resetvalue = 0 },
 877     { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
 878       .access = PL0_RW,
 879       .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidr_el0),
 880       .resetfn = arm_cp_reset_ignore },
 881     { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64,
 882       .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
 883       .access = PL0_R|PL1_W,
 884       .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el0), .resetvalue = 0 },
 885     { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
 886       .access = PL0_R|PL1_W,
 887       .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidrro_el0),
 888       .resetfn = arm_cp_reset_ignore },
 889     { .name = "TPIDR_EL1", .state = ARM_CP_STATE_BOTH,
 890       .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0,
 891       .access = PL1_RW,
 892       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el1), .resetvalue = 0 },
 893     REGINFO_SENTINEL
 894 };
 895
 896 #ifndef CONFIG_USER_ONLY
 897
 898 static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri)
 899 {
 900     /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero */
 901     if (arm_current_pl(env) == 0 && !extract32(env->cp15.c14_cntkctl, 0, 2)) {
 902         return CP_ACCESS_TRAP;
 903     }
 904     return CP_ACCESS_OK;
 905 }
 906
 907 static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx)
 908 {
 909     /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
 910     if (arm_current_pl(env) == 0 &&
 911         !extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
 912         return CP_ACCESS_TRAP;
 913     }
 914     return CP_ACCESS_OK;
 915 }
 916
 917 static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx)
 918 {
 919     /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
 920      * EL0[PV]TEN is zero.
 921      */
 922     if (arm_current_pl(env) == 0 &&
 923         !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
 924         return CP_ACCESS_TRAP;
 925     }
 926     return CP_ACCESS_OK;
 927 }
 928
 929 static CPAccessResult gt_pct_access(CPUARMState *env,
 930                                          const ARMCPRegInfo *ri)
 931 {
 932     return gt_counter_access(env, GTIMER_PHYS);
 933 }
 934
 935 static CPAccessResult gt_vct_access(CPUARMState *env,
 936                                          const ARMCPRegInfo *ri)
 937 {
 938     return gt_counter_access(env, GTIMER_VIRT);
 939 }
 940
 941 static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri)
 942 {
 943     return gt_timer_access(env, GTIMER_PHYS);
 944 }
 945
 946 static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri)
 947 {
 948     return gt_timer_access(env, GTIMER_VIRT);
 949 }
 950
 951 static uint64_t gt_get_countervalue(CPUARMState *env)
 952 {
 953     return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE;
 954 }
 955
 956 static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
 957 {
 958     ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
 959
 960     if (gt->ctl & 1) {
 961         /* Timer enabled: calculate and set current ISTATUS, irq, and
 962          * reset timer to when ISTATUS next has to change
 963          */
 964         uint64_t count = gt_get_countervalue(&cpu->env);
 965         /* Note that this must be unsigned 64 bit arithmetic: */
 966         int istatus = count >= gt->cval;
 967         uint64_t nexttick;
 968
 969         gt->ctl = deposit32(gt->ctl, 2, 1, istatus);
 970         qemu_set_irq(cpu->gt_timer_outputs[timeridx],
 971                      (istatus && !(gt->ctl & 2)));
 972         if (istatus) {
 973             /* Next transition is when count rolls back over to zero */
 974             nexttick = UINT64_MAX;
 975         } else {
 976             /* Next transition is when we hit cval */
 977             nexttick = gt->cval;
 978         }
 979         /* Note that the desired next expiry time might be beyond the
 980          * signed-64-bit range of a QEMUTimer -- in this case we just
 981          * set the timer for as far in the future as possible. When the
 982          * timer expires we will reset the timer for any remaining period.
 983          */
 984         if (nexttick > INT64_MAX / GTIMER_SCALE) {
 985             nexttick = INT64_MAX / GTIMER_SCALE;
 986         }
 987         timer_mod(cpu->gt_timer[timeridx], nexttick);
 988     } else {
 989         /* Timer disabled: ISTATUS and timer output always clear */
 990         gt->ctl &= ~4;
 991         qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0);
 992         timer_del(cpu->gt_timer[timeridx]);
 993     }
 994 }
 995
 996 static void gt_cnt_reset(CPUARMState *env, const ARMCPRegInfo *ri)
 997 {
 998     ARMCPU *cpu = arm_env_get_cpu(env);
 999     int timeridx = ri->opc1 & 1;
1000
1001     timer_del(cpu->gt_timer[timeridx]);
1002 }
1003
1004 static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
1005 {
1006     return gt_get_countervalue(env);
1007 }
1008
1009 static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1010                           uint64_t value)
1011 {
1012     int timeridx = ri->opc1 & 1;
1013
1014     env->cp15.c14_timer[timeridx].cval = value;
1015     gt_recalc_timer(arm_env_get_cpu(env), timeridx);
1016 }
1017
1018 static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1019 {
1020     int timeridx = ri->crm & 1;
1021
1022     return (uint32_t)(env->cp15.c14_timer[timeridx].cval -
1023                       gt_get_countervalue(env));
1024 }
1025
1026 static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1027                           uint64_t value)
1028 {
1029     int timeridx = ri->crm & 1;
1030
1031     env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) +
1032         + sextract64(value, 0, 32);
1033     gt_recalc_timer(arm_env_get_cpu(env), timeridx);
1034 }
1035
1036 static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1037                          uint64_t value)
1038 {
1039     ARMCPU *cpu = arm_env_get_cpu(env);
1040     int timeridx = ri->crm & 1;
1041     uint32_t oldval = env->cp15.c14_timer[timeridx].ctl;
1042
1043     env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value);
1044     if ((oldval ^ value) & 1) {
1045         /* Enable toggled */
1046         gt_recalc_timer(cpu, timeridx);
1047     } else if ((oldval ^ value) & 2) {
1048         /* IMASK toggled: don't need to recalculate,
1049          * just set the interrupt line based on ISTATUS
1050          */
1051         qemu_set_irq(cpu->gt_timer_outputs[timeridx],
1052                      (oldval & 4) && !(value & 2));
1053     }
1054 }
1055
1056 void arm_gt_ptimer_cb(void *opaque)
1057 {
1058     ARMCPU *cpu = opaque;
1059
1060     gt_recalc_timer(cpu, GTIMER_PHYS);
1061 }
1062
1063 void arm_gt_vtimer_cb(void *opaque)
1064 {
1065     ARMCPU *cpu = opaque;
1066
1067     gt_recalc_timer(cpu, GTIMER_VIRT);
1068 }
1069
1070 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1071     /* Note that CNTFRQ is purely reads-as-written for the benefit
1072      * of software; writing it doesn't actually change the timer frequency.
1073      * Our reset value matches the fixed frequency we implement the timer at.
1074      */
1075     { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0,
1076       .type = ARM_CP_NO_MIGRATE,
1077       .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
1078       .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq),
1079       .resetfn = arm_cp_reset_ignore,
1080     },
1081     { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64,
1082       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0,
1083       .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
1084       .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq),
1085       .resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE,
1086     },
1087     /* overall control: mostly access permissions */
1088     { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH,
1089       .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0,
1090       .access = PL1_RW,
1091       .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl),
1092       .resetvalue = 0,
1093     },
1094     /* per-timer control */
1095     { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
1096       .type = ARM_CP_IO | ARM_CP_NO_MIGRATE, .access = PL1_RW | PL0_R,
1097       .accessfn = gt_ptimer_access,
1098       .fieldoffset = offsetoflow32(CPUARMState,
1099                                    cp15.c14_timer[GTIMER_PHYS].ctl),
1100       .resetfn = arm_cp_reset_ignore,
1101       .writefn = gt_ctl_write, .raw_writefn = raw_write,
1102     },
1103     { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64,
1104       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1,
1105       .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1106       .accessfn = gt_ptimer_access,
1107       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
1108       .resetvalue = 0,
1109       .writefn = gt_ctl_write, .raw_writefn = raw_write,
1110     },
1111     { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1,
1112       .type = ARM_CP_IO | ARM_CP_NO_MIGRATE, .access = PL1_RW | PL0_R,
1113       .accessfn = gt_vtimer_access,
1114       .fieldoffset = offsetoflow32(CPUARMState,
1115                                    cp15.c14_timer[GTIMER_VIRT].ctl),
1116       .resetfn = arm_cp_reset_ignore,
1117       .writefn = gt_ctl_write, .raw_writefn = raw_write,
1118     },
1119     { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64,
1120       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1,
1121       .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1122       .accessfn = gt_vtimer_access,
1123       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
1124       .resetvalue = 0,
1125       .writefn = gt_ctl_write, .raw_writefn = raw_write,
1126     },
1127     /* TimerValue views: a 32 bit downcounting view of the underlying state */
1128     { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
1129       .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
1130       .accessfn = gt_ptimer_access,
1131       .readfn = gt_tval_read, .writefn = gt_tval_write,
1132     },
1133     { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64,
1134       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0,
1135       .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
1136       .readfn = gt_tval_read, .writefn = gt_tval_write,
1137     },
1138     { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0,
1139       .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
1140       .accessfn = gt_vtimer_access,
1141       .readfn = gt_tval_read, .writefn = gt_tval_write,
1142     },
1143     { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64,
1144       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0,
1145       .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
1146       .readfn = gt_tval_read, .writefn = gt_tval_write,
1147     },
1148     /* The counter itself */
1149     { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0,
1150       .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO,
1151       .accessfn = gt_pct_access,
1152       .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
1153     },
1154     { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64,
1155       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1,
1156       .access = PL0_R, .type = ARM_CP_NO_MIGRATE | ARM_CP_IO,
1157       .accessfn = gt_pct_access,
1158       .readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
1159     },
1160     { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1,
1161       .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO,
1162       .accessfn = gt_vct_access,
1163       .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
1164     },
1165     { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64,
1166       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2,
1167       .access = PL0_R, .type = ARM_CP_NO_MIGRATE | ARM_CP_IO,
1168       .accessfn = gt_vct_access,
1169       .readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
1170     },
1171     /* Comparison value, indicating when the timer goes off */
1172     { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2,
1173       .access = PL1_RW | PL0_R,
1174       .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_MIGRATE,
1175       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1176       .accessfn = gt_ptimer_access, .resetfn = arm_cp_reset_ignore,
1177       .writefn = gt_cval_write, .raw_writefn = raw_write,
1178     },
1179     { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64,
1180       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2,
1181       .access = PL1_RW | PL0_R,
1182       .type = ARM_CP_IO,
1183       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1184       .resetvalue = 0, .accessfn = gt_vtimer_access,
1185       .writefn = gt_cval_write, .raw_writefn = raw_write,
1186     },
1187     { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3,
1188       .access = PL1_RW | PL0_R,
1189       .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_MIGRATE,
1190       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1191       .accessfn = gt_vtimer_access, .resetfn = arm_cp_reset_ignore,
1192       .writefn = gt_cval_write, .raw_writefn = raw_write,
1193     },
1194     { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64,
1195       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2,
1196       .access = PL1_RW | PL0_R,
1197       .type = ARM_CP_IO,
1198       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1199       .resetvalue = 0, .accessfn = gt_vtimer_access,
1200       .writefn = gt_cval_write, .raw_writefn = raw_write,
1201     },
1202     REGINFO_SENTINEL
1203 };
1204
1205 #else
1206 /* In user-mode none of the generic timer registers are accessible,
1207  * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs,
1208  * so instead just don't register any of them.
1209  */
1210 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1211     REGINFO_SENTINEL
1212 };
1213
1214 #endif
1215
1216 static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1217 {
1218     if (arm_feature(env, ARM_FEATURE_LPAE)) {
1219         raw_write(env, ri, value);
1220     } else if (arm_feature(env, ARM_FEATURE_V7)) {
1221         raw_write(env, ri, value & 0xfffff6ff);
1222     } else {
1223         raw_write(env, ri, value & 0xfffff1ff);
1224     }
1225 }
1226
1227 #ifndef CONFIG_USER_ONLY
1228 /* get_phys_addr() isn't present for user-mode-only targets */
1229
1230 static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri)
1231 {
1232     if (ri->opc2 & 4) {
1233         /* Other states are only available with TrustZone; in
1234          * a non-TZ implementation these registers don't exist
1235          * at all, which is an Uncategorized trap. This underdecoding
1236          * is safe because the reginfo is NO_MIGRATE.
1237          */
1238         return CP_ACCESS_TRAP_UNCATEGORIZED;
1239     }
1240     return CP_ACCESS_OK;
1241 }
1242
1243 static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1244 {
1245     hwaddr phys_addr;
1246     target_ulong page_size;
1247     int prot;
1248     int ret, is_user = ri->opc2 & 2;
1249     int access_type = ri->opc2 & 1;
1250
1251     ret = get_phys_addr(env, value, access_type, is_user,
1252                         &phys_addr, &prot, &page_size);
1253     if (extended_addresses_enabled(env)) {
1254         /* ret is a DFSR/IFSR value for the long descriptor
1255          * translation table format, but with WnR always clear.
1256          * Convert it to a 64-bit PAR.
1257          */
1258         uint64_t par64 = (1 << 11); /* LPAE bit always set */
1259         if (ret == 0) {
1260             par64 |= phys_addr & ~0xfffULL;
1261             /* We don't set the ATTR or SH fields in the PAR. */
1262         } else {
1263             par64 |= 1; /* F */
1264             par64 |= (ret & 0x3f) << 1; /* FS */
1265             /* Note that S2WLK and FSTAGE are always zero, because we don't
1266              * implement virtualization and therefore there can't be a stage 2
1267              * fault.
1268              */
1269         }
1270         env->cp15.par_el1 = par64;
1271     } else {
1272         /* ret is a DFSR/IFSR value for the short descriptor
1273          * translation table format (with WnR always clear).
1274          * Convert it to a 32-bit PAR.
1275          */
1276         if (ret == 0) {
1277             /* We do not set any attribute bits in the PAR */
1278             if (page_size == (1 << 24)
1279                 && arm_feature(env, ARM_FEATURE_V7)) {
1280                 env->cp15.par_el1 = (phys_addr & 0xff000000) | 1 << 1;
1281             } else {
1282                 env->cp15.par_el1 = phys_addr & 0xfffff000;
1283             }
1284         } else {
1285             env->cp15.par_el1 = ((ret & (1 << 10)) >> 5) |
1286                 ((ret & (1 << 12)) >> 6) |
1287                 ((ret & 0xf) << 1) | 1;
1288         }
1289     }
1290 }
1291 #endif
1292
1293 static const ARMCPRegInfo vapa_cp_reginfo[] = {
1294     { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
1295       .access = PL1_RW, .resetvalue = 0,
1296       .fieldoffset = offsetoflow32(CPUARMState, cp15.par_el1),
1297       .writefn = par_write },
1298 #ifndef CONFIG_USER_ONLY
1299     { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
1300       .access = PL1_W, .accessfn = ats_access,
1301       .writefn = ats_write, .type = ARM_CP_NO_MIGRATE },
1302 #endif
1303     REGINFO_SENTINEL
1304 };
1305
1306 /* Return basic MPU access permission bits.  */
1307 static uint32_t simple_mpu_ap_bits(uint32_t val)
1308 {
1309     uint32_t ret;
1310     uint32_t mask;
1311     int i;
1312     ret = 0;
1313     mask = 3;
1314     for (i = 0; i < 16; i += 2) {
1315         ret |= (val >> i) & mask;
1316         mask <<= 2;
1317     }
1318     return ret;
1319 }
1320
1321 /* Pad basic MPU access permission bits to extended format.  */
1322 static uint32_t extended_mpu_ap_bits(uint32_t val)
1323 {
1324     uint32_t ret;
1325     uint32_t mask;
1326     int i;
1327     ret = 0;
1328     mask = 3;
1329     for (i = 0; i < 16; i += 2) {
1330         ret |= (val & mask) << i;
1331         mask <<= 2;
1332     }
1333     return ret;
1334 }
1335
1336 static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
1337                                  uint64_t value)
1338 {
1339     env->cp15.pmsav5_data_ap = extended_mpu_ap_bits(value);
1340 }
1341
1342 static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
1343 {
1344     return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap);
1345 }
1346
1347 static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
1348                                  uint64_t value)
1349 {
1350     env->cp15.pmsav5_insn_ap = extended_mpu_ap_bits(value);
1351 }
1352
1353 static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
1354 {
1355     return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap);
1356 }
1357
1358 static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
1359     { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
1360       .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
1361       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
1362       .resetvalue = 0,
1363       .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
1364     { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
1365       .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
1366       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
1367       .resetvalue = 0,
1368       .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
1369     { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
1370       .access = PL1_RW,
1371       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
1372       .resetvalue = 0, },
1373     { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
1374       .access = PL1_RW,
1375       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
1376       .resetvalue = 0, },
1377     { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
1378       .access = PL1_RW,
1379       .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
1380     { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
1381       .access = PL1_RW,
1382       .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
1383     /* Protection region base and size registers */
1384     { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0,
1385       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1386       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) },
1387     { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0,
1388       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1389       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) },
1390     { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0,
1391       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1392       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) },
1393     { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0,
1394       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1395       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) },
1396     { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0,
1397       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1398       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) },
1399     { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0,
1400       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1401       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) },
1402     { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0,
1403       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1404       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) },
1405     { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0,
1406       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1407       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) },
1408     REGINFO_SENTINEL
1409 };
1410
1411 static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
1412                                  uint64_t value)
1413 {
1414     int maskshift = extract32(value, 0, 3);
1415
1416     if (!arm_feature(env, ARM_FEATURE_V8)) {
1417         if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) {
1418             /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
1419              * using Long-desciptor translation table format */
1420             value &= ~((7 << 19) | (3 << 14) | (0xf << 3));
1421         } else if (arm_feature(env, ARM_FEATURE_EL3)) {
1422             /* In an implementation that includes the Security Extensions
1423              * TTBCR has additional fields PD0 [4] and PD1 [5] for
1424              * Short-descriptor translation table format.
1425              */
1426             value &= TTBCR_PD1 | TTBCR_PD0 | TTBCR_N;
1427         } else {
1428             value &= TTBCR_N;
1429         }
1430     }
1431
1432     /* Note that we always calculate c2_mask and c2_base_mask, but
1433      * they are only used for short-descriptor tables (ie if EAE is 0);
1434      * for long-descriptor tables the TTBCR fields are used differently
1435      * and the c2_mask and c2_base_mask values are meaningless.
1436      */
1437     raw_write(env, ri, value);
1438     env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> maskshift);
1439     env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> maskshift);
1440 }
1441
1442 static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1443                              uint64_t value)
1444 {
1445     ARMCPU *cpu = arm_env_get_cpu(env);
1446
1447     if (arm_feature(env, ARM_FEATURE_LPAE)) {
1448         /* With LPAE the TTBCR could result in a change of ASID
1449          * via the TTBCR.A1 bit, so do a TLB flush.
1450          */
1451         tlb_flush(CPU(cpu), 1);
1452     }
1453     vmsa_ttbcr_raw_write(env, ri, value);
1454 }
1455
1456 static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1457 {
1458     env->cp15.c2_base_mask = 0xffffc000u;
1459     raw_write(env, ri, 0);
1460     env->cp15.c2_mask = 0;
1461 }
1462
1463 static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
1464                                uint64_t value)
1465 {
1466     ARMCPU *cpu = arm_env_get_cpu(env);
1467
1468     /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
1469     tlb_flush(CPU(cpu), 1);
1470     raw_write(env, ri, value);
1471 }
1472
1473 static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1474                             uint64_t value)
1475 {
1476     /* 64 bit accesses to the TTBRs can change the ASID and so we
1477      * must flush the TLB.
1478      */
1479     if (cpreg_field_is_64bit(ri)) {
1480         ARMCPU *cpu = arm_env_get_cpu(env);
1481
1482         tlb_flush(CPU(cpu), 1);
1483     }
1484     raw_write(env, ri, value);
1485 }
1486
1487 static const ARMCPRegInfo vmsa_cp_reginfo[] = {
1488     { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
1489       .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
1490       .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]),
1491       .resetfn = arm_cp_reset_ignore, },
1492     { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
1493       .access = PL1_RW,
1494       .fieldoffset = offsetof(CPUARMState, cp15.ifsr_el2), .resetvalue = 0, },
1495     { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64,
1496       .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0,
1497       .access = PL1_RW,
1498       .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, },
1499     { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
1500       .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
1501       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el1),
1502       .writefn = vmsa_ttbr_write, .resetvalue = 0 },
1503     { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH,
1504       .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
1505       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el1),
1506       .writefn = vmsa_ttbr_write, .resetvalue = 0 },
1507     { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64,
1508       .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
1509       .access = PL1_RW, .writefn = vmsa_tcr_el1_write,
1510       .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
1511       .fieldoffset = offsetof(CPUARMState, cp15.c2_control) },
1512     { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
1513       .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, .writefn = vmsa_ttbcr_write,
1514       .resetfn = arm_cp_reset_ignore, .raw_writefn = vmsa_ttbcr_raw_write,
1515       .fieldoffset = offsetoflow32(CPUARMState, cp15.c2_control) },
1516     /* 64-bit FAR; this entry also gives us the AArch32 DFAR */
1517     { .name = "FAR_EL1", .state = ARM_CP_STATE_BOTH,
1518       .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
1519       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]),
1520       .resetvalue = 0, },
1521     REGINFO_SENTINEL
1522 };
1523
1524 static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
1525                                 uint64_t value)
1526 {
1527     env->cp15.c15_ticonfig = value & 0xe7;
1528     /* The OS_TYPE bit in this register changes the reported CPUID! */
1529     env->cp15.c0_cpuid = (value & (1 << 5)) ?
1530         ARM_CPUID_TI915T : ARM_CPUID_TI925T;
1531 }
1532
1533 static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,
1534                                 uint64_t value)
1535 {
1536     env->cp15.c15_threadid = value & 0xffff;
1537 }
1538
1539 static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
1540                            uint64_t value)
1541 {
1542     /* Wait-for-interrupt (deprecated) */
1543     cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT);
1544 }
1545
1546 static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
1547                                   uint64_t value)
1548 {
1549     /* On OMAP there are registers indicating the max/min index of dcache lines
1550      * containing a dirty line; cache flush operations have to reset these.
1551      */
1552     env->cp15.c15_i_max = 0x000;
1553     env->cp15.c15_i_min = 0xff0;
1554 }
1555
1556 static const ARMCPRegInfo omap_cp_reginfo[] = {
1557     { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
1558       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
1559       .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]),
1560       .resetvalue = 0, },
1561     { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
1562       .access = PL1_RW, .type = ARM_CP_NOP },
1563     { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
1564       .access = PL1_RW,
1565       .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
1566       .writefn = omap_ticonfig_write },
1567     { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,
1568       .access = PL1_RW,
1569       .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
1570     { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
1571       .access = PL1_RW, .resetvalue = 0xff0,
1572       .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },
1573     { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,
1574       .access = PL1_RW,
1575       .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
1576       .writefn = omap_threadid_write },
1577     { .name = "TI925T_STATUS", .cp = 15, .crn = 15,
1578       .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
1579       .type = ARM_CP_NO_MIGRATE,
1580       .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
1581     /* TODO: Peripheral port remap register:
1582      * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
1583      * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
1584      * when MMU is off.
1585      */
1586     { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
1587       .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
1588       .type = ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE,
1589       .writefn = omap_cachemaint_write },
1590     { .name = "C9", .cp = 15, .crn = 9,
1591       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
1592       .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
1593     REGINFO_SENTINEL
1594 };
1595
1596 static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
1597                               uint64_t value)
1598 {
1599     value &= 0x3fff;
1600     if (env->cp15.c15_cpar != value) {
1601         /* Changes cp0 to cp13 behavior, so needs a TB flush.  */
1602         tb_flush(env);
1603         env->cp15.c15_cpar = value;
1604     }
1605 }
1606
1607 static const ARMCPRegInfo xscale_cp_reginfo[] = {
1608     { .name = "XSCALE_CPAR",
1609       .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
1610       .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
1611       .writefn = xscale_cpar_write, },
1612     { .name = "XSCALE_AUXCR",
1613       .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
1614       .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
1615       .resetvalue = 0, },
1616     /* XScale specific cache-lockdown: since we have no cache we NOP these
1617      * and hope the guest does not really rely on cache behaviour.
1618      */
1619     { .name = "XSCALE_LOCK_ICACHE_LINE",
1620       .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
1621       .access = PL1_W, .type = ARM_CP_NOP },
1622     { .name = "XSCALE_UNLOCK_ICACHE",
1623       .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
1624       .access = PL1_W, .type = ARM_CP_NOP },
1625     { .name = "XSCALE_DCACHE_LOCK",
1626       .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 0,
1627       .access = PL1_RW, .type = ARM_CP_NOP },
1628     { .name = "XSCALE_UNLOCK_DCACHE",
1629       .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1,
1630       .access = PL1_W, .type = ARM_CP_NOP },
1631     REGINFO_SENTINEL
1632 };
1633
1634 static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
1635     /* RAZ/WI the whole crn=15 space, when we don't have a more specific
1636      * implementation of this implementation-defined space.
1637      * Ideally this should eventually disappear in favour of actually
1638      * implementing the correct behaviour for all cores.
1639      */
1640     { .name = "C15_IMPDEF", .cp = 15, .crn = 15,
1641       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
1642       .access = PL1_RW,
1643       .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE | ARM_CP_OVERRIDE,
1644       .resetvalue = 0 },
1645     REGINFO_SENTINEL
1646 };
1647
1648 static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
1649     /* Cache status: RAZ because we have no cache so it's always clean */
1650     { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
1651       .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1652       .resetvalue = 0 },
1653     REGINFO_SENTINEL
1654 };
1655
1656 static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
1657     /* We never have a a block transfer operation in progress */
1658     { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
1659       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1660       .resetvalue = 0 },
1661     /* The cache ops themselves: these all NOP for QEMU */
1662     { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
1663       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1664     { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
1665       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1666     { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
1667       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1668     { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
1669       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1670     { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
1671       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1672     { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
1673       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1674     REGINFO_SENTINEL
1675 };
1676
1677 static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
1678     /* The cache test-and-clean instructions always return (1 << 30)
1679      * to indicate that there are no dirty cache lines.
1680      */
1681     { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
1682       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1683       .resetvalue = (1 << 30) },
1684     { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
1685       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1686       .resetvalue = (1 << 30) },
1687     REGINFO_SENTINEL
1688 };
1689
1690 static const ARMCPRegInfo strongarm_cp_reginfo[] = {
1691     /* Ignore ReadBuffer accesses */
1692     { .name = "C9_READBUFFER", .cp = 15, .crn = 9,
1693       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
1694       .access = PL1_RW, .resetvalue = 0,
1695       .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE },
1696     REGINFO_SENTINEL
1697 };
1698
1699 static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1700 {
1701     CPUState *cs = CPU(arm_env_get_cpu(env));
1702     uint32_t mpidr = cs->cpu_index;
1703     /* We don't support setting cluster ID ([8..11]) (known as Aff1
1704      * in later ARM ARM versions), or any of the higher affinity level fields,
1705      * so these bits always RAZ.
1706      */
1707     if (arm_feature(env, ARM_FEATURE_V7MP)) {
1708         mpidr |= (1U << 31);
1709         /* Cores which are uniprocessor (non-coherent)
1710          * but still implement the MP extensions set
1711          * bit 30. (For instance, A9UP.) However we do
1712          * not currently model any of those cores.
1713          */
1714     }
1715     return mpidr;
1716 }
1717
1718 static const ARMCPRegInfo mpidr_cp_reginfo[] = {
1719     { .name = "MPIDR", .state = ARM_CP_STATE_BOTH,
1720       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
1721       .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_MIGRATE },
1722     REGINFO_SENTINEL
1723 };
1724
1725 static const ARMCPRegInfo lpae_cp_reginfo[] = {
1726     /* NOP AMAIR0/1: the override is because these clash with the rather
1727      * broadly specified TLB_LOCKDOWN entry in the generic cp_reginfo.
1728      */
1729     { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH,
1730       .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
1731       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
1732       .resetvalue = 0 },
1733     /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
1734     { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
1735       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
1736       .resetvalue = 0 },
1737     /* 64 bit access versions of the (dummy) debug registers */
1738     { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
1739       .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
1740     { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
1741       .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
1742     { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0,
1743       .access = PL1_RW, .type = ARM_CP_64BIT,
1744       .fieldoffset = offsetof(CPUARMState, cp15.par_el1), .resetvalue = 0 },
1745     { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0,
1746       .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE,
1747       .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el1),
1748       .writefn = vmsa_ttbr_write, .resetfn = arm_cp_reset_ignore },
1749     { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
1750       .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE,
1751       .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el1),
1752       .writefn = vmsa_ttbr_write, .resetfn = arm_cp_reset_ignore },
1753     REGINFO_SENTINEL
1754 };
1755
1756 static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1757 {
1758     return vfp_get_fpcr(env);
1759 }
1760
1761 static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1762                             uint64_t value)
1763 {
1764     vfp_set_fpcr(env, value);
1765 }
1766
1767 static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1768 {
1769     return vfp_get_fpsr(env);
1770 }
1771
1772 static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1773                             uint64_t value)
1774 {
1775     vfp_set_fpsr(env, value);
1776 }
1777
1778 static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri)
1779 {
1780     if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UMA)) {
1781         return CP_ACCESS_TRAP;
1782     }
1783     return CP_ACCESS_OK;
1784 }
1785
1786 static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri,
1787                             uint64_t value)
1788 {
1789     env->daif = value & PSTATE_DAIF;
1790 }
1791
1792 static CPAccessResult aa64_cacheop_access(CPUARMState *env,
1793                                           const ARMCPRegInfo *ri)
1794 {
1795     /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless
1796      * SCTLR_EL1.UCI is set.
1797      */
1798     if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UCI)) {
1799         return CP_ACCESS_TRAP;
1800     }
1801     return CP_ACCESS_OK;
1802 }
1803
1804 static void tlbi_aa64_va_write(CPUARMState *env, const ARMCPRegInfo *ri,
1805                                uint64_t value)
1806 {
1807     /* Invalidate by VA (AArch64 version) */
1808     ARMCPU *cpu = arm_env_get_cpu(env);
1809     uint64_t pageaddr = value << 12;
1810     tlb_flush_page(CPU(cpu), pageaddr);
1811 }
1812
1813 static void tlbi_aa64_vaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
1814                                 uint64_t value)
1815 {
1816     /* Invalidate by VA, all ASIDs (AArch64 version) */
1817     ARMCPU *cpu = arm_env_get_cpu(env);
1818     uint64_t pageaddr = value << 12;
1819     tlb_flush_page(CPU(cpu), pageaddr);
1820 }
1821
1822 static void tlbi_aa64_asid_write(CPUARMState *env, const ARMCPRegInfo *ri,
1823                                  uint64_t value)
1824 {
1825     /* Invalidate by ASID (AArch64 version) */
1826     ARMCPU *cpu = arm_env_get_cpu(env);
1827     int asid = extract64(value, 48, 16);
1828     tlb_flush(CPU(cpu), asid == 0);
1829 }
1830
1831 static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri)
1832 {
1833     /* We don't implement EL2, so the only control on DC ZVA is the
1834      * bit in the SCTLR which can prohibit access for EL0.
1835      */
1836     if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_DZE)) {
1837         return CP_ACCESS_TRAP;
1838     }
1839     return CP_ACCESS_OK;
1840 }
1841
1842 static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri)
1843 {
1844     ARMCPU *cpu = arm_env_get_cpu(env);
1845     int dzp_bit = 1 << 4;
1846
1847     /* DZP indicates whether DC ZVA access is allowed */
1848     if (aa64_zva_access(env, NULL) != CP_ACCESS_OK) {
1849         dzp_bit = 0;
1850     }
1851     return cpu->dcz_blocksize | dzp_bit;
1852 }
1853
1854 static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri)
1855 {
1856     if (!env->pstate & PSTATE_SP) {
1857         /* Access to SP_EL0 is undefined if it's being used as
1858          * the stack pointer.
1859          */
1860         return CP_ACCESS_TRAP_UNCATEGORIZED;
1861     }
1862     return CP_ACCESS_OK;
1863 }
1864
1865 static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri)
1866 {
1867     return env->pstate & PSTATE_SP;
1868 }
1869
1870 static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
1871 {
1872     update_spsel(env, val);
1873 }
1874
1875 static const ARMCPRegInfo v8_cp_reginfo[] = {
1876     /* Minimal set of EL0-visible registers. This will need to be expanded
1877      * significantly for system emulation of AArch64 CPUs.
1878      */
1879     { .name = "NZCV", .state = ARM_CP_STATE_AA64,
1880       .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2,
1881       .access = PL0_RW, .type = ARM_CP_NZCV },
1882     { .name = "DAIF", .state = ARM_CP_STATE_AA64,
1883       .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2,
1884       .type = ARM_CP_NO_MIGRATE,
1885       .access = PL0_RW, .accessfn = aa64_daif_access,
1886       .fieldoffset = offsetof(CPUARMState, daif),
1887       .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore },
1888     { .name = "FPCR", .state = ARM_CP_STATE_AA64,
1889       .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4,
1890       .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write },
1891     { .name = "FPSR", .state = ARM_CP_STATE_AA64,
1892       .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4,
1893       .access = PL0_RW, .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write },
1894     { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64,
1895       .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0,
1896       .access = PL0_R, .type = ARM_CP_NO_MIGRATE,
1897       .readfn = aa64_dczid_read },
1898     { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64,
1899       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1,
1900       .access = PL0_W, .type = ARM_CP_DC_ZVA,
1901 #ifndef CONFIG_USER_ONLY
1902       /* Avoid overhead of an access check that always passes in user-mode */
1903       .accessfn = aa64_zva_access,
1904 #endif
1905     },
1906     { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64,
1907       .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2,
1908       .access = PL1_R, .type = ARM_CP_CURRENTEL },
1909     /* Cache ops: all NOPs since we don't emulate caches */
1910     { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64,
1911       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
1912       .access = PL1_W, .type = ARM_CP_NOP },
1913     { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64,
1914       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
1915       .access = PL1_W, .type = ARM_CP_NOP },
1916     { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64,
1917       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1,
1918       .access = PL0_W, .type = ARM_CP_NOP,
1919       .accessfn = aa64_cacheop_access },
1920     { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64,
1921       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
1922       .access = PL1_W, .type = ARM_CP_NOP },
1923     { .name = "DC_ISW", .state = ARM_CP_STATE_AA64,
1924       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
1925       .access = PL1_W, .type = ARM_CP_NOP },
1926     { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64,
1927       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1,
1928       .access = PL0_W, .type = ARM_CP_NOP,
1929       .accessfn = aa64_cacheop_access },
1930     { .name = "DC_CSW", .state = ARM_CP_STATE_AA64,
1931       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
1932       .access = PL1_W, .type = ARM_CP_NOP },
1933     { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64,
1934       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1,
1935       .access = PL0_W, .type = ARM_CP_NOP,
1936       .accessfn = aa64_cacheop_access },
1937     { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64,
1938       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1,
1939       .access = PL0_W, .type = ARM_CP_NOP,
1940       .accessfn = aa64_cacheop_access },
1941     { .name = "DC_CISW", .state = ARM_CP_STATE_AA64,
1942       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
1943       .access = PL1_W, .type = ARM_CP_NOP },
1944     /* TLBI operations */
1945     { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
1946       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
1947       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1948       .writefn = tlbiall_write },
1949     { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
1950       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
1951       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1952       .writefn = tlbi_aa64_va_write },
1953     { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
1954       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
1955       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1956       .writefn = tlbi_aa64_asid_write },
1957     { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
1958       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
1959       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1960       .writefn = tlbi_aa64_vaa_write },
1961     { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
1962       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
1963       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1964       .writefn = tlbi_aa64_va_write },
1965     { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
1966       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
1967       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1968       .writefn = tlbi_aa64_vaa_write },
1969     { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
1970       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
1971       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1972       .writefn = tlbiall_write },
1973     { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64,
1974       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
1975       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1976       .writefn = tlbi_aa64_va_write },
1977     { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64,
1978       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
1979       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1980       .writefn = tlbi_aa64_asid_write },
1981     { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64,
1982       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
1983       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1984       .writefn = tlbi_aa64_vaa_write },
1985     { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64,
1986       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
1987       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1988       .writefn = tlbi_aa64_va_write },
1989     { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64,
1990       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
1991       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1992       .writefn = tlbi_aa64_vaa_write },
1993 #ifndef CONFIG_USER_ONLY
1994     /* 64 bit address translation operations */
1995     { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
1996       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0,
1997       .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write },
1998     { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64,
1999       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1,
2000       .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write },
2001     { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64,
2002       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2,
2003       .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write },
2004     { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64,
2005       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3,
2006       .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write },
2007 #endif
2008     /* 32 bit TLB invalidates, Inner Shareable */
2009     { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
2010       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiall_write },
2011     { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
2012       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write },
2013     { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
2014       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiasid_write },
2015     { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
2016       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimvaa_write },
2017     { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
2018       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write },
2019     { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
2020       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimvaa_write },
2021     /* 32 bit ITLB invalidates */
2022     { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0,
2023       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiall_write },
2024     { .name = "ITLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1,
2025       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write },
2026     { .name = "ITLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 2,
2027       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiasid_write },
2028     /* 32 bit DTLB invalidates */
2029     { .name = "DTLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 0,
2030       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiall_write },
2031     { .name = "DTLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1,
2032       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write },
2033     { .name = "DTLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 2,
2034       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiasid_write },
2035     /* 32 bit TLB invalidates */
2036     { .name = "TLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
2037       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiall_write },
2038     { .name = "TLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
2039       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write },
2040     { .name = "TLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
2041       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiasid_write },
2042     { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
2043       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimvaa_write },
2044     { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
2045       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write },
2046     { .name = "TLBIMVAAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
2047       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimvaa_write },
2048     /* 32 bit cache operations */
2049     { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
2050       .type = ARM_CP_NOP, .access = PL1_W },
2051     { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6,
2052       .type = ARM_CP_NOP, .access = PL1_W },
2053     { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
2054       .type = ARM_CP_NOP, .access = PL1_W },
2055     { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1,
2056       .type = ARM_CP_NOP, .access = PL1_W },
2057     { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6,
2058       .type = ARM_CP_NOP, .access = PL1_W },
2059     { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7,
2060       .type = ARM_CP_NOP, .access = PL1_W },
2061     { .name = "DCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
2062       .type = ARM_CP_NOP, .access = PL1_W },
2063     { .name = "DCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
2064       .type = ARM_CP_NOP, .access = PL1_W },
2065     { .name = "DCCMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 1,
2066       .type = ARM_CP_NOP, .access = PL1_W },
2067     { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
2068       .type = ARM_CP_NOP, .access = PL1_W },
2069     { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1,
2070       .type = ARM_CP_NOP, .access = PL1_W },
2071     { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1,
2072       .type = ARM_CP_NOP, .access = PL1_W },
2073     { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
2074       .type = ARM_CP_NOP, .access = PL1_W },
2075     /* MMU Domain access control / MPU write buffer control */
2076     { .name = "DACR", .cp = 15,
2077       .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0,
2078       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3),
2079       .resetvalue = 0, .writefn = dacr_write, .raw_writefn = raw_write, },
2080     /* Dummy implementation of monitor debug system control register:
2081      * we don't support debug.
2082      */
2083     { .name = "MDSCR_EL1", .state = ARM_CP_STATE_AA64,
2084       .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
2085       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
2086     /* We define a dummy WI OSLAR_EL1, because Linux writes to it. */
2087     { .name = "OSLAR_EL1", .state = ARM_CP_STATE_AA64,
2088       .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
2089       .access = PL1_W, .type = ARM_CP_NOP },
2090     { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64,
2091       .type = ARM_CP_NO_MIGRATE,
2092       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1,
2093       .access = PL1_RW,
2094       .fieldoffset = offsetof(CPUARMState, elr_el[1]) },
2095     { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64,
2096       .type = ARM_CP_NO_MIGRATE,
2097       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0,
2098       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[0]) },
2099     /* We rely on the access checks not allowing the guest to write to the
2100      * state field when SPSel indicates that it's being used as the stack
2101      * pointer.
2102      */
2103     { .name = "SP_EL0", .state = ARM_CP_STATE_AA64,
2104       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0,
2105       .access = PL1_RW, .accessfn = sp_el0_access,
2106       .type = ARM_CP_NO_MIGRATE,
2107       .fieldoffset = offsetof(CPUARMState, sp_el[0]) },
2108     { .name = "SPSel", .state = ARM_CP_STATE_AA64,
2109       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0,
2110       .type = ARM_CP_NO_MIGRATE,
2111       .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write },
2112     REGINFO_SENTINEL
2113 };
2114
2115 /* Used to describe the behaviour of EL2 regs when EL2 does not exist.  */
2116 static const ARMCPRegInfo v8_el3_no_el2_cp_reginfo[] = {
2117     { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
2118       .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
2119       .access = PL2_RW,
2120       .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
2121     REGINFO_SENTINEL
2122 };
2123
2124 static const ARMCPRegInfo v8_el2_cp_reginfo[] = {
2125     { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64,
2126       .type = ARM_CP_NO_MIGRATE,
2127       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1,
2128       .access = PL2_RW,
2129       .fieldoffset = offsetof(CPUARMState, elr_el[2]) },
2130     { .name = "ESR_EL2", .state = ARM_CP_STATE_AA64,
2131       .type = ARM_CP_NO_MIGRATE,
2132       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0,
2133       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) },
2134     { .name = "FAR_EL2", .state = ARM_CP_STATE_AA64,
2135       .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0,
2136       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) },
2137     { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64,
2138       .type = ARM_CP_NO_MIGRATE,
2139       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0,
2140       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[6]) },
2141     { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
2142       .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
2143       .access = PL2_RW, .writefn = vbar_write,
2144       .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]),
2145       .resetvalue = 0 },
2146     REGINFO_SENTINEL
2147 };
2148
2149 static const ARMCPRegInfo v8_el3_cp_reginfo[] = {
2150     { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64,
2151       .type = ARM_CP_NO_MIGRATE,
2152       .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1,
2153       .access = PL3_RW,
2154       .fieldoffset = offsetof(CPUARMState, elr_el[3]) },
2155     { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64,
2156       .type = ARM_CP_NO_MIGRATE,
2157       .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0,
2158       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) },
2159     { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64,
2160       .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0,
2161       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) },
2162     { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64,
2163       .type = ARM_CP_NO_MIGRATE,
2164       .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0,
2165       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[7]) },
2166     { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64,
2167       .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0,
2168       .access = PL3_RW, .writefn = vbar_write,
2169       .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]),
2170       .resetvalue = 0 },
2171     REGINFO_SENTINEL
2172 };
2173
2174 static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2175                         uint64_t value)
2176 {
2177     ARMCPU *cpu = arm_env_get_cpu(env);
2178
2179     if (raw_read(env, ri) == value) {
2180         /* Skip the TLB flush if nothing actually changed; Linux likes
2181          * to do a lot of pointless SCTLR writes.
2182          */
2183         return;
2184     }
2185
2186     raw_write(env, ri, value);
2187     /* ??? Lots of these bits are not implemented.  */
2188     /* This may enable/disable the MMU, so do a TLB flush.  */
2189     tlb_flush(CPU(cpu), 1);
2190 }
2191
2192 static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri)
2193 {
2194     /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64,
2195      * but the AArch32 CTR has its own reginfo struct)
2196      */
2197     if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UCT)) {
2198         return CP_ACCESS_TRAP;
2199     }
2200     return CP_ACCESS_OK;
2201 }
2202
2203 static void define_aarch64_debug_regs(ARMCPU *cpu)
2204 {
2205     /* Define breakpoint and watchpoint registers. These do nothing
2206      * but read as written, for now.
2207      */
2208     int i;
2209
2210     for (i = 0; i < 16; i++) {
2211         ARMCPRegInfo dbgregs[] = {
2212             { .name = "DBGBVR", .state = ARM_CP_STATE_AA64,
2213               .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4,
2214               .access = PL1_RW,
2215               .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]) },
2216             { .name = "DBGBCR", .state = ARM_CP_STATE_AA64,
2217               .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5,
2218               .access = PL1_RW,
2219               .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]) },
2220             { .name = "DBGWVR", .state = ARM_CP_STATE_AA64,
2221               .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6,
2222               .access = PL1_RW,
2223               .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]) },
2224             { .name = "DBGWCR", .state = ARM_CP_STATE_AA64,
2225               .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7,
2226               .access = PL1_RW,
2227               .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]) },
2228                REGINFO_SENTINEL
2229         };
2230         define_arm_cp_regs(cpu, dbgregs);
2231     }
2232 }
2233
2234 void register_cp_regs_for_features(ARMCPU *cpu)
2235 {
2236     /* Register all the coprocessor registers based on feature bits */
2237     CPUARMState *env = &cpu->env;
2238     if (arm_feature(env, ARM_FEATURE_M)) {
2239         /* M profile has no coprocessor registers */
2240         return;
2241     }
2242
2243     define_arm_cp_regs(cpu, cp_reginfo);
2244     if (!arm_feature(env, ARM_FEATURE_V8)) {
2245         /* Must go early as it is full of wildcards that may be
2246          * overridden by later definitions.
2247          */
2248         define_arm_cp_regs(cpu, not_v8_cp_reginfo);
2249     }
2250
2251     if (arm_feature(env, ARM_FEATURE_V6)) {
2252         /* The ID registers all have impdef reset values */
2253         ARMCPRegInfo v6_idregs[] = {
2254             { .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH,
2255               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
2256               .access = PL1_R, .type = ARM_CP_CONST,
2257               .resetvalue = cpu->id_pfr0 },
2258             { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH,
2259               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1,
2260               .access = PL1_R, .type = ARM_CP_CONST,
2261               .resetvalue = cpu->id_pfr1 },
2262             { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH,
2263               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
2264               .access = PL1_R, .type = ARM_CP_CONST,
2265               .resetvalue = cpu->id_dfr0 },
2266             { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH,
2267               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3,
2268               .access = PL1_R, .type = ARM_CP_CONST,
2269               .resetvalue = cpu->id_afr0 },
2270             { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH,
2271               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4,
2272               .access = PL1_R, .type = ARM_CP_CONST,
2273               .resetvalue = cpu->id_mmfr0 },
2274             { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH,
2275               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5,
2276               .access = PL1_R, .type = ARM_CP_CONST,
2277               .resetvalue = cpu->id_mmfr1 },
2278             { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH,
2279               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6,
2280               .access = PL1_R, .type = ARM_CP_CONST,
2281               .resetvalue = cpu->id_mmfr2 },
2282             { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH,
2283               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7,
2284               .access = PL1_R, .type = ARM_CP_CONST,
2285               .resetvalue = cpu->id_mmfr3 },
2286             { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH,
2287               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
2288               .access = PL1_R, .type = ARM_CP_CONST,
2289               .resetvalue = cpu->id_isar0 },
2290             { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH,
2291               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1,
2292               .access = PL1_R, .type = ARM_CP_CONST,
2293               .resetvalue = cpu->id_isar1 },
2294             { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH,
2295               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
2296               .access = PL1_R, .type = ARM_CP_CONST,
2297               .resetvalue = cpu->id_isar2 },
2298             { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH,
2299               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3,
2300               .access = PL1_R, .type = ARM_CP_CONST,
2301               .resetvalue = cpu->id_isar3 },
2302             { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH,
2303               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4,
2304               .access = PL1_R, .type = ARM_CP_CONST,
2305               .resetvalue = cpu->id_isar4 },
2306             { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH,
2307               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5,
2308               .access = PL1_R, .type = ARM_CP_CONST,
2309               .resetvalue = cpu->id_isar5 },
2310             /* 6..7 are as yet unallocated and must RAZ */
2311             { .name = "ID_ISAR6", .cp = 15, .crn = 0, .crm = 2,
2312               .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
2313               .resetvalue = 0 },
2314             { .name = "ID_ISAR7", .cp = 15, .crn = 0, .crm = 2,
2315               .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
2316               .resetvalue = 0 },
2317             REGINFO_SENTINEL
2318         };
2319         define_arm_cp_regs(cpu, v6_idregs);
2320         define_arm_cp_regs(cpu, v6_cp_reginfo);
2321     } else {
2322         define_arm_cp_regs(cpu, not_v6_cp_reginfo);
2323     }
2324     if (arm_feature(env, ARM_FEATURE_V6K)) {
2325         define_arm_cp_regs(cpu, v6k_cp_reginfo);
2326     }
2327     if (arm_feature(env, ARM_FEATURE_V7)) {
2328         /* v7 performance monitor control register: same implementor
2329          * field as main ID register, and we implement only the cycle
2330          * count register.
2331          */
2332 #ifndef CONFIG_USER_ONLY
2333         ARMCPRegInfo pmcr = {
2334             .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
2335             .access = PL0_RW, .resetvalue = cpu->midr & 0xff000000,
2336             .type = ARM_CP_IO,
2337             .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
2338             .accessfn = pmreg_access, .writefn = pmcr_write,
2339             .raw_writefn = raw_write,
2340         };
2341         define_one_arm_cp_reg(cpu, &pmcr);
2342 #endif
2343         ARMCPRegInfo clidr = {
2344             .name = "CLIDR", .state = ARM_CP_STATE_BOTH,
2345             .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
2346             .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr
2347         };
2348         define_one_arm_cp_reg(cpu, &clidr);
2349         define_arm_cp_regs(cpu, v7_cp_reginfo);
2350     } else {
2351         define_arm_cp_regs(cpu, not_v7_cp_reginfo);
2352     }
2353     if (arm_feature(env, ARM_FEATURE_V8)) {
2354         /* AArch64 ID registers, which all have impdef reset values */
2355         ARMCPRegInfo v8_idregs[] = {
2356             { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64,
2357               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0,
2358               .access = PL1_R, .type = ARM_CP_CONST,
2359               .resetvalue = cpu->id_aa64pfr0 },
2360             { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64,
2361               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1,
2362               .access = PL1_R, .type = ARM_CP_CONST,
2363               .resetvalue = cpu->id_aa64pfr1},
2364             { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
2365               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
2366               .access = PL1_R, .type = ARM_CP_CONST,
2367               /* We mask out the PMUVer field, because we don't currently
2368                * implement the PMU. Not advertising it prevents the guest
2369                * from trying to use it and getting UNDEFs on registers we
2370                * don't implement.
2371                */
2372               .resetvalue = cpu->id_aa64dfr0 & ~0xf00 },
2373             { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
2374               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
2375               .access = PL1_R, .type = ARM_CP_CONST,
2376               .resetvalue = cpu->id_aa64dfr1 },
2377             { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64,
2378               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4,
2379               .access = PL1_R, .type = ARM_CP_CONST,
2380               .resetvalue = cpu->id_aa64afr0 },
2381             { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64,
2382               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5,
2383               .access = PL1_R, .type = ARM_CP_CONST,
2384               .resetvalue = cpu->id_aa64afr1 },
2385             { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64,
2386               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0,
2387               .access = PL1_R, .type = ARM_CP_CONST,
2388               .resetvalue = cpu->id_aa64isar0 },
2389             { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64,
2390               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1,
2391               .access = PL1_R, .type = ARM_CP_CONST,
2392               .resetvalue = cpu->id_aa64isar1 },
2393             { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64,
2394               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
2395               .access = PL1_R, .type = ARM_CP_CONST,
2396               .resetvalue = cpu->id_aa64mmfr0 },
2397             { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64,
2398               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1,
2399               .access = PL1_R, .type = ARM_CP_CONST,
2400               .resetvalue = cpu->id_aa64mmfr1 },
2401             { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64,
2402               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0,
2403               .access = PL1_R, .type = ARM_CP_CONST,
2404               .resetvalue = cpu->mvfr0 },
2405             { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64,
2406               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1,
2407               .access = PL1_R, .type = ARM_CP_CONST,
2408               .resetvalue = cpu->mvfr1 },
2409             { .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64,
2410               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
2411               .access = PL1_R, .type = ARM_CP_CONST,
2412               .resetvalue = cpu->mvfr2 },
2413             REGINFO_SENTINEL
2414         };
2415         ARMCPRegInfo rvbar = {
2416             .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64,
2417             .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 2,
2418             .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar
2419         };
2420         define_one_arm_cp_reg(cpu, &rvbar);
2421         define_arm_cp_regs(cpu, v8_idregs);
2422         define_arm_cp_regs(cpu, v8_cp_reginfo);
2423         define_aarch64_debug_regs(cpu);
2424     }
2425     if (arm_feature(env, ARM_FEATURE_EL2)) {
2426         define_arm_cp_regs(cpu, v8_el2_cp_reginfo);
2427     } else {
2428         /* If EL2 is missing but higher ELs are enabled, we need to
2429          * register the no_el2 reginfos.
2430          */
2431         if (arm_feature(env, ARM_FEATURE_EL3)) {
2432             define_arm_cp_regs(cpu, v8_el3_no_el2_cp_reginfo);
2433         }
2434     }
2435     if (arm_feature(env, ARM_FEATURE_EL3)) {
2436         define_arm_cp_regs(cpu, v8_el3_cp_reginfo);
2437     }
2438     if (arm_feature(env, ARM_FEATURE_MPU)) {
2439         /* These are the MPU registers prior to PMSAv6. Any new
2440          * PMSA core later than the ARM946 will require that we
2441          * implement the PMSAv6 or PMSAv7 registers, which are
2442          * completely different.
2443          */
2444         assert(!arm_feature(env, ARM_FEATURE_V6));
2445         define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
2446     } else {
2447         define_arm_cp_regs(cpu, vmsa_cp_reginfo);
2448     }
2449     if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
2450         define_arm_cp_regs(cpu, t2ee_cp_reginfo);
2451     }
2452     if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
2453         define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
2454     }
2455     if (arm_feature(env, ARM_FEATURE_VAPA)) {
2456         define_arm_cp_regs(cpu, vapa_cp_reginfo);
2457     }
2458     if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) {
2459         define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo);
2460     }
2461     if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) {
2462         define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo);
2463     }
2464     if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) {
2465         define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo);
2466     }
2467     if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
2468         define_arm_cp_regs(cpu, omap_cp_reginfo);
2469     }
2470     if (arm_feature(env, ARM_FEATURE_STRONGARM)) {
2471         define_arm_cp_regs(cpu, strongarm_cp_reginfo);
2472     }
2473     if (arm_feature(env, ARM_FEATURE_XSCALE)) {
2474         define_arm_cp_regs(cpu, xscale_cp_reginfo);
2475     }
2476     if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
2477         define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
2478     }
2479     if (arm_feature(env, ARM_FEATURE_LPAE)) {
2480         define_arm_cp_regs(cpu, lpae_cp_reginfo);
2481     }
2482     /* Slightly awkwardly, the OMAP and StrongARM cores need all of
2483      * cp15 crn=0 to be writes-ignored, whereas for other cores they should
2484      * be read-only (ie write causes UNDEF exception).
2485      */
2486     {
2487         ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] = {
2488             /* Pre-v8 MIDR space.
2489              * Note that the MIDR isn't a simple constant register because
2490              * of the TI925 behaviour where writes to another register can
2491              * cause the MIDR value to change.
2492              *
2493              * Unimplemented registers in the c15 0 0 0 space default to
2494              * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
2495              * and friends override accordingly.
2496              */
2497             { .name = "MIDR",
2498               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY,
2499               .access = PL1_R, .resetvalue = cpu->midr,
2500               .writefn = arm_cp_write_ignore, .raw_writefn = raw_write,
2501               .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
2502               .type = ARM_CP_OVERRIDE },
2503             /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
2504             { .name = "DUMMY",
2505               .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY,
2506               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2507             { .name = "DUMMY",
2508               .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY,
2509               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2510             { .name = "DUMMY",
2511               .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY,
2512               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2513             { .name = "DUMMY",
2514               .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY,
2515               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2516             { .name = "DUMMY",
2517               .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
2518               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2519             REGINFO_SENTINEL
2520         };
2521         ARMCPRegInfo id_v8_midr_cp_reginfo[] = {
2522             /* v8 MIDR -- the wildcard isn't necessary, and nor is the
2523              * variable-MIDR TI925 behaviour. Instead we have a single
2524              * (strictly speaking IMPDEF) alias of the MIDR, REVIDR.
2525              */
2526             { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH,
2527               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0,
2528               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->midr },
2529             { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH,
2530               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6,
2531               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->midr },
2532             REGINFO_SENTINEL
2533         };
2534         ARMCPRegInfo id_cp_reginfo[] = {
2535             /* These are common to v8 and pre-v8 */
2536             { .name = "CTR",
2537               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
2538               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
2539             { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64,
2540               .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0,
2541               .access = PL0_R, .accessfn = ctr_el0_access,
2542               .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
2543             /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
2544             { .name = "TCMTR",
2545               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2,
2546               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2547             { .name = "TLBTR",
2548               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
2549               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2550             REGINFO_SENTINEL
2551         };
2552         ARMCPRegInfo crn0_wi_reginfo = {
2553             .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
2554             .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
2555             .type = ARM_CP_NOP | ARM_CP_OVERRIDE
2556         };
2557         if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
2558             arm_feature(env, ARM_FEATURE_STRONGARM)) {
2559             ARMCPRegInfo *r;
2560             /* Register the blanket "writes ignored" value first to cover the
2561              * whole space. Then update the specific ID registers to allow write
2562              * access, so that they ignore writes rather than causing them to
2563              * UNDEF.
2564              */
2565             define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
2566             for (r = id_pre_v8_midr_cp_reginfo;
2567                  r->type != ARM_CP_SENTINEL; r++) {
2568                 r->access = PL1_RW;
2569             }
2570             for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
2571                 r->access = PL1_RW;
2572             }
2573         }
2574         if (arm_feature(env, ARM_FEATURE_V8)) {
2575             define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo);
2576         } else {
2577             define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo);
2578         }
2579         define_arm_cp_regs(cpu, id_cp_reginfo);
2580     }
2581
2582     if (arm_feature(env, ARM_FEATURE_MPIDR)) {
2583         define_arm_cp_regs(cpu, mpidr_cp_reginfo);
2584     }
2585
2586     if (arm_feature(env, ARM_FEATURE_AUXCR)) {
2587         ARMCPRegInfo auxcr = {
2588             .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH,
2589             .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1,
2590             .access = PL1_RW, .type = ARM_CP_CONST,
2591             .resetvalue = cpu->reset_auxcr
2592         };
2593         define_one_arm_cp_reg(cpu, &auxcr);
2594     }
2595
2596     if (arm_feature(env, ARM_FEATURE_CBAR)) {
2597         if (arm_feature(env, ARM_FEATURE_AARCH64)) {
2598             /* 32 bit view is [31:18] 0...0 [43:32]. */
2599             uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18)
2600                 | extract64(cpu->reset_cbar, 32, 12);
2601             ARMCPRegInfo cbar_reginfo[] = {
2602                 { .name = "CBAR",
2603                   .type = ARM_CP_CONST,
2604                   .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
2605                   .access = PL1_R, .resetvalue = cpu->reset_cbar },
2606                 { .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64,
2607                   .type = ARM_CP_CONST,
2608                   .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0,
2609                   .access = PL1_R, .resetvalue = cbar32 },
2610                 REGINFO_SENTINEL
2611             };
2612             /* We don't implement a r/w 64 bit CBAR currently */
2613             assert(arm_feature(env, ARM_FEATURE_CBAR_RO));
2614             define_arm_cp_regs(cpu, cbar_reginfo);
2615         } else {
2616             ARMCPRegInfo cbar = {
2617                 .name = "CBAR",
2618                 .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
2619                 .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
2620                 .fieldoffset = offsetof(CPUARMState,
2621                                         cp15.c15_config_base_address)
2622             };
2623             if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
2624                 cbar.access = PL1_R;
2625                 cbar.fieldoffset = 0;
2626                 cbar.type = ARM_CP_CONST;
2627             }
2628             define_one_arm_cp_reg(cpu, &cbar);
2629         }
2630     }
2631
2632     /* Generic registers whose values depend on the implementation */
2633     {
2634         ARMCPRegInfo sctlr = {
2635             .name = "SCTLR", .state = ARM_CP_STATE_BOTH,
2636             .opc0 = 3, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
2637             .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_sys),
2638             .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
2639             .raw_writefn = raw_write,
2640         };
2641         if (arm_feature(env, ARM_FEATURE_XSCALE)) {
2642             /* Normally we would always end the TB on an SCTLR write, but Linux
2643              * arch/arm/mach-pxa/sleep.S expects two instructions following
2644              * an MMU enable to execute from cache.  Imitate this behaviour.
2645              */
2646             sctlr.type |= ARM_CP_SUPPRESS_TB_END;
2647         }
2648         define_one_arm_cp_reg(cpu, &sctlr);
2649     }
2650 }
2651
2652 ARMCPU *cpu_arm_init(const char *cpu_model)
2653 {
2654     return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model));
2655 }
2656
2657 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
2658 {
2659     CPUState *cs = CPU(cpu);
2660     CPUARMState *env = &cpu->env;
2661
2662     if (arm_feature(env, ARM_FEATURE_AARCH64)) {
2663         gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
2664                                  aarch64_fpu_gdb_set_reg,
2665                                  34, "aarch64-fpu.xml", 0);
2666     } else if (arm_feature(env, ARM_FEATURE_NEON)) {
2667         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
2668                                  51, "arm-neon.xml", 0);
2669     } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
2670         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
2671                                  35, "arm-vfp3.xml", 0);
2672     } else if (arm_feature(env, ARM_FEATURE_VFP)) {
2673         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
2674                                  19, "arm-vfp.xml", 0);
2675     }
2676 }
2677
2678 /* Sort alphabetically by type name, except for "any". */
2679 static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
2680 {
2681     ObjectClass *class_a = (ObjectClass *)a;
2682     ObjectClass *class_b = (ObjectClass *)b;
2683     const char *name_a, *name_b;
2684
2685     name_a = object_class_get_name(class_a);
2686     name_b = object_class_get_name(class_b);
2687     if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) {
2688         return 1;
2689     } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) {
2690         return -1;
2691     } else {
2692         return strcmp(name_a, name_b);
2693     }
2694 }
2695
2696 static void arm_cpu_list_entry(gpointer data, gpointer user_data)
2697 {
2698     ObjectClass *oc = data;
2699     CPUListState *s = user_data;
2700     const char *typename;
2701     char *name;
2702
2703     typename = object_class_get_name(oc);
2704     name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU));
2705     (*s->cpu_fprintf)(s->file, "  %s\n",
2706                       name);
2707     g_free(name);
2708 }
2709
2710 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
2711 {
2712     CPUListState s = {
2713         .file = f,
2714         .cpu_fprintf = cpu_fprintf,
2715     };
2716     GSList *list;
2717
2718     list = object_class_get_list(TYPE_ARM_CPU, false);
2719     list = g_slist_sort(list, arm_cpu_list_compare);
2720     (*cpu_fprintf)(f, "Available CPUs:\n");
2721     g_slist_foreach(list, arm_cpu_list_entry, &s);
2722     g_slist_free(list);
2723 #ifdef CONFIG_KVM
2724     /* The 'host' CPU type is dynamically registered only if KVM is
2725      * enabled, so we have to special-case it here:
2726      */
2727     (*cpu_fprintf)(f, "  host (only available in KVM mode)\n");
2728 #endif
2729 }
2730
2731 static void arm_cpu_add_definition(gpointer data, gpointer user_data)
2732 {
2733     ObjectClass *oc = data;
2734     CpuDefinitionInfoList **cpu_list = user_data;
2735     CpuDefinitionInfoList *entry;
2736     CpuDefinitionInfo *info;
2737     const char *typename;
2738
2739     typename = object_class_get_name(oc);
2740     info = g_malloc0(sizeof(*info));
2741     info->name = g_strndup(typename,
2742                            strlen(typename) - strlen("-" TYPE_ARM_CPU));
2743
2744     entry = g_malloc0(sizeof(*entry));
2745     entry->value = info;
2746     entry->next = *cpu_list;
2747     *cpu_list = entry;
2748 }
2749
2750 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
2751 {
2752     CpuDefinitionInfoList *cpu_list = NULL;
2753     GSList *list;
2754
2755     list = object_class_get_list(TYPE_ARM_CPU, false);
2756     g_slist_foreach(list, arm_cpu_add_definition, &cpu_list);
2757     g_slist_free(list);
2758
2759     return cpu_list;
2760 }
2761
2762 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
2763                                    void *opaque, int state,
2764                                    int crm, int opc1, int opc2)
2765 {
2766     /* Private utility function for define_one_arm_cp_reg_with_opaque():
2767      * add a single reginfo struct to the hash table.
2768      */
2769     uint32_t *key = g_new(uint32_t, 1);
2770     ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
2771     int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
2772     if (r->state == ARM_CP_STATE_BOTH && state == ARM_CP_STATE_AA32) {
2773         /* The AArch32 view of a shared register sees the lower 32 bits
2774          * of a 64 bit backing field. It is not migratable as the AArch64
2775          * view handles that. AArch64 also handles reset.
2776          * We assume it is a cp15 register.
2777          */
2778         r2->cp = 15;
2779         r2->type |= ARM_CP_NO_MIGRATE;
2780         r2->resetfn = arm_cp_reset_ignore;
2781 #ifdef HOST_WORDS_BIGENDIAN
2782         if (r2->fieldoffset) {
2783             r2->fieldoffset += sizeof(uint32_t);
2784         }
2785 #endif
2786     }
2787     if (state == ARM_CP_STATE_AA64) {
2788         /* To allow abbreviation of ARMCPRegInfo
2789          * definitions, we treat cp == 0 as equivalent to
2790          * the value for "standard guest-visible sysreg".
2791          */
2792         if (r->cp == 0) {
2793             r2->cp = CP_REG_ARM64_SYSREG_CP;
2794         }
2795         *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
2796                                   r2->opc0, opc1, opc2);
2797     } else {
2798         *key = ENCODE_CP_REG(r2->cp, is64, r2->crn, crm, opc1, opc2);
2799     }
2800     if (opaque) {
2801         r2->opaque = opaque;
2802     }
2803     /* reginfo passed to helpers is correct for the actual access,
2804      * and is never ARM_CP_STATE_BOTH:
2805      */
2806     r2->state = state;
2807     /* Make sure reginfo passed to helpers for wildcarded regs
2808      * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
2809      */
2810     r2->crm = crm;
2811     r2->opc1 = opc1;
2812     r2->opc2 = opc2;
2813     /* By convention, for wildcarded registers only the first
2814      * entry is used for migration; the others are marked as
2815      * NO_MIGRATE so we don't try to transfer the register
2816      * multiple times. Special registers (ie NOP/WFI) are
2817      * never migratable.
2818      */
2819     if ((r->type & ARM_CP_SPECIAL) ||
2820         ((r->crm == CP_ANY) && crm != 0) ||
2821         ((r->opc1 == CP_ANY) && opc1 != 0) ||
2822         ((r->opc2 == CP_ANY) && opc2 != 0)) {
2823         r2->type |= ARM_CP_NO_MIGRATE;
2824     }
2825
2826     /* Overriding of an existing definition must be explicitly
2827      * requested.
2828      */
2829     if (!(r->type & ARM_CP_OVERRIDE)) {
2830         ARMCPRegInfo *oldreg;
2831         oldreg = g_hash_table_lookup(cpu->cp_regs, key);
2832         if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
2833             fprintf(stderr, "Register redefined: cp=%d %d bit "
2834                     "crn=%d crm=%d opc1=%d opc2=%d, "
2835                     "was %s, now %s\n", r2->cp, 32 + 32 * is64,
2836                     r2->crn, r2->crm, r2->opc1, r2->opc2,
2837                     oldreg->name, r2->name);
2838             g_assert_not_reached();
2839         }
2840     }
2841     g_hash_table_insert(cpu->cp_regs, key, r2);
2842 }
2843
2844
2845 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
2846                                        const ARMCPRegInfo *r, void *opaque)
2847 {
2848     /* Define implementations of coprocessor registers.
2849      * We store these in a hashtable because typically
2850      * there are less than 150 registers in a space which
2851      * is 16*16*16*8*8 = 262144 in size.
2852      * Wildcarding is supported for the crm, opc1 and opc2 fields.
2853      * If a register is defined twice then the second definition is
2854      * used, so this can be used to define some generic registers and
2855      * then override them with implementation specific variations.
2856      * At least one of the original and the second definition should
2857      * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
2858      * against accidental use.
2859      *
2860      * The state field defines whether the register is to be
2861      * visible in the AArch32 or AArch64 execution state. If the
2862      * state is set to ARM_CP_STATE_BOTH then we synthesise a
2863      * reginfo structure for the AArch32 view, which sees the lower
2864      * 32 bits of the 64 bit register.
2865      *
2866      * Only registers visible in AArch64 may set r->opc0; opc0 cannot
2867      * be wildcarded. AArch64 registers are always considered to be 64
2868      * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
2869      * the register, if any.
2870      */
2871     int crm, opc1, opc2, state;
2872     int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
2873     int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
2874     int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
2875     int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
2876     int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
2877     int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
2878     /* 64 bit registers have only CRm and Opc1 fields */
2879     assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
2880     /* op0 only exists in the AArch64 encodings */
2881     assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0));
2882     /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
2883     assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT));
2884     /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
2885      * encodes a minimum access level for the register. We roll this
2886      * runtime check into our general permission check code, so check
2887      * here that the reginfo's specified permissions are strict enough
2888      * to encompass the generic architectural permission check.
2889      */
2890     if (r->state != ARM_CP_STATE_AA32) {
2891         int mask = 0;
2892         switch (r->opc1) {
2893         case 0: case 1: case 2:
2894             /* min_EL EL1 */
2895             mask = PL1_RW;
2896             break;
2897         case 3:
2898             /* min_EL EL0 */
2899             mask = PL0_RW;
2900             break;
2901         case 4:
2902             /* min_EL EL2 */
2903             mask = PL2_RW;
2904             break;
2905         case 5:
2906             /* unallocated encoding, so not possible */
2907             assert(false);
2908             break;
2909         case 6:
2910             /* min_EL EL3 */
2911             mask = PL3_RW;
2912             break;
2913         case 7:
2914             /* min_EL EL1, secure mode only (we don't check the latter) */
2915             mask = PL1_RW;
2916             break;
2917         default:
2918             /* broken reginfo with out-of-range opc1 */
2919             assert(false);
2920             break;
2921         }
2922         /* assert our permissions are not too lax (stricter is fine) */
2923         assert((r->access & ~mask) == 0);
2924     }
2925
2926     /* Check that the register definition has enough info to handle
2927      * reads and writes if they are permitted.
2928      */
2929     if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
2930         if (r->access & PL3_R) {
2931             assert(r->fieldoffset || r->readfn);
2932         }
2933         if (r->access & PL3_W) {
2934             assert(r->fieldoffset || r->writefn);
2935         }
2936     }
2937     /* Bad type field probably means missing sentinel at end of reg list */
2938     assert(cptype_valid(r->type));
2939     for (crm = crmmin; crm <= crmmax; crm++) {
2940         for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
2941             for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
2942                 for (state = ARM_CP_STATE_AA32;
2943                      state <= ARM_CP_STATE_AA64; state++) {
2944                     if (r->state != state && r->state != ARM_CP_STATE_BOTH) {
2945                         continue;
2946                     }
2947                     add_cpreg_to_hashtable(cpu, r, opaque, state,
2948                                            crm, opc1, opc2);
2949                 }
2950             }
2951         }
2952     }
2953 }
2954
2955 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
2956                                     const ARMCPRegInfo *regs, void *opaque)
2957 {
2958     /* Define a whole list of registers */
2959     const ARMCPRegInfo *r;
2960     for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
2961         define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
2962     }
2963 }
2964
2965 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp)
2966 {
2967     return g_hash_table_lookup(cpregs, &encoded_cp);
2968 }
2969
2970 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
2971                          uint64_t value)
2972 {
2973     /* Helper coprocessor write function for write-ignore registers */
2974 }
2975
2976 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri)
2977 {
2978     /* Helper coprocessor write function for read-as-zero registers */
2979     return 0;
2980 }
2981
2982 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque)
2983 {
2984     /* Helper coprocessor reset function for do-nothing-on-reset registers */
2985 }
2986
2987 static int bad_mode_switch(CPUARMState *env, int mode)
2988 {
2989     /* Return true if it is not valid for us to switch to
2990      * this CPU mode (ie all the UNPREDICTABLE cases in
2991      * the ARM ARM CPSRWriteByInstr pseudocode).
2992      */
2993     switch (mode) {
2994     case ARM_CPU_MODE_USR:
2995     case ARM_CPU_MODE_SYS:
2996     case ARM_CPU_MODE_SVC:
2997     case ARM_CPU_MODE_ABT:
2998     case ARM_CPU_MODE_UND:
2999     case ARM_CPU_MODE_IRQ:
3000     case ARM_CPU_MODE_FIQ:
3001         return 0;
3002     default:
3003         return 1;
3004     }
3005 }
3006
3007 uint32_t cpsr_read(CPUARMState *env)
3008 {
3009     int ZF;
3010     ZF = (env->ZF == 0);
3011     return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
3012         (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
3013         | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
3014         | ((env->condexec_bits & 0xfc) << 8)
3015         | (env->GE << 16) | (env->daif & CPSR_AIF);
3016 }
3017
3018 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
3019 {
3020     if (mask & CPSR_NZCV) {
3021         env->ZF = (~val) & CPSR_Z;
3022         env->NF = val;
3023         env->CF = (val >> 29) & 1;
3024         env->VF = (val << 3) & 0x80000000;
3025     }
3026     if (mask & CPSR_Q)
3027         env->QF = ((val & CPSR_Q) != 0);
3028     if (mask & CPSR_T)
3029         env->thumb = ((val & CPSR_T) != 0);
3030     if (mask & CPSR_IT_0_1) {
3031         env->condexec_bits &= ~3;
3032         env->condexec_bits |= (val >> 25) & 3;
3033     }
3034     if (mask & CPSR_IT_2_7) {
3035         env->condexec_bits &= 3;
3036         env->condexec_bits |= (val >> 8) & 0xfc;
3037     }
3038     if (mask & CPSR_GE) {
3039         env->GE = (val >> 16) & 0xf;
3040     }
3041
3042     env->daif &= ~(CPSR_AIF & mask);
3043     env->daif |= val & CPSR_AIF & mask;
3044
3045     if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
3046         if (bad_mode_switch(env, val & CPSR_M)) {
3047             /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
3048              * We choose to ignore the attempt and leave the CPSR M field
3049              * untouched.
3050              */
3051             mask &= ~CPSR_M;
3052         } else {
3053             switch_mode(env, val & CPSR_M);
3054         }
3055     }
3056     mask &= ~CACHED_CPSR_BITS;
3057     env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
3058 }
3059
3060 /* Sign/zero extend */
3061 uint32_t HELPER(sxtb16)(uint32_t x)
3062 {
3063     uint32_t res;
3064     res = (uint16_t)(int8_t)x;
3065     res |= (uint32_t)(int8_t)(x >> 16) << 16;
3066     return res;
3067 }
3068
3069 uint32_t HELPER(uxtb16)(uint32_t x)
3070 {
3071     uint32_t res;
3072     res = (uint16_t)(uint8_t)x;
3073     res |= (uint32_t)(uint8_t)(x >> 16) << 16;
3074     return res;
3075 }
3076
3077 uint32_t HELPER(clz)(uint32_t x)
3078 {
3079     return clz32(x);
3080 }
3081
3082 int32_t HELPER(sdiv)(int32_t num, int32_t den)
3083 {
3084     if (den == 0)
3085       return 0;
3086     if (num == INT_MIN && den == -1)
3087       return INT_MIN;
3088     return num / den;
3089 }
3090
3091 uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
3092 {
3093     if (den == 0)
3094       return 0;
3095     return num / den;
3096 }
3097
3098 uint32_t HELPER(rbit)(uint32_t x)
3099 {
3100     x =  ((x & 0xff000000) >> 24)
3101        | ((x & 0x00ff0000) >> 8)
3102        | ((x & 0x0000ff00) << 8)
3103        | ((x & 0x000000ff) << 24);
3104     x =  ((x & 0xf0f0f0f0) >> 4)
3105        | ((x & 0x0f0f0f0f) << 4);
3106     x =  ((x & 0x88888888) >> 3)
3107        | ((x & 0x44444444) >> 1)
3108        | ((x & 0x22222222) << 1)
3109        | ((x & 0x11111111) << 3);
3110     return x;
3111 }
3112
3113 #if defined(CONFIG_USER_ONLY)
3114
3115 void arm_cpu_do_interrupt(CPUState *cs)
3116 {
3117     cs->exception_index = -1;
3118 }
3119
3120 int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
3121                              int mmu_idx)
3122 {
3123     ARMCPU *cpu = ARM_CPU(cs);
3124     CPUARMState *env = &cpu->env;
3125
3126     env->exception.vaddress = address;
3127     if (rw == 2) {
3128         cs->exception_index = EXCP_PREFETCH_ABORT;
3129     } else {
3130         cs->exception_index = EXCP_DATA_ABORT;
3131     }
3132     return 1;
3133 }
3134
3135 /* These should probably raise undefined insn exceptions.  */
3136 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
3137 {
3138     ARMCPU *cpu = arm_env_get_cpu(env);
3139
3140     cpu_abort(CPU(cpu), "v7m_msr %d\n", reg);
3141 }
3142
3143 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
3144 {
3145     ARMCPU *cpu = arm_env_get_cpu(env);
3146
3147     cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg);
3148     return 0;
3149 }
3150
3151 void switch_mode(CPUARMState *env, int mode)
3152 {
3153     ARMCPU *cpu = arm_env_get_cpu(env);
3154
3155     if (mode != ARM_CPU_MODE_USR) {
3156         cpu_abort(CPU(cpu), "Tried to switch out of user mode\n");
3157     }
3158 }
3159
3160 void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
3161 {
3162     ARMCPU *cpu = arm_env_get_cpu(env);
3163
3164     cpu_abort(CPU(cpu), "banked r13 write\n");
3165 }
3166
3167 uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
3168 {
3169     ARMCPU *cpu = arm_env_get_cpu(env);
3170
3171     cpu_abort(CPU(cpu), "banked r13 read\n");
3172     return 0;
3173 }
3174
3175 #else
3176
3177 /* Map CPU modes onto saved register banks.  */
3178 int bank_number(int mode)
3179 {
3180     switch (mode) {
3181     case ARM_CPU_MODE_USR:
3182     case ARM_CPU_MODE_SYS:
3183         return 0;
3184     case ARM_CPU_MODE_SVC:
3185         return 1;
3186     case ARM_CPU_MODE_ABT:
3187         return 2;
3188     case ARM_CPU_MODE_UND:
3189         return 3;
3190     case ARM_CPU_MODE_IRQ:
3191         return 4;
3192     case ARM_CPU_MODE_FIQ:
3193         return 5;
3194     case ARM_CPU_MODE_HYP:
3195         return 6;
3196     case ARM_CPU_MODE_MON:
3197         return 7;
3198     }
3199     hw_error("bank number requested for bad CPSR mode value 0x%x\n", mode);
3200 }
3201
3202 void switch_mode(CPUARMState *env, int mode)
3203 {
3204     int old_mode;
3205     int i;
3206
3207     old_mode = env->uncached_cpsr & CPSR_M;
3208     if (mode == old_mode)
3209         return;
3210
3211     if (old_mode == ARM_CPU_MODE_FIQ) {
3212         memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
3213         memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
3214     } else if (mode == ARM_CPU_MODE_FIQ) {
3215         memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
3216         memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
3217     }
3218
3219     i = bank_number(old_mode);
3220     env->banked_r13[i] = env->regs[13];
3221     env->banked_r14[i] = env->regs[14];
3222     env->banked_spsr[i] = env->spsr;
3223
3224     i = bank_number(mode);
3225     env->regs[13] = env->banked_r13[i];
3226     env->regs[14] = env->banked_r14[i];
3227     env->spsr = env->banked_spsr[i];
3228 }
3229
3230 static void v7m_push(CPUARMState *env, uint32_t val)
3231 {
3232     CPUState *cs = CPU(arm_env_get_cpu(env));
3233
3234     env->regs[13] -= 4;
3235     stl_phys(cs->as, env->regs[13], val);
3236 }
3237
3238 static uint32_t v7m_pop(CPUARMState *env)
3239 {
3240     CPUState *cs = CPU(arm_env_get_cpu(env));
3241     uint32_t val;
3242
3243     val = ldl_phys(cs->as, env->regs[13]);
3244     env->regs[13] += 4;
3245     return val;
3246 }
3247
3248 /* Switch to V7M main or process stack pointer.  */
3249 static void switch_v7m_sp(CPUARMState *env, int process)
3250 {
3251     uint32_t tmp;
3252     if (env->v7m.current_sp != process) {
3253         tmp = env->v7m.other_sp;
3254         env->v7m.other_sp = env->regs[13];
3255         env->regs[13] = tmp;
3256         env->v7m.current_sp = process;
3257     }
3258 }
3259
3260 static void do_v7m_exception_exit(CPUARMState *env)
3261 {
3262     uint32_t type;
3263     uint32_t xpsr;
3264
3265     type = env->regs[15];
3266     if (env->v7m.exception != 0)
3267         armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
3268
3269     /* Switch to the target stack.  */
3270     switch_v7m_sp(env, (type & 4) != 0);
3271     /* Pop registers.  */
3272     env->regs[0] = v7m_pop(env);
3273     env->regs[1] = v7m_pop(env);
3274     env->regs[2] = v7m_pop(env);
3275     env->regs[3] = v7m_pop(env);
3276     env->regs[12] = v7m_pop(env);
3277     env->regs[14] = v7m_pop(env);
3278     env->regs[15] = v7m_pop(env);
3279     xpsr = v7m_pop(env);
3280     xpsr_write(env, xpsr, 0xfffffdff);
3281     /* Undo stack alignment.  */
3282     if (xpsr & 0x200)
3283         env->regs[13] |= 4;
3284     /* ??? The exception return type specifies Thread/Handler mode.  However
3285        this is also implied by the xPSR value. Not sure what to do
3286        if there is a mismatch.  */
3287     /* ??? Likewise for mismatches between the CONTROL register and the stack
3288        pointer.  */
3289 }
3290
3291 void arm_v7m_cpu_do_interrupt(CPUState *cs)
3292 {
3293     ARMCPU *cpu = ARM_CPU(cs);
3294     CPUARMState *env = &cpu->env;
3295     uint32_t xpsr = xpsr_read(env);
3296     uint32_t lr;
3297     uint32_t addr;
3298
3299     arm_log_exception(cs->exception_index);
3300
3301     lr = 0xfffffff1;
3302     if (env->v7m.current_sp)
3303         lr |= 4;
3304     if (env->v7m.exception == 0)
3305         lr |= 8;
3306
3307     /* For exceptions we just mark as pending on the NVIC, and let that
3308        handle it.  */
3309     /* TODO: Need to escalate if the current priority is higher than the
3310        one we're raising.  */
3311     switch (cs->exception_index) {
3312     case EXCP_UDEF:
3313         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
3314         return;
3315     case EXCP_SWI:
3316         /* The PC already points to the next instruction.  */
3317         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
3318         return;
3319     case EXCP_PREFETCH_ABORT:
3320     case EXCP_DATA_ABORT:
3321         /* TODO: if we implemented the MPU registers, this is where we
3322          * should set the MMFAR, etc from exception.fsr and exception.vaddress.
3323          */
3324         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
3325         return;
3326     case EXCP_BKPT:
3327         if (semihosting_enabled) {
3328             int nr;
3329             nr = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
3330             if (nr == 0xab) {
3331                 env->regs[15] += 2;
3332                 env->regs[0] = do_arm_semihosting(env);
3333                 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
3334                 return;
3335             }
3336         }
3337         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
3338         return;
3339     case EXCP_IRQ:
3340         env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
3341         break;
3342     case EXCP_EXCEPTION_EXIT:
3343         do_v7m_exception_exit(env);
3344         return;
3345     default:
3346         cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
3347         return; /* Never happens.  Keep compiler happy.  */
3348     }
3349
3350     /* Align stack pointer.  */
3351     /* ??? Should only do this if Configuration Control Register
3352        STACKALIGN bit is set.  */
3353     if (env->regs[13] & 4) {
3354         env->regs[13] -= 4;
3355         xpsr |= 0x200;
3356     }
3357     /* Switch to the handler mode.  */
3358     v7m_push(env, xpsr);
3359     v7m_push(env, env->regs[15]);
3360     v7m_push(env, env->regs[14]);
3361     v7m_push(env, env->regs[12]);
3362     v7m_push(env, env->regs[3]);
3363     v7m_push(env, env->regs[2]);
3364     v7m_push(env, env->regs[1]);
3365     v7m_push(env, env->regs[0]);
3366     switch_v7m_sp(env, 0);
3367     /* Clear IT bits */
3368     env->condexec_bits = 0;
3369     env->regs[14] = lr;
3370     addr = ldl_phys(cs->as, env->v7m.vecbase + env->v7m.exception * 4);
3371     env->regs[15] = addr & 0xfffffffe;
3372     env->thumb = addr & 1;
3373 }
3374
3375 /* Handle a CPU exception.  */
3376 void arm_cpu_do_interrupt(CPUState *cs)
3377 {
3378     ARMCPU *cpu = ARM_CPU(cs);
3379     CPUARMState *env = &cpu->env;
3380     uint32_t addr;
3381     uint32_t mask;
3382     int new_mode;
3383     uint32_t offset;
3384
3385     assert(!IS_M(env));
3386
3387     arm_log_exception(cs->exception_index);
3388
3389     /* TODO: Vectored interrupt controller.  */
3390     switch (cs->exception_index) {
3391     case EXCP_UDEF:
3392         new_mode = ARM_CPU_MODE_UND;
3393         addr = 0x04;
3394         mask = CPSR_I;
3395         if (env->thumb)
3396             offset = 2;
3397         else
3398             offset = 4;
3399         break;
3400     case EXCP_SWI:
3401         if (semihosting_enabled) {
3402             /* Check for semihosting interrupt.  */
3403             if (env->thumb) {
3404                 mask = arm_lduw_code(env, env->regs[15] - 2, env->bswap_code)
3405                     & 0xff;
3406             } else {
3407                 mask = arm_ldl_code(env, env->regs[15] - 4, env->bswap_code)
3408                     & 0xffffff;
3409             }
3410             /* Only intercept calls from privileged modes, to provide some
3411                semblance of security.  */
3412             if (((mask == 0x123456 && !env->thumb)
3413                     || (mask == 0xab && env->thumb))
3414                   && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
3415                 env->regs[0] = do_arm_semihosting(env);
3416                 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
3417                 return;
3418             }
3419         }
3420         new_mode = ARM_CPU_MODE_SVC;
3421         addr = 0x08;
3422         mask = CPSR_I;
3423         /* The PC already points to the next instruction.  */
3424         offset = 0;
3425         break;
3426     case EXCP_BKPT:
3427         /* See if this is a semihosting syscall.  */
3428         if (env->thumb && semihosting_enabled) {
3429             mask = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
3430             if (mask == 0xab
3431                   && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
3432                 env->regs[15] += 2;
3433                 env->regs[0] = do_arm_semihosting(env);
3434                 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
3435                 return;
3436             }
3437         }
3438         env->exception.fsr = 2;
3439         /* Fall through to prefetch abort.  */
3440     case EXCP_PREFETCH_ABORT:
3441         env->cp15.ifsr_el2 = env->exception.fsr;
3442         env->cp15.far_el[1] = deposit64(env->cp15.far_el[1], 32, 32,
3443                                         env->exception.vaddress);
3444         qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n",
3445                       env->cp15.ifsr_el2, (uint32_t)env->exception.vaddress);
3446         new_mode = ARM_CPU_MODE_ABT;
3447         addr = 0x0c;
3448         mask = CPSR_A | CPSR_I;
3449         offset = 4;
3450         break;
3451     case EXCP_DATA_ABORT:
3452         env->cp15.esr_el[1] = env->exception.fsr;
3453         env->cp15.far_el[1] = deposit64(env->cp15.far_el[1], 0, 32,
3454                                         env->exception.vaddress);
3455         qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n",
3456                       (uint32_t)env->cp15.esr_el[1],
3457                       (uint32_t)env->exception.vaddress);
3458         new_mode = ARM_CPU_MODE_ABT;
3459         addr = 0x10;
3460         mask = CPSR_A | CPSR_I;
3461         offset = 8;
3462         break;
3463     case EXCP_IRQ:
3464         new_mode = ARM_CPU_MODE_IRQ;
3465         addr = 0x18;
3466         /* Disable IRQ and imprecise data aborts.  */
3467         mask = CPSR_A | CPSR_I;
3468         offset = 4;
3469         break;
3470     case EXCP_FIQ:
3471         new_mode = ARM_CPU_MODE_FIQ;
3472         addr = 0x1c;
3473         /* Disable FIQ, IRQ and imprecise data aborts.  */
3474         mask = CPSR_A | CPSR_I | CPSR_F;
3475         offset = 4;
3476         break;
3477     default:
3478         cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
3479         return; /* Never happens.  Keep compiler happy.  */
3480     }
3481     /* High vectors.  */
3482     if (env->cp15.c1_sys & SCTLR_V) {
3483         /* when enabled, base address cannot be remapped.  */
3484         addr += 0xffff0000;
3485     } else {
3486         /* ARM v7 architectures provide a vector base address register to remap
3487          * the interrupt vector table.
3488          * This register is only followed in non-monitor mode, and has a secure
3489          * and un-secure copy. Since the cpu is always in a un-secure operation
3490          * and is never in monitor mode this feature is always active.
3491          * Note: only bits 31:5 are valid.
3492          */
3493         addr += env->cp15.vbar_el[1];
3494     }
3495     switch_mode (env, new_mode);
3496     env->spsr = cpsr_read(env);
3497     /* Clear IT bits.  */
3498     env->condexec_bits = 0;
3499     /* Switch to the new mode, and to the correct instruction set.  */
3500     env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
3501     env->daif |= mask;
3502     /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
3503      * and we should just guard the thumb mode on V4 */
3504     if (arm_feature(env, ARM_FEATURE_V4T)) {
3505         env->thumb = (env->cp15.c1_sys & SCTLR_TE) != 0;
3506     }
3507     env->regs[14] = env->regs[15] + offset;
3508     env->regs[15] = addr;
3509     cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
3510 }
3511
3512 /* Check section/page access permissions.
3513    Returns the page protection flags, or zero if the access is not
3514    permitted.  */
3515 static inline int check_ap(CPUARMState *env, int ap, int domain_prot,
3516                            int access_type, int is_user)
3517 {
3518   int prot_ro;
3519
3520   if (domain_prot == 3) {
3521     return PAGE_READ | PAGE_WRITE;
3522   }
3523
3524   if (access_type == 1)
3525       prot_ro = 0;
3526   else
3527       prot_ro = PAGE_READ;
3528
3529   switch (ap) {
3530   case 0:
3531       if (arm_feature(env, ARM_FEATURE_V7)) {
3532           return 0;
3533       }
3534       if (access_type == 1)
3535           return 0;
3536       switch (env->cp15.c1_sys & (SCTLR_S | SCTLR_R)) {
3537       case SCTLR_S:
3538           return is_user ? 0 : PAGE_READ;
3539       case SCTLR_R:
3540           return PAGE_READ;
3541       default:
3542           return 0;
3543       }
3544   case 1:
3545       return is_user ? 0 : PAGE_READ | PAGE_WRITE;
3546   case 2:
3547       if (is_user)
3548           return prot_ro;
3549       else
3550           return PAGE_READ | PAGE_WRITE;
3551   case 3:
3552       return PAGE_READ | PAGE_WRITE;
3553   case 4: /* Reserved.  */
3554       return 0;
3555   case 5:
3556       return is_user ? 0 : prot_ro;
3557   case 6:
3558       return prot_ro;
3559   case 7:
3560       if (!arm_feature (env, ARM_FEATURE_V6K))
3561           return 0;
3562       return prot_ro;
3563   default:
3564       abort();
3565   }
3566 }
3567
3568 static bool get_level1_table_address(CPUARMState *env, uint32_t *table,
3569                                          uint32_t address)
3570 {
3571     if (address & env->cp15.c2_mask) {
3572         if ((env->cp15.c2_control & TTBCR_PD1)) {
3573             /* Translation table walk disabled for TTBR1 */
3574             return false;
3575         }
3576         *table = env->cp15.ttbr1_el1 & 0xffffc000;
3577     } else {
3578         if ((env->cp15.c2_control & TTBCR_PD0)) {
3579             /* Translation table walk disabled for TTBR0 */
3580             return false;
3581         }
3582         *table = env->cp15.ttbr0_el1 & env->cp15.c2_base_mask;
3583     }
3584     *table |= (address >> 18) & 0x3ffc;
3585     return true;
3586 }
3587
3588 static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type,
3589                             int is_user, hwaddr *phys_ptr,
3590                             int *prot, target_ulong *page_size)
3591 {
3592     CPUState *cs = CPU(arm_env_get_cpu(env));
3593     int code;
3594     uint32_t table;
3595     uint32_t desc;
3596     int type;
3597     int ap;
3598     int domain = 0;
3599     int domain_prot;
3600     hwaddr phys_addr;
3601
3602     /* Pagetable walk.  */
3603     /* Lookup l1 descriptor.  */
3604     if (!get_level1_table_address(env, &table, address)) {
3605         /* Section translation fault if page walk is disabled by PD0 or PD1 */
3606         code = 5;
3607         goto do_fault;
3608     }
3609     desc = ldl_phys(cs->as, table);
3610     type = (desc & 3);
3611     domain = (desc >> 5) & 0x0f;
3612     domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
3613     if (type == 0) {
3614         /* Section translation fault.  */
3615         code = 5;
3616         goto do_fault;
3617     }
3618     if (domain_prot == 0 || domain_prot == 2) {
3619         if (type == 2)
3620             code = 9; /* Section domain fault.  */
3621         else
3622             code = 11; /* Page domain fault.  */
3623         goto do_fault;
3624     }
3625     if (type == 2) {
3626         /* 1Mb section.  */
3627         phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
3628         ap = (desc >> 10) & 3;
3629         code = 13;
3630         *page_size = 1024 * 1024;
3631     } else {
3632         /* Lookup l2 entry.  */
3633         if (type == 1) {
3634             /* Coarse pagetable.  */
3635             table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
3636         } else {
3637             /* Fine pagetable.  */
3638             table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
3639         }
3640         desc = ldl_phys(cs->as, table);
3641         switch (desc & 3) {
3642         case 0: /* Page translation fault.  */
3643             code = 7;
3644             goto do_fault;
3645         case 1: /* 64k page.  */
3646             phys_addr = (desc & 0xffff0000) | (address & 0xffff);
3647             ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
3648             *page_size = 0x10000;
3649             break;
3650         case 2: /* 4k page.  */
3651             phys_addr = (desc & 0xfffff000) | (address & 0xfff);
3652             ap = (desc >> (4 + ((address >> 9) & 6))) & 3;
3653             *page_size = 0x1000;
3654             break;
3655         case 3: /* 1k page.  */
3656             if (type == 1) {
3657                 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
3658                     phys_addr = (desc & 0xfffff000) | (address & 0xfff);
3659                 } else {
3660                     /* Page translation fault.  */
3661                     code = 7;
3662                     goto do_fault;
3663                 }
3664             } else {
3665                 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
3666             }
3667             ap = (desc >> 4) & 3;
3668             *page_size = 0x400;
3669             break;
3670         default:
3671             /* Never happens, but compiler isn't smart enough to tell.  */
3672             abort();
3673         }
3674         code = 15;
3675     }
3676     *prot = check_ap(env, ap, domain_prot, access_type, is_user);
3677     if (!*prot) {
3678         /* Access permission fault.  */
3679         goto do_fault;
3680     }
3681     *prot |= PAGE_EXEC;
3682     *phys_ptr = phys_addr;
3683     return 0;
3684 do_fault:
3685     return code | (domain << 4);
3686 }
3687
3688 static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type,
3689                             int is_user, hwaddr *phys_ptr,
3690                             int *prot, target_ulong *page_size)
3691 {
3692     CPUState *cs = CPU(arm_env_get_cpu(env));
3693     int code;
3694     uint32_t table;
3695     uint32_t desc;
3696     uint32_t xn;
3697     uint32_t pxn = 0;
3698     int type;
3699     int ap;
3700     int domain = 0;
3701     int domain_prot;
3702     hwaddr phys_addr;
3703
3704     /* Pagetable walk.  */
3705     /* Lookup l1 descriptor.  */
3706     if (!get_level1_table_address(env, &table, address)) {
3707         /* Section translation fault if page walk is disabled by PD0 or PD1 */
3708         code = 5;
3709         goto do_fault;
3710     }
3711     desc = ldl_phys(cs->as, table);
3712     type = (desc & 3);
3713     if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
3714         /* Section translation fault, or attempt to use the encoding
3715          * which is Reserved on implementations without PXN.
3716          */
3717         code = 5;
3718         goto do_fault;
3719     }
3720     if ((type == 1) || !(desc & (1 << 18))) {
3721         /* Page or Section.  */
3722         domain = (desc >> 5) & 0x0f;
3723     }
3724     domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
3725     if (domain_prot == 0 || domain_prot == 2) {
3726         if (type != 1) {
3727             code = 9; /* Section domain fault.  */
3728         } else {
3729             code = 11; /* Page domain fault.  */
3730         }
3731         goto do_fault;
3732     }
3733     if (type != 1) {
3734         if (desc & (1 << 18)) {
3735             /* Supersection.  */
3736             phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
3737             *page_size = 0x1000000;
3738         } else {
3739             /* Section.  */
3740             phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
3741             *page_size = 0x100000;
3742         }
3743         ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
3744         xn = desc & (1 << 4);
3745         pxn = desc & 1;
3746         code = 13;
3747     } else {
3748         if (arm_feature(env, ARM_FEATURE_PXN)) {
3749             pxn = (desc >> 2) & 1;
3750         }
3751         /* Lookup l2 entry.  */
3752         table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
3753         desc = ldl_phys(cs->as, table);
3754         ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
3755         switch (desc & 3) {
3756         case 0: /* Page translation fault.  */
3757             code = 7;
3758             goto do_fault;
3759         case 1: /* 64k page.  */
3760             phys_addr = (desc & 0xffff0000) | (address & 0xffff);
3761             xn = desc & (1 << 15);
3762             *page_size = 0x10000;
3763             break;
3764         case 2: case 3: /* 4k page.  */
3765             phys_addr = (desc & 0xfffff000) | (address & 0xfff);
3766             xn = desc & 1;
3767             *page_size = 0x1000;
3768             break;
3769         default:
3770             /* Never happens, but compiler isn't smart enough to tell.  */
3771             abort();
3772         }
3773         code = 15;
3774     }
3775     if (domain_prot == 3) {
3776         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
3777     } else {
3778         if (pxn && !is_user) {
3779             xn = 1;
3780         }
3781         if (xn && access_type == 2)
3782             goto do_fault;
3783
3784         /* The simplified model uses AP[0] as an access control bit.  */
3785         if ((env->cp15.c1_sys & SCTLR_AFE) && (ap & 1) == 0) {
3786             /* Access flag fault.  */
3787             code = (code == 15) ? 6 : 3;
3788             goto do_fault;
3789         }
3790         *prot = check_ap(env, ap, domain_prot, access_type, is_user);
3791         if (!*prot) {
3792             /* Access permission fault.  */
3793             goto do_fault;
3794         }
3795         if (!xn) {
3796             *prot |= PAGE_EXEC;
3797         }
3798     }
3799     *phys_ptr = phys_addr;
3800     return 0;
3801 do_fault:
3802     return code | (domain << 4);
3803 }
3804
3805 /* Fault type for long-descriptor MMU fault reporting; this corresponds
3806  * to bits [5..2] in the STATUS field in long-format DFSR/IFSR.
3807  */
3808 typedef enum {
3809     translation_fault = 1,
3810     access_fault = 2,
3811     permission_fault = 3,
3812 } MMUFaultType;
3813
3814 static int get_phys_addr_lpae(CPUARMState *env, target_ulong address,
3815                               int access_type, int is_user,
3816                               hwaddr *phys_ptr, int *prot,
3817                               target_ulong *page_size_ptr)
3818 {
3819     CPUState *cs = CPU(arm_env_get_cpu(env));
3820     /* Read an LPAE long-descriptor translation table. */
3821     MMUFaultType fault_type = translation_fault;
3822     uint32_t level = 1;
3823     uint32_t epd;
3824     int32_t tsz;
3825     uint32_t tg;
3826     uint64_t ttbr;
3827     int ttbr_select;
3828     hwaddr descaddr, descmask;
3829     uint32_t tableattrs;
3830     target_ulong page_size;
3831     uint32_t attrs;
3832     int32_t granule_sz = 9;
3833     int32_t va_size = 32;
3834     int32_t tbi = 0;
3835
3836     if (arm_el_is_aa64(env, 1)) {
3837         va_size = 64;
3838         if (extract64(address, 55, 1))
3839             tbi = extract64(env->cp15.c2_control, 38, 1);
3840         else
3841             tbi = extract64(env->cp15.c2_control, 37, 1);
3842         tbi *= 8;
3843     }
3844
3845     /* Determine whether this address is in the region controlled by
3846      * TTBR0 or TTBR1 (or if it is in neither region and should fault).
3847      * This is a Non-secure PL0/1 stage 1 translation, so controlled by
3848      * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
3849      */
3850     uint32_t t0sz = extract32(env->cp15.c2_control, 0, 6);
3851     if (arm_el_is_aa64(env, 1)) {
3852         t0sz = MIN(t0sz, 39);
3853         t0sz = MAX(t0sz, 16);
3854     }
3855     uint32_t t1sz = extract32(env->cp15.c2_control, 16, 6);
3856     if (arm_el_is_aa64(env, 1)) {
3857         t1sz = MIN(t1sz, 39);
3858         t1sz = MAX(t1sz, 16);
3859     }
3860     if (t0sz && !extract64(address, va_size - t0sz, t0sz - tbi)) {
3861         /* there is a ttbr0 region and we are in it (high bits all zero) */
3862         ttbr_select = 0;
3863     } else if (t1sz && !extract64(~address, va_size - t1sz, t1sz - tbi)) {
3864         /* there is a ttbr1 region and we are in it (high bits all one) */
3865         ttbr_select = 1;
3866     } else if (!t0sz) {
3867         /* ttbr0 region is "everything not in the ttbr1 region" */
3868         ttbr_select = 0;
3869     } else if (!t1sz) {
3870         /* ttbr1 region is "everything not in the ttbr0 region" */
3871         ttbr_select = 1;
3872     } else {
3873         /* in the gap between the two regions, this is a Translation fault */
3874         fault_type = translation_fault;
3875         goto do_fault;
3876     }
3877
3878     /* Note that QEMU ignores shareability and cacheability attributes,
3879      * so we don't need to do anything with the SH, ORGN, IRGN fields
3880      * in the TTBCR.  Similarly, TTBCR:A1 selects whether we get the
3881      * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
3882      * implement any ASID-like capability so we can ignore it (instead
3883      * we will always flush the TLB any time the ASID is changed).
3884      */
3885     if (ttbr_select == 0) {
3886         ttbr = env->cp15.ttbr0_el1;
3887         epd = extract32(env->cp15.c2_control, 7, 1);
3888         tsz = t0sz;
3889
3890         tg = extract32(env->cp15.c2_control, 14, 2);
3891         if (tg == 1) { /* 64KB pages */
3892             granule_sz = 13;
3893         }
3894         if (tg == 2) { /* 16KB pages */
3895             granule_sz = 11;
3896         }
3897     } else {
3898         ttbr = env->cp15.ttbr1_el1;
3899         epd = extract32(env->cp15.c2_control, 23, 1);
3900         tsz = t1sz;
3901
3902         tg = extract32(env->cp15.c2_control, 30, 2);
3903         if (tg == 3)  { /* 64KB pages */
3904             granule_sz = 13;
3905         }
3906         if (tg == 1) { /* 16KB pages */
3907             granule_sz = 11;
3908         }
3909     }
3910
3911     if (epd) {
3912         /* Translation table walk disabled => Translation fault on TLB miss */
3913         goto do_fault;
3914     }
3915
3916     /* The starting level depends on the virtual address size which can be
3917      * up to 48-bits and the translation granule size.
3918      */
3919     if ((va_size - tsz) > (granule_sz * 4 + 3)) {
3920         level = 0;
3921     } else if ((va_size - tsz) > (granule_sz * 3 + 3)) {
3922         level = 1;
3923     } else {
3924         level = 2;
3925     }
3926
3927     /* Clear the vaddr bits which aren't part of the within-region address,
3928      * so that we don't have to special case things when calculating the
3929      * first descriptor address.
3930      */
3931     if (tsz) {
3932         address &= (1ULL << (va_size - tsz)) - 1;
3933     }
3934
3935     descmask = (1ULL << (granule_sz + 3)) - 1;
3936
3937     /* Now we can extract the actual base address from the TTBR */
3938     descaddr = extract64(ttbr, 0, 48);
3939     descaddr &= ~((1ULL << (va_size - tsz - (granule_sz * (4 - level)))) - 1);
3940
3941     tableattrs = 0;
3942     for (;;) {
3943         uint64_t descriptor;
3944
3945         descaddr |= (address >> (granule_sz * (4 - level))) & descmask;
3946         descaddr &= ~7ULL;
3947         descriptor = ldq_phys(cs->as, descaddr);
3948         if (!(descriptor & 1) ||
3949             (!(descriptor & 2) && (level == 3))) {
3950             /* Invalid, or the Reserved level 3 encoding */
3951             goto do_fault;
3952         }
3953         descaddr = descriptor & 0xfffffff000ULL;
3954
3955         if ((descriptor & 2) && (level < 3)) {
3956             /* Table entry. The top five bits are attributes which  may
3957              * propagate down through lower levels of the table (and
3958              * which are all arranged so that 0 means "no effect", so
3959              * we can gather them up by ORing in the bits at each level).
3960              */
3961             tableattrs |= extract64(descriptor, 59, 5);
3962             level++;
3963             continue;
3964         }
3965         /* Block entry at level 1 or 2, or page entry at level 3.
3966          * These are basically the same thing, although the number
3967          * of bits we pull in from the vaddr varies.
3968          */
3969         page_size = (1ULL << ((granule_sz * (4 - level)) + 3));
3970         descaddr |= (address & (page_size - 1));
3971         /* Extract attributes from the descriptor and merge with table attrs */
3972         attrs = extract64(descriptor, 2, 10)
3973             | (extract64(descriptor, 52, 12) << 10);
3974         attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
3975         attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */
3976         /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
3977          * means "force PL1 access only", which means forcing AP[1] to 0.
3978          */
3979         if (extract32(tableattrs, 2, 1)) {
3980             attrs &= ~(1 << 4);
3981         }
3982         /* Since we're always in the Non-secure state, NSTable is ignored. */
3983         break;
3984     }
3985     /* Here descaddr is the final physical address, and attributes
3986      * are all in attrs.
3987      */
3988     fault_type = access_fault;
3989     if ((attrs & (1 << 8)) == 0) {
3990         /* Access flag */
3991         goto do_fault;
3992     }
3993     fault_type = permission_fault;
3994     if (is_user && !(attrs & (1 << 4))) {
3995         /* Unprivileged access not enabled */
3996         goto do_fault;
3997     }
3998     *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
3999     if ((arm_feature(env, ARM_FEATURE_V8) && is_user && (attrs & (1 << 12))) ||
4000         (!arm_feature(env, ARM_FEATURE_V8) && (attrs & (1 << 12))) ||
4001         (!is_user && (attrs & (1 << 11)))) {
4002         /* XN/UXN or PXN. Since we only implement EL0/EL1 we unconditionally
4003          * treat XN/UXN as UXN for v8.
4004          */
4005         if (access_type == 2) {
4006             goto do_fault;
4007         }
4008         *prot &= ~PAGE_EXEC;
4009     }
4010     if (attrs & (1 << 5)) {
4011         /* Write access forbidden */
4012         if (access_type == 1) {
4013             goto do_fault;
4014         }
4015         *prot &= ~PAGE_WRITE;
4016     }
4017
4018     *phys_ptr = descaddr;
4019     *page_size_ptr = page_size;
4020     return 0;
4021
4022 do_fault:
4023     /* Long-descriptor format IFSR/DFSR value */
4024     return (1 << 9) | (fault_type << 2) | level;
4025 }
4026
4027 static int get_phys_addr_mpu(CPUARMState *env, uint32_t address,
4028                              int access_type, int is_user,
4029                              hwaddr *phys_ptr, int *prot)
4030 {
4031     int n;
4032     uint32_t mask;
4033     uint32_t base;
4034
4035     *phys_ptr = address;
4036     for (n = 7; n >= 0; n--) {
4037         base = env->cp15.c6_region[n];
4038         if ((base & 1) == 0)
4039             continue;
4040         mask = 1 << ((base >> 1) & 0x1f);
4041         /* Keep this shift separate from the above to avoid an
4042            (undefined) << 32.  */
4043         mask = (mask << 1) - 1;
4044         if (((base ^ address) & ~mask) == 0)
4045             break;
4046     }
4047     if (n < 0)
4048         return 2;
4049
4050     if (access_type == 2) {
4051         mask = env->cp15.pmsav5_insn_ap;
4052     } else {
4053         mask = env->cp15.pmsav5_data_ap;
4054     }
4055     mask = (mask >> (n * 4)) & 0xf;
4056     switch (mask) {
4057     case 0:
4058         return 1;
4059     case 1:
4060         if (is_user)
4061           return 1;
4062         *prot = PAGE_READ | PAGE_WRITE;
4063         break;
4064     case 2:
4065         *prot = PAGE_READ;
4066         if (!is_user)
4067             *prot |= PAGE_WRITE;
4068         break;
4069     case 3:
4070         *prot = PAGE_READ | PAGE_WRITE;
4071         break;
4072     case 5:
4073         if (is_user)
4074             return 1;
4075         *prot = PAGE_READ;
4076         break;
4077     case 6:
4078         *prot = PAGE_READ;
4079         break;
4080     default:
4081         /* Bad permission.  */
4082         return 1;
4083     }
4084     *prot |= PAGE_EXEC;
4085     return 0;
4086 }
4087
4088 /* get_phys_addr - get the physical address for this virtual address
4089  *
4090  * Find the physical address corresponding to the given virtual address,
4091  * by doing a translation table walk on MMU based systems or using the
4092  * MPU state on MPU based systems.
4093  *
4094  * Returns 0 if the translation was successful. Otherwise, phys_ptr,
4095  * prot and page_size are not filled in, and the return value provides
4096  * information on why the translation aborted, in the format of a
4097  * DFSR/IFSR fault register, with the following caveats:
4098  *  * we honour the short vs long DFSR format differences.
4099  *  * the WnR bit is never set (the caller must do this).
4100  *  * for MPU based systems we don't bother to return a full FSR format
4101  *    value.
4102  *
4103  * @env: CPUARMState
4104  * @address: virtual address to get physical address for
4105  * @access_type: 0 for read, 1 for write, 2 for execute
4106  * @is_user: 0 for privileged access, 1 for user
4107  * @phys_ptr: set to the physical address corresponding to the virtual address
4108  * @prot: set to the permissions for the page containing phys_ptr
4109  * @page_size: set to the size of the page containing phys_ptr
4110  */
4111 static inline int get_phys_addr(CPUARMState *env, target_ulong address,
4112                                 int access_type, int is_user,
4113                                 hwaddr *phys_ptr, int *prot,
4114                                 target_ulong *page_size)
4115 {
4116     /* Fast Context Switch Extension.  */
4117     if (address < 0x02000000)
4118         address += env->cp15.c13_fcse;
4119
4120     if ((env->cp15.c1_sys & SCTLR_M) == 0) {
4121         /* MMU/MPU disabled.  */
4122         *phys_ptr = address;
4123         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
4124         *page_size = TARGET_PAGE_SIZE;
4125         return 0;
4126     } else if (arm_feature(env, ARM_FEATURE_MPU)) {
4127         *page_size = TARGET_PAGE_SIZE;
4128         return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr,
4129                                  prot);
4130     } else if (extended_addresses_enabled(env)) {
4131         return get_phys_addr_lpae(env, address, access_type, is_user, phys_ptr,
4132                                   prot, page_size);
4133     } else if (env->cp15.c1_sys & SCTLR_XP) {
4134         return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr,
4135                                 prot, page_size);
4136     } else {
4137         return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr,
4138                                 prot, page_size);
4139     }
4140 }
4141
4142 int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
4143                              int access_type, int mmu_idx)
4144 {
4145     ARMCPU *cpu = ARM_CPU(cs);
4146     CPUARMState *env = &cpu->env;
4147     hwaddr phys_addr;
4148     target_ulong page_size;
4149     int prot;
4150     int ret, is_user;
4151     uint32_t syn;
4152     bool same_el = (arm_current_pl(env) != 0);
4153
4154     is_user = mmu_idx == MMU_USER_IDX;
4155     ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot,
4156                         &page_size);
4157     if (ret == 0) {
4158         /* Map a single [sub]page.  */
4159         phys_addr &= ~(hwaddr)0x3ff;
4160         address &= ~(target_ulong)0x3ff;
4161         tlb_set_page(cs, address, phys_addr, prot, mmu_idx, page_size);
4162         return 0;
4163     }
4164
4165     /* AArch64 syndrome does not have an LPAE bit */
4166     syn = ret & ~(1 << 9);
4167
4168     /* For insn and data aborts we assume there is no instruction syndrome
4169      * information; this is always true for exceptions reported to EL1.
4170      */
4171     if (access_type == 2) {
4172         syn = syn_insn_abort(same_el, 0, 0, syn);
4173         cs->exception_index = EXCP_PREFETCH_ABORT;
4174     } else {
4175         syn = syn_data_abort(same_el, 0, 0, 0, access_type == 1, syn);
4176         if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6)) {
4177             ret |= (1 << 11);
4178         }
4179         cs->exception_index = EXCP_DATA_ABORT;
4180     }
4181
4182     env->exception.syndrome = syn;
4183     env->exception.vaddress = address;
4184     env->exception.fsr = ret;
4185     return 1;
4186 }
4187
4188 hwaddr arm_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
4189 {
4190     ARMCPU *cpu = ARM_CPU(cs);
4191     hwaddr phys_addr;
4192     target_ulong page_size;
4193     int prot;
4194     int ret;
4195
4196     ret = get_phys_addr(&cpu->env, addr, 0, 0, &phys_addr, &prot, &page_size);
4197
4198     if (ret != 0) {
4199         return -1;
4200     }
4201
4202     return phys_addr;
4203 }
4204
4205 void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
4206 {
4207     if ((env->uncached_cpsr & CPSR_M) == mode) {
4208         env->regs[13] = val;
4209     } else {
4210         env->banked_r13[bank_number(mode)] = val;
4211     }
4212 }
4213
4214 uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
4215 {
4216     if ((env->uncached_cpsr & CPSR_M) == mode) {
4217         return env->regs[13];
4218     } else {
4219         return env->banked_r13[bank_number(mode)];
4220     }
4221 }
4222
4223 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
4224 {
4225     ARMCPU *cpu = arm_env_get_cpu(env);
4226
4227     switch (reg) {
4228     case 0: /* APSR */
4229         return xpsr_read(env) & 0xf8000000;
4230     case 1: /* IAPSR */
4231         return xpsr_read(env) & 0xf80001ff;
4232     case 2: /* EAPSR */
4233         return xpsr_read(env) & 0xff00fc00;
4234     case 3: /* xPSR */
4235         return xpsr_read(env) & 0xff00fdff;
4236     case 5: /* IPSR */
4237         return xpsr_read(env) & 0x000001ff;
4238     case 6: /* EPSR */
4239         return xpsr_read(env) & 0x0700fc00;
4240     case 7: /* IEPSR */
4241         return xpsr_read(env) & 0x0700edff;
4242     case 8: /* MSP */
4243         return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
4244     case 9: /* PSP */
4245         return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
4246     case 16: /* PRIMASK */
4247         return (env->daif & PSTATE_I) != 0;
4248     case 17: /* BASEPRI */
4249     case 18: /* BASEPRI_MAX */
4250         return env->v7m.basepri;
4251     case 19: /* FAULTMASK */
4252         return (env->daif & PSTATE_F) != 0;
4253     case 20: /* CONTROL */
4254         return env->v7m.control;
4255     default:
4256         /* ??? For debugging only.  */
4257         cpu_abort(CPU(cpu), "Unimplemented system register read (%d)\n", reg);
4258         return 0;
4259     }
4260 }
4261
4262 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
4263 {
4264     ARMCPU *cpu = arm_env_get_cpu(env);
4265
4266     switch (reg) {
4267     case 0: /* APSR */
4268         xpsr_write(env, val, 0xf8000000);
4269         break;
4270     case 1: /* IAPSR */
4271         xpsr_write(env, val, 0xf8000000);
4272         break;
4273     case 2: /* EAPSR */
4274         xpsr_write(env, val, 0xfe00fc00);
4275         break;
4276     case 3: /* xPSR */
4277         xpsr_write(env, val, 0xfe00fc00);
4278         break;
4279     case 5: /* IPSR */
4280         /* IPSR bits are readonly.  */
4281         break;
4282     case 6: /* EPSR */
4283         xpsr_write(env, val, 0x0600fc00);
4284         break;
4285     case 7: /* IEPSR */
4286         xpsr_write(env, val, 0x0600fc00);
4287         break;
4288     case 8: /* MSP */
4289         if (env->v7m.current_sp)
4290             env->v7m.other_sp = val;
4291         else
4292             env->regs[13] = val;
4293         break;
4294     case 9: /* PSP */
4295         if (env->v7m.current_sp)
4296             env->regs[13] = val;
4297         else
4298             env->v7m.other_sp = val;
4299         break;
4300     case 16: /* PRIMASK */
4301         if (val & 1) {
4302             env->daif |= PSTATE_I;
4303         } else {
4304             env->daif &= ~PSTATE_I;
4305         }
4306         break;
4307     case 17: /* BASEPRI */
4308         env->v7m.basepri = val & 0xff;
4309         break;
4310     case 18: /* BASEPRI_MAX */
4311         val &= 0xff;
4312         if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
4313             env->v7m.basepri = val;
4314         break;
4315     case 19: /* FAULTMASK */
4316         if (val & 1) {
4317             env->daif |= PSTATE_F;
4318         } else {
4319             env->daif &= ~PSTATE_F;
4320         }
4321         break;
4322     case 20: /* CONTROL */
4323         env->v7m.control = val & 3;
4324         switch_v7m_sp(env, (val & 2) != 0);
4325         break;
4326     default:
4327         /* ??? For debugging only.  */
4328         cpu_abort(CPU(cpu), "Unimplemented system register write (%d)\n", reg);
4329         return;
4330     }
4331 }
4332
4333 #endif
4334
4335 void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
4336 {
4337     /* Implement DC ZVA, which zeroes a fixed-length block of memory.
4338      * Note that we do not implement the (architecturally mandated)
4339      * alignment fault for attempts to use this on Device memory
4340      * (which matches the usual QEMU behaviour of not implementing either
4341      * alignment faults or any memory attribute handling).
4342      */
4343
4344     ARMCPU *cpu = arm_env_get_cpu(env);
4345     uint64_t blocklen = 4 << cpu->dcz_blocksize;
4346     uint64_t vaddr = vaddr_in & ~(blocklen - 1);
4347
4348 #ifndef CONFIG_USER_ONLY
4349     {
4350         /* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than
4351          * the block size so we might have to do more than one TLB lookup.
4352          * We know that in fact for any v8 CPU the page size is at least 4K
4353          * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only
4354          * 1K as an artefact of legacy v5 subpage support being present in the
4355          * same QEMU executable.
4356          */
4357         int maxidx = DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE);
4358         void *hostaddr[maxidx];
4359         int try, i;
4360
4361         for (try = 0; try < 2; try++) {
4362
4363             for (i = 0; i < maxidx; i++) {
4364                 hostaddr[i] = tlb_vaddr_to_host(env,
4365                                                 vaddr + TARGET_PAGE_SIZE * i,
4366                                                 1, cpu_mmu_index(env));
4367                 if (!hostaddr[i]) {
4368                     break;
4369                 }
4370             }
4371             if (i == maxidx) {
4372                 /* If it's all in the TLB it's fair game for just writing to;
4373                  * we know we don't need to update dirty status, etc.
4374                  */
4375                 for (i = 0; i < maxidx - 1; i++) {
4376                     memset(hostaddr[i], 0, TARGET_PAGE_SIZE);
4377                 }
4378                 memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE));
4379                 return;
4380             }
4381             /* OK, try a store and see if we can populate the tlb. This
4382              * might cause an exception if the memory isn't writable,
4383              * in which case we will longjmp out of here. We must for
4384              * this purpose use the actual register value passed to us
4385              * so that we get the fault address right.
4386              */
4387             helper_ret_stb_mmu(env, vaddr_in, 0, cpu_mmu_index(env), GETRA());
4388             /* Now we can populate the other TLB entries, if any */
4389             for (i = 0; i < maxidx; i++) {
4390                 uint64_t va = vaddr + TARGET_PAGE_SIZE * i;
4391                 if (va != (vaddr_in & TARGET_PAGE_MASK)) {
4392                     helper_ret_stb_mmu(env, va, 0, cpu_mmu_index(env), GETRA());
4393                 }
4394             }
4395         }
4396
4397         /* Slow path (probably attempt to do this to an I/O device or
4398          * similar, or clearing of a block of code we have translations
4399          * cached for). Just do a series of byte writes as the architecture
4400          * demands. It's not worth trying to use a cpu_physical_memory_map(),
4401          * memset(), unmap() sequence here because:
4402          *  + we'd need to account for the blocksize being larger than a page
4403          *  + the direct-RAM access case is almost always going to be dealt
4404          *    with in the fastpath code above, so there's no speed benefit
4405          *  + we would have to deal with the map returning NULL because the
4406          *    bounce buffer was in use
4407          */
4408         for (i = 0; i < blocklen; i++) {
4409             helper_ret_stb_mmu(env, vaddr + i, 0, cpu_mmu_index(env), GETRA());
4410         }
4411     }
4412 #else
4413     memset(g2h(vaddr), 0, blocklen);
4414 #endif
4415 }
4416
4417 /* Note that signed overflow is undefined in C.  The following routines are
4418    careful to use unsigned types where modulo arithmetic is required.
4419    Failure to do so _will_ break on newer gcc.  */
4420
4421 /* Signed saturating arithmetic.  */
4422
4423 /* Perform 16-bit signed saturating addition.  */
4424 static inline uint16_t add16_sat(uint16_t a, uint16_t b)
4425 {
4426     uint16_t res;
4427
4428     res = a + b;
4429     if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
4430         if (a & 0x8000)
4431             res = 0x8000;
4432         else
4433             res = 0x7fff;
4434     }
4435     return res;
4436 }
4437
4438 /* Perform 8-bit signed saturating addition.  */
4439 static inline uint8_t add8_sat(uint8_t a, uint8_t b)
4440 {
4441     uint8_t res;
4442
4443     res = a + b;
4444     if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
4445         if (a & 0x80)
4446             res = 0x80;
4447         else
4448             res = 0x7f;
4449     }
4450     return res;
4451 }
4452
4453 /* Perform 16-bit signed saturating subtraction.  */
4454 static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
4455 {
4456     uint16_t res;
4457
4458     res = a - b;
4459     if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
4460         if (a & 0x8000)
4461             res = 0x8000;
4462         else
4463             res = 0x7fff;
4464     }
4465     return res;
4466 }
4467
4468 /* Perform 8-bit signed saturating subtraction.  */
4469 static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
4470 {
4471     uint8_t res;
4472
4473     res = a - b;
4474     if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
4475         if (a & 0x80)
4476             res = 0x80;
4477         else
4478             res = 0x7f;
4479     }
4480     return res;
4481 }
4482
4483 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
4484 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
4485 #define ADD8(a, b, n)  RESULT(add8_sat(a, b), n, 8);
4486 #define SUB8(a, b, n)  RESULT(sub8_sat(a, b), n, 8);
4487 #define PFX q
4488
4489 #include "op_addsub.h"
4490
4491 /* Unsigned saturating arithmetic.  */
4492 static inline uint16_t add16_usat(uint16_t a, uint16_t b)
4493 {
4494     uint16_t res;
4495     res = a + b;
4496     if (res < a)
4497         res = 0xffff;
4498     return res;
4499 }
4500
4501 static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
4502 {
4503     if (a > b)
4504         return a - b;
4505     else
4506         return 0;
4507 }
4508
4509 static inline uint8_t add8_usat(uint8_t a, uint8_t b)
4510 {
4511     uint8_t res;
4512     res = a + b;
4513     if (res < a)
4514         res = 0xff;
4515     return res;
4516 }
4517
4518 static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
4519 {
4520     if (a > b)
4521         return a - b;
4522     else
4523         return 0;
4524 }
4525
4526 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
4527 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
4528 #define ADD8(a, b, n)  RESULT(add8_usat(a, b), n, 8);
4529 #define SUB8(a, b, n)  RESULT(sub8_usat(a, b), n, 8);
4530 #define PFX uq
4531
4532 #include "op_addsub.h"
4533
4534 /* Signed modulo arithmetic.  */
4535 #define SARITH16(a, b, n, op) do { \
4536     int32_t sum; \
4537     sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
4538     RESULT(sum, n, 16); \
4539     if (sum >= 0) \
4540         ge |= 3 << (n * 2); \
4541     } while(0)
4542
4543 #define SARITH8(a, b, n, op) do { \
4544     int32_t sum; \
4545     sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
4546     RESULT(sum, n, 8); \
4547     if (sum >= 0) \
4548         ge |= 1 << n; \
4549     } while(0)
4550
4551
4552 #define ADD16(a, b, n) SARITH16(a, b, n, +)
4553 #define SUB16(a, b, n) SARITH16(a, b, n, -)
4554 #define ADD8(a, b, n)  SARITH8(a, b, n, +)
4555 #define SUB8(a, b, n)  SARITH8(a, b, n, -)
4556 #define PFX s
4557 #define ARITH_GE
4558
4559 #include "op_addsub.h"
4560
4561 /* Unsigned modulo arithmetic.  */
4562 #define ADD16(a, b, n) do { \
4563     uint32_t sum; \
4564     sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
4565     RESULT(sum, n, 16); \
4566     if ((sum >> 16) == 1) \
4567         ge |= 3 << (n * 2); \
4568     } while(0)
4569
4570 #define ADD8(a, b, n) do { \
4571     uint32_t sum; \
4572     sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
4573     RESULT(sum, n, 8); \
4574     if ((sum >> 8) == 1) \
4575         ge |= 1 << n; \
4576     } while(0)
4577
4578 #define SUB16(a, b, n) do { \
4579     uint32_t sum; \
4580     sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
4581     RESULT(sum, n, 16); \
4582     if ((sum >> 16) == 0) \
4583         ge |= 3 << (n * 2); \
4584     } while(0)
4585
4586 #define SUB8(a, b, n) do { \
4587     uint32_t sum; \
4588     sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
4589     RESULT(sum, n, 8); \
4590     if ((sum >> 8) == 0) \
4591         ge |= 1 << n; \
4592     } while(0)
4593
4594 #define PFX u
4595 #define ARITH_GE
4596
4597 #include "op_addsub.h"
4598
4599 /* Halved signed arithmetic.  */
4600 #define ADD16(a, b, n) \
4601   RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
4602 #define SUB16(a, b, n) \
4603   RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
4604 #define ADD8(a, b, n) \
4605   RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
4606 #define SUB8(a, b, n) \
4607   RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
4608 #define PFX sh
4609
4610 #include "op_addsub.h"
4611
4612 /* Halved unsigned arithmetic.  */
4613 #define ADD16(a, b, n) \
4614   RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
4615 #define SUB16(a, b, n) \
4616   RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
4617 #define ADD8(a, b, n) \
4618   RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
4619 #define SUB8(a, b, n) \
4620   RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
4621 #define PFX uh
4622
4623 #include "op_addsub.h"
4624
4625 static inline uint8_t do_usad(uint8_t a, uint8_t b)
4626 {
4627     if (a > b)
4628         return a - b;
4629     else
4630         return b - a;
4631 }
4632
4633 /* Unsigned sum of absolute byte differences.  */
4634 uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
4635 {
4636     uint32_t sum;
4637     sum = do_usad(a, b);
4638     sum += do_usad(a >> 8, b >> 8);
4639     sum += do_usad(a >> 16, b >>16);
4640     sum += do_usad(a >> 24, b >> 24);
4641     return sum;
4642 }
4643
4644 /* For ARMv6 SEL instruction.  */
4645 uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
4646 {
4647     uint32_t mask;
4648
4649     mask = 0;
4650     if (flags & 1)
4651         mask |= 0xff;
4652     if (flags & 2)
4653         mask |= 0xff00;
4654     if (flags & 4)
4655         mask |= 0xff0000;
4656     if (flags & 8)
4657         mask |= 0xff000000;
4658     return (a & mask) | (b & ~mask);
4659 }
4660
4661 /* VFP support.  We follow the convention used for VFP instructions:
4662    Single precision routines have a "s" suffix, double precision a
4663    "d" suffix.  */
4664
4665 /* Convert host exception flags to vfp form.  */
4666 static inline int vfp_exceptbits_from_host(int host_bits)
4667 {
4668     int target_bits = 0;
4669
4670     if (host_bits & float_flag_invalid)
4671         target_bits |= 1;
4672     if (host_bits & float_flag_divbyzero)
4673         target_bits |= 2;
4674     if (host_bits & float_flag_overflow)
4675         target_bits |= 4;
4676     if (host_bits & (float_flag_underflow | float_flag_output_denormal))
4677         target_bits |= 8;
4678     if (host_bits & float_flag_inexact)
4679         target_bits |= 0x10;
4680     if (host_bits & float_flag_input_denormal)
4681         target_bits |= 0x80;
4682     return target_bits;
4683 }
4684
4685 uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
4686 {
4687     int i;
4688     uint32_t fpscr;
4689
4690     fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
4691             | (env->vfp.vec_len << 16)
4692             | (env->vfp.vec_stride << 20);
4693     i = get_float_exception_flags(&env->vfp.fp_status);
4694     i |= get_float_exception_flags(&env->vfp.standard_fp_status);
4695     fpscr |= vfp_exceptbits_from_host(i);
4696     return fpscr;
4697 }
4698
4699 uint32_t vfp_get_fpscr(CPUARMState *env)
4700 {
4701     return HELPER(vfp_get_fpscr)(env);
4702 }
4703
4704 /* Convert vfp exception flags to target form.  */
4705 static inline int vfp_exceptbits_to_host(int target_bits)
4706 {
4707     int host_bits = 0;
4708
4709     if (target_bits & 1)
4710         host_bits |= float_flag_invalid;
4711     if (target_bits & 2)
4712         host_bits |= float_flag_divbyzero;
4713     if (target_bits & 4)
4714         host_bits |= float_flag_overflow;
4715     if (target_bits & 8)
4716         host_bits |= float_flag_underflow;
4717     if (target_bits & 0x10)
4718         host_bits |= float_flag_inexact;
4719     if (target_bits & 0x80)
4720         host_bits |= float_flag_input_denormal;
4721     return host_bits;
4722 }
4723
4724 void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
4725 {
4726     int i;
4727     uint32_t changed;
4728
4729     changed = env->vfp.xregs[ARM_VFP_FPSCR];
4730     env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
4731     env->vfp.vec_len = (val >> 16) & 7;
4732     env->vfp.vec_stride = (val >> 20) & 3;
4733
4734     changed ^= val;
4735     if (changed & (3 << 22)) {
4736         i = (val >> 22) & 3;
4737         switch (i) {
4738         case FPROUNDING_TIEEVEN:
4739             i = float_round_nearest_even;
4740             break;
4741         case FPROUNDING_POSINF:
4742             i = float_round_up;
4743             break;
4744         case FPROUNDING_NEGINF:
4745             i = float_round_down;
4746             break;
4747         case FPROUNDING_ZERO:
4748             i = float_round_to_zero;
4749             break;
4750         }
4751         set_float_rounding_mode(i, &env->vfp.fp_status);
4752     }
4753     if (changed & (1 << 24)) {
4754         set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
4755         set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
4756     }
4757     if (changed & (1 << 25))
4758         set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
4759
4760     i = vfp_exceptbits_to_host(val);
4761     set_float_exception_flags(i, &env->vfp.fp_status);
4762     set_float_exception_flags(0, &env->vfp.standard_fp_status);
4763 }
4764
4765 void vfp_set_fpscr(CPUARMState *env, uint32_t val)
4766 {
4767     HELPER(vfp_set_fpscr)(env, val);
4768 }
4769
4770 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
4771
4772 #define VFP_BINOP(name) \
4773 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
4774 { \
4775     float_status *fpst = fpstp; \
4776     return float32_ ## name(a, b, fpst); \
4777 } \
4778 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
4779 { \
4780     float_status *fpst = fpstp; \
4781     return float64_ ## name(a, b, fpst); \
4782 }
4783 VFP_BINOP(add)
4784 VFP_BINOP(sub)
4785 VFP_BINOP(mul)
4786 VFP_BINOP(div)
4787 VFP_BINOP(min)
4788 VFP_BINOP(max)
4789 VFP_BINOP(minnum)
4790 VFP_BINOP(maxnum)
4791 #undef VFP_BINOP
4792
4793 float32 VFP_HELPER(neg, s)(float32 a)
4794 {
4795     return float32_chs(a);
4796 }
4797
4798 float64 VFP_HELPER(neg, d)(float64 a)
4799 {
4800     return float64_chs(a);
4801 }
4802
4803 float32 VFP_HELPER(abs, s)(float32 a)
4804 {
4805     return float32_abs(a);
4806 }
4807
4808 float64 VFP_HELPER(abs, d)(float64 a)
4809 {
4810     return float64_abs(a);
4811 }
4812
4813 float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
4814 {
4815     return float32_sqrt(a, &env->vfp.fp_status);
4816 }
4817
4818 float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
4819 {
4820     return float64_sqrt(a, &env->vfp.fp_status);
4821 }
4822
4823 /* XXX: check quiet/signaling case */
4824 #define DO_VFP_cmp(p, type) \
4825 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env)  \
4826 { \
4827     uint32_t flags; \
4828     switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
4829     case 0: flags = 0x6; break; \
4830     case -1: flags = 0x8; break; \
4831     case 1: flags = 0x2; break; \
4832     default: case 2: flags = 0x3; break; \
4833     } \
4834     env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
4835         | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
4836 } \
4837 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
4838 { \
4839     uint32_t flags; \
4840     switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
4841     case 0: flags = 0x6; break; \
4842     case -1: flags = 0x8; break; \
4843     case 1: flags = 0x2; break; \
4844     default: case 2: flags = 0x3; break; \
4845     } \
4846     env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
4847         | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
4848 }
4849 DO_VFP_cmp(s, float32)
4850 DO_VFP_cmp(d, float64)
4851 #undef DO_VFP_cmp
4852
4853 /* Integer to float and float to integer conversions */
4854
4855 #define CONV_ITOF(name, fsz, sign) \
4856     float##fsz HELPER(name)(uint32_t x, void *fpstp) \
4857 { \
4858     float_status *fpst = fpstp; \
4859     return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
4860 }
4861
4862 #define CONV_FTOI(name, fsz, sign, round) \
4863 uint32_t HELPER(name)(float##fsz x, void *fpstp) \
4864 { \
4865     float_status *fpst = fpstp; \
4866     if (float##fsz##_is_any_nan(x)) { \
4867         float_raise(float_flag_invalid, fpst); \
4868         return 0; \
4869     } \
4870     return float##fsz##_to_##sign##int32##round(x, fpst); \
4871 }
4872
4873 #define FLOAT_CONVS(name, p, fsz, sign) \
4874 CONV_ITOF(vfp_##name##to##p, fsz, sign) \
4875 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
4876 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
4877
4878 FLOAT_CONVS(si, s, 32, )
4879 FLOAT_CONVS(si, d, 64, )
4880 FLOAT_CONVS(ui, s, 32, u)
4881 FLOAT_CONVS(ui, d, 64, u)
4882
4883 #undef CONV_ITOF
4884 #undef CONV_FTOI
4885 #undef FLOAT_CONVS
4886
4887 /* floating point conversion */
4888 float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
4889 {
4890     float64 r = float32_to_float64(x, &env->vfp.fp_status);
4891     /* ARM requires that S<->D conversion of any kind of NaN generates
4892      * a quiet NaN by forcing the most significant frac bit to 1.
4893      */
4894     return float64_maybe_silence_nan(r);
4895 }
4896
4897 float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
4898 {
4899     float32 r =  float64_to_float32(x, &env->vfp.fp_status);
4900     /* ARM requires that S<->D conversion of any kind of NaN generates
4901      * a quiet NaN by forcing the most significant frac bit to 1.
4902      */
4903     return float32_maybe_silence_nan(r);
4904 }
4905
4906 /* VFP3 fixed point conversion.  */
4907 #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
4908 float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t  x, uint32_t shift, \
4909                                      void *fpstp) \
4910 { \
4911     float_status *fpst = fpstp; \
4912     float##fsz tmp; \
4913     tmp = itype##_to_##float##fsz(x, fpst); \
4914     return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
4915 }
4916
4917 /* Notice that we want only input-denormal exception flags from the
4918  * scalbn operation: the other possible flags (overflow+inexact if
4919  * we overflow to infinity, output-denormal) aren't correct for the
4920  * complete scale-and-convert operation.
4921  */
4922 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \
4923 uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \
4924                                              uint32_t shift, \
4925                                              void *fpstp) \
4926 { \
4927     float_status *fpst = fpstp; \
4928     int old_exc_flags = get_float_exception_flags(fpst); \
4929     float##fsz tmp; \
4930     if (float##fsz##_is_any_nan(x)) { \
4931         float_raise(float_flag_invalid, fpst); \
4932         return 0; \
4933     } \
4934     tmp = float##fsz##_scalbn(x, shift, fpst); \
4935     old_exc_flags |= get_float_exception_flags(fpst) \
4936         & float_flag_input_denormal; \
4937     set_float_exception_flags(old_exc_flags, fpst); \
4938     return float##fsz##_to_##itype##round(tmp, fpst); \
4939 }
4940
4941 #define VFP_CONV_FIX(name, p, fsz, isz, itype)                   \
4942 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype)                     \
4943 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero) \
4944 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
4945
4946 #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype)               \
4947 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype)                     \
4948 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
4949
4950 VFP_CONV_FIX(sh, d, 64, 64, int16)
4951 VFP_CONV_FIX(sl, d, 64, 64, int32)
4952 VFP_CONV_FIX_A64(sq, d, 64, 64, int64)
4953 VFP_CONV_FIX(uh, d, 64, 64, uint16)
4954 VFP_CONV_FIX(ul, d, 64, 64, uint32)
4955 VFP_CONV_FIX_A64(uq, d, 64, 64, uint64)
4956 VFP_CONV_FIX(sh, s, 32, 32, int16)
4957 VFP_CONV_FIX(sl, s, 32, 32, int32)
4958 VFP_CONV_FIX_A64(sq, s, 32, 64, int64)
4959 VFP_CONV_FIX(uh, s, 32, 32, uint16)
4960 VFP_CONV_FIX(ul, s, 32, 32, uint32)
4961 VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
4962 #undef VFP_CONV_FIX
4963 #undef VFP_CONV_FIX_FLOAT
4964 #undef VFP_CONV_FLOAT_FIX_ROUND
4965
4966 /* Set the current fp rounding mode and return the old one.
4967  * The argument is a softfloat float_round_ value.
4968  */
4969 uint32_t HELPER(set_rmode)(uint32_t rmode, CPUARMState *env)
4970 {
4971     float_status *fp_status = &env->vfp.fp_status;
4972
4973     uint32_t prev_rmode = get_float_rounding_mode(fp_status);
4974     set_float_rounding_mode(rmode, fp_status);
4975
4976     return prev_rmode;
4977 }
4978
4979 /* Set the current fp rounding mode in the standard fp status and return
4980  * the old one. This is for NEON instructions that need to change the
4981  * rounding mode but wish to use the standard FPSCR values for everything
4982  * else. Always set the rounding mode back to the correct value after
4983  * modifying it.
4984  * The argument is a softfloat float_round_ value.
4985  */
4986 uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env)
4987 {
4988     float_status *fp_status = &env->vfp.standard_fp_status;
4989
4990     uint32_t prev_rmode = get_float_rounding_mode(fp_status);
4991     set_float_rounding_mode(rmode, fp_status);
4992
4993     return prev_rmode;
4994 }
4995
4996 /* Half precision conversions.  */
4997 static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s)
4998 {
4999     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
5000     float32 r = float16_to_float32(make_float16(a), ieee, s);
5001     if (ieee) {
5002         return float32_maybe_silence_nan(r);
5003     }
5004     return r;
5005 }
5006
5007 static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s)
5008 {
5009     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
5010     float16 r = float32_to_float16(a, ieee, s);
5011     if (ieee) {
5012         r = float16_maybe_silence_nan(r);
5013     }
5014     return float16_val(r);
5015 }
5016
5017 float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
5018 {
5019     return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
5020 }
5021
5022 uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
5023 {
5024     return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
5025 }
5026
5027 float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
5028 {
5029     return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
5030 }
5031
5032 uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
5033 {
5034     return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
5035 }
5036
5037 float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, CPUARMState *env)
5038 {
5039     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
5040     float64 r = float16_to_float64(make_float16(a), ieee, &env->vfp.fp_status);
5041     if (ieee) {
5042         return float64_maybe_silence_nan(r);
5043     }
5044     return r;
5045 }
5046
5047 uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, CPUARMState *env)
5048 {
5049     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
5050     float16 r = float64_to_float16(a, ieee, &env->vfp.fp_status);
5051     if (ieee) {
5052         r = float16_maybe_silence_nan(r);
5053     }
5054     return float16_val(r);
5055 }
5056
5057 #define float32_two make_float32(0x40000000)
5058 #define float32_three make_float32(0x40400000)
5059 #define float32_one_point_five make_float32(0x3fc00000)
5060
5061 float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env)
5062 {
5063     float_status *s = &env->vfp.standard_fp_status;
5064     if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
5065         (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
5066         if (!(float32_is_zero(a) || float32_is_zero(b))) {
5067             float_raise(float_flag_input_denormal, s);
5068         }
5069         return float32_two;
5070     }
5071     return float32_sub(float32_two, float32_mul(a, b, s), s);
5072 }
5073
5074 float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
5075 {
5076     float_status *s = &env->vfp.standard_fp_status;
5077     float32 product;
5078     if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
5079         (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
5080         if (!(float32_is_zero(a) || float32_is_zero(b))) {
5081             float_raise(float_flag_input_denormal, s);
5082         }
5083         return float32_one_point_five;
5084     }
5085     product = float32_mul(a, b, s);
5086     return float32_div(float32_sub(float32_three, product, s), float32_two, s);
5087 }
5088
5089 /* NEON helpers.  */
5090
5091 /* Constants 256 and 512 are used in some helpers; we avoid relying on
5092  * int->float conversions at run-time.  */
5093 #define float64_256 make_float64(0x4070000000000000LL)
5094 #define float64_512 make_float64(0x4080000000000000LL)
5095 #define float32_maxnorm make_float32(0x7f7fffff)
5096 #define float64_maxnorm make_float64(0x7fefffffffffffffLL)
5097
5098 /* Reciprocal functions
5099  *
5100  * The algorithm that must be used to calculate the estimate
5101  * is specified by the ARM ARM, see FPRecipEstimate()
5102  */
5103
5104 static float64 recip_estimate(float64 a, float_status *real_fp_status)
5105 {
5106     /* These calculations mustn't set any fp exception flags,
5107      * so we use a local copy of the fp_status.
5108      */
5109     float_status dummy_status = *real_fp_status;
5110     float_status *s = &dummy_status;
5111     /* q = (int)(a * 512.0) */
5112     float64 q = float64_mul(float64_512, a, s);
5113     int64_t q_int = float64_to_int64_round_to_zero(q, s);
5114
5115     /* r = 1.0 / (((double)q + 0.5) / 512.0) */
5116     q = int64_to_float64(q_int, s);
5117     q = float64_add(q, float64_half, s);
5118     q = float64_div(q, float64_512, s);
5119     q = float64_div(float64_one, q, s);
5120
5121     /* s = (int)(256.0 * r + 0.5) */
5122     q = float64_mul(q, float64_256, s);
5123     q = float64_add(q, float64_half, s);
5124     q_int = float64_to_int64_round_to_zero(q, s);
5125
5126     /* return (double)s / 256.0 */
5127     return float64_div(int64_to_float64(q_int, s), float64_256, s);
5128 }
5129
5130 /* Common wrapper to call recip_estimate */
5131 static float64 call_recip_estimate(float64 num, int off, float_status *fpst)
5132 {
5133     uint64_t val64 = float64_val(num);
5134     uint64_t frac = extract64(val64, 0, 52);
5135     int64_t exp = extract64(val64, 52, 11);
5136     uint64_t sbit;
5137     float64 scaled, estimate;
5138
5139     /* Generate the scaled number for the estimate function */
5140     if (exp == 0) {
5141         if (extract64(frac, 51, 1) == 0) {
5142             exp = -1;
5143             frac = extract64(frac, 0, 50) << 2;
5144         } else {
5145             frac = extract64(frac, 0, 51) << 1;
5146         }
5147     }
5148
5149     /* scaled = '0' : '01111111110' : fraction<51:44> : Zeros(44); */
5150     scaled = make_float64((0x3feULL << 52)
5151                           | extract64(frac, 44, 8) << 44);
5152
5153     estimate = recip_estimate(scaled, fpst);
5154
5155     /* Build new result */
5156     val64 = float64_val(estimate);
5157     sbit = 0x8000000000000000ULL & val64;
5158     exp = off - exp;
5159     frac = extract64(val64, 0, 52);
5160
5161     if (exp == 0) {
5162         frac = 1ULL << 51 | extract64(frac, 1, 51);
5163     } else if (exp == -1) {
5164         frac = 1ULL << 50 | extract64(frac, 2, 50);
5165         exp = 0;
5166     }
5167
5168     return make_float64(sbit | (exp << 52) | frac);
5169 }
5170
5171 static bool round_to_inf(float_status *fpst, bool sign_bit)
5172 {
5173     switch (fpst->float_rounding_mode) {
5174     case float_round_nearest_even: /* Round to Nearest */
5175         return true;
5176     case float_round_up: /* Round to +Inf */
5177         return !sign_bit;
5178     case float_round_down: /* Round to -Inf */
5179         return sign_bit;
5180     case float_round_to_zero: /* Round to Zero */
5181         return false;
5182     }
5183
5184     g_assert_not_reached();
5185 }
5186
5187 float32 HELPER(recpe_f32)(float32 input, void *fpstp)
5188 {
5189     float_status *fpst = fpstp;
5190     float32 f32 = float32_squash_input_denormal(input, fpst);
5191     uint32_t f32_val = float32_val(f32);
5192     uint32_t f32_sbit = 0x80000000ULL & f32_val;
5193     int32_t f32_exp = extract32(f32_val, 23, 8);
5194     uint32_t f32_frac = extract32(f32_val, 0, 23);
5195     float64 f64, r64;
5196     uint64_t r64_val;
5197     int64_t r64_exp;
5198     uint64_t r64_frac;
5199
5200     if (float32_is_any_nan(f32)) {
5201         float32 nan = f32;
5202         if (float32_is_signaling_nan(f32)) {
5203             float_raise(float_flag_invalid, fpst);
5204             nan = float32_maybe_silence_nan(f32);
5205         }
5206         if (fpst->default_nan_mode) {
5207             nan =  float32_default_nan;
5208         }
5209         return nan;
5210     } else if (float32_is_infinity(f32)) {
5211         return float32_set_sign(float32_zero, float32_is_neg(f32));
5212     } else if (float32_is_zero(f32)) {
5213         float_raise(float_flag_divbyzero, fpst);
5214         return float32_set_sign(float32_infinity, float32_is_neg(f32));
5215     } else if ((f32_val & ~(1ULL << 31)) < (1ULL << 21)) {
5216         /* Abs(value) < 2.0^-128 */
5217         float_raise(float_flag_overflow | float_flag_inexact, fpst);
5218         if (round_to_inf(fpst, f32_sbit)) {
5219             return float32_set_sign(float32_infinity, float32_is_neg(f32));
5220         } else {
5221             return float32_set_sign(float32_maxnorm, float32_is_neg(f32));
5222         }
5223     } else if (f32_exp >= 253 && fpst->flush_to_zero) {
5224         float_raise(float_flag_underflow, fpst);
5225         return float32_set_sign(float32_zero, float32_is_neg(f32));
5226     }
5227
5228
5229     f64 = make_float64(((int64_t)(f32_exp) << 52) | (int64_t)(f32_frac) << 29);
5230     r64 = call_recip_estimate(f64, 253, fpst);
5231     r64_val = float64_val(r64);
5232     r64_exp = extract64(r64_val, 52, 11);
5233     r64_frac = extract64(r64_val, 0, 52);
5234
5235     /* result = sign : result_exp<7:0> : fraction<51:29>; */
5236     return make_float32(f32_sbit |
5237                         (r64_exp & 0xff) << 23 |
5238                         extract64(r64_frac, 29, 24));
5239 }
5240
5241 float64 HELPER(recpe_f64)(float64 input, void *fpstp)
5242 {
5243     float_status *fpst = fpstp;
5244     float64 f64 = float64_squash_input_denormal(input, fpst);
5245     uint64_t f64_val = float64_val(f64);
5246     uint64_t f64_sbit = 0x8000000000000000ULL & f64_val;
5247     int64_t f64_exp = extract64(f64_val, 52, 11);
5248     float64 r64;
5249     uint64_t r64_val;
5250     int64_t r64_exp;
5251     uint64_t r64_frac;
5252
5253     /* Deal with any special cases */
5254     if (float64_is_any_nan(f64)) {
5255         float64 nan = f64;
5256         if (float64_is_signaling_nan(f64)) {
5257             float_raise(float_flag_invalid, fpst);
5258             nan = float64_maybe_silence_nan(f64);
5259         }
5260         if (fpst->default_nan_mode) {
5261             nan =  float64_default_nan;
5262         }
5263         return nan;
5264     } else if (float64_is_infinity(f64)) {
5265         return float64_set_sign(float64_zero, float64_is_neg(f64));
5266     } else if (float64_is_zero(f64)) {
5267         float_raise(float_flag_divbyzero, fpst);
5268         return float64_set_sign(float64_infinity, float64_is_neg(f64));
5269     } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) {
5270         /* Abs(value) < 2.0^-1024 */
5271         float_raise(float_flag_overflow | float_flag_inexact, fpst);
5272         if (round_to_inf(fpst, f64_sbit)) {
5273             return float64_set_sign(float64_infinity, float64_is_neg(f64));
5274         } else {
5275             return float64_set_sign(float64_maxnorm, float64_is_neg(f64));
5276         }
5277     } else if (f64_exp >= 1023 && fpst->flush_to_zero) {
5278         float_raise(float_flag_underflow, fpst);
5279         return float64_set_sign(float64_zero, float64_is_neg(f64));
5280     }
5281
5282     r64 = call_recip_estimate(f64, 2045, fpst);
5283     r64_val = float64_val(r64);
5284     r64_exp = extract64(r64_val, 52, 11);
5285     r64_frac = extract64(r64_val, 0, 52);
5286
5287     /* result = sign : result_exp<10:0> : fraction<51:0> */
5288     return make_float64(f64_sbit |
5289                         ((r64_exp & 0x7ff) << 52) |
5290                         r64_frac);
5291 }
5292
5293 /* The algorithm that must be used to calculate the estimate
5294  * is specified by the ARM ARM.
5295  */
5296 static float64 recip_sqrt_estimate(float64 a, float_status *real_fp_status)
5297 {
5298     /* These calculations mustn't set any fp exception flags,
5299      * so we use a local copy of the fp_status.
5300      */
5301     float_status dummy_status = *real_fp_status;
5302     float_status *s = &dummy_status;
5303     float64 q;
5304     int64_t q_int;
5305
5306     if (float64_lt(a, float64_half, s)) {
5307         /* range 0.25 <= a < 0.5 */
5308
5309         /* a in units of 1/512 rounded down */
5310         /* q0 = (int)(a * 512.0);  */
5311         q = float64_mul(float64_512, a, s);
5312         q_int = float64_to_int64_round_to_zero(q, s);
5313
5314         /* reciprocal root r */
5315         /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0);  */
5316         q = int64_to_float64(q_int, s);
5317         q = float64_add(q, float64_half, s);
5318         q = float64_div(q, float64_512, s);
5319         q = float64_sqrt(q, s);
5320         q = float64_div(float64_one, q, s);
5321     } else {
5322         /* range 0.5 <= a < 1.0 */
5323
5324         /* a in units of 1/256 rounded down */
5325         /* q1 = (int)(a * 256.0); */
5326         q = float64_mul(float64_256, a, s);
5327         int64_t q_int = float64_to_int64_round_to_zero(q, s);
5328
5329         /* reciprocal root r */
5330         /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
5331         q = int64_to_float64(q_int, s);
5332         q = float64_add(q, float64_half, s);
5333         q = float64_div(q, float64_256, s);
5334         q = float64_sqrt(q, s);
5335         q = float64_div(float64_one, q, s);
5336     }
5337     /* r in units of 1/256 rounded to nearest */
5338     /* s = (int)(256.0 * r + 0.5); */
5339
5340     q = float64_mul(q, float64_256,s );
5341     q = float64_add(q, float64_half, s);
5342     q_int = float64_to_int64_round_to_zero(q, s);
5343
5344     /* return (double)s / 256.0;*/
5345     return float64_div(int64_to_float64(q_int, s), float64_256, s);
5346 }
5347
5348 float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
5349 {
5350     float_status *s = fpstp;
5351     float32 f32 = float32_squash_input_denormal(input, s);
5352     uint32_t val = float32_val(f32);
5353     uint32_t f32_sbit = 0x80000000 & val;
5354     int32_t f32_exp = extract32(val, 23, 8);
5355     uint32_t f32_frac = extract32(val, 0, 23);
5356     uint64_t f64_frac;
5357     uint64_t val64;
5358     int result_exp;
5359     float64 f64;
5360
5361     if (float32_is_any_nan(f32)) {
5362         float32 nan = f32;
5363         if (float32_is_signaling_nan(f32)) {
5364             float_raise(float_flag_invalid, s);
5365             nan = float32_maybe_silence_nan(f32);
5366         }
5367         if (s->default_nan_mode) {
5368             nan =  float32_default_nan;
5369         }
5370         return nan;
5371     } else if (float32_is_zero(f32)) {
5372         float_raise(float_flag_divbyzero, s);
5373         return float32_set_sign(float32_infinity, float32_is_neg(f32));
5374     } else if (float32_is_neg(f32)) {
5375         float_raise(float_flag_invalid, s);
5376         return float32_default_nan;
5377     } else if (float32_is_infinity(f32)) {
5378         return float32_zero;
5379     }
5380
5381     /* Scale and normalize to a double-precision value between 0.25 and 1.0,
5382      * preserving the parity of the exponent.  */
5383
5384     f64_frac = ((uint64_t) f32_frac) << 29;
5385     if (f32_exp == 0) {
5386         while (extract64(f64_frac, 51, 1) == 0) {
5387             f64_frac = f64_frac << 1;
5388             f32_exp = f32_exp-1;
5389         }
5390         f64_frac = extract64(f64_frac, 0, 51) << 1;
5391     }
5392
5393     if (extract64(f32_exp, 0, 1) == 0) {
5394         f64 = make_float64(((uint64_t) f32_sbit) << 32
5395                            | (0x3feULL << 52)
5396                            | f64_frac);
5397     } else {
5398         f64 = make_float64(((uint64_t) f32_sbit) << 32
5399                            | (0x3fdULL << 52)
5400                            | f64_frac);
5401     }
5402
5403     result_exp = (380 - f32_exp) / 2;
5404
5405     f64 = recip_sqrt_estimate(f64, s);
5406
5407     val64 = float64_val(f64);
5408
5409     val = ((result_exp & 0xff) << 23)
5410         | ((val64 >> 29)  & 0x7fffff);
5411     return make_float32(val);
5412 }
5413
5414 float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
5415 {
5416     float_status *s = fpstp;
5417     float64 f64 = float64_squash_input_denormal(input, s);
5418     uint64_t val = float64_val(f64);
5419     uint64_t f64_sbit = 0x8000000000000000ULL & val;
5420     int64_t f64_exp = extract64(val, 52, 11);
5421     uint64_t f64_frac = extract64(val, 0, 52);
5422     int64_t result_exp;
5423     uint64_t result_frac;
5424
5425     if (float64_is_any_nan(f64)) {
5426         float64 nan = f64;
5427         if (float64_is_signaling_nan(f64)) {
5428             float_raise(float_flag_invalid, s);
5429             nan = float64_maybe_silence_nan(f64);
5430         }
5431         if (s->default_nan_mode) {
5432             nan =  float64_default_nan;
5433         }
5434         return nan;
5435     } else if (float64_is_zero(f64)) {
5436         float_raise(float_flag_divbyzero, s);
5437         return float64_set_sign(float64_infinity, float64_is_neg(f64));
5438     } else if (float64_is_neg(f64)) {
5439         float_raise(float_flag_invalid, s);
5440         return float64_default_nan;
5441     } else if (float64_is_infinity(f64)) {
5442         return float64_zero;
5443     }
5444
5445     /* Scale and normalize to a double-precision value between 0.25 and 1.0,
5446      * preserving the parity of the exponent.  */
5447
5448     if (f64_exp == 0) {
5449         while (extract64(f64_frac, 51, 1) == 0) {
5450             f64_frac = f64_frac << 1;
5451             f64_exp = f64_exp - 1;
5452         }
5453         f64_frac = extract64(f64_frac, 0, 51) << 1;
5454     }
5455
5456     if (extract64(f64_exp, 0, 1) == 0) {
5457         f64 = make_float64(f64_sbit
5458                            | (0x3feULL << 52)
5459                            | f64_frac);
5460     } else {
5461         f64 = make_float64(f64_sbit
5462                            | (0x3fdULL << 52)
5463                            | f64_frac);
5464     }
5465
5466     result_exp = (3068 - f64_exp) / 2;
5467
5468     f64 = recip_sqrt_estimate(f64, s);
5469
5470     result_frac = extract64(float64_val(f64), 0, 52);
5471
5472     return make_float64(f64_sbit |
5473                         ((result_exp & 0x7ff) << 52) |
5474                         result_frac);
5475 }
5476
5477 uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp)
5478 {
5479     float_status *s = fpstp;
5480     float64 f64;
5481
5482     if ((a & 0x80000000) == 0) {
5483         return 0xffffffff;
5484     }
5485
5486     f64 = make_float64((0x3feULL << 52)
5487                        | ((int64_t)(a & 0x7fffffff) << 21));
5488
5489     f64 = recip_estimate(f64, s);
5490
5491     return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
5492 }
5493
5494 uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp)
5495 {
5496     float_status *fpst = fpstp;
5497     float64 f64;
5498
5499     if ((a & 0xc0000000) == 0) {
5500         return 0xffffffff;
5501     }
5502
5503     if (a & 0x80000000) {
5504         f64 = make_float64((0x3feULL << 52)
5505                            | ((uint64_t)(a & 0x7fffffff) << 21));
5506     } else { /* bits 31-30 == '01' */
5507         f64 = make_float64((0x3fdULL << 52)
5508                            | ((uint64_t)(a & 0x3fffffff) << 22));
5509     }
5510
5511     f64 = recip_sqrt_estimate(f64, fpst);
5512
5513     return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
5514 }
5515
5516 /* VFPv4 fused multiply-accumulate */
5517 float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
5518 {
5519     float_status *fpst = fpstp;
5520     return float32_muladd(a, b, c, 0, fpst);
5521 }
5522
5523 float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
5524 {
5525     float_status *fpst = fpstp;
5526     return float64_muladd(a, b, c, 0, fpst);
5527 }
5528
5529 /* ARMv8 round to integral */
5530 float32 HELPER(rints_exact)(float32 x, void *fp_status)
5531 {
5532     return float32_round_to_int(x, fp_status);
5533 }
5534
5535 float64 HELPER(rintd_exact)(float64 x, void *fp_status)
5536 {
5537     return float64_round_to_int(x, fp_status);
5538 }
5539
5540 float32 HELPER(rints)(float32 x, void *fp_status)
5541 {
5542     int old_flags = get_float_exception_flags(fp_status), new_flags;
5543     float32 ret;
5544
5545     ret = float32_round_to_int(x, fp_status);
5546
5547     /* Suppress any inexact exceptions the conversion produced */
5548     if (!(old_flags & float_flag_inexact)) {
5549         new_flags = get_float_exception_flags(fp_status);
5550         set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
5551     }
5552
5553     return ret;
5554 }
5555
5556 float64 HELPER(rintd)(float64 x, void *fp_status)
5557 {
5558     int old_flags = get_float_exception_flags(fp_status), new_flags;
5559     float64 ret;
5560
5561     ret = float64_round_to_int(x, fp_status);
5562
5563     new_flags = get_float_exception_flags(fp_status);
5564
5565     /* Suppress any inexact exceptions the conversion produced */
5566     if (!(old_flags & float_flag_inexact)) {
5567         new_flags = get_float_exception_flags(fp_status);
5568         set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
5569     }
5570
5571     return ret;
5572 }
5573
5574 /* Convert ARM rounding mode to softfloat */
5575 int arm_rmode_to_sf(int rmode)
5576 {
5577     switch (rmode) {
5578     case FPROUNDING_TIEAWAY:
5579         rmode = float_round_ties_away;
5580         break;
5581     case FPROUNDING_ODD:
5582         /* FIXME: add support for TIEAWAY and ODD */
5583         qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n",
5584                       rmode);
5585     case FPROUNDING_TIEEVEN:
5586     default:
5587         rmode = float_round_nearest_even;
5588         break;
5589     case FPROUNDING_POSINF:
5590         rmode = float_round_up;
5591         break;
5592     case FPROUNDING_NEGINF:
5593         rmode = float_round_down;
5594         break;
5595     case FPROUNDING_ZERO:
5596         rmode = float_round_to_zero;
5597         break;
5598     }
5599     return rmode;
5600 }
5601
5602 /* CRC helpers.
5603  * The upper bytes of val (above the number specified by 'bytes') must have
5604  * been zeroed out by the caller.
5605  */
5606 uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes)
5607 {
5608     uint8_t buf[4];
5609
5610     stl_le_p(buf, val);
5611
5612     /* zlib crc32 converts the accumulator and output to one's complement.  */
5613     return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff;
5614 }
5615
5616 uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes)
5617 {
5618     uint8_t buf[4];
5619
5620     stl_le_p(buf, val);
5621
5622     /* Linux crc32c converts the output to one's complement.  */
5623     return crc32c(acc, buf, bytes) ^ 0xffffffff;
5624 }