hw/sh_timer.c

   1 /*
   2  * SuperH Timer modules.
   3  *
   4  * Copyright (c) 2007 Magnus Damm
   5  * Based on arm_timer.c by Paul Brook
   6  * Copyright (c) 2005-2006 CodeSourcery.
   7  *
   8  * This code is licensed under the GPL.
   9  */
  10
  11 #include "hw.h"
  12 #include "sh.h"
  13 #include "qemu-timer.h"
  14 #include "exec-memory.h"
  15
  16 //#define DEBUG_TIMER
  17
  18 #define TIMER_TCR_TPSC          (7 << 0)
  19 #define TIMER_TCR_CKEG          (3 << 3)
  20 #define TIMER_TCR_UNIE          (1 << 5)
  21 #define TIMER_TCR_ICPE          (3 << 6)
  22 #define TIMER_TCR_UNF           (1 << 8)
  23 #define TIMER_TCR_ICPF          (1 << 9)
  24 #define TIMER_TCR_RESERVED      (0x3f << 10)
  25
  26 #define TIMER_FEAT_CAPT   (1 << 0)
  27 #define TIMER_FEAT_EXTCLK (1 << 1)
  28
  29 #define OFFSET_TCOR   0
  30 #define OFFSET_TCNT   1
  31 #define OFFSET_TCR    2
  32 #define OFFSET_TCPR   3
  33
  34 typedef struct {
  35     ptimer_state *timer;
  36     uint32_t tcnt;
  37     uint32_t tcor;
  38     uint32_t tcr;
  39     uint32_t tcpr;
  40     int freq;
  41     int int_level;
  42     int old_level;
  43     int feat;
  44     int enabled;
  45     qemu_irq irq;
  46 } sh_timer_state;
  47
  48 /* Check all active timers, and schedule the next timer interrupt. */
  49
  50 static void sh_timer_update(sh_timer_state *s)
  51 {
  52     int new_level = s->int_level && (s->tcr & TIMER_TCR_UNIE);
  53
  54     if (new_level != s->old_level)
  55       qemu_set_irq (s->irq, new_level);
  56
  57     s->old_level = s->int_level;
  58     s->int_level = new_level;
  59 }
  60
  61 static uint32_t sh_timer_read(void *opaque, target_phys_addr_t offset)
  62 {
  63     sh_timer_state *s = (sh_timer_state *)opaque;
  64
  65     switch (offset >> 2) {
  66     case OFFSET_TCOR:
  67         return s->tcor;
  68     case OFFSET_TCNT:
  69         return ptimer_get_count(s->timer);
  70     case OFFSET_TCR:
  71         return s->tcr | (s->int_level ? TIMER_TCR_UNF : 0);
  72     case OFFSET_TCPR:
  73         if (s->feat & TIMER_FEAT_CAPT)
  74             return s->tcpr;
  75     default:
  76         hw_error("sh_timer_read: Bad offset %x\n", (int)offset);
  77         return 0;
  78     }
  79 }
  80
  81 static void sh_timer_write(void *opaque, target_phys_addr_t offset,
  82                             uint32_t value)
  83 {
  84     sh_timer_state *s = (sh_timer_state *)opaque;
  85     int freq;
  86
  87     switch (offset >> 2) {
  88     case OFFSET_TCOR:
  89         s->tcor = value;
  90         ptimer_set_limit(s->timer, s->tcor, 0);
  91         break;
  92     case OFFSET_TCNT:
  93         s->tcnt = value;
  94         ptimer_set_count(s->timer, s->tcnt);
  95         break;
  96     case OFFSET_TCR:
  97         if (s->enabled) {
  98             /* Pause the timer if it is running.  This may cause some
  99                inaccuracy dure to rounding, but avoids a whole lot of other
 100                messyness.  */
 101             ptimer_stop(s->timer);
 102         }
 103         freq = s->freq;
 104         /* ??? Need to recalculate expiry time after changing divisor.  */
 105         switch (value & TIMER_TCR_TPSC) {
 106         case 0: freq >>= 2; break;
 107         case 1: freq >>= 4; break;
 108         case 2: freq >>= 6; break;
 109         case 3: freq >>= 8; break;
 110         case 4: freq >>= 10; break;
 111         case 6:
 112         case 7: if (s->feat & TIMER_FEAT_EXTCLK) break;
 113         default: hw_error("sh_timer_write: Reserved TPSC value\n"); break;
 114         }
 115         switch ((value & TIMER_TCR_CKEG) >> 3) {
 116         case 0: break;
 117         case 1:
 118         case 2:
 119         case 3: if (s->feat & TIMER_FEAT_EXTCLK) break;
 120         default: hw_error("sh_timer_write: Reserved CKEG value\n"); break;
 121         }
 122         switch ((value & TIMER_TCR_ICPE) >> 6) {
 123         case 0: break;
 124         case 2:
 125         case 3: if (s->feat & TIMER_FEAT_CAPT) break;
 126         default: hw_error("sh_timer_write: Reserved ICPE value\n"); break;
 127         }
 128         if ((value & TIMER_TCR_UNF) == 0)
 129             s->int_level = 0;
 130
 131         value &= ~TIMER_TCR_UNF;
 132
 133         if ((value & TIMER_TCR_ICPF) && (!(s->feat & TIMER_FEAT_CAPT)))
 134             hw_error("sh_timer_write: Reserved ICPF value\n");
 135
 136         value &= ~TIMER_TCR_ICPF; /* capture not supported */
 137
 138         if (value & TIMER_TCR_RESERVED)
 139             hw_error("sh_timer_write: Reserved TCR bits set\n");
 140         s->tcr = value;
 141         ptimer_set_limit(s->timer, s->tcor, 0);
 142         ptimer_set_freq(s->timer, freq);
 143         if (s->enabled) {
 144             /* Restart the timer if still enabled.  */
 145             ptimer_run(s->timer, 0);
 146         }
 147         break;
 148     case OFFSET_TCPR:
 149         if (s->feat & TIMER_FEAT_CAPT) {
 150             s->tcpr = value;
 151             break;
 152         }
 153     default:
 154         hw_error("sh_timer_write: Bad offset %x\n", (int)offset);
 155     }
 156     sh_timer_update(s);
 157 }
 158
 159 static void sh_timer_start_stop(void *opaque, int enable)
 160 {
 161     sh_timer_state *s = (sh_timer_state *)opaque;
 162
 163 #ifdef DEBUG_TIMER
 164     printf("sh_timer_start_stop %d (%d)\n", enable, s->enabled);
 165 #endif
 166
 167     if (s->enabled && !enable) {
 168         ptimer_stop(s->timer);
 169     }
 170     if (!s->enabled && enable) {
 171         ptimer_run(s->timer, 0);
 172     }
 173     s->enabled = !!enable;
 174
 175 #ifdef DEBUG_TIMER
 176     printf("sh_timer_start_stop done %d\n", s->enabled);
 177 #endif
 178 }
 179
 180 static void sh_timer_tick(void *opaque)
 181 {
 182     sh_timer_state *s = (sh_timer_state *)opaque;
 183     s->int_level = s->enabled;
 184     sh_timer_update(s);
 185 }
 186
 187 static void *sh_timer_init(uint32_t freq, int feat, qemu_irq irq)
 188 {
 189     sh_timer_state *s;
 190     QEMUBH *bh;
 191
 192     s = (sh_timer_state *)g_malloc0(sizeof(sh_timer_state));
 193     s->freq = freq;
 194     s->feat = feat;
 195     s->tcor = 0xffffffff;
 196     s->tcnt = 0xffffffff;
 197     s->tcpr = 0xdeadbeef;
 198     s->tcr = 0;
 199     s->enabled = 0;
 200     s->irq = irq;
 201
 202     bh = qemu_bh_new(sh_timer_tick, s);
 203     s->timer = ptimer_init(bh);
 204
 205     sh_timer_write(s, OFFSET_TCOR >> 2, s->tcor);
 206     sh_timer_write(s, OFFSET_TCNT >> 2, s->tcnt);
 207     sh_timer_write(s, OFFSET_TCPR >> 2, s->tcpr);
 208     sh_timer_write(s, OFFSET_TCR  >> 2, s->tcpr);
 209     /* ??? Save/restore.  */
 210     return s;
 211 }
 212
 213 typedef struct {
 214     MemoryRegion iomem;
 215     MemoryRegion iomem_p4;
 216     MemoryRegion iomem_a7;
 217     void *timer[3];
 218     int level[3];
 219     uint32_t tocr;
 220     uint32_t tstr;
 221     int feat;
 222 } tmu012_state;
 223
 224 static uint64_t tmu012_read(void *opaque, target_phys_addr_t offset,
 225                             unsigned size)
 226 {
 227     tmu012_state *s = (tmu012_state *)opaque;
 228
 229 #ifdef DEBUG_TIMER
 230     printf("tmu012_read 0x%lx\n", (unsigned long) offset);
 231 #endif
 232
 233     if (offset >= 0x20) {
 234         if (!(s->feat & TMU012_FEAT_3CHAN))
 235             hw_error("tmu012_write: Bad channel offset %x\n", (int)offset);
 236         return sh_timer_read(s->timer[2], offset - 0x20);
 237     }
 238
 239     if (offset >= 0x14)
 240         return sh_timer_read(s->timer[1], offset - 0x14);
 241
 242     if (offset >= 0x08)
 243         return sh_timer_read(s->timer[0], offset - 0x08);
 244
 245     if (offset == 4)
 246         return s->tstr;
 247
 248     if ((s->feat & TMU012_FEAT_TOCR) && offset == 0)
 249         return s->tocr;
 250
 251     hw_error("tmu012_write: Bad offset %x\n", (int)offset);
 252     return 0;
 253 }
 254
 255 static void tmu012_write(void *opaque, target_phys_addr_t offset,
 256                         uint64_t value, unsigned size)
 257 {
 258     tmu012_state *s = (tmu012_state *)opaque;
 259
 260 #ifdef DEBUG_TIMER
 261     printf("tmu012_write 0x%lx 0x%08x\n", (unsigned long) offset, value);
 262 #endif
 263
 264     if (offset >= 0x20) {
 265         if (!(s->feat & TMU012_FEAT_3CHAN))
 266             hw_error("tmu012_write: Bad channel offset %x\n", (int)offset);
 267         sh_timer_write(s->timer[2], offset - 0x20, value);
 268         return;
 269     }
 270
 271     if (offset >= 0x14) {
 272         sh_timer_write(s->timer[1], offset - 0x14, value);
 273         return;
 274     }
 275
 276     if (offset >= 0x08) {
 277         sh_timer_write(s->timer[0], offset - 0x08, value);
 278         return;
 279     }
 280
 281     if (offset == 4) {
 282         sh_timer_start_stop(s->timer[0], value & (1 << 0));
 283         sh_timer_start_stop(s->timer[1], value & (1 << 1));
 284         if (s->feat & TMU012_FEAT_3CHAN)
 285             sh_timer_start_stop(s->timer[2], value & (1 << 2));
 286         else
 287             if (value & (1 << 2))
 288                 hw_error("tmu012_write: Bad channel\n");
 289
 290         s->tstr = value;
 291         return;
 292     }
 293
 294     if ((s->feat & TMU012_FEAT_TOCR) && offset == 0) {
 295         s->tocr = value & (1 << 0);
 296     }
 297 }
 298
 299 static const MemoryRegionOps tmu012_ops = {
 300     .read = tmu012_read,
 301     .write = tmu012_write,
 302     .endianness = DEVICE_NATIVE_ENDIAN,
 303 };
 304
 305 void tmu012_init(MemoryRegion *sysmem, target_phys_addr_t base,
 306                  int feat, uint32_t freq,
 307                  qemu_irq ch0_irq, qemu_irq ch1_irq,
 308                  qemu_irq ch2_irq0, qemu_irq ch2_irq1)
 309 {
 310     tmu012_state *s;
 311     int timer_feat = (feat & TMU012_FEAT_EXTCLK) ? TIMER_FEAT_EXTCLK : 0;
 312
 313     s = (tmu012_state *)g_malloc0(sizeof(tmu012_state));
 314     s->feat = feat;
 315     s->timer[0] = sh_timer_init(freq, timer_feat, ch0_irq);
 316     s->timer[1] = sh_timer_init(freq, timer_feat, ch1_irq);
 317     if (feat & TMU012_FEAT_3CHAN)
 318         s->timer[2] = sh_timer_init(freq, timer_feat | TIMER_FEAT_CAPT,
 319                                     ch2_irq0); /* ch2_irq1 not supported */
 320
 321     memory_region_init_io(&s->iomem, &tmu012_ops, s,
 322                           "timer", 0x100000000ULL);
 323
 324     memory_region_init_alias(&s->iomem_p4, "timer-p4",
 325                              &s->iomem, 0, 0x1000);
 326     memory_region_add_subregion(sysmem, P4ADDR(base), &s->iomem_p4);
 327
 328     memory_region_init_alias(&s->iomem_a7, "timer-a7",
 329                              &s->iomem, 0, 0x1000);
 330     memory_region_add_subregion(sysmem, A7ADDR(base), &s->iomem_a7);
 331     /* ??? Save/restore.  */
 332 }