hw/ppce500_pci.c

   1 /*
   2  * QEMU PowerPC E500 embedded processors pci controller emulation
   3  *
   4  * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
   5  *
   6  * Author: Yu Liu,     <yu.liu@freescale.com>
   7  *
   8  * This file is derived from hw/ppc4xx_pci.c,
   9  * the copyright for that material belongs to the original owners.
  10  *
  11  * This is free software; you can redistribute it and/or modify
  12  * it under the terms of  the GNU General  Public License as published by
  13  * the Free Software Foundation;  either version 2 of the  License, or
  14  * (at your option) any later version.
  15  */
  16
  17 #include "hw.h"
  18 #include "pci.h"
  19 #include "pci_host.h"
  20 #include "bswap.h"
  21
  22 #ifdef DEBUG_PCI
  23 #define pci_debug(fmt, ...) fprintf(stderr, fmt, ## __VA_ARGS__)
  24 #else
  25 #define pci_debug(fmt, ...)
  26 #endif
  27
  28 #define PCIE500_CFGADDR       0x0
  29 #define PCIE500_CFGDATA       0x4
  30 #define PCIE500_REG_BASE      0xC00
  31 #define PCIE500_ALL_SIZE      0x1000
  32 #define PCIE500_REG_SIZE      (PCIE500_ALL_SIZE - PCIE500_REG_BASE)
  33
  34 #define PPCE500_PCI_CONFIG_ADDR         0x0
  35 #define PPCE500_PCI_CONFIG_DATA         0x4
  36 #define PPCE500_PCI_INTACK              0x8
  37
  38 #define PPCE500_PCI_OW1                 (0xC20 - PCIE500_REG_BASE)
  39 #define PPCE500_PCI_OW2                 (0xC40 - PCIE500_REG_BASE)
  40 #define PPCE500_PCI_OW3                 (0xC60 - PCIE500_REG_BASE)
  41 #define PPCE500_PCI_OW4                 (0xC80 - PCIE500_REG_BASE)
  42 #define PPCE500_PCI_IW3                 (0xDA0 - PCIE500_REG_BASE)
  43 #define PPCE500_PCI_IW2                 (0xDC0 - PCIE500_REG_BASE)
  44 #define PPCE500_PCI_IW1                 (0xDE0 - PCIE500_REG_BASE)
  45
  46 #define PPCE500_PCI_GASKET_TIMR         (0xE20 - PCIE500_REG_BASE)
  47
  48 #define PCI_POTAR               0x0
  49 #define PCI_POTEAR              0x4
  50 #define PCI_POWBAR              0x8
  51 #define PCI_POWAR               0x10
  52
  53 #define PCI_PITAR               0x0
  54 #define PCI_PIWBAR              0x8
  55 #define PCI_PIWBEAR             0xC
  56 #define PCI_PIWAR               0x10
  57
  58 #define PPCE500_PCI_NR_POBS     5
  59 #define PPCE500_PCI_NR_PIBS     3
  60
  61 struct  pci_outbound {
  62     uint32_t potar;
  63     uint32_t potear;
  64     uint32_t powbar;
  65     uint32_t powar;
  66 };
  67
  68 struct pci_inbound {
  69     uint32_t pitar;
  70     uint32_t piwbar;
  71     uint32_t piwbear;
  72     uint32_t piwar;
  73 };
  74
  75 struct PPCE500PCIState {
  76     PCIHostState pci_state;
  77     struct pci_outbound pob[PPCE500_PCI_NR_POBS];
  78     struct pci_inbound pib[PPCE500_PCI_NR_PIBS];
  79     uint32_t gasket_time;
  80     qemu_irq irq[4];
  81     /* mmio maps */
  82     MemoryRegion iomem;
  83 };
  84
  85 typedef struct PPCE500PCIState PPCE500PCIState;
  86
  87 static uint64_t pci_reg_read4(void *opaque, target_phys_addr_t addr,
  88                               unsigned size)
  89 {
  90     PPCE500PCIState *pci = opaque;
  91     unsigned long win;
  92     uint32_t value = 0;
  93     int idx;
  94
  95     win = addr & 0xfe0;
  96
  97     switch (win) {
  98     case PPCE500_PCI_OW1:
  99     case PPCE500_PCI_OW2:
 100     case PPCE500_PCI_OW3:
 101     case PPCE500_PCI_OW4:
 102         idx = (addr >> 5) & 0x7;
 103         switch (addr & 0xC) {
 104         case PCI_POTAR:
 105             value = pci->pob[idx].potar;
 106             break;
 107         case PCI_POTEAR:
 108             value = pci->pob[idx].potear;
 109             break;
 110         case PCI_POWBAR:
 111             value = pci->pob[idx].powbar;
 112             break;
 113         case PCI_POWAR:
 114             value = pci->pob[idx].powar;
 115             break;
 116         default:
 117             break;
 118         }
 119         break;
 120
 121     case PPCE500_PCI_IW3:
 122     case PPCE500_PCI_IW2:
 123     case PPCE500_PCI_IW1:
 124         idx = ((addr >> 5) & 0x3) - 1;
 125         switch (addr & 0xC) {
 126         case PCI_PITAR:
 127             value = pci->pib[idx].pitar;
 128             break;
 129         case PCI_PIWBAR:
 130             value = pci->pib[idx].piwbar;
 131             break;
 132         case PCI_PIWBEAR:
 133             value = pci->pib[idx].piwbear;
 134             break;
 135         case PCI_PIWAR:
 136             value = pci->pib[idx].piwar;
 137             break;
 138         default:
 139             break;
 140         };
 141         break;
 142
 143     case PPCE500_PCI_GASKET_TIMR:
 144         value = pci->gasket_time;
 145         break;
 146
 147     default:
 148         break;
 149     }
 150
 151     pci_debug("%s: win:%lx(addr:" TARGET_FMT_plx ") -> value:%x\n", __func__,
 152               win, addr, value);
 153     return value;
 154 }
 155
 156 static void pci_reg_write4(void *opaque, target_phys_addr_t addr,
 157                            uint64_t value, unsigned size)
 158 {
 159     PPCE500PCIState *pci = opaque;
 160     unsigned long win;
 161     int idx;
 162
 163     win = addr & 0xfe0;
 164
 165     pci_debug("%s: value:%x -> win:%lx(addr:" TARGET_FMT_plx ")\n",
 166               __func__, (unsigned)value, win, addr);
 167
 168     switch (win) {
 169     case PPCE500_PCI_OW1:
 170     case PPCE500_PCI_OW2:
 171     case PPCE500_PCI_OW3:
 172     case PPCE500_PCI_OW4:
 173         idx = (addr >> 5) & 0x7;
 174         switch (addr & 0xC) {
 175         case PCI_POTAR:
 176             pci->pob[idx].potar = value;
 177             break;
 178         case PCI_POTEAR:
 179             pci->pob[idx].potear = value;
 180             break;
 181         case PCI_POWBAR:
 182             pci->pob[idx].powbar = value;
 183             break;
 184         case PCI_POWAR:
 185             pci->pob[idx].powar = value;
 186             break;
 187         default:
 188             break;
 189         };
 190         break;
 191
 192     case PPCE500_PCI_IW3:
 193     case PPCE500_PCI_IW2:
 194     case PPCE500_PCI_IW1:
 195         idx = ((addr >> 5) & 0x3) - 1;
 196         switch (addr & 0xC) {
 197         case PCI_PITAR:
 198             pci->pib[idx].pitar = value;
 199             break;
 200         case PCI_PIWBAR:
 201             pci->pib[idx].piwbar = value;
 202             break;
 203         case PCI_PIWBEAR:
 204             pci->pib[idx].piwbear = value;
 205             break;
 206         case PCI_PIWAR:
 207             pci->pib[idx].piwar = value;
 208             break;
 209         default:
 210             break;
 211         };
 212         break;
 213
 214     case PPCE500_PCI_GASKET_TIMR:
 215         pci->gasket_time = value;
 216         break;
 217
 218     default:
 219         break;
 220     };
 221 }
 222
 223 static const MemoryRegionOps e500_pci_reg_ops = {
 224     .read = pci_reg_read4,
 225     .write = pci_reg_write4,
 226     .endianness = DEVICE_BIG_ENDIAN,
 227 };
 228
 229 static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
 230 {
 231     int devno = pci_dev->devfn >> 3, ret = 0;
 232
 233     switch (devno) {
 234         /* Two PCI slot */
 235         case 0x11:
 236         case 0x12:
 237             ret = (irq_num + devno - 0x10) % 4;
 238             break;
 239         default:
 240             printf("Error:%s:unknown dev number\n", __func__);
 241     }
 242
 243     pci_debug("%s: devfn %x irq %d -> %d  devno:%x\n", __func__,
 244            pci_dev->devfn, irq_num, ret, devno);
 245
 246     return ret;
 247 }
 248
 249 static void mpc85xx_pci_set_irq(void *opaque, int irq_num, int level)
 250 {
 251     qemu_irq *pic = opaque;
 252
 253     pci_debug("%s: PCI irq %d, level:%d\n", __func__, irq_num, level);
 254
 255     qemu_set_irq(pic[irq_num], level);
 256 }
 257
 258 static const VMStateDescription vmstate_pci_outbound = {
 259     .name = "pci_outbound",
 260     .version_id = 0,
 261     .minimum_version_id = 0,
 262     .minimum_version_id_old = 0,
 263     .fields      = (VMStateField[]) {
 264         VMSTATE_UINT32(potar, struct pci_outbound),
 265         VMSTATE_UINT32(potear, struct pci_outbound),
 266         VMSTATE_UINT32(powbar, struct pci_outbound),
 267         VMSTATE_UINT32(powar, struct pci_outbound),
 268         VMSTATE_END_OF_LIST()
 269     }
 270 };
 271
 272 static const VMStateDescription vmstate_pci_inbound = {
 273     .name = "pci_inbound",
 274     .version_id = 0,
 275     .minimum_version_id = 0,
 276     .minimum_version_id_old = 0,
 277     .fields      = (VMStateField[]) {
 278         VMSTATE_UINT32(pitar, struct pci_inbound),
 279         VMSTATE_UINT32(piwbar, struct pci_inbound),
 280         VMSTATE_UINT32(piwbear, struct pci_inbound),
 281         VMSTATE_UINT32(piwar, struct pci_inbound),
 282         VMSTATE_END_OF_LIST()
 283     }
 284 };
 285
 286 static const VMStateDescription vmstate_ppce500_pci = {
 287     .name = "ppce500_pci",
 288     .version_id = 1,
 289     .minimum_version_id = 1,
 290     .minimum_version_id_old = 1,
 291     .fields      = (VMStateField[]) {
 292         VMSTATE_STRUCT_ARRAY(pob, PPCE500PCIState, PPCE500_PCI_NR_POBS, 1,
 293                              vmstate_pci_outbound, struct pci_outbound),
 294         VMSTATE_STRUCT_ARRAY(pib, PPCE500PCIState, PPCE500_PCI_NR_PIBS, 1,
 295                              vmstate_pci_outbound, struct pci_inbound),
 296         VMSTATE_UINT32(gasket_time, PPCE500PCIState),
 297         VMSTATE_END_OF_LIST()
 298     }
 299 };
 300
 301 static void e500_pci_map(SysBusDevice *dev, target_phys_addr_t base)
 302 {
 303     PCIHostState *h = FROM_SYSBUS(PCIHostState, sysbus_from_qdev(dev));
 304     PPCE500PCIState *s = DO_UPCAST(PPCE500PCIState, pci_state, h);
 305
 306     sysbus_add_memory(dev, base + PCIE500_CFGADDR, &h->conf_mem);
 307     sysbus_add_memory(dev, base + PCIE500_CFGDATA, &h->data_mem);
 308     sysbus_add_memory(dev, base + PCIE500_REG_BASE, &s->iomem);
 309 }
 310
 311 static void e500_pci_unmap(SysBusDevice *dev, target_phys_addr_t base)
 312 {
 313     PCIHostState *h = FROM_SYSBUS(PCIHostState, sysbus_from_qdev(dev));
 314     PPCE500PCIState *s = DO_UPCAST(PPCE500PCIState, pci_state, h);
 315
 316     sysbus_del_memory(dev, &h->conf_mem);
 317     sysbus_del_memory(dev, &h->data_mem);
 318     sysbus_del_memory(dev, &s->iomem);
 319 }
 320
 321 #include "exec-memory.h"
 322
 323 static int e500_pcihost_initfn(SysBusDevice *dev)
 324 {
 325     PCIHostState *h;
 326     PPCE500PCIState *s;
 327     PCIBus *b;
 328     int i;
 329     MemoryRegion *address_space_mem = get_system_memory();
 330     MemoryRegion *address_space_io = get_system_io();
 331
 332     h = FROM_SYSBUS(PCIHostState, sysbus_from_qdev(dev));
 333     s = DO_UPCAST(PPCE500PCIState, pci_state, h);
 334
 335     for (i = 0; i < ARRAY_SIZE(s->irq); i++) {
 336         sysbus_init_irq(dev, &s->irq[i]);
 337     }
 338
 339     b = pci_register_bus(&s->pci_state.busdev.qdev, NULL, mpc85xx_pci_set_irq,
 340                          mpc85xx_pci_map_irq, s->irq, address_space_mem,
 341                          address_space_io, PCI_DEVFN(0x11, 0), 4);
 342     s->pci_state.bus = b;
 343
 344     pci_create_simple(b, 0, "e500-host-bridge");
 345
 346     memory_region_init_io(&h->conf_mem, &pci_host_conf_be_ops, h,
 347                           "pci-conf-idx", 4);
 348     memory_region_init_io(&h->data_mem, &pci_host_data_le_ops, h,
 349                           "pci-conf-data", 4);
 350     memory_region_init_io(&s->iomem, &e500_pci_reg_ops, s,
 351                           "pci.reg", PCIE500_REG_SIZE);
 352     sysbus_init_mmio_cb2(dev, e500_pci_map, e500_pci_unmap);
 353
 354     return 0;
 355 }
 356
 357 static PCIDeviceInfo e500_host_bridge_info = {
 358     .qdev.name    = "e500-host-bridge",
 359     .qdev.desc    = "Host bridge",
 360     .qdev.size    = sizeof(PCIDevice),
 361     .vendor_id    = PCI_VENDOR_ID_FREESCALE,
 362     .device_id    = PCI_DEVICE_ID_MPC8533E,
 363     .class_id     = PCI_CLASS_PROCESSOR_POWERPC,
 364 };
 365
 366 static SysBusDeviceInfo e500_pcihost_info = {
 367     .init         = e500_pcihost_initfn,
 368     .qdev.name    = "e500-pcihost",
 369     .qdev.size    = sizeof(PPCE500PCIState),
 370     .qdev.vmsd    = &vmstate_ppce500_pci,
 371 };
 372
 373 static void e500_pci_register(void)
 374 {
 375     sysbus_register_withprop(&e500_pcihost_info);
 376     pci_qdev_register(&e500_host_bridge_info);
 377 }
 378 device_init(e500_pci_register);