hw/arm_gic.c

   1 /*
   2  * ARM Generic/Distributed Interrupt Controller
   3  *
   4  * Copyright (c) 2006-2007 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GPL.
   8  */
   9
  10 /* This file contains implementation code for the RealView EB interrupt
  11    controller, MPCore distributed interrupt controller and ARMv7-M
  12    Nested Vectored Interrupt Controller.  */
  13
  14 //#define DEBUG_GIC
  15
  16 #ifdef DEBUG_GIC
  17 #define DPRINTF(fmt, ...) \
  18 do { printf("arm_gic: " fmt , ## __VA_ARGS__); } while (0)
  19 #else
  20 #define DPRINTF(fmt, ...) do {} while(0)
  21 #endif
  22
  23 #ifdef NVIC
  24 static const uint8_t gic_id[] =
  25 { 0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1 };
  26 /* The NVIC has 16 internal vectors.  However these are not exposed
  27    through the normal GIC interface.  */
  28 #define GIC_BASE_IRQ    32
  29 #else
  30 static const uint8_t gic_id[] =
  31 { 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
  32 #define GIC_BASE_IRQ    0
  33 #endif
  34
  35 #define FROM_SYSBUSGIC(type, dev) \
  36     DO_UPCAST(type, gic, FROM_SYSBUS(gic_state, dev))
  37
  38 typedef struct gic_irq_state
  39 {
  40     /* The enable bits are only banked for per-cpu interrupts.  */
  41     unsigned enabled:NCPU;
  42     unsigned pending:NCPU;
  43     unsigned active:NCPU;
  44     unsigned level:NCPU;
  45     unsigned model:1; /* 0 = N:N, 1 = 1:N */
  46     unsigned trigger:1; /* nonzero = edge triggered.  */
  47 } gic_irq_state;
  48
  49 #define ALL_CPU_MASK ((1 << NCPU) - 1)
  50 #if NCPU > 1
  51 #define NUM_CPU(s) ((s)->num_cpu)
  52 #else
  53 #define NUM_CPU(s) 1
  54 #endif
  55
  56 #define GIC_SET_ENABLED(irq, cm) s->irq_state[irq].enabled |= (cm)
  57 #define GIC_CLEAR_ENABLED(irq, cm) s->irq_state[irq].enabled &= ~(cm)
  58 #define GIC_TEST_ENABLED(irq, cm) ((s->irq_state[irq].enabled & (cm)) != 0)
  59 #define GIC_SET_PENDING(irq, cm) s->irq_state[irq].pending |= (cm)
  60 #define GIC_CLEAR_PENDING(irq, cm) s->irq_state[irq].pending &= ~(cm)
  61 #define GIC_TEST_PENDING(irq, cm) ((s->irq_state[irq].pending & (cm)) != 0)
  62 #define GIC_SET_ACTIVE(irq, cm) s->irq_state[irq].active |= (cm)
  63 #define GIC_CLEAR_ACTIVE(irq, cm) s->irq_state[irq].active &= ~(cm)
  64 #define GIC_TEST_ACTIVE(irq, cm) ((s->irq_state[irq].active & (cm)) != 0)
  65 #define GIC_SET_MODEL(irq) s->irq_state[irq].model = 1
  66 #define GIC_CLEAR_MODEL(irq) s->irq_state[irq].model = 0
  67 #define GIC_TEST_MODEL(irq) s->irq_state[irq].model
  68 #define GIC_SET_LEVEL(irq, cm) s->irq_state[irq].level = (cm)
  69 #define GIC_CLEAR_LEVEL(irq, cm) s->irq_state[irq].level &= ~(cm)
  70 #define GIC_TEST_LEVEL(irq, cm) ((s->irq_state[irq].level & (cm)) != 0)
  71 #define GIC_SET_TRIGGER(irq) s->irq_state[irq].trigger = 1
  72 #define GIC_CLEAR_TRIGGER(irq) s->irq_state[irq].trigger = 0
  73 #define GIC_TEST_TRIGGER(irq) s->irq_state[irq].trigger
  74 #define GIC_GET_PRIORITY(irq, cpu) \
  75   (((irq) < 32) ? s->priority1[irq][cpu] : s->priority2[(irq) - 32])
  76 #ifdef NVIC
  77 #define GIC_TARGET(irq) 1
  78 #else
  79 #define GIC_TARGET(irq) s->irq_target[irq]
  80 #endif
  81
  82 typedef struct gic_state
  83 {
  84     SysBusDevice busdev;
  85     qemu_irq parent_irq[NCPU];
  86     int enabled;
  87     int cpu_enabled[NCPU];
  88
  89     gic_irq_state irq_state[GIC_NIRQ];
  90 #ifndef NVIC
  91     int irq_target[GIC_NIRQ];
  92 #endif
  93     int priority1[32][NCPU];
  94     int priority2[GIC_NIRQ - 32];
  95     int last_active[GIC_NIRQ][NCPU];
  96
  97     int priority_mask[NCPU];
  98     int running_irq[NCPU];
  99     int running_priority[NCPU];
 100     int current_pending[NCPU];
 101
 102 #if NCPU > 1
 103     int num_cpu;
 104 #endif
 105
 106     MemoryRegion iomem;
 107 } gic_state;
 108
 109 /* TODO: Many places that call this routine could be optimized.  */
 110 /* Update interrupt status after enabled or pending bits have been changed.  */
 111 static void gic_update(gic_state *s)
 112 {
 113     int best_irq;
 114     int best_prio;
 115     int irq;
 116     int level;
 117     int cpu;
 118     int cm;
 119
 120     for (cpu = 0; cpu < NUM_CPU(s); cpu++) {
 121         cm = 1 << cpu;
 122         s->current_pending[cpu] = 1023;
 123         if (!s->enabled || !s->cpu_enabled[cpu]) {
 124             qemu_irq_lower(s->parent_irq[cpu]);
 125             return;
 126         }
 127         best_prio = 0x100;
 128         best_irq = 1023;
 129         for (irq = 0; irq < GIC_NIRQ; irq++) {
 130             if (GIC_TEST_ENABLED(irq, cm) && GIC_TEST_PENDING(irq, cm)) {
 131                 if (GIC_GET_PRIORITY(irq, cpu) < best_prio) {
 132                     best_prio = GIC_GET_PRIORITY(irq, cpu);
 133                     best_irq = irq;
 134                 }
 135             }
 136         }
 137         level = 0;
 138         if (best_prio <= s->priority_mask[cpu]) {
 139             s->current_pending[cpu] = best_irq;
 140             if (best_prio < s->running_priority[cpu]) {
 141                 DPRINTF("Raised pending IRQ %d\n", best_irq);
 142                 level = 1;
 143             }
 144         }
 145         qemu_set_irq(s->parent_irq[cpu], level);
 146     }
 147 }
 148
 149 static void __attribute__((unused))
 150 gic_set_pending_private(gic_state *s, int cpu, int irq)
 151 {
 152     int cm = 1 << cpu;
 153
 154     if (GIC_TEST_PENDING(irq, cm))
 155         return;
 156
 157     DPRINTF("Set %d pending cpu %d\n", irq, cpu);
 158     GIC_SET_PENDING(irq, cm);
 159     gic_update(s);
 160 }
 161
 162 /* Process a change in an external IRQ input.  */
 163 static void gic_set_irq(void *opaque, int irq, int level)
 164 {
 165     gic_state *s = (gic_state *)opaque;
 166     /* The first external input line is internal interrupt 32.  */
 167     irq += 32;
 168     if (level == GIC_TEST_LEVEL(irq, ALL_CPU_MASK))
 169         return;
 170
 171     if (level) {
 172         GIC_SET_LEVEL(irq, ALL_CPU_MASK);
 173         if (GIC_TEST_TRIGGER(irq) || GIC_TEST_ENABLED(irq, ALL_CPU_MASK)) {
 174             DPRINTF("Set %d pending mask %x\n", irq, GIC_TARGET(irq));
 175             GIC_SET_PENDING(irq, GIC_TARGET(irq));
 176         }
 177     } else {
 178         GIC_CLEAR_LEVEL(irq, ALL_CPU_MASK);
 179     }
 180     gic_update(s);
 181 }
 182
 183 static void gic_set_running_irq(gic_state *s, int cpu, int irq)
 184 {
 185     s->running_irq[cpu] = irq;
 186     if (irq == 1023) {
 187         s->running_priority[cpu] = 0x100;
 188     } else {
 189         s->running_priority[cpu] = GIC_GET_PRIORITY(irq, cpu);
 190     }
 191     gic_update(s);
 192 }
 193
 194 static uint32_t gic_acknowledge_irq(gic_state *s, int cpu)
 195 {
 196     int new_irq;
 197     int cm = 1 << cpu;
 198     new_irq = s->current_pending[cpu];
 199     if (new_irq == 1023
 200             || GIC_GET_PRIORITY(new_irq, cpu) >= s->running_priority[cpu]) {
 201         DPRINTF("ACK no pending IRQ\n");
 202         return 1023;
 203     }
 204     s->last_active[new_irq][cpu] = s->running_irq[cpu];
 205     /* Clear pending flags for both level and edge triggered interrupts.
 206        Level triggered IRQs will be reasserted once they become inactive.  */
 207     GIC_CLEAR_PENDING(new_irq, GIC_TEST_MODEL(new_irq) ? ALL_CPU_MASK : cm);
 208     gic_set_running_irq(s, cpu, new_irq);
 209     DPRINTF("ACK %d\n", new_irq);
 210     return new_irq;
 211 }
 212
 213 static void gic_complete_irq(gic_state * s, int cpu, int irq)
 214 {
 215     int update = 0;
 216     int cm = 1 << cpu;
 217     DPRINTF("EOI %d\n", irq);
 218     if (irq >= GIC_NIRQ) {
 219         /* This handles two cases:
 220          * 1. If software writes the ID of a spurious interrupt [ie 1023]
 221          * to the GICC_EOIR, the GIC ignores that write.
 222          * 2. If software writes the number of a non-existent interrupt
 223          * this must be a subcase of "value written does not match the last
 224          * valid interrupt value read from the Interrupt Acknowledge
 225          * register" and so this is UNPREDICTABLE. We choose to ignore it.
 226          */
 227         return;
 228     }
 229     if (s->running_irq[cpu] == 1023)
 230         return; /* No active IRQ.  */
 231     /* Mark level triggered interrupts as pending if they are still
 232        raised.  */
 233     if (!GIC_TEST_TRIGGER(irq) && GIC_TEST_ENABLED(irq, cm)
 234         && GIC_TEST_LEVEL(irq, cm) && (GIC_TARGET(irq) & cm) != 0) {
 235         DPRINTF("Set %d pending mask %x\n", irq, cm);
 236         GIC_SET_PENDING(irq, cm);
 237         update = 1;
 238     }
 239     if (irq != s->running_irq[cpu]) {
 240         /* Complete an IRQ that is not currently running.  */
 241         int tmp = s->running_irq[cpu];
 242         while (s->last_active[tmp][cpu] != 1023) {
 243             if (s->last_active[tmp][cpu] == irq) {
 244                 s->last_active[tmp][cpu] = s->last_active[irq][cpu];
 245                 break;
 246             }
 247             tmp = s->last_active[tmp][cpu];
 248         }
 249         if (update) {
 250             gic_update(s);
 251         }
 252     } else {
 253         /* Complete the current running IRQ.  */
 254         gic_set_running_irq(s, cpu, s->last_active[s->running_irq[cpu]][cpu]);
 255     }
 256 }
 257
 258 static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset)
 259 {
 260     gic_state *s = (gic_state *)opaque;
 261     uint32_t res;
 262     int irq;
 263     int i;
 264     int cpu;
 265     int cm;
 266     int mask;
 267
 268     cpu = gic_get_current_cpu();
 269     cm = 1 << cpu;
 270     if (offset < 0x100) {
 271 #ifndef NVIC
 272         if (offset == 0)
 273             return s->enabled;
 274         if (offset == 4)
 275             return ((GIC_NIRQ / 32) - 1) | ((NUM_CPU(s) - 1) << 5);
 276         if (offset < 0x08)
 277             return 0;
 278 #endif
 279         goto bad_reg;
 280     } else if (offset < 0x200) {
 281         /* Interrupt Set/Clear Enable.  */
 282         if (offset < 0x180)
 283             irq = (offset - 0x100) * 8;
 284         else
 285             irq = (offset - 0x180) * 8;
 286         irq += GIC_BASE_IRQ;
 287         if (irq >= GIC_NIRQ)
 288             goto bad_reg;
 289         res = 0;
 290         for (i = 0; i < 8; i++) {
 291             if (GIC_TEST_ENABLED(irq + i, cm)) {
 292                 res |= (1 << i);
 293             }
 294         }
 295     } else if (offset < 0x300) {
 296         /* Interrupt Set/Clear Pending.  */
 297         if (offset < 0x280)
 298             irq = (offset - 0x200) * 8;
 299         else
 300             irq = (offset - 0x280) * 8;
 301         irq += GIC_BASE_IRQ;
 302         if (irq >= GIC_NIRQ)
 303             goto bad_reg;
 304         res = 0;
 305         mask = (irq < 32) ?  cm : ALL_CPU_MASK;
 306         for (i = 0; i < 8; i++) {
 307             if (GIC_TEST_PENDING(irq + i, mask)) {
 308                 res |= (1 << i);
 309             }
 310         }
 311     } else if (offset < 0x400) {
 312         /* Interrupt Active.  */
 313         irq = (offset - 0x300) * 8 + GIC_BASE_IRQ;
 314         if (irq >= GIC_NIRQ)
 315             goto bad_reg;
 316         res = 0;
 317         mask = (irq < 32) ?  cm : ALL_CPU_MASK;
 318         for (i = 0; i < 8; i++) {
 319             if (GIC_TEST_ACTIVE(irq + i, mask)) {
 320                 res |= (1 << i);
 321             }
 322         }
 323     } else if (offset < 0x800) {
 324         /* Interrupt Priority.  */
 325         irq = (offset - 0x400) + GIC_BASE_IRQ;
 326         if (irq >= GIC_NIRQ)
 327             goto bad_reg;
 328         res = GIC_GET_PRIORITY(irq, cpu);
 329 #ifndef NVIC
 330     } else if (offset < 0xc00) {
 331         /* Interrupt CPU Target.  */
 332         irq = (offset - 0x800) + GIC_BASE_IRQ;
 333         if (irq >= GIC_NIRQ)
 334             goto bad_reg;
 335         if (irq >= 29 && irq <= 31) {
 336             res = cm;
 337         } else {
 338             res = GIC_TARGET(irq);
 339         }
 340     } else if (offset < 0xf00) {
 341         /* Interrupt Configuration.  */
 342         irq = (offset - 0xc00) * 2 + GIC_BASE_IRQ;
 343         if (irq >= GIC_NIRQ)
 344             goto bad_reg;
 345         res = 0;
 346         for (i = 0; i < 4; i++) {
 347             if (GIC_TEST_MODEL(irq + i))
 348                 res |= (1 << (i * 2));
 349             if (GIC_TEST_TRIGGER(irq + i))
 350                 res |= (2 << (i * 2));
 351         }
 352 #endif
 353     } else if (offset < 0xfe0) {
 354         goto bad_reg;
 355     } else /* offset >= 0xfe0 */ {
 356         if (offset & 3) {
 357             res = 0;
 358         } else {
 359             res = gic_id[(offset - 0xfe0) >> 2];
 360         }
 361     }
 362     return res;
 363 bad_reg:
 364     hw_error("gic_dist_readb: Bad offset %x\n", (int)offset);
 365     return 0;
 366 }
 367
 368 static uint32_t gic_dist_readw(void *opaque, target_phys_addr_t offset)
 369 {
 370     uint32_t val;
 371     val = gic_dist_readb(opaque, offset);
 372     val |= gic_dist_readb(opaque, offset + 1) << 8;
 373     return val;
 374 }
 375
 376 static uint32_t gic_dist_readl(void *opaque, target_phys_addr_t offset)
 377 {
 378     uint32_t val;
 379 #ifdef NVIC
 380     gic_state *s = (gic_state *)opaque;
 381     uint32_t addr;
 382     addr = offset;
 383     if (addr < 0x100 || addr > 0xd00)
 384         return nvic_readl(s, addr);
 385 #endif
 386     val = gic_dist_readw(opaque, offset);
 387     val |= gic_dist_readw(opaque, offset + 2) << 16;
 388     return val;
 389 }
 390
 391 static void gic_dist_writeb(void *opaque, target_phys_addr_t offset,
 392                             uint32_t value)
 393 {
 394     gic_state *s = (gic_state *)opaque;
 395     int irq;
 396     int i;
 397     int cpu;
 398
 399     cpu = gic_get_current_cpu();
 400     if (offset < 0x100) {
 401 #ifdef NVIC
 402         goto bad_reg;
 403 #else
 404         if (offset == 0) {
 405             s->enabled = (value & 1);
 406             DPRINTF("Distribution %sabled\n", s->enabled ? "En" : "Dis");
 407         } else if (offset < 4) {
 408             /* ignored.  */
 409         } else {
 410             goto bad_reg;
 411         }
 412 #endif
 413     } else if (offset < 0x180) {
 414         /* Interrupt Set Enable.  */
 415         irq = (offset - 0x100) * 8 + GIC_BASE_IRQ;
 416         if (irq >= GIC_NIRQ)
 417             goto bad_reg;
 418         if (irq < 16)
 419           value = 0xff;
 420         for (i = 0; i < 8; i++) {
 421             if (value & (1 << i)) {
 422                 int mask = (irq < 32) ? (1 << cpu) : GIC_TARGET(irq);
 423                 int cm = (irq < 32) ? (1 << cpu) : ALL_CPU_MASK;
 424
 425                 if (!GIC_TEST_ENABLED(irq + i, cm)) {
 426                     DPRINTF("Enabled IRQ %d\n", irq + i);
 427                 }
 428                 GIC_SET_ENABLED(irq + i, cm);
 429                 /* If a raised level triggered IRQ enabled then mark
 430                    is as pending.  */
 431                 if (GIC_TEST_LEVEL(irq + i, mask)
 432                         && !GIC_TEST_TRIGGER(irq + i)) {
 433                     DPRINTF("Set %d pending mask %x\n", irq + i, mask);
 434                     GIC_SET_PENDING(irq + i, mask);
 435                 }
 436             }
 437         }
 438     } else if (offset < 0x200) {
 439         /* Interrupt Clear Enable.  */
 440         irq = (offset - 0x180) * 8 + GIC_BASE_IRQ;
 441         if (irq >= GIC_NIRQ)
 442             goto bad_reg;
 443         if (irq < 16)
 444           value = 0;
 445         for (i = 0; i < 8; i++) {
 446             if (value & (1 << i)) {
 447                 int cm = (irq < 32) ? (1 << cpu) : ALL_CPU_MASK;
 448
 449                 if (GIC_TEST_ENABLED(irq + i, cm)) {
 450                     DPRINTF("Disabled IRQ %d\n", irq + i);
 451                 }
 452                 GIC_CLEAR_ENABLED(irq + i, cm);
 453             }
 454         }
 455     } else if (offset < 0x280) {
 456         /* Interrupt Set Pending.  */
 457         irq = (offset - 0x200) * 8 + GIC_BASE_IRQ;
 458         if (irq >= GIC_NIRQ)
 459             goto bad_reg;
 460         if (irq < 16)
 461           irq = 0;
 462
 463         for (i = 0; i < 8; i++) {
 464             if (value & (1 << i)) {
 465                 GIC_SET_PENDING(irq + i, GIC_TARGET(irq));
 466             }
 467         }
 468     } else if (offset < 0x300) {
 469         /* Interrupt Clear Pending.  */
 470         irq = (offset - 0x280) * 8 + GIC_BASE_IRQ;
 471         if (irq >= GIC_NIRQ)
 472             goto bad_reg;
 473         for (i = 0; i < 8; i++) {
 474             /* ??? This currently clears the pending bit for all CPUs, even
 475                for per-CPU interrupts.  It's unclear whether this is the
 476                corect behavior.  */
 477             if (value & (1 << i)) {
 478                 GIC_CLEAR_PENDING(irq + i, ALL_CPU_MASK);
 479             }
 480         }
 481     } else if (offset < 0x400) {
 482         /* Interrupt Active.  */
 483         goto bad_reg;
 484     } else if (offset < 0x800) {
 485         /* Interrupt Priority.  */
 486         irq = (offset - 0x400) + GIC_BASE_IRQ;
 487         if (irq >= GIC_NIRQ)
 488             goto bad_reg;
 489         if (irq < 32) {
 490             s->priority1[irq][cpu] = value;
 491         } else {
 492             s->priority2[irq - 32] = value;
 493         }
 494 #ifndef NVIC
 495     } else if (offset < 0xc00) {
 496         /* Interrupt CPU Target.  */
 497         irq = (offset - 0x800) + GIC_BASE_IRQ;
 498         if (irq >= GIC_NIRQ)
 499             goto bad_reg;
 500         if (irq < 29)
 501             value = 0;
 502         else if (irq < 32)
 503             value = ALL_CPU_MASK;
 504         s->irq_target[irq] = value & ALL_CPU_MASK;
 505     } else if (offset < 0xf00) {
 506         /* Interrupt Configuration.  */
 507         irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ;
 508         if (irq >= GIC_NIRQ)
 509             goto bad_reg;
 510         if (irq < 32)
 511             value |= 0xaa;
 512         for (i = 0; i < 4; i++) {
 513             if (value & (1 << (i * 2))) {
 514                 GIC_SET_MODEL(irq + i);
 515             } else {
 516                 GIC_CLEAR_MODEL(irq + i);
 517             }
 518             if (value & (2 << (i * 2))) {
 519                 GIC_SET_TRIGGER(irq + i);
 520             } else {
 521                 GIC_CLEAR_TRIGGER(irq + i);
 522             }
 523         }
 524 #endif
 525     } else {
 526         /* 0xf00 is only handled for 32-bit writes.  */
 527         goto bad_reg;
 528     }
 529     gic_update(s);
 530     return;
 531 bad_reg:
 532     hw_error("gic_dist_writeb: Bad offset %x\n", (int)offset);
 533 }
 534
 535 static void gic_dist_writew(void *opaque, target_phys_addr_t offset,
 536                             uint32_t value)
 537 {
 538     gic_dist_writeb(opaque, offset, value & 0xff);
 539     gic_dist_writeb(opaque, offset + 1, value >> 8);
 540 }
 541
 542 static void gic_dist_writel(void *opaque, target_phys_addr_t offset,
 543                             uint32_t value)
 544 {
 545     gic_state *s = (gic_state *)opaque;
 546 #ifdef NVIC
 547     uint32_t addr;
 548     addr = offset;
 549     if (addr < 0x100 || (addr > 0xd00 && addr != 0xf00)) {
 550         nvic_writel(s, addr, value);
 551         return;
 552     }
 553 #endif
 554     if (offset == 0xf00) {
 555         int cpu;
 556         int irq;
 557         int mask;
 558
 559         cpu = gic_get_current_cpu();
 560         irq = value & 0x3ff;
 561         switch ((value >> 24) & 3) {
 562         case 0:
 563             mask = (value >> 16) & ALL_CPU_MASK;
 564             break;
 565         case 1:
 566             mask = ALL_CPU_MASK ^ (1 << cpu);
 567             break;
 568         case 2:
 569             mask = 1 << cpu;
 570             break;
 571         default:
 572             DPRINTF("Bad Soft Int target filter\n");
 573             mask = ALL_CPU_MASK;
 574             break;
 575         }
 576         GIC_SET_PENDING(irq, mask);
 577         gic_update(s);
 578         return;
 579     }
 580     gic_dist_writew(opaque, offset, value & 0xffff);
 581     gic_dist_writew(opaque, offset + 2, value >> 16);
 582 }
 583
 584 static const MemoryRegionOps gic_dist_ops = {
 585     .old_mmio = {
 586         .read = { gic_dist_readb, gic_dist_readw, gic_dist_readl, },
 587         .write = { gic_dist_writeb, gic_dist_writew, gic_dist_writel, },
 588     },
 589     .endianness = DEVICE_NATIVE_ENDIAN,
 590 };
 591
 592 #ifndef NVIC
 593 static uint32_t gic_cpu_read(gic_state *s, int cpu, int offset)
 594 {
 595     switch (offset) {
 596     case 0x00: /* Control */
 597         return s->cpu_enabled[cpu];
 598     case 0x04: /* Priority mask */
 599         return s->priority_mask[cpu];
 600     case 0x08: /* Binary Point */
 601         /* ??? Not implemented.  */
 602         return 0;
 603     case 0x0c: /* Acknowledge */
 604         return gic_acknowledge_irq(s, cpu);
 605     case 0x14: /* Runing Priority */
 606         return s->running_priority[cpu];
 607     case 0x18: /* Highest Pending Interrupt */
 608         return s->current_pending[cpu];
 609     default:
 610         hw_error("gic_cpu_read: Bad offset %x\n", (int)offset);
 611         return 0;
 612     }
 613 }
 614
 615 static void gic_cpu_write(gic_state *s, int cpu, int offset, uint32_t value)
 616 {
 617     switch (offset) {
 618     case 0x00: /* Control */
 619         s->cpu_enabled[cpu] = (value & 1);
 620         DPRINTF("CPU %d %sabled\n", cpu, s->cpu_enabled ? "En" : "Dis");
 621         break;
 622     case 0x04: /* Priority mask */
 623         s->priority_mask[cpu] = (value & 0xff);
 624         break;
 625     case 0x08: /* Binary Point */
 626         /* ??? Not implemented.  */
 627         break;
 628     case 0x10: /* End Of Interrupt */
 629         return gic_complete_irq(s, cpu, value & 0x3ff);
 630     default:
 631         hw_error("gic_cpu_write: Bad offset %x\n", (int)offset);
 632         return;
 633     }
 634     gic_update(s);
 635 }
 636 #endif
 637
 638 static void gic_reset(gic_state *s)
 639 {
 640     int i;
 641     memset(s->irq_state, 0, GIC_NIRQ * sizeof(gic_irq_state));
 642     for (i = 0 ; i < NUM_CPU(s); i++) {
 643         s->priority_mask[i] = 0xf0;
 644         s->current_pending[i] = 1023;
 645         s->running_irq[i] = 1023;
 646         s->running_priority[i] = 0x100;
 647 #ifdef NVIC
 648         /* The NVIC doesn't have per-cpu interfaces, so enable by default.  */
 649         s->cpu_enabled[i] = 1;
 650 #else
 651         s->cpu_enabled[i] = 0;
 652 #endif
 653     }
 654     for (i = 0; i < 16; i++) {
 655         GIC_SET_ENABLED(i, ALL_CPU_MASK);
 656         GIC_SET_TRIGGER(i);
 657     }
 658 #ifdef NVIC
 659     /* The NVIC is always enabled.  */
 660     s->enabled = 1;
 661 #else
 662     s->enabled = 0;
 663 #endif
 664 }
 665
 666 static void gic_save(QEMUFile *f, void *opaque)
 667 {
 668     gic_state *s = (gic_state *)opaque;
 669     int i;
 670     int j;
 671
 672     qemu_put_be32(f, s->enabled);
 673     for (i = 0; i < NUM_CPU(s); i++) {
 674         qemu_put_be32(f, s->cpu_enabled[i]);
 675         for (j = 0; j < 32; j++)
 676             qemu_put_be32(f, s->priority1[j][i]);
 677         for (j = 0; j < GIC_NIRQ; j++)
 678             qemu_put_be32(f, s->last_active[j][i]);
 679         qemu_put_be32(f, s->priority_mask[i]);
 680         qemu_put_be32(f, s->running_irq[i]);
 681         qemu_put_be32(f, s->running_priority[i]);
 682         qemu_put_be32(f, s->current_pending[i]);
 683     }
 684     for (i = 0; i < GIC_NIRQ - 32; i++) {
 685         qemu_put_be32(f, s->priority2[i]);
 686     }
 687     for (i = 0; i < GIC_NIRQ; i++) {
 688 #ifndef NVIC
 689         qemu_put_be32(f, s->irq_target[i]);
 690 #endif
 691         qemu_put_byte(f, s->irq_state[i].enabled);
 692         qemu_put_byte(f, s->irq_state[i].pending);
 693         qemu_put_byte(f, s->irq_state[i].active);
 694         qemu_put_byte(f, s->irq_state[i].level);
 695         qemu_put_byte(f, s->irq_state[i].model);
 696         qemu_put_byte(f, s->irq_state[i].trigger);
 697     }
 698 }
 699
 700 static int gic_load(QEMUFile *f, void *opaque, int version_id)
 701 {
 702     gic_state *s = (gic_state *)opaque;
 703     int i;
 704     int j;
 705
 706     if (version_id != 2)
 707         return -EINVAL;
 708
 709     s->enabled = qemu_get_be32(f);
 710     for (i = 0; i < NUM_CPU(s); i++) {
 711         s->cpu_enabled[i] = qemu_get_be32(f);
 712         for (j = 0; j < 32; j++)
 713             s->priority1[j][i] = qemu_get_be32(f);
 714         for (j = 0; j < GIC_NIRQ; j++)
 715             s->last_active[j][i] = qemu_get_be32(f);
 716         s->priority_mask[i] = qemu_get_be32(f);
 717         s->running_irq[i] = qemu_get_be32(f);
 718         s->running_priority[i] = qemu_get_be32(f);
 719         s->current_pending[i] = qemu_get_be32(f);
 720     }
 721     for (i = 0; i < GIC_NIRQ - 32; i++) {
 722         s->priority2[i] = qemu_get_be32(f);
 723     }
 724     for (i = 0; i < GIC_NIRQ; i++) {
 725 #ifndef NVIC
 726         s->irq_target[i] = qemu_get_be32(f);
 727 #endif
 728         s->irq_state[i].enabled = qemu_get_byte(f);
 729         s->irq_state[i].pending = qemu_get_byte(f);
 730         s->irq_state[i].active = qemu_get_byte(f);
 731         s->irq_state[i].level = qemu_get_byte(f);
 732         s->irq_state[i].model = qemu_get_byte(f);
 733         s->irq_state[i].trigger = qemu_get_byte(f);
 734     }
 735
 736     return 0;
 737 }
 738
 739 #if NCPU > 1
 740 static void gic_init(gic_state *s, int num_cpu)
 741 #else
 742 static void gic_init(gic_state *s)
 743 #endif
 744 {
 745     int i;
 746
 747 #if NCPU > 1
 748     s->num_cpu = num_cpu;
 749 #endif
 750     qdev_init_gpio_in(&s->busdev.qdev, gic_set_irq, GIC_NIRQ - 32);
 751     for (i = 0; i < NUM_CPU(s); i++) {
 752         sysbus_init_irq(&s->busdev, &s->parent_irq[i]);
 753     }
 754     memory_region_init_io(&s->iomem, &gic_dist_ops, s, "gic_dist", 0x1000);
 755     gic_reset(s);
 756     register_savevm(NULL, "arm_gic", -1, 2, gic_save, gic_load, s);
 757 }