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net: cadence_gem: Make phy respond to broadcast
[qemu.git] / target-openrisc / translate.c
blob852b5e6107081c97bf1113532e36e4f95c8f585e
1 /*
2 * OpenRISC translation
3 *
4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
5 * Feng Gao <gf91597@gmail.com>
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "cpu.h"
22 #include "exec/exec-all.h"
23 #include "disas/disas.h"
24 #include "tcg-op.h"
25 #include "qemu-common.h"
26 #include "qemu/log.h"
27 #include "config.h"
28 #include "qemu/bitops.h"
29
30 #include "helper.h"
31 #define GEN_HELPER 1
32 #include "helper.h"
33
34 #define OPENRISC_DISAS
35
36 #ifdef OPENRISC_DISAS
37 # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
38 #else
39 # define LOG_DIS(...) do { } while (0)
40 #endif
41
42 typedef struct DisasContext {
43 TranslationBlock *tb;
44 target_ulong pc, ppc, npc;
45 uint32_t tb_flags, synced_flags, flags;
46 uint32_t is_jmp;
47 uint32_t mem_idx;
48 int singlestep_enabled;
49 uint32_t delayed_branch;
50 } DisasContext;
51
52 static TCGv_ptr cpu_env;
53 static TCGv cpu_sr;
54 static TCGv cpu_R[32];
55 static TCGv cpu_pc;
56 static TCGv jmp_pc; /* l.jr/l.jalr temp pc */
57 static TCGv cpu_npc;
58 static TCGv cpu_ppc;
59 static TCGv_i32 env_btaken; /* bf/bnf , F flag taken */
60 static TCGv_i32 fpcsr;
61 static TCGv machi, maclo;
62 static TCGv fpmaddhi, fpmaddlo;
63 static TCGv_i32 env_flags;
64 #include "exec/gen-icount.h"
65
66 void openrisc_translate_init(void)
67 {
68 static const char * const regnames[] = {
69 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
70 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
71 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
72 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
73 };
74 int i;
75
76 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
77 cpu_sr = tcg_global_mem_new(TCG_AREG0,
78 offsetof(CPUOpenRISCState, sr), "sr");
79 env_flags = tcg_global_mem_new_i32(TCG_AREG0,
80 offsetof(CPUOpenRISCState, flags),
81 "flags");
82 cpu_pc = tcg_global_mem_new(TCG_AREG0,
83 offsetof(CPUOpenRISCState, pc), "pc");
84 cpu_npc = tcg_global_mem_new(TCG_AREG0,
85 offsetof(CPUOpenRISCState, npc), "npc");
86 cpu_ppc = tcg_global_mem_new(TCG_AREG0,
87 offsetof(CPUOpenRISCState, ppc), "ppc");
88 jmp_pc = tcg_global_mem_new(TCG_AREG0,
89 offsetof(CPUOpenRISCState, jmp_pc), "jmp_pc");
90 env_btaken = tcg_global_mem_new_i32(TCG_AREG0,
91 offsetof(CPUOpenRISCState, btaken),
92 "btaken");
93 fpcsr = tcg_global_mem_new_i32(TCG_AREG0,
94 offsetof(CPUOpenRISCState, fpcsr),
95 "fpcsr");
96 machi = tcg_global_mem_new(TCG_AREG0,
97 offsetof(CPUOpenRISCState, machi),
98 "machi");
99 maclo = tcg_global_mem_new(TCG_AREG0,
100 offsetof(CPUOpenRISCState, maclo),
101 "maclo");
102 fpmaddhi = tcg_global_mem_new(TCG_AREG0,
103 offsetof(CPUOpenRISCState, fpmaddhi),
104 "fpmaddhi");
105 fpmaddlo = tcg_global_mem_new(TCG_AREG0,
106 offsetof(CPUOpenRISCState, fpmaddlo),
107 "fpmaddlo");
108 for (i = 0; i < 32; i++) {
109 cpu_R[i] = tcg_global_mem_new(TCG_AREG0,
110 offsetof(CPUOpenRISCState, gpr[i]),
111 regnames[i]);
112 }
113 }
114
115 /* Writeback SR_F translation space to execution space. */
116 static inline void wb_SR_F(void)
117 {
118 int label;
119
120 label = gen_new_label();
121 tcg_gen_andi_tl(cpu_sr, cpu_sr, ~SR_F);
122 tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, label);
123 tcg_gen_ori_tl(cpu_sr, cpu_sr, SR_F);
124 gen_set_label(label);
125 }
126
127 static inline int zero_extend(unsigned int val, int width)
128 {
129 return val & ((1 << width) - 1);
130 }
131
132 static inline int sign_extend(unsigned int val, int width)
133 {
134 int sval;
135
136 /* LSL */
137 val <<= TARGET_LONG_BITS - width;
138 sval = val;
139 /* ASR. */
140 sval >>= TARGET_LONG_BITS - width;
141 return sval;
142 }
143
144 static inline void gen_sync_flags(DisasContext *dc)
145 {
146 /* Sync the tb dependent flag between translate and runtime. */
147 if (dc->tb_flags != dc->synced_flags) {
148 tcg_gen_movi_tl(env_flags, dc->tb_flags);
149 dc->synced_flags = dc->tb_flags;
150 }
151 }
152
153 static void gen_exception(DisasContext *dc, unsigned int excp)
154 {
155 TCGv_i32 tmp = tcg_const_i32(excp);
156 gen_helper_exception(cpu_env, tmp);
157 tcg_temp_free_i32(tmp);
158 }
159
160 static void gen_illegal_exception(DisasContext *dc)
161 {
162 tcg_gen_movi_tl(cpu_pc, dc->pc);
163 gen_exception(dc, EXCP_ILLEGAL);
164 dc->is_jmp = DISAS_UPDATE;
165 }
166
167 /* not used yet, open it when we need or64. */
168 /*#ifdef TARGET_OPENRISC64
169 static void check_ob64s(DisasContext *dc)
170 {
171 if (!(dc->flags & CPUCFGR_OB64S)) {
172 gen_illegal_exception(dc);
173 }
174 }
175
176 static void check_of64s(DisasContext *dc)
177 {
178 if (!(dc->flags & CPUCFGR_OF64S)) {
179 gen_illegal_exception(dc);
180 }
181 }
182
183 static void check_ov64s(DisasContext *dc)
184 {
185 if (!(dc->flags & CPUCFGR_OV64S)) {
186 gen_illegal_exception(dc);
187 }
188 }
189 #endif*/
190
191 static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
192 {
193 TranslationBlock *tb;
194 tb = dc->tb;
195 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
196 likely(!dc->singlestep_enabled)) {
197 tcg_gen_movi_tl(cpu_pc, dest);
198 tcg_gen_goto_tb(n);
199 tcg_gen_exit_tb((uintptr_t)tb + n);
200 } else {
201 tcg_gen_movi_tl(cpu_pc, dest);
202 if (dc->singlestep_enabled) {
203 gen_exception(dc, EXCP_DEBUG);
204 }
205 tcg_gen_exit_tb(0);
206 }
207 }
208
209 static void gen_jump(DisasContext *dc, uint32_t imm, uint32_t reg, uint32_t op0)
210 {
211 target_ulong tmp_pc;
212 /* N26, 26bits imm */
213 tmp_pc = sign_extend((imm<<2), 26) + dc->pc;
214
215 switch (op0) {
216 case 0x00: /* l.j */
217 tcg_gen_movi_tl(jmp_pc, tmp_pc);
218 break;
219 case 0x01: /* l.jal */
220 tcg_gen_movi_tl(cpu_R[9], (dc->pc + 8));
221 tcg_gen_movi_tl(jmp_pc, tmp_pc);
222 break;
223 case 0x03: /* l.bnf */
224 case 0x04: /* l.bf */
225 {
226 int lab = gen_new_label();
227 TCGv sr_f = tcg_temp_new();
228 tcg_gen_movi_tl(jmp_pc, dc->pc+8);
229 tcg_gen_andi_tl(sr_f, cpu_sr, SR_F);
230 tcg_gen_brcondi_i32(op0 == 0x03 ? TCG_COND_EQ : TCG_COND_NE,
231 sr_f, SR_F, lab);
232 tcg_gen_movi_tl(jmp_pc, tmp_pc);
233 gen_set_label(lab);
234 tcg_temp_free(sr_f);
235 }
236 break;
237 case 0x11: /* l.jr */
238 tcg_gen_mov_tl(jmp_pc, cpu_R[reg]);
239 break;
240 case 0x12: /* l.jalr */
241 tcg_gen_movi_tl(cpu_R[9], (dc->pc + 8));
242 tcg_gen_mov_tl(jmp_pc, cpu_R[reg]);
243 break;
244 default:
245 gen_illegal_exception(dc);
246 break;
247 }
248
249 dc->delayed_branch = 2;
250 dc->tb_flags |= D_FLAG;
251 gen_sync_flags(dc);
252 }
253
254
255 static void dec_calc(DisasContext *dc, uint32_t insn)
256 {
257 uint32_t op0, op1, op2;
258 uint32_t ra, rb, rd;
259 op0 = extract32(insn, 0, 4);
260 op1 = extract32(insn, 8, 2);
261 op2 = extract32(insn, 6, 2);
262 ra = extract32(insn, 16, 5);
263 rb = extract32(insn, 11, 5);
264 rd = extract32(insn, 21, 5);
265
266 switch (op0) {
267 case 0x0000:
268 switch (op1) {
269 case 0x00: /* l.add */
270 LOG_DIS("l.add r%d, r%d, r%d\n", rd, ra, rb);
271 {
272 int lab = gen_new_label();
273 TCGv_i64 ta = tcg_temp_new_i64();
274 TCGv_i64 tb = tcg_temp_new_i64();
275 TCGv_i64 td = tcg_temp_local_new_i64();
276 TCGv_i32 res = tcg_temp_local_new_i32();
277 TCGv_i32 sr_ove = tcg_temp_local_new_i32();
278 tcg_gen_extu_i32_i64(ta, cpu_R[ra]);
279 tcg_gen_extu_i32_i64(tb, cpu_R[rb]);
280 tcg_gen_add_i64(td, ta, tb);
281 tcg_gen_trunc_i64_i32(res, td);
282 tcg_gen_shri_i64(td, td, 31);
283 tcg_gen_andi_i64(td, td, 0x3);
284 /* Jump to lab when no overflow. */
285 tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x0, lab);
286 tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x3, lab);
287 tcg_gen_ori_i32(cpu_sr, cpu_sr, (SR_OV | SR_CY));
288 tcg_gen_andi_i32(sr_ove, cpu_sr, SR_OVE);
289 tcg_gen_brcondi_i32(TCG_COND_NE, sr_ove, SR_OVE, lab);
290 gen_exception(dc, EXCP_RANGE);
291 gen_set_label(lab);
292 tcg_gen_mov_i32(cpu_R[rd], res);
293 tcg_temp_free_i64(ta);
294 tcg_temp_free_i64(tb);
295 tcg_temp_free_i64(td);
296 tcg_temp_free_i32(res);
297 tcg_temp_free_i32(sr_ove);
298 }
299 break;
300 default:
301 gen_illegal_exception(dc);
302 break;
303 }
304 break;
305
306 case 0x0001: /* l.addc */
307 switch (op1) {
308 case 0x00:
309 LOG_DIS("l.addc r%d, r%d, r%d\n", rd, ra, rb);
310 {
311 int lab = gen_new_label();
312 TCGv_i64 ta = tcg_temp_new_i64();
313 TCGv_i64 tb = tcg_temp_new_i64();
314 TCGv_i64 tcy = tcg_temp_local_new_i64();
315 TCGv_i64 td = tcg_temp_local_new_i64();
316 TCGv_i32 res = tcg_temp_local_new_i32();
317 TCGv_i32 sr_cy = tcg_temp_local_new_i32();
318 TCGv_i32 sr_ove = tcg_temp_local_new_i32();
319 tcg_gen_extu_i32_i64(ta, cpu_R[ra]);
320 tcg_gen_extu_i32_i64(tb, cpu_R[rb]);
321 tcg_gen_andi_i32(sr_cy, cpu_sr, SR_CY);
322 tcg_gen_extu_i32_i64(tcy, sr_cy);
323 tcg_gen_shri_i64(tcy, tcy, 10);
324 tcg_gen_add_i64(td, ta, tb);
325 tcg_gen_add_i64(td, td, tcy);
326 tcg_gen_trunc_i64_i32(res, td);
327 tcg_gen_shri_i64(td, td, 32);
328 tcg_gen_andi_i64(td, td, 0x3);
329 /* Jump to lab when no overflow. */
330 tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x0, lab);
331 tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x3, lab);
332 tcg_gen_ori_i32(cpu_sr, cpu_sr, (SR_OV | SR_CY));
333 tcg_gen_andi_i32(sr_ove, cpu_sr, SR_OVE);
334 tcg_gen_brcondi_i32(TCG_COND_NE, sr_ove, SR_OVE, lab);
335 gen_exception(dc, EXCP_RANGE);
336 gen_set_label(lab);
337 tcg_gen_mov_i32(cpu_R[rd], res);
338 tcg_temp_free_i64(ta);
339 tcg_temp_free_i64(tb);
340 tcg_temp_free_i64(tcy);
341 tcg_temp_free_i64(td);
342 tcg_temp_free_i32(res);
343 tcg_temp_free_i32(sr_cy);
344 tcg_temp_free_i32(sr_ove);
345 }
346 break;
347 default:
348 gen_illegal_exception(dc);
349 break;
350 }
351 break;
352
353 case 0x0002: /* l.sub */
354 switch (op1) {
355 case 0x00:
356 LOG_DIS("l.sub r%d, r%d, r%d\n", rd, ra, rb);
357 {
358 int lab = gen_new_label();
359 TCGv_i64 ta = tcg_temp_new_i64();
360 TCGv_i64 tb = tcg_temp_new_i64();
361 TCGv_i64 td = tcg_temp_local_new_i64();
362 TCGv_i32 res = tcg_temp_local_new_i32();
363 TCGv_i32 sr_ove = tcg_temp_local_new_i32();
364
365 tcg_gen_extu_i32_i64(ta, cpu_R[ra]);
366 tcg_gen_extu_i32_i64(tb, cpu_R[rb]);
367 tcg_gen_sub_i64(td, ta, tb);
368 tcg_gen_trunc_i64_i32(res, td);
369 tcg_gen_shri_i64(td, td, 31);
370 tcg_gen_andi_i64(td, td, 0x3);
371 /* Jump to lab when no overflow. */
372 tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x0, lab);
373 tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x3, lab);
374 tcg_gen_ori_i32(cpu_sr, cpu_sr, (SR_OV | SR_CY));
375 tcg_gen_andi_i32(sr_ove, cpu_sr, SR_OVE);
376 tcg_gen_brcondi_i32(TCG_COND_NE, sr_ove, SR_OVE, lab);
377 gen_exception(dc, EXCP_RANGE);
378 gen_set_label(lab);
379 tcg_gen_mov_i32(cpu_R[rd], res);
380 tcg_temp_free_i64(ta);
381 tcg_temp_free_i64(tb);
382 tcg_temp_free_i64(td);
383 tcg_temp_free_i32(res);
384 tcg_temp_free_i32(sr_ove);
385 }
386 break;
387 default:
388 gen_illegal_exception(dc);
389 break;
390 }
391 break;
392
393 case 0x0003: /* l.and */
394 switch (op1) {
395 case 0x00:
396 LOG_DIS("l.and r%d, r%d, r%d\n", rd, ra, rb);
397 tcg_gen_and_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
398 break;
399 default:
400 gen_illegal_exception(dc);
401 break;
402 }
403 break;
404
405 case 0x0004: /* l.or */
406 switch (op1) {
407 case 0x00:
408 LOG_DIS("l.or r%d, r%d, r%d\n", rd, ra, rb);
409 tcg_gen_or_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
410 break;
411 default:
412 gen_illegal_exception(dc);
413 break;
414 }
415 break;
416
417 case 0x0005:
418 switch (op1) {
419 case 0x00: /* l.xor */
420 LOG_DIS("l.xor r%d, r%d, r%d\n", rd, ra, rb);
421 tcg_gen_xor_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
422 break;
423 default:
424 gen_illegal_exception(dc);
425 break;
426 }
427 break;
428
429 case 0x0006:
430 switch (op1) {
431 case 0x03: /* l.mul */
432 LOG_DIS("l.mul r%d, r%d, r%d\n", rd, ra, rb);
433 if (ra != 0 && rb != 0) {
434 gen_helper_mul32(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
435 } else {
436 tcg_gen_movi_tl(cpu_R[rd], 0x0);
437 }
438 break;
439 default:
440 gen_illegal_exception(dc);
441 break;
442 }
443 break;
444
445 case 0x0009:
446 switch (op1) {
447 case 0x03: /* l.div */
448 LOG_DIS("l.div r%d, r%d, r%d\n", rd, ra, rb);
449 {
450 int lab0 = gen_new_label();
451 int lab1 = gen_new_label();
452 int lab2 = gen_new_label();
453 int lab3 = gen_new_label();
454 TCGv_i32 sr_ove = tcg_temp_local_new_i32();
455 if (rb == 0) {
456 tcg_gen_ori_tl(cpu_sr, cpu_sr, (SR_OV | SR_CY));
457 tcg_gen_andi_tl(sr_ove, cpu_sr, SR_OVE);
458 tcg_gen_brcondi_tl(TCG_COND_NE, sr_ove, SR_OVE, lab0);
459 gen_exception(dc, EXCP_RANGE);
460 gen_set_label(lab0);
461 } else {
462 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_R[rb],
463 0x00000000, lab1);
464 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_R[ra],
465 0x80000000, lab2);
466 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_R[rb],
467 0xffffffff, lab2);
468 gen_set_label(lab1);
469 tcg_gen_ori_tl(cpu_sr, cpu_sr, (SR_OV | SR_CY));
470 tcg_gen_andi_tl(sr_ove, cpu_sr, SR_OVE);
471 tcg_gen_brcondi_tl(TCG_COND_NE, sr_ove, SR_OVE, lab3);
472 gen_exception(dc, EXCP_RANGE);
473 gen_set_label(lab2);
474 tcg_gen_div_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
475 gen_set_label(lab3);
476 }
477 tcg_temp_free_i32(sr_ove);
478 }
479 break;
480
481 default:
482 gen_illegal_exception(dc);
483 break;
484 }
485 break;
486
487 case 0x000a:
488 switch (op1) {
489 case 0x03: /* l.divu */
490 LOG_DIS("l.divu r%d, r%d, r%d\n", rd, ra, rb);
491 {
492 int lab0 = gen_new_label();
493 int lab1 = gen_new_label();
494 int lab2 = gen_new_label();
495 TCGv_i32 sr_ove = tcg_temp_local_new_i32();
496 if (rb == 0) {
497 tcg_gen_ori_tl(cpu_sr, cpu_sr, (SR_OV | SR_CY));
498 tcg_gen_andi_tl(sr_ove, cpu_sr, SR_OVE);
499 tcg_gen_brcondi_tl(TCG_COND_NE, sr_ove, SR_OVE, lab0);
500 gen_exception(dc, EXCP_RANGE);
501 gen_set_label(lab0);
502 } else {
503 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_R[rb],
504 0x00000000, lab1);
505 tcg_gen_ori_tl(cpu_sr, cpu_sr, (SR_OV | SR_CY));
506 tcg_gen_andi_tl(sr_ove, cpu_sr, SR_OVE);
507 tcg_gen_brcondi_tl(TCG_COND_NE, sr_ove, SR_OVE, lab2);
508 gen_exception(dc, EXCP_RANGE);
509 gen_set_label(lab1);
510 tcg_gen_divu_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
511 gen_set_label(lab2);
512 }
513 tcg_temp_free_i32(sr_ove);
514 }
515 break;
516
517 default:
518 gen_illegal_exception(dc);
519 break;
520 }
521 break;
522
523 case 0x000b:
524 switch (op1) {
525 case 0x03: /* l.mulu */
526 LOG_DIS("l.mulu r%d, r%d, r%d\n", rd, ra, rb);
527 if (rb != 0 && ra != 0) {
528 TCGv_i64 result = tcg_temp_local_new_i64();
529 TCGv_i64 tra = tcg_temp_local_new_i64();
530 TCGv_i64 trb = tcg_temp_local_new_i64();
531 TCGv_i64 high = tcg_temp_new_i64();
532 TCGv_i32 sr_ove = tcg_temp_local_new_i32();
533 int lab = gen_new_label();
534 /* Calculate the each result. */
535 tcg_gen_extu_i32_i64(tra, cpu_R[ra]);
536 tcg_gen_extu_i32_i64(trb, cpu_R[rb]);
537 tcg_gen_mul_i64(result, tra, trb);
538 tcg_temp_free_i64(tra);
539 tcg_temp_free_i64(trb);
540 tcg_gen_shri_i64(high, result, TARGET_LONG_BITS);
541 /* Overflow or not. */
542 tcg_gen_brcondi_i64(TCG_COND_EQ, high, 0x00000000, lab);
543 tcg_gen_ori_tl(cpu_sr, cpu_sr, (SR_OV | SR_CY));
544 tcg_gen_andi_tl(sr_ove, cpu_sr, SR_OVE);
545 tcg_gen_brcondi_tl(TCG_COND_NE, sr_ove, SR_OVE, lab);
546 gen_exception(dc, EXCP_RANGE);
547 gen_set_label(lab);
548 tcg_temp_free_i64(high);
549 tcg_gen_trunc_i64_tl(cpu_R[rd], result);
550 tcg_temp_free_i64(result);
551 tcg_temp_free_i32(sr_ove);
552 } else {
553 tcg_gen_movi_tl(cpu_R[rd], 0);
554 }
555 break;
556
557 default:
558 gen_illegal_exception(dc);
559 break;
560 }
561 break;
562
563 case 0x000e:
564 switch (op1) {
565 case 0x00: /* l.cmov */
566 LOG_DIS("l.cmov r%d, r%d, r%d\n", rd, ra, rb);
567 {
568 int lab = gen_new_label();
569 TCGv res = tcg_temp_local_new();
570 TCGv sr_f = tcg_temp_new();
571 tcg_gen_andi_tl(sr_f, cpu_sr, SR_F);
572 tcg_gen_mov_tl(res, cpu_R[rb]);
573 tcg_gen_brcondi_tl(TCG_COND_NE, sr_f, SR_F, lab);
574 tcg_gen_mov_tl(res, cpu_R[ra]);
575 gen_set_label(lab);
576 tcg_gen_mov_tl(cpu_R[rd], res);
577 tcg_temp_free(sr_f);
578 tcg_temp_free(res);
579 }
580 break;
581
582 default:
583 gen_illegal_exception(dc);
584 break;
585 }
586 break;
587
588 case 0x000f:
589 switch (op1) {
590 case 0x00: /* l.ff1 */
591 LOG_DIS("l.ff1 r%d, r%d, r%d\n", rd, ra, rb);
592 gen_helper_ff1(cpu_R[rd], cpu_R[ra]);
593 break;
594 case 0x01: /* l.fl1 */
595 LOG_DIS("l.fl1 r%d, r%d, r%d\n", rd, ra, rb);
596 gen_helper_fl1(cpu_R[rd], cpu_R[ra]);
597 break;
598
599 default:
600 gen_illegal_exception(dc);
601 break;
602 }
603 break;
604
605 case 0x0008:
606 switch (op1) {
607 case 0x00:
608 switch (op2) {
609 case 0x00: /* l.sll */
610 LOG_DIS("l.sll r%d, r%d, r%d\n", rd, ra, rb);
611 tcg_gen_shl_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
612 break;
613 case 0x01: /* l.srl */
614 LOG_DIS("l.srl r%d, r%d, r%d\n", rd, ra, rb);
615 tcg_gen_shr_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
616 break;
617 case 0x02: /* l.sra */
618 LOG_DIS("l.sra r%d, r%d, r%d\n", rd, ra, rb);
619 tcg_gen_sar_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
620 break;
621 case 0x03: /* l.ror */
622 LOG_DIS("l.ror r%d, r%d, r%d\n", rd, ra, rb);
623 tcg_gen_rotr_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
624 break;
625
626 default:
627 gen_illegal_exception(dc);
628 break;
629 }
630 break;
631
632 default:
633 gen_illegal_exception(dc);
634 break;
635 }
636 break;
637
638 case 0x000c:
639 switch (op1) {
640 case 0x00:
641 switch (op2) {
642 case 0x00: /* l.exths */
643 LOG_DIS("l.exths r%d, r%d\n", rd, ra);
644 tcg_gen_ext16s_tl(cpu_R[rd], cpu_R[ra]);
645 break;
646 case 0x01: /* l.extbs */
647 LOG_DIS("l.extbs r%d, r%d\n", rd, ra);
648 tcg_gen_ext8s_tl(cpu_R[rd], cpu_R[ra]);
649 break;
650 case 0x02: /* l.exthz */
651 LOG_DIS("l.exthz r%d, r%d\n", rd, ra);
652 tcg_gen_ext16u_tl(cpu_R[rd], cpu_R[ra]);
653 break;
654 case 0x03: /* l.extbz */
655 LOG_DIS("l.extbz r%d, r%d\n", rd, ra);
656 tcg_gen_ext8u_tl(cpu_R[rd], cpu_R[ra]);
657 break;
658
659 default:
660 gen_illegal_exception(dc);
661 break;
662 }
663 break;
664
665 default:
666 gen_illegal_exception(dc);
667 break;
668 }
669 break;
670
671 case 0x000d:
672 switch (op1) {
673 case 0x00:
674 switch (op2) {
675 case 0x00: /* l.extws */
676 LOG_DIS("l.extws r%d, r%d\n", rd, ra);
677 tcg_gen_ext32s_tl(cpu_R[rd], cpu_R[ra]);
678 break;
679 case 0x01: /* l.extwz */
680 LOG_DIS("l.extwz r%d, r%d\n", rd, ra);
681 tcg_gen_ext32u_tl(cpu_R[rd], cpu_R[ra]);
682 break;
683
684 default:
685 gen_illegal_exception(dc);
686 break;
687 }
688 break;
689
690 default:
691 gen_illegal_exception(dc);
692 break;
693 }
694 break;
695
696 default:
697 gen_illegal_exception(dc);
698 break;
699 }
700 }
701
702 static void dec_misc(DisasContext *dc, uint32_t insn)
703 {
704 uint32_t op0, op1;
705 uint32_t ra, rb, rd;
706 #ifdef OPENRISC_DISAS
707 uint32_t L6, K5;
708 #endif
709 uint32_t I16, I5, I11, N26, tmp;
710 TCGMemOp mop;
711
712 op0 = extract32(insn, 26, 6);
713 op1 = extract32(insn, 24, 2);
714 ra = extract32(insn, 16, 5);
715 rb = extract32(insn, 11, 5);
716 rd = extract32(insn, 21, 5);
717 #ifdef OPENRISC_DISAS
718 L6 = extract32(insn, 5, 6);
719 K5 = extract32(insn, 0, 5);
720 #endif
721 I16 = extract32(insn, 0, 16);
722 I5 = extract32(insn, 21, 5);
723 I11 = extract32(insn, 0, 11);
724 N26 = extract32(insn, 0, 26);
725 tmp = (I5<<11) + I11;
726
727 switch (op0) {
728 case 0x00: /* l.j */
729 LOG_DIS("l.j %d\n", N26);
730 gen_jump(dc, N26, 0, op0);
731 break;
732
733 case 0x01: /* l.jal */
734 LOG_DIS("l.jal %d\n", N26);
735 gen_jump(dc, N26, 0, op0);
736 break;
737
738 case 0x03: /* l.bnf */
739 LOG_DIS("l.bnf %d\n", N26);
740 gen_jump(dc, N26, 0, op0);
741 break;
742
743 case 0x04: /* l.bf */
744 LOG_DIS("l.bf %d\n", N26);
745 gen_jump(dc, N26, 0, op0);
746 break;
747
748 case 0x05:
749 switch (op1) {
750 case 0x01: /* l.nop */
751 LOG_DIS("l.nop %d\n", I16);
752 break;
753
754 default:
755 gen_illegal_exception(dc);
756 break;
757 }
758 break;
759
760 case 0x11: /* l.jr */
761 LOG_DIS("l.jr r%d\n", rb);
762 gen_jump(dc, 0, rb, op0);
763 break;
764
765 case 0x12: /* l.jalr */
766 LOG_DIS("l.jalr r%d\n", rb);
767 gen_jump(dc, 0, rb, op0);
768 break;
769
770 case 0x13: /* l.maci */
771 LOG_DIS("l.maci %d, r%d, %d\n", I5, ra, I11);
772 {
773 TCGv_i64 t1 = tcg_temp_new_i64();
774 TCGv_i64 t2 = tcg_temp_new_i64();
775 TCGv_i32 dst = tcg_temp_new_i32();
776 TCGv ttmp = tcg_const_tl(tmp);
777 tcg_gen_mul_tl(dst, cpu_R[ra], ttmp);
778 tcg_gen_ext_i32_i64(t1, dst);
779 tcg_gen_concat_i32_i64(t2, maclo, machi);
780 tcg_gen_add_i64(t2, t2, t1);
781 tcg_gen_trunc_i64_i32(maclo, t2);
782 tcg_gen_shri_i64(t2, t2, 32);
783 tcg_gen_trunc_i64_i32(machi, t2);
784 tcg_temp_free_i32(dst);
785 tcg_temp_free(ttmp);
786 tcg_temp_free_i64(t1);
787 tcg_temp_free_i64(t2);
788 }
789 break;
790
791 case 0x09: /* l.rfe */
792 LOG_DIS("l.rfe\n");
793 {
794 #if defined(CONFIG_USER_ONLY)
795 return;
796 #else
797 if (dc->mem_idx == MMU_USER_IDX) {
798 gen_illegal_exception(dc);
799 return;
800 }
801 gen_helper_rfe(cpu_env);
802 dc->is_jmp = DISAS_UPDATE;
803 #endif
804 }
805 break;
806
807 case 0x1c: /* l.cust1 */
808 LOG_DIS("l.cust1\n");
809 break;
810
811 case 0x1d: /* l.cust2 */
812 LOG_DIS("l.cust2\n");
813 break;
814
815 case 0x1e: /* l.cust3 */
816 LOG_DIS("l.cust3\n");
817 break;
818
819 case 0x1f: /* l.cust4 */
820 LOG_DIS("l.cust4\n");
821 break;
822
823 case 0x3c: /* l.cust5 */
824 LOG_DIS("l.cust5 r%d, r%d, r%d, %d, %d\n", rd, ra, rb, L6, K5);
825 break;
826
827 case 0x3d: /* l.cust6 */
828 LOG_DIS("l.cust6\n");
829 break;
830
831 case 0x3e: /* l.cust7 */
832 LOG_DIS("l.cust7\n");
833 break;
834
835 case 0x3f: /* l.cust8 */
836 LOG_DIS("l.cust8\n");
837 break;
838
839 /* not used yet, open it when we need or64. */
840 /*#ifdef TARGET_OPENRISC64
841 case 0x20: l.ld
842 LOG_DIS("l.ld r%d, r%d, %d\n", rd, ra, I16);
843 check_ob64s(dc);
844 mop = MO_TEQ;
845 goto do_load;
846 #endif*/
847
848 case 0x21: /* l.lwz */
849 LOG_DIS("l.lwz r%d, r%d, %d\n", rd, ra, I16);
850 mop = MO_TEUL;
851 goto do_load;
852
853 case 0x22: /* l.lws */
854 LOG_DIS("l.lws r%d, r%d, %d\n", rd, ra, I16);
855 mop = MO_TESL;
856 goto do_load;
857
858 case 0x23: /* l.lbz */
859 LOG_DIS("l.lbz r%d, r%d, %d\n", rd, ra, I16);
860 mop = MO_UB;
861 goto do_load;
862
863 case 0x24: /* l.lbs */
864 LOG_DIS("l.lbs r%d, r%d, %d\n", rd, ra, I16);
865 mop = MO_SB;
866 goto do_load;
867
868 case 0x25: /* l.lhz */
869 LOG_DIS("l.lhz r%d, r%d, %d\n", rd, ra, I16);
870 mop = MO_TEUW;
871 goto do_load;
872
873 case 0x26: /* l.lhs */
874 LOG_DIS("l.lhs r%d, r%d, %d\n", rd, ra, I16);
875 mop = MO_TESW;
876 goto do_load;
877
878 do_load:
879 {
880 TCGv t0 = tcg_temp_new();
881 tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16));
882 tcg_gen_qemu_ld_tl(cpu_R[rd], t0, dc->mem_idx, mop);
883 tcg_temp_free(t0);
884 }
885 break;
886
887 case 0x27: /* l.addi */
888 LOG_DIS("l.addi r%d, r%d, %d\n", rd, ra, I16);
889 {
890 if (I16 == 0) {
891 tcg_gen_mov_tl(cpu_R[rd], cpu_R[ra]);
892 } else {
893 int lab = gen_new_label();
894 TCGv_i64 ta = tcg_temp_new_i64();
895 TCGv_i64 td = tcg_temp_local_new_i64();
896 TCGv_i32 res = tcg_temp_local_new_i32();
897 TCGv_i32 sr_ove = tcg_temp_local_new_i32();
898 tcg_gen_extu_i32_i64(ta, cpu_R[ra]);
899 tcg_gen_addi_i64(td, ta, sign_extend(I16, 16));
900 tcg_gen_trunc_i64_i32(res, td);
901 tcg_gen_shri_i64(td, td, 32);
902 tcg_gen_andi_i64(td, td, 0x3);
903 /* Jump to lab when no overflow. */
904 tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x0, lab);
905 tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x3, lab);
906 tcg_gen_ori_i32(cpu_sr, cpu_sr, (SR_OV | SR_CY));
907 tcg_gen_andi_i32(sr_ove, cpu_sr, SR_OVE);
908 tcg_gen_brcondi_i32(TCG_COND_NE, sr_ove, SR_OVE, lab);
909 gen_exception(dc, EXCP_RANGE);
910 gen_set_label(lab);
911 tcg_gen_mov_i32(cpu_R[rd], res);
912 tcg_temp_free_i64(ta);
913 tcg_temp_free_i64(td);
914 tcg_temp_free_i32(res);
915 tcg_temp_free_i32(sr_ove);
916 }
917 }
918 break;
919
920 case 0x28: /* l.addic */
921 LOG_DIS("l.addic r%d, r%d, %d\n", rd, ra, I16);
922 {
923 int lab = gen_new_label();
924 TCGv_i64 ta = tcg_temp_new_i64();
925 TCGv_i64 td = tcg_temp_local_new_i64();
926 TCGv_i64 tcy = tcg_temp_local_new_i64();
927 TCGv_i32 res = tcg_temp_local_new_i32();
928 TCGv_i32 sr_cy = tcg_temp_local_new_i32();
929 TCGv_i32 sr_ove = tcg_temp_local_new_i32();
930 tcg_gen_extu_i32_i64(ta, cpu_R[ra]);
931 tcg_gen_andi_i32(sr_cy, cpu_sr, SR_CY);
932 tcg_gen_shri_i32(sr_cy, sr_cy, 10);
933 tcg_gen_extu_i32_i64(tcy, sr_cy);
934 tcg_gen_addi_i64(td, ta, sign_extend(I16, 16));
935 tcg_gen_add_i64(td, td, tcy);
936 tcg_gen_trunc_i64_i32(res, td);
937 tcg_gen_shri_i64(td, td, 32);
938 tcg_gen_andi_i64(td, td, 0x3);
939 /* Jump to lab when no overflow. */
940 tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x0, lab);
941 tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x3, lab);
942 tcg_gen_ori_i32(cpu_sr, cpu_sr, (SR_OV | SR_CY));
943 tcg_gen_andi_i32(sr_ove, cpu_sr, SR_OVE);
944 tcg_gen_brcondi_i32(TCG_COND_NE, sr_ove, SR_OVE, lab);
945 gen_exception(dc, EXCP_RANGE);
946 gen_set_label(lab);
947 tcg_gen_mov_i32(cpu_R[rd], res);
948 tcg_temp_free_i64(ta);
949 tcg_temp_free_i64(td);
950 tcg_temp_free_i64(tcy);
951 tcg_temp_free_i32(res);
952 tcg_temp_free_i32(sr_cy);
953 tcg_temp_free_i32(sr_ove);
954 }
955 break;
956
957 case 0x29: /* l.andi */
958 LOG_DIS("l.andi r%d, r%d, %d\n", rd, ra, I16);
959 tcg_gen_andi_tl(cpu_R[rd], cpu_R[ra], zero_extend(I16, 16));
960 break;
961
962 case 0x2a: /* l.ori */
963 LOG_DIS("l.ori r%d, r%d, %d\n", rd, ra, I16);
964 tcg_gen_ori_tl(cpu_R[rd], cpu_R[ra], zero_extend(I16, 16));
965 break;
966
967 case 0x2b: /* l.xori */
968 LOG_DIS("l.xori r%d, r%d, %d\n", rd, ra, I16);
969 tcg_gen_xori_tl(cpu_R[rd], cpu_R[ra], sign_extend(I16, 16));
970 break;
971
972 case 0x2c: /* l.muli */
973 LOG_DIS("l.muli r%d, r%d, %d\n", rd, ra, I16);
974 if (ra != 0 && I16 != 0) {
975 TCGv_i32 im = tcg_const_i32(I16);
976 gen_helper_mul32(cpu_R[rd], cpu_env, cpu_R[ra], im);
977 tcg_temp_free_i32(im);
978 } else {
979 tcg_gen_movi_tl(cpu_R[rd], 0x0);
980 }
981 break;
982
983 case 0x2d: /* l.mfspr */
984 LOG_DIS("l.mfspr r%d, r%d, %d\n", rd, ra, I16);
985 {
986 #if defined(CONFIG_USER_ONLY)
987 return;
988 #else
989 TCGv_i32 ti = tcg_const_i32(I16);
990 if (dc->mem_idx == MMU_USER_IDX) {
991 gen_illegal_exception(dc);
992 return;
993 }
994 gen_helper_mfspr(cpu_R[rd], cpu_env, cpu_R[rd], cpu_R[ra], ti);
995 tcg_temp_free_i32(ti);
996 #endif
997 }
998 break;
999
1000 case 0x30: /* l.mtspr */
1001 LOG_DIS("l.mtspr %d, r%d, r%d, %d\n", I5, ra, rb, I11);
1002 {
1003 #if defined(CONFIG_USER_ONLY)
1004 return;
1005 #else
1006 TCGv_i32 im = tcg_const_i32(tmp);
1007 if (dc->mem_idx == MMU_USER_IDX) {
1008 gen_illegal_exception(dc);
1009 return;
1010 }
1011 gen_helper_mtspr(cpu_env, cpu_R[ra], cpu_R[rb], im);
1012 tcg_temp_free_i32(im);
1013 #endif
1014 }
1015 break;
1016
1017 /* not used yet, open it when we need or64. */
1018 /*#ifdef TARGET_OPENRISC64
1019 case 0x34: l.sd
1020 LOG_DIS("l.sd %d, r%d, r%d, %d\n", I5, ra, rb, I11);
1021 check_ob64s(dc);
1022 mop = MO_TEQ;
1023 goto do_store;
1024 #endif*/
1025
1026 case 0x35: /* l.sw */
1027 LOG_DIS("l.sw %d, r%d, r%d, %d\n", I5, ra, rb, I11);
1028 mop = MO_TEUL;
1029 goto do_store;
1030
1031 case 0x36: /* l.sb */
1032 LOG_DIS("l.sb %d, r%d, r%d, %d\n", I5, ra, rb, I11);
1033 mop = MO_UB;
1034 goto do_store;
1035
1036 case 0x37: /* l.sh */
1037 LOG_DIS("l.sh %d, r%d, r%d, %d\n", I5, ra, rb, I11);
1038 mop = MO_TEUW;
1039 goto do_store;
1040
1041 do_store:
1042 {
1043 TCGv t0 = tcg_temp_new();
1044 tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(tmp, 16));
1045 tcg_gen_qemu_st_tl(cpu_R[rb], t0, dc->mem_idx, mop);
1046 tcg_temp_free(t0);
1047 }
1048 break;
1049
1050 default:
1051 gen_illegal_exception(dc);
1052 break;
1053 }
1054 }
1055
1056 static void dec_mac(DisasContext *dc, uint32_t insn)
1057 {
1058 uint32_t op0;
1059 uint32_t ra, rb;
1060 op0 = extract32(insn, 0, 4);
1061 ra = extract32(insn, 16, 5);
1062 rb = extract32(insn, 11, 5);
1063
1064 switch (op0) {
1065 case 0x0001: /* l.mac */
1066 LOG_DIS("l.mac r%d, r%d\n", ra, rb);
1067 {
1068 TCGv_i32 t0 = tcg_temp_new_i32();
1069 TCGv_i64 t1 = tcg_temp_new_i64();
1070 TCGv_i64 t2 = tcg_temp_new_i64();
1071 tcg_gen_mul_tl(t0, cpu_R[ra], cpu_R[rb]);
1072 tcg_gen_ext_i32_i64(t1, t0);
1073 tcg_gen_concat_i32_i64(t2, maclo, machi);
1074 tcg_gen_add_i64(t2, t2, t1);
1075 tcg_gen_trunc_i64_i32(maclo, t2);
1076 tcg_gen_shri_i64(t2, t2, 32);
1077 tcg_gen_trunc_i64_i32(machi, t2);
1078 tcg_temp_free_i32(t0);
1079 tcg_temp_free_i64(t1);
1080 tcg_temp_free_i64(t2);
1081 }
1082 break;
1083
1084 case 0x0002: /* l.msb */
1085 LOG_DIS("l.msb r%d, r%d\n", ra, rb);
1086 {
1087 TCGv_i32 t0 = tcg_temp_new_i32();
1088 TCGv_i64 t1 = tcg_temp_new_i64();
1089 TCGv_i64 t2 = tcg_temp_new_i64();
1090 tcg_gen_mul_tl(t0, cpu_R[ra], cpu_R[rb]);
1091 tcg_gen_ext_i32_i64(t1, t0);
1092 tcg_gen_concat_i32_i64(t2, maclo, machi);
1093 tcg_gen_sub_i64(t2, t2, t1);
1094 tcg_gen_trunc_i64_i32(maclo, t2);
1095 tcg_gen_shri_i64(t2, t2, 32);
1096 tcg_gen_trunc_i64_i32(machi, t2);
1097 tcg_temp_free_i32(t0);
1098 tcg_temp_free_i64(t1);
1099 tcg_temp_free_i64(t2);
1100 }
1101 break;
1102
1103 default:
1104 gen_illegal_exception(dc);
1105 break;
1106 }
1107 }
1108
1109 static void dec_logic(DisasContext *dc, uint32_t insn)
1110 {
1111 uint32_t op0;
1112 uint32_t rd, ra, L6;
1113 op0 = extract32(insn, 6, 2);
1114 rd = extract32(insn, 21, 5);
1115 ra = extract32(insn, 16, 5);
1116 L6 = extract32(insn, 0, 6);
1117
1118 switch (op0) {
1119 case 0x00: /* l.slli */
1120 LOG_DIS("l.slli r%d, r%d, %d\n", rd, ra, L6);
1121 tcg_gen_shli_tl(cpu_R[rd], cpu_R[ra], (L6 & 0x1f));
1122 break;
1123
1124 case 0x01: /* l.srli */
1125 LOG_DIS("l.srli r%d, r%d, %d\n", rd, ra, L6);
1126 tcg_gen_shri_tl(cpu_R[rd], cpu_R[ra], (L6 & 0x1f));
1127 break;
1128
1129 case 0x02: /* l.srai */
1130 LOG_DIS("l.srai r%d, r%d, %d\n", rd, ra, L6);
1131 tcg_gen_sari_tl(cpu_R[rd], cpu_R[ra], (L6 & 0x1f)); break;
1132
1133 case 0x03: /* l.rori */
1134 LOG_DIS("l.rori r%d, r%d, %d\n", rd, ra, L6);
1135 tcg_gen_rotri_tl(cpu_R[rd], cpu_R[ra], (L6 & 0x1f));
1136 break;
1137
1138 default:
1139 gen_illegal_exception(dc);
1140 break;
1141 }
1142 }
1143
1144 static void dec_M(DisasContext *dc, uint32_t insn)
1145 {
1146 uint32_t op0;
1147 uint32_t rd;
1148 uint32_t K16;
1149 op0 = extract32(insn, 16, 1);
1150 rd = extract32(insn, 21, 5);
1151 K16 = extract32(insn, 0, 16);
1152
1153 switch (op0) {
1154 case 0x0: /* l.movhi */
1155 LOG_DIS("l.movhi r%d, %d\n", rd, K16);
1156 tcg_gen_movi_tl(cpu_R[rd], (K16 << 16));
1157 break;
1158
1159 case 0x1: /* l.macrc */
1160 LOG_DIS("l.macrc r%d\n", rd);
1161 tcg_gen_mov_tl(cpu_R[rd], maclo);
1162 tcg_gen_movi_tl(maclo, 0x0);
1163 tcg_gen_movi_tl(machi, 0x0);
1164 break;
1165
1166 default:
1167 gen_illegal_exception(dc);
1168 break;
1169 }
1170 }
1171
1172 static void dec_comp(DisasContext *dc, uint32_t insn)
1173 {
1174 uint32_t op0;
1175 uint32_t ra, rb;
1176
1177 op0 = extract32(insn, 21, 5);
1178 ra = extract32(insn, 16, 5);
1179 rb = extract32(insn, 11, 5);
1180
1181 tcg_gen_movi_i32(env_btaken, 0x0);
1182 /* unsigned integers */
1183 tcg_gen_ext32u_tl(cpu_R[ra], cpu_R[ra]);
1184 tcg_gen_ext32u_tl(cpu_R[rb], cpu_R[rb]);
1185
1186 switch (op0) {
1187 case 0x0: /* l.sfeq */
1188 LOG_DIS("l.sfeq r%d, r%d\n", ra, rb);
1189 tcg_gen_setcond_tl(TCG_COND_EQ, env_btaken, cpu_R[ra], cpu_R[rb]);
1190 break;
1191
1192 case 0x1: /* l.sfne */
1193 LOG_DIS("l.sfne r%d, r%d\n", ra, rb);
1194 tcg_gen_setcond_tl(TCG_COND_NE, env_btaken, cpu_R[ra], cpu_R[rb]);
1195 break;
1196
1197 case 0x2: /* l.sfgtu */
1198 LOG_DIS("l.sfgtu r%d, r%d\n", ra, rb);
1199 tcg_gen_setcond_tl(TCG_COND_GTU, env_btaken, cpu_R[ra], cpu_R[rb]);
1200 break;
1201
1202 case 0x3: /* l.sfgeu */
1203 LOG_DIS("l.sfgeu r%d, r%d\n", ra, rb);
1204 tcg_gen_setcond_tl(TCG_COND_GEU, env_btaken, cpu_R[ra], cpu_R[rb]);
1205 break;
1206
1207 case 0x4: /* l.sfltu */
1208 LOG_DIS("l.sfltu r%d, r%d\n", ra, rb);
1209 tcg_gen_setcond_tl(TCG_COND_LTU, env_btaken, cpu_R[ra], cpu_R[rb]);
1210 break;
1211
1212 case 0x5: /* l.sfleu */
1213 LOG_DIS("l.sfleu r%d, r%d\n", ra, rb);
1214 tcg_gen_setcond_tl(TCG_COND_LEU, env_btaken, cpu_R[ra], cpu_R[rb]);
1215 break;
1216
1217 case 0xa: /* l.sfgts */
1218 LOG_DIS("l.sfgts r%d, r%d\n", ra, rb);
1219 tcg_gen_setcond_tl(TCG_COND_GT, env_btaken, cpu_R[ra], cpu_R[rb]);
1220 break;
1221
1222 case 0xb: /* l.sfges */
1223 LOG_DIS("l.sfges r%d, r%d\n", ra, rb);
1224 tcg_gen_setcond_tl(TCG_COND_GE, env_btaken, cpu_R[ra], cpu_R[rb]);
1225 break;
1226
1227 case 0xc: /* l.sflts */
1228 LOG_DIS("l.sflts r%d, r%d\n", ra, rb);
1229 tcg_gen_setcond_tl(TCG_COND_LT, env_btaken, cpu_R[ra], cpu_R[rb]);
1230 break;
1231
1232 case 0xd: /* l.sfles */
1233 LOG_DIS("l.sfles r%d, r%d\n", ra, rb);
1234 tcg_gen_setcond_tl(TCG_COND_LE, env_btaken, cpu_R[ra], cpu_R[rb]);
1235 break;
1236
1237 default:
1238 gen_illegal_exception(dc);
1239 break;
1240 }
1241 wb_SR_F();
1242 }
1243
1244 static void dec_compi(DisasContext *dc, uint32_t insn)
1245 {
1246 uint32_t op0;
1247 uint32_t ra, I16;
1248
1249 op0 = extract32(insn, 21, 5);
1250 ra = extract32(insn, 16, 5);
1251 I16 = extract32(insn, 0, 16);
1252
1253 tcg_gen_movi_i32(env_btaken, 0x0);
1254 I16 = sign_extend(I16, 16);
1255
1256 switch (op0) {
1257 case 0x0: /* l.sfeqi */
1258 LOG_DIS("l.sfeqi r%d, %d\n", ra, I16);
1259 tcg_gen_setcondi_tl(TCG_COND_EQ, env_btaken, cpu_R[ra], I16);
1260 break;
1261
1262 case 0x1: /* l.sfnei */
1263 LOG_DIS("l.sfnei r%d, %d\n", ra, I16);
1264 tcg_gen_setcondi_tl(TCG_COND_NE, env_btaken, cpu_R[ra], I16);
1265 break;
1266
1267 case 0x2: /* l.sfgtui */
1268 LOG_DIS("l.sfgtui r%d, %d\n", ra, I16);
1269 tcg_gen_setcondi_tl(TCG_COND_GTU, env_btaken, cpu_R[ra], I16);
1270 break;
1271
1272 case 0x3: /* l.sfgeui */
1273 LOG_DIS("l.sfgeui r%d, %d\n", ra, I16);
1274 tcg_gen_setcondi_tl(TCG_COND_GEU, env_btaken, cpu_R[ra], I16);
1275 break;
1276
1277 case 0x4: /* l.sfltui */
1278 LOG_DIS("l.sfltui r%d, %d\n", ra, I16);
1279 tcg_gen_setcondi_tl(TCG_COND_LTU, env_btaken, cpu_R[ra], I16);
1280 break;
1281
1282 case 0x5: /* l.sfleui */
1283 LOG_DIS("l.sfleui r%d, %d\n", ra, I16);
1284 tcg_gen_setcondi_tl(TCG_COND_LEU, env_btaken, cpu_R[ra], I16);
1285 break;
1286
1287 case 0xa: /* l.sfgtsi */
1288 LOG_DIS("l.sfgtsi r%d, %d\n", ra, I16);
1289 tcg_gen_setcondi_tl(TCG_COND_GT, env_btaken, cpu_R[ra], I16);
1290 break;
1291
1292 case 0xb: /* l.sfgesi */
1293 LOG_DIS("l.sfgesi r%d, %d\n", ra, I16);
1294 tcg_gen_setcondi_tl(TCG_COND_GE, env_btaken, cpu_R[ra], I16);
1295 break;
1296
1297 case 0xc: /* l.sfltsi */
1298 LOG_DIS("l.sfltsi r%d, %d\n", ra, I16);
1299 tcg_gen_setcondi_tl(TCG_COND_LT, env_btaken, cpu_R[ra], I16);
1300 break;
1301
1302 case 0xd: /* l.sflesi */
1303 LOG_DIS("l.sflesi r%d, %d\n", ra, I16);
1304 tcg_gen_setcondi_tl(TCG_COND_LE, env_btaken, cpu_R[ra], I16);
1305 break;
1306
1307 default:
1308 gen_illegal_exception(dc);
1309 break;
1310 }
1311 wb_SR_F();
1312 }
1313
1314 static void dec_sys(DisasContext *dc, uint32_t insn)
1315 {
1316 uint32_t op0;
1317 #ifdef OPENRISC_DISAS
1318 uint32_t K16;
1319 #endif
1320 op0 = extract32(insn, 16, 8);
1321 #ifdef OPENRISC_DISAS
1322 K16 = extract32(insn, 0, 16);
1323 #endif
1324
1325 switch (op0) {
1326 case 0x000: /* l.sys */
1327 LOG_DIS("l.sys %d\n", K16);
1328 tcg_gen_movi_tl(cpu_pc, dc->pc);
1329 gen_exception(dc, EXCP_SYSCALL);
1330 dc->is_jmp = DISAS_UPDATE;
1331 break;
1332
1333 case 0x100: /* l.trap */
1334 LOG_DIS("l.trap %d\n", K16);
1335 #if defined(CONFIG_USER_ONLY)
1336 return;
1337 #else
1338 if (dc->mem_idx == MMU_USER_IDX) {
1339 gen_illegal_exception(dc);
1340 return;
1341 }
1342 tcg_gen_movi_tl(cpu_pc, dc->pc);
1343 gen_exception(dc, EXCP_TRAP);
1344 #endif
1345 break;
1346
1347 case 0x300: /* l.csync */
1348 LOG_DIS("l.csync\n");
1349 #if defined(CONFIG_USER_ONLY)
1350 return;
1351 #else
1352 if (dc->mem_idx == MMU_USER_IDX) {
1353 gen_illegal_exception(dc);
1354 return;
1355 }
1356 #endif
1357 break;
1358
1359 case 0x200: /* l.msync */
1360 LOG_DIS("l.msync\n");
1361 #if defined(CONFIG_USER_ONLY)
1362 return;
1363 #else
1364 if (dc->mem_idx == MMU_USER_IDX) {
1365 gen_illegal_exception(dc);
1366 return;
1367 }
1368 #endif
1369 break;
1370
1371 case 0x270: /* l.psync */
1372 LOG_DIS("l.psync\n");
1373 #if defined(CONFIG_USER_ONLY)
1374 return;
1375 #else
1376 if (dc->mem_idx == MMU_USER_IDX) {
1377 gen_illegal_exception(dc);
1378 return;
1379 }
1380 #endif
1381 break;
1382
1383 default:
1384 gen_illegal_exception(dc);
1385 break;
1386 }
1387 }
1388
1389 static void dec_float(DisasContext *dc, uint32_t insn)
1390 {
1391 uint32_t op0;
1392 uint32_t ra, rb, rd;
1393 op0 = extract32(insn, 0, 8);
1394 ra = extract32(insn, 16, 5);
1395 rb = extract32(insn, 11, 5);
1396 rd = extract32(insn, 21, 5);
1397
1398 switch (op0) {
1399 case 0x00: /* lf.add.s */
1400 LOG_DIS("lf.add.s r%d, r%d, r%d\n", rd, ra, rb);
1401 gen_helper_float_add_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
1402 break;
1403
1404 case 0x01: /* lf.sub.s */
1405 LOG_DIS("lf.sub.s r%d, r%d, r%d\n", rd, ra, rb);
1406 gen_helper_float_sub_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
1407 break;
1408
1409
1410 case 0x02: /* lf.mul.s */
1411 LOG_DIS("lf.mul.s r%d, r%d, r%d\n", rd, ra, rb);
1412 if (ra != 0 && rb != 0) {
1413 gen_helper_float_mul_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
1414 } else {
1415 tcg_gen_ori_tl(fpcsr, fpcsr, FPCSR_ZF);
1416 tcg_gen_movi_i32(cpu_R[rd], 0x0);
1417 }
1418 break;
1419
1420 case 0x03: /* lf.div.s */
1421 LOG_DIS("lf.div.s r%d, r%d, r%d\n", rd, ra, rb);
1422 gen_helper_float_div_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
1423 break;
1424
1425 case 0x04: /* lf.itof.s */
1426 LOG_DIS("lf.itof r%d, r%d\n", rd, ra);
1427 gen_helper_itofs(cpu_R[rd], cpu_env, cpu_R[ra]);
1428 break;
1429
1430 case 0x05: /* lf.ftoi.s */
1431 LOG_DIS("lf.ftoi r%d, r%d\n", rd, ra);
1432 gen_helper_ftois(cpu_R[rd], cpu_env, cpu_R[ra]);
1433 break;
1434
1435 case 0x06: /* lf.rem.s */
1436 LOG_DIS("lf.rem.s r%d, r%d, r%d\n", rd, ra, rb);
1437 gen_helper_float_rem_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
1438 break;
1439
1440 case 0x07: /* lf.madd.s */
1441 LOG_DIS("lf.madd.s r%d, r%d, r%d\n", rd, ra, rb);
1442 gen_helper_float_muladd_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
1443 break;
1444
1445 case 0x08: /* lf.sfeq.s */
1446 LOG_DIS("lf.sfeq.s r%d, r%d\n", ra, rb);
1447 gen_helper_float_eq_s(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
1448 break;
1449
1450 case 0x09: /* lf.sfne.s */
1451 LOG_DIS("lf.sfne.s r%d, r%d\n", ra, rb);
1452 gen_helper_float_ne_s(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
1453 break;
1454
1455 case 0x0a: /* lf.sfgt.s */
1456 LOG_DIS("lf.sfgt.s r%d, r%d\n", ra, rb);
1457 gen_helper_float_gt_s(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
1458 break;
1459
1460 case 0x0b: /* lf.sfge.s */
1461 LOG_DIS("lf.sfge.s r%d, r%d\n", ra, rb);
1462 gen_helper_float_ge_s(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
1463 break;
1464
1465 case 0x0c: /* lf.sflt.s */
1466 LOG_DIS("lf.sflt.s r%d, r%d\n", ra, rb);
1467 gen_helper_float_lt_s(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
1468 break;
1469
1470 case 0x0d: /* lf.sfle.s */
1471 LOG_DIS("lf.sfle.s r%d, r%d\n", ra, rb);
1472 gen_helper_float_le_s(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
1473 break;
1474
1475 /* not used yet, open it when we need or64. */
1476 /*#ifdef TARGET_OPENRISC64
1477 case 0x10: lf.add.d
1478 LOG_DIS("lf.add.d r%d, r%d, r%d\n", rd, ra, rb);
1479 check_of64s(dc);
1480 gen_helper_float_add_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
1481 break;
1482
1483 case 0x11: lf.sub.d
1484 LOG_DIS("lf.sub.d r%d, r%d, r%d\n", rd, ra, rb);
1485 check_of64s(dc);
1486 gen_helper_float_sub_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
1487 break;
1488
1489 case 0x12: lf.mul.d
1490 LOG_DIS("lf.mul.d r%d, r%d, r%d\n", rd, ra, rb);
1491 check_of64s(dc);
1492 if (ra != 0 && rb != 0) {
1493 gen_helper_float_mul_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
1494 } else {
1495 tcg_gen_ori_tl(fpcsr, fpcsr, FPCSR_ZF);
1496 tcg_gen_movi_i64(cpu_R[rd], 0x0);
1497 }
1498 break;
1499
1500 case 0x13: lf.div.d
1501 LOG_DIS("lf.div.d r%d, r%d, r%d\n", rd, ra, rb);
1502 check_of64s(dc);
1503 gen_helper_float_div_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
1504 break;
1505
1506 case 0x14: lf.itof.d
1507 LOG_DIS("lf.itof r%d, r%d\n", rd, ra);
1508 check_of64s(dc);
1509 gen_helper_itofd(cpu_R[rd], cpu_env, cpu_R[ra]);
1510 break;
1511
1512 case 0x15: lf.ftoi.d
1513 LOG_DIS("lf.ftoi r%d, r%d\n", rd, ra);
1514 check_of64s(dc);
1515 gen_helper_ftoid(cpu_R[rd], cpu_env, cpu_R[ra]);
1516 break;
1517
1518 case 0x16: lf.rem.d
1519 LOG_DIS("lf.rem.d r%d, r%d, r%d\n", rd, ra, rb);
1520 check_of64s(dc);
1521 gen_helper_float_rem_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
1522 break;
1523
1524 case 0x17: lf.madd.d
1525 LOG_DIS("lf.madd.d r%d, r%d, r%d\n", rd, ra, rb);
1526 check_of64s(dc);
1527 gen_helper_float_muladd_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
1528 break;
1529
1530 case 0x18: lf.sfeq.d
1531 LOG_DIS("lf.sfeq.d r%d, r%d\n", ra, rb);
1532 check_of64s(dc);
1533 gen_helper_float_eq_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
1534 break;
1535
1536 case 0x1a: lf.sfgt.d
1537 LOG_DIS("lf.sfgt.d r%d, r%d\n", ra, rb);
1538 check_of64s(dc);
1539 gen_helper_float_gt_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
1540 break;
1541
1542 case 0x1b: lf.sfge.d
1543 LOG_DIS("lf.sfge.d r%d, r%d\n", ra, rb);
1544 check_of64s(dc);
1545 gen_helper_float_ge_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
1546 break;
1547
1548 case 0x19: lf.sfne.d
1549 LOG_DIS("lf.sfne.d r%d, r%d\n", ra, rb);
1550 check_of64s(dc);
1551 gen_helper_float_ne_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
1552 break;
1553
1554 case 0x1c: lf.sflt.d
1555 LOG_DIS("lf.sflt.d r%d, r%d\n", ra, rb);
1556 check_of64s(dc);
1557 gen_helper_float_lt_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
1558 break;
1559
1560 case 0x1d: lf.sfle.d
1561 LOG_DIS("lf.sfle.d r%d, r%d\n", ra, rb);
1562 check_of64s(dc);
1563 gen_helper_float_le_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
1564 break;
1565 #endif*/
1566
1567 default:
1568 gen_illegal_exception(dc);
1569 break;
1570 }
1571 wb_SR_F();
1572 }
1573
1574 static void disas_openrisc_insn(DisasContext *dc, OpenRISCCPU *cpu)
1575 {
1576 uint32_t op0;
1577 uint32_t insn;
1578 insn = cpu_ldl_code(&cpu->env, dc->pc);
1579 op0 = extract32(insn, 26, 6);
1580
1581 switch (op0) {
1582 case 0x06:
1583 dec_M(dc, insn);
1584 break;
1585
1586 case 0x08:
1587 dec_sys(dc, insn);
1588 break;
1589
1590 case 0x2e:
1591 dec_logic(dc, insn);
1592 break;
1593
1594 case 0x2f:
1595 dec_compi(dc, insn);
1596 break;
1597
1598 case 0x31:
1599 dec_mac(dc, insn);
1600 break;
1601
1602 case 0x32:
1603 dec_float(dc, insn);
1604 break;
1605
1606 case 0x38:
1607 dec_calc(dc, insn);
1608 break;
1609
1610 case 0x39:
1611 dec_comp(dc, insn);
1612 break;
1613
1614 default:
1615 dec_misc(dc, insn);
1616 break;
1617 }
1618 }
1619
1620 static void check_breakpoint(OpenRISCCPU *cpu, DisasContext *dc)
1621 {
1622 CPUState *cs = CPU(cpu);
1623 CPUBreakpoint *bp;
1624
1625 if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
1626 QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
1627 if (bp->pc == dc->pc) {
1628 tcg_gen_movi_tl(cpu_pc, dc->pc);
1629 gen_exception(dc, EXCP_DEBUG);
1630 dc->is_jmp = DISAS_UPDATE;
1631 }
1632 }
1633 }
1634 }
1635
1636 static inline void gen_intermediate_code_internal(OpenRISCCPU *cpu,
1637 TranslationBlock *tb,
1638 int search_pc)
1639 {
1640 CPUState *cs = CPU(cpu);
1641 struct DisasContext ctx, *dc = &ctx;
1642 uint16_t *gen_opc_end;
1643 uint32_t pc_start;
1644 int j, k;
1645 uint32_t next_page_start;
1646 int num_insns;
1647 int max_insns;
1648
1649 pc_start = tb->pc;
1650 dc->tb = tb;
1651
1652 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
1653 dc->is_jmp = DISAS_NEXT;
1654 dc->ppc = pc_start;
1655 dc->pc = pc_start;
1656 dc->flags = cpu->env.cpucfgr;
1657 dc->mem_idx = cpu_mmu_index(&cpu->env);
1658 dc->synced_flags = dc->tb_flags = tb->flags;
1659 dc->delayed_branch = !!(dc->tb_flags & D_FLAG);
1660 dc->singlestep_enabled = cs->singlestep_enabled;
1661 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1662 qemu_log("-----------------------------------------\n");
1663 log_cpu_state(CPU(cpu), 0);
1664 }
1665
1666 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
1667 k = -1;
1668 num_insns = 0;
1669 max_insns = tb->cflags & CF_COUNT_MASK;
1670
1671 if (max_insns == 0) {
1672 max_insns = CF_COUNT_MASK;
1673 }
1674
1675 gen_tb_start();
1676
1677 do {
1678 check_breakpoint(cpu, dc);
1679 if (search_pc) {
1680 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
1681 if (k < j) {
1682 k++;
1683 while (k < j) {
1684 tcg_ctx.gen_opc_instr_start[k++] = 0;
1685 }
1686 }
1687 tcg_ctx.gen_opc_pc[k] = dc->pc;
1688 tcg_ctx.gen_opc_instr_start[k] = 1;
1689 tcg_ctx.gen_opc_icount[k] = num_insns;
1690 }
1691
1692 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
1693 tcg_gen_debug_insn_start(dc->pc);
1694 }
1695
1696 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
1697 gen_io_start();
1698 }
1699 dc->ppc = dc->pc - 4;
1700 dc->npc = dc->pc + 4;
1701 tcg_gen_movi_tl(cpu_ppc, dc->ppc);
1702 tcg_gen_movi_tl(cpu_npc, dc->npc);
1703 disas_openrisc_insn(dc, cpu);
1704 dc->pc = dc->npc;
1705 num_insns++;
1706 /* delay slot */
1707 if (dc->delayed_branch) {
1708 dc->delayed_branch--;
1709 if (!dc->delayed_branch) {
1710 dc->tb_flags &= ~D_FLAG;
1711 gen_sync_flags(dc);
1712 tcg_gen_mov_tl(cpu_pc, jmp_pc);
1713 tcg_gen_mov_tl(cpu_npc, jmp_pc);
1714 tcg_gen_movi_tl(jmp_pc, 0);
1715 tcg_gen_exit_tb(0);
1716 dc->is_jmp = DISAS_JUMP;
1717 break;
1718 }
1719 }
1720 } while (!dc->is_jmp
1721 && tcg_ctx.gen_opc_ptr < gen_opc_end
1722 && !cs->singlestep_enabled
1723 && !singlestep
1724 && (dc->pc < next_page_start)
1725 && num_insns < max_insns);
1726
1727 if (tb->cflags & CF_LAST_IO) {
1728 gen_io_end();
1729 }
1730 if (dc->is_jmp == DISAS_NEXT) {
1731 dc->is_jmp = DISAS_UPDATE;
1732 tcg_gen_movi_tl(cpu_pc, dc->pc);
1733 }
1734 if (unlikely(cs->singlestep_enabled)) {
1735 if (dc->is_jmp == DISAS_NEXT) {
1736 tcg_gen_movi_tl(cpu_pc, dc->pc);
1737 }
1738 gen_exception(dc, EXCP_DEBUG);
1739 } else {
1740 switch (dc->is_jmp) {
1741 case DISAS_NEXT:
1742 gen_goto_tb(dc, 0, dc->pc);
1743 break;
1744 default:
1745 case DISAS_JUMP:
1746 break;
1747 case DISAS_UPDATE:
1748 /* indicate that the hash table must be used
1749 to find the next TB */
1750 tcg_gen_exit_tb(0);
1751 break;
1752 case DISAS_TB_JUMP:
1753 /* nothing more to generate */
1754 break;
1755 }
1756 }
1757
1758 gen_tb_end(tb, num_insns);
1759 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
1760 if (search_pc) {
1761 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
1762 k++;
1763 while (k <= j) {
1764 tcg_ctx.gen_opc_instr_start[k++] = 0;
1765 }
1766 } else {
1767 tb->size = dc->pc - pc_start;
1768 tb->icount = num_insns;
1769 }
1770
1771 #ifdef DEBUG_DISAS
1772 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1773 qemu_log("\n");
1774 log_target_disas(&cpu->env, pc_start, dc->pc - pc_start, 0);
1775 qemu_log("\nisize=%d osize=%td\n",
1776 dc->pc - pc_start, tcg_ctx.gen_opc_ptr -
1777 tcg_ctx.gen_opc_buf);
1778 }
1779 #endif
1780 }
1781
1782 void gen_intermediate_code(CPUOpenRISCState *env, struct TranslationBlock *tb)
1783 {
1784 gen_intermediate_code_internal(openrisc_env_get_cpu(env), tb, 0);
1785 }
1786
1787 void gen_intermediate_code_pc(CPUOpenRISCState *env,
1788 struct TranslationBlock *tb)
1789 {
1790 gen_intermediate_code_internal(openrisc_env_get_cpu(env), tb, 1);
1791 }
1792
1793 void openrisc_cpu_dump_state(CPUState *cs, FILE *f,
1794 fprintf_function cpu_fprintf,
1795 int flags)
1796 {
1797 OpenRISCCPU *cpu = OPENRISC_CPU(cs);
1798 CPUOpenRISCState *env = &cpu->env;
1799 int i;
1800
1801 cpu_fprintf(f, "PC=%08x\n", env->pc);
1802 for (i = 0; i < 32; ++i) {
1803 cpu_fprintf(f, "R%02d=%08x%c", i, env->gpr[i],
1804 (i % 4) == 3 ? '\n' : ' ');
1805 }
1806 }
1807
1808 void restore_state_to_opc(CPUOpenRISCState *env, TranslationBlock *tb,
1809 int pc_pos)
1810 {
1811 env->pc = tcg_ctx.gen_opc_pc[pc_pos];
1812 }
QEmu