target-cris/helper.c

   1 /*
   2  *  CRIS helper routines.
   3  *
   4  *  Copyright (c) 2007 AXIS Communications AB
   5  *  Written by Edgar E. Iglesias.
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "cpu.h"
  22 #include "mmu.h"
  23 #include "qemu/host-utils.h"
  24
  25
  26 //#define CRIS_HELPER_DEBUG
  27
  28
  29 #ifdef CRIS_HELPER_DEBUG
  30 #define D(x) x
  31 #define D_LOG(...) qemu_log(__VA_ARGS__)
  32 #else
  33 #define D(x)
  34 #define D_LOG(...) do { } while (0)
  35 #endif
  36
  37 #if defined(CONFIG_USER_ONLY)
  38
  39 void cris_cpu_do_interrupt(CPUState *cs)
  40 {
  41     CRISCPU *cpu = CRIS_CPU(cs);
  42     CPUCRISState *env = &cpu->env;
  43
  44     cs->exception_index = -1;
  45     env->pregs[PR_ERP] = env->pc;
  46 }
  47
  48 void crisv10_cpu_do_interrupt(CPUState *cs)
  49 {
  50     cris_cpu_do_interrupt(cs);
  51 }
  52
  53 int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
  54                               int mmu_idx)
  55 {
  56     CRISCPU *cpu = CRIS_CPU(cs);
  57
  58     cs->exception_index = 0xaa;
  59     cpu->env.pregs[PR_EDA] = address;
  60     cpu_dump_state(cs, stderr, fprintf, 0);
  61     return 1;
  62 }
  63
  64 #else /* !CONFIG_USER_ONLY */
  65
  66
  67 static void cris_shift_ccs(CPUCRISState *env)
  68 {
  69     uint32_t ccs;
  70     /* Apply the ccs shift.  */
  71     ccs = env->pregs[PR_CCS];
  72     ccs = ((ccs & 0xc0000000) | ((ccs << 12) >> 2)) & ~0x3ff;
  73     env->pregs[PR_CCS] = ccs;
  74 }
  75
  76 int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
  77                               int mmu_idx)
  78 {
  79     CRISCPU *cpu = CRIS_CPU(cs);
  80     CPUCRISState *env = &cpu->env;
  81     struct cris_mmu_result res;
  82     int prot, miss;
  83     int r = -1;
  84     target_ulong phy;
  85
  86     D(printf("%s addr=%" VADDR_PRIx " pc=%x rw=%x\n",
  87              __func__, address, env->pc, rw));
  88     miss = cris_mmu_translate(&res, env, address & TARGET_PAGE_MASK,
  89                               rw, mmu_idx, 0);
  90     if (miss) {
  91         if (cs->exception_index == EXCP_BUSFAULT) {
  92             cpu_abort(cs,
  93                       "CRIS: Illegal recursive bus fault."
  94                       "addr=%" VADDR_PRIx " rw=%d\n",
  95                       address, rw);
  96         }
  97
  98         env->pregs[PR_EDA] = address;
  99         cs->exception_index = EXCP_BUSFAULT;
 100         env->fault_vector = res.bf_vec;
 101         r = 1;
 102     } else {
 103         /*
 104          * Mask off the cache selection bit. The ETRAX busses do not
 105          * see the top bit.
 106          */
 107         phy = res.phy & ~0x80000000;
 108         prot = res.prot;
 109         tlb_set_page(cs, address & TARGET_PAGE_MASK, phy,
 110                      prot, mmu_idx, TARGET_PAGE_SIZE);
 111         r = 0;
 112     }
 113     if (r > 0) {
 114         D_LOG("%s returns %d irqreq=%x addr=%" VADDR_PRIx " phy=%x vec=%x"
 115               " pc=%x\n", __func__, r, cs->interrupt_request, address, res.phy,
 116               res.bf_vec, env->pc);
 117     }
 118     return r;
 119 }
 120
 121 void crisv10_cpu_do_interrupt(CPUState *cs)
 122 {
 123     CRISCPU *cpu = CRIS_CPU(cs);
 124     CPUCRISState *env = &cpu->env;
 125     int ex_vec = -1;
 126
 127     D_LOG("exception index=%d interrupt_req=%d\n",
 128           cs->exception_index,
 129           cs->interrupt_request);
 130
 131     if (env->dslot) {
 132         /* CRISv10 never takes interrupts while in a delay-slot.  */
 133         cpu_abort(cs, "CRIS: Interrupt on delay-slot\n");
 134     }
 135
 136     assert(!(env->pregs[PR_CCS] & PFIX_FLAG));
 137     switch (cs->exception_index) {
 138     case EXCP_BREAK:
 139         /* These exceptions are genereated by the core itself.
 140            ERP should point to the insn following the brk.  */
 141         ex_vec = env->trap_vector;
 142         env->pregs[PRV10_BRP] = env->pc;
 143         break;
 144
 145     case EXCP_NMI:
 146         /* NMI is hardwired to vector zero.  */
 147         ex_vec = 0;
 148         env->pregs[PR_CCS] &= ~M_FLAG_V10;
 149         env->pregs[PRV10_BRP] = env->pc;
 150         break;
 151
 152     case EXCP_BUSFAULT:
 153         cpu_abort(cs, "Unhandled busfault");
 154         break;
 155
 156     default:
 157         /* The interrupt controller gives us the vector.  */
 158         ex_vec = env->interrupt_vector;
 159         /* Normal interrupts are taken between
 160            TB's.  env->pc is valid here.  */
 161         env->pregs[PR_ERP] = env->pc;
 162         break;
 163     }
 164
 165     if (env->pregs[PR_CCS] & U_FLAG) {
 166         /* Swap stack pointers.  */
 167         env->pregs[PR_USP] = env->regs[R_SP];
 168         env->regs[R_SP] = env->ksp;
 169     }
 170
 171     /* Now that we are in kernel mode, load the handlers address.  */
 172     env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
 173     env->locked_irq = 1;
 174     env->pregs[PR_CCS] |= F_FLAG_V10; /* set F.  */
 175
 176     qemu_log_mask(CPU_LOG_INT, "%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
 177                   __func__, env->pc, ex_vec,
 178                   env->pregs[PR_CCS],
 179                   env->pregs[PR_PID],
 180                   env->pregs[PR_ERP]);
 181 }
 182
 183 void cris_cpu_do_interrupt(CPUState *cs)
 184 {
 185     CRISCPU *cpu = CRIS_CPU(cs);
 186     CPUCRISState *env = &cpu->env;
 187     int ex_vec = -1;
 188
 189     D_LOG("exception index=%d interrupt_req=%d\n",
 190           cs->exception_index,
 191           cs->interrupt_request);
 192
 193     switch (cs->exception_index) {
 194     case EXCP_BREAK:
 195         /* These exceptions are genereated by the core itself.
 196            ERP should point to the insn following the brk.  */
 197         ex_vec = env->trap_vector;
 198         env->pregs[PR_ERP] = env->pc;
 199         break;
 200
 201     case EXCP_NMI:
 202         /* NMI is hardwired to vector zero.  */
 203         ex_vec = 0;
 204         env->pregs[PR_CCS] &= ~M_FLAG_V32;
 205         env->pregs[PR_NRP] = env->pc;
 206         break;
 207
 208     case EXCP_BUSFAULT:
 209         ex_vec = env->fault_vector;
 210         env->pregs[PR_ERP] = env->pc;
 211         break;
 212
 213     default:
 214         /* The interrupt controller gives us the vector.  */
 215         ex_vec = env->interrupt_vector;
 216         /* Normal interrupts are taken between
 217            TB's.  env->pc is valid here.  */
 218         env->pregs[PR_ERP] = env->pc;
 219         break;
 220     }
 221
 222     /* Fill in the IDX field.  */
 223     env->pregs[PR_EXS] = (ex_vec & 0xff) << 8;
 224
 225     if (env->dslot) {
 226         D_LOG("excp isr=%x PC=%x ds=%d SP=%x"
 227               " ERP=%x pid=%x ccs=%x cc=%d %x\n",
 228               ex_vec, env->pc, env->dslot,
 229               env->regs[R_SP],
 230               env->pregs[PR_ERP], env->pregs[PR_PID],
 231               env->pregs[PR_CCS],
 232               env->cc_op, env->cc_mask);
 233         /* We loose the btarget, btaken state here so rexec the
 234            branch.  */
 235         env->pregs[PR_ERP] -= env->dslot;
 236         /* Exception starts with dslot cleared.  */
 237         env->dslot = 0;
 238     }
 239
 240     if (env->pregs[PR_CCS] & U_FLAG) {
 241         /* Swap stack pointers.  */
 242         env->pregs[PR_USP] = env->regs[R_SP];
 243         env->regs[R_SP] = env->ksp;
 244     }
 245
 246     /* Apply the CRIS CCS shift. Clears U if set.  */
 247     cris_shift_ccs(env);
 248
 249     /* Now that we are in kernel mode, load the handlers address.
 250        This load may not fault, real hw leaves that behaviour as
 251        undefined.  */
 252     env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
 253
 254     /* Clear the excption_index to avoid spurios hw_aborts for recursive
 255        bus faults.  */
 256     cs->exception_index = -1;
 257
 258     D_LOG("%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
 259           __func__, env->pc, ex_vec,
 260           env->pregs[PR_CCS],
 261           env->pregs[PR_PID],
 262           env->pregs[PR_ERP]);
 263 }
 264
 265 hwaddr cris_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
 266 {
 267     CRISCPU *cpu = CRIS_CPU(cs);
 268     uint32_t phy = addr;
 269     struct cris_mmu_result res;
 270     int miss;
 271
 272     miss = cris_mmu_translate(&res, &cpu->env, addr, 0, 0, 1);
 273     /* If D TLB misses, try I TLB.  */
 274     if (miss) {
 275         miss = cris_mmu_translate(&res, &cpu->env, addr, 2, 0, 1);
 276     }
 277
 278     if (!miss) {
 279         phy = res.phy;
 280     }
 281     D(fprintf(stderr, "%s %x -> %x\n", __func__, addr, phy));
 282     return phy;
 283 }
 284 #endif