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net: cadence_gem: Make phy respond to broadcast
[qemu.git] / hw / pci-host / bonito.c
blob902441f10b2fe5bb9d35e0cbdeab285aeee0c6ca
1 /*
2 * bonito north bridge support
3 *
4 * Copyright (c) 2008 yajin (yajin@vm-kernel.org)
5 * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com)
6 *
7 * This code is licensed under the GNU GPL v2.
8 *
9 * Contributions after 2012-01-13 are licensed under the terms of the
10 * GNU GPL, version 2 or (at your option) any later version.
11 */
12
13 /*
14 * fulong 2e mini pc has a bonito north bridge.
15 */
16
17 /* what is the meaning of devfn in qemu and IDSEL in bonito northbridge?
18 *
19 * devfn pci_slot<<3 + funno
20 * one pci bus can have 32 devices and each device can have 8 functions.
21 *
22 * In bonito north bridge, pci slot = IDSEL bit - 12.
23 * For example, PCI_IDSEL_VIA686B = 17,
24 * pci slot = 17-12=5
25 *
26 * so
27 * VT686B_FUN0's devfn = (5<<3)+0
28 * VT686B_FUN1's devfn = (5<<3)+1
29 *
30 * qemu also uses pci address for north bridge to access pci config register.
31 * bus_no [23:16]
32 * dev_no [15:11]
33 * fun_no [10:8]
34 * reg_no [7:2]
35 *
36 * so function bonito_sbridge_pciaddr for the translation from
37 * north bridge address to pci address.
38 */
39
40 #include <assert.h>
41
42 #include "hw/hw.h"
43 #include "hw/pci/pci.h"
44 #include "hw/i386/pc.h"
45 #include "hw/mips/mips.h"
46 #include "hw/pci/pci_host.h"
47 #include "sysemu/sysemu.h"
48 #include "exec/address-spaces.h"
49
50 //#define DEBUG_BONITO
51
52 #ifdef DEBUG_BONITO
53 #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__)
54 #else
55 #define DPRINTF(fmt, ...)
56 #endif
57
58 /* from linux soure code. include/asm-mips/mips-boards/bonito64.h*/
59 #define BONITO_BOOT_BASE 0x1fc00000
60 #define BONITO_BOOT_SIZE 0x00100000
61 #define BONITO_BOOT_TOP (BONITO_BOOT_BASE+BONITO_BOOT_SIZE-1)
62 #define BONITO_FLASH_BASE 0x1c000000
63 #define BONITO_FLASH_SIZE 0x03000000
64 #define BONITO_FLASH_TOP (BONITO_FLASH_BASE+BONITO_FLASH_SIZE-1)
65 #define BONITO_SOCKET_BASE 0x1f800000
66 #define BONITO_SOCKET_SIZE 0x00400000
67 #define BONITO_SOCKET_TOP (BONITO_SOCKET_BASE+BONITO_SOCKET_SIZE-1)
68 #define BONITO_REG_BASE 0x1fe00000
69 #define BONITO_REG_SIZE 0x00040000
70 #define BONITO_REG_TOP (BONITO_REG_BASE+BONITO_REG_SIZE-1)
71 #define BONITO_DEV_BASE 0x1ff00000
72 #define BONITO_DEV_SIZE 0x00100000
73 #define BONITO_DEV_TOP (BONITO_DEV_BASE+BONITO_DEV_SIZE-1)
74 #define BONITO_PCILO_BASE 0x10000000
75 #define BONITO_PCILO_BASE_VA 0xb0000000
76 #define BONITO_PCILO_SIZE 0x0c000000
77 #define BONITO_PCILO_TOP (BONITO_PCILO_BASE+BONITO_PCILO_SIZE-1)
78 #define BONITO_PCILO0_BASE 0x10000000
79 #define BONITO_PCILO1_BASE 0x14000000
80 #define BONITO_PCILO2_BASE 0x18000000
81 #define BONITO_PCIHI_BASE 0x20000000
82 #define BONITO_PCIHI_SIZE 0x20000000
83 #define BONITO_PCIHI_TOP (BONITO_PCIHI_BASE+BONITO_PCIHI_SIZE-1)
84 #define BONITO_PCIIO_BASE 0x1fd00000
85 #define BONITO_PCIIO_BASE_VA 0xbfd00000
86 #define BONITO_PCIIO_SIZE 0x00010000
87 #define BONITO_PCIIO_TOP (BONITO_PCIIO_BASE+BONITO_PCIIO_SIZE-1)
88 #define BONITO_PCICFG_BASE 0x1fe80000
89 #define BONITO_PCICFG_SIZE 0x00080000
90 #define BONITO_PCICFG_TOP (BONITO_PCICFG_BASE+BONITO_PCICFG_SIZE-1)
91
92
93 #define BONITO_PCICONFIGBASE 0x00
94 #define BONITO_REGBASE 0x100
95
96 #define BONITO_PCICONFIG_BASE (BONITO_PCICONFIGBASE+BONITO_REG_BASE)
97 #define BONITO_PCICONFIG_SIZE (0x100)
98
99 #define BONITO_INTERNAL_REG_BASE (BONITO_REGBASE+BONITO_REG_BASE)
100 #define BONITO_INTERNAL_REG_SIZE (0x70)
101
102 #define BONITO_SPCICONFIG_BASE (BONITO_PCICFG_BASE)
103 #define BONITO_SPCICONFIG_SIZE (BONITO_PCICFG_SIZE)
104
105
106
107 /* 1. Bonito h/w Configuration */
108 /* Power on register */
109
110 #define BONITO_BONPONCFG (0x00 >> 2) /* 0x100 */
111 #define BONITO_BONGENCFG_OFFSET 0x4
112 #define BONITO_BONGENCFG (BONITO_BONGENCFG_OFFSET>>2) /*0x104 */
113
114 /* 2. IO & IDE configuration */
115 #define BONITO_IODEVCFG (0x08 >> 2) /* 0x108 */
116
117 /* 3. IO & IDE configuration */
118 #define BONITO_SDCFG (0x0c >> 2) /* 0x10c */
119
120 /* 4. PCI address map control */
121 #define BONITO_PCIMAP (0x10 >> 2) /* 0x110 */
122 #define BONITO_PCIMEMBASECFG (0x14 >> 2) /* 0x114 */
123 #define BONITO_PCIMAP_CFG (0x18 >> 2) /* 0x118 */
124
125 /* 5. ICU & GPIO regs */
126 /* GPIO Regs - r/w */
127 #define BONITO_GPIODATA_OFFSET 0x1c
128 #define BONITO_GPIODATA (BONITO_GPIODATA_OFFSET >> 2) /* 0x11c */
129 #define BONITO_GPIOIE (0x20 >> 2) /* 0x120 */
130
131 /* ICU Configuration Regs - r/w */
132 #define BONITO_INTEDGE (0x24 >> 2) /* 0x124 */
133 #define BONITO_INTSTEER (0x28 >> 2) /* 0x128 */
134 #define BONITO_INTPOL (0x2c >> 2) /* 0x12c */
135
136 /* ICU Enable Regs - IntEn & IntISR are r/o. */
137 #define BONITO_INTENSET (0x30 >> 2) /* 0x130 */
138 #define BONITO_INTENCLR (0x34 >> 2) /* 0x134 */
139 #define BONITO_INTEN (0x38 >> 2) /* 0x138 */
140 #define BONITO_INTISR (0x3c >> 2) /* 0x13c */
141
142 /* PCI mail boxes */
143 #define BONITO_PCIMAIL0_OFFSET 0x40
144 #define BONITO_PCIMAIL1_OFFSET 0x44
145 #define BONITO_PCIMAIL2_OFFSET 0x48
146 #define BONITO_PCIMAIL3_OFFSET 0x4c
147 #define BONITO_PCIMAIL0 (0x40 >> 2) /* 0x140 */
148 #define BONITO_PCIMAIL1 (0x44 >> 2) /* 0x144 */
149 #define BONITO_PCIMAIL2 (0x48 >> 2) /* 0x148 */
150 #define BONITO_PCIMAIL3 (0x4c >> 2) /* 0x14c */
151
152 /* 6. PCI cache */
153 #define BONITO_PCICACHECTRL (0x50 >> 2) /* 0x150 */
154 #define BONITO_PCICACHETAG (0x54 >> 2) /* 0x154 */
155 #define BONITO_PCIBADADDR (0x58 >> 2) /* 0x158 */
156 #define BONITO_PCIMSTAT (0x5c >> 2) /* 0x15c */
157
158 /* 7. other*/
159 #define BONITO_TIMECFG (0x60 >> 2) /* 0x160 */
160 #define BONITO_CPUCFG (0x64 >> 2) /* 0x164 */
161 #define BONITO_DQCFG (0x68 >> 2) /* 0x168 */
162 #define BONITO_MEMSIZE (0x6C >> 2) /* 0x16c */
163
164 #define BONITO_REGS (0x70 >> 2)
165
166 /* PCI config for south bridge. type 0 */
167 #define BONITO_PCICONF_IDSEL_MASK 0xfffff800 /* [31:11] */
168 #define BONITO_PCICONF_IDSEL_OFFSET 11
169 #define BONITO_PCICONF_FUN_MASK 0x700 /* [10:8] */
170 #define BONITO_PCICONF_FUN_OFFSET 8
171 #define BONITO_PCICONF_REG_MASK 0xFC
172 #define BONITO_PCICONF_REG_OFFSET 0
173
174
175 /* idsel BIT = pci slot number +12 */
176 #define PCI_SLOT_BASE 12
177 #define PCI_IDSEL_VIA686B_BIT (17)
178 #define PCI_IDSEL_VIA686B (1<<PCI_IDSEL_VIA686B_BIT)
179
180 #define PCI_ADDR(busno,devno,funno,regno) \
181 ((((busno)<<16)&0xff0000) + (((devno)<<11)&0xf800) + (((funno)<<8)&0x700) + (regno))
182
183 #define TYPE_BONITO_PCI_HOST_BRIDGE "Bonito-pcihost"
184
185 typedef struct BonitoState BonitoState;
186
187 typedef struct PCIBonitoState
188 {
189 PCIDevice dev;
190
191 BonitoState *pcihost;
192 uint32_t regs[BONITO_REGS];
193
194 struct bonldma {
195 uint32_t ldmactrl;
196 uint32_t ldmastat;
197 uint32_t ldmaaddr;
198 uint32_t ldmago;
199 } bonldma;
200
201 /* Based at 1fe00300, bonito Copier */
202 struct boncop {
203 uint32_t copctrl;
204 uint32_t copstat;
205 uint32_t coppaddr;
206 uint32_t copgo;
207 } boncop;
208
209 /* Bonito registers */
210 MemoryRegion iomem;
211 MemoryRegion iomem_ldma;
212 MemoryRegion iomem_cop;
213 MemoryRegion bonito_pciio;
214 MemoryRegion bonito_localio;
215
216 } PCIBonitoState;
217
218 #define BONITO_PCI_HOST_BRIDGE(obj) \
219 OBJECT_CHECK(BonitoState, (obj), TYPE_BONITO_PCI_HOST_BRIDGE)
220
221 struct BonitoState {
222 PCIHostState parent_obj;
223
224 qemu_irq *pic;
225
226 PCIBonitoState *pci_dev;
227 };
228
229 static void bonito_writel(void *opaque, hwaddr addr,
230 uint64_t val, unsigned size)
231 {
232 PCIBonitoState *s = opaque;
233 uint32_t saddr;
234 int reset = 0;
235
236 saddr = (addr - BONITO_REGBASE) >> 2;
237
238 DPRINTF("bonito_writel "TARGET_FMT_plx" val %x saddr %x\n", addr, val, saddr);
239 switch (saddr) {
240 case BONITO_BONPONCFG:
241 case BONITO_IODEVCFG:
242 case BONITO_SDCFG:
243 case BONITO_PCIMAP:
244 case BONITO_PCIMEMBASECFG:
245 case BONITO_PCIMAP_CFG:
246 case BONITO_GPIODATA:
247 case BONITO_GPIOIE:
248 case BONITO_INTEDGE:
249 case BONITO_INTSTEER:
250 case BONITO_INTPOL:
251 case BONITO_PCIMAIL0:
252 case BONITO_PCIMAIL1:
253 case BONITO_PCIMAIL2:
254 case BONITO_PCIMAIL3:
255 case BONITO_PCICACHECTRL:
256 case BONITO_PCICACHETAG:
257 case BONITO_PCIBADADDR:
258 case BONITO_PCIMSTAT:
259 case BONITO_TIMECFG:
260 case BONITO_CPUCFG:
261 case BONITO_DQCFG:
262 case BONITO_MEMSIZE:
263 s->regs[saddr] = val;
264 break;
265 case BONITO_BONGENCFG:
266 if (!(s->regs[saddr] & 0x04) && (val & 0x04)) {
267 reset = 1; /* bit 2 jump from 0 to 1 cause reset */
268 }
269 s->regs[saddr] = val;
270 if (reset) {
271 qemu_system_reset_request();
272 }
273 break;
274 case BONITO_INTENSET:
275 s->regs[BONITO_INTENSET] = val;
276 s->regs[BONITO_INTEN] |= val;
277 break;
278 case BONITO_INTENCLR:
279 s->regs[BONITO_INTENCLR] = val;
280 s->regs[BONITO_INTEN] &= ~val;
281 break;
282 case BONITO_INTEN:
283 case BONITO_INTISR:
284 DPRINTF("write to readonly bonito register %x\n", saddr);
285 break;
286 default:
287 DPRINTF("write to unknown bonito register %x\n", saddr);
288 break;
289 }
290 }
291
292 static uint64_t bonito_readl(void *opaque, hwaddr addr,
293 unsigned size)
294 {
295 PCIBonitoState *s = opaque;
296 uint32_t saddr;
297
298 saddr = (addr - BONITO_REGBASE) >> 2;
299
300 DPRINTF("bonito_readl "TARGET_FMT_plx"\n", addr);
301 switch (saddr) {
302 case BONITO_INTISR:
303 return s->regs[saddr];
304 default:
305 return s->regs[saddr];
306 }
307 }
308
309 static const MemoryRegionOps bonito_ops = {
310 .read = bonito_readl,
311 .write = bonito_writel,
312 .endianness = DEVICE_NATIVE_ENDIAN,
313 .valid = {
314 .min_access_size = 4,
315 .max_access_size = 4,
316 },
317 };
318
319 static void bonito_pciconf_writel(void *opaque, hwaddr addr,
320 uint64_t val, unsigned size)
321 {
322 PCIBonitoState *s = opaque;
323 PCIDevice *d = PCI_DEVICE(s);
324
325 DPRINTF("bonito_pciconf_writel "TARGET_FMT_plx" val %x\n", addr, val);
326 d->config_write(d, addr, val, 4);
327 }
328
329 static uint64_t bonito_pciconf_readl(void *opaque, hwaddr addr,
330 unsigned size)
331 {
332
333 PCIBonitoState *s = opaque;
334 PCIDevice *d = PCI_DEVICE(s);
335
336 DPRINTF("bonito_pciconf_readl "TARGET_FMT_plx"\n", addr);
337 return d->config_read(d, addr, 4);
338 }
339
340 /* north bridge PCI configure space. 0x1fe0 0000 - 0x1fe0 00ff */
341
342 static const MemoryRegionOps bonito_pciconf_ops = {
343 .read = bonito_pciconf_readl,
344 .write = bonito_pciconf_writel,
345 .endianness = DEVICE_NATIVE_ENDIAN,
346 .valid = {
347 .min_access_size = 4,
348 .max_access_size = 4,
349 },
350 };
351
352 static uint64_t bonito_ldma_readl(void *opaque, hwaddr addr,
353 unsigned size)
354 {
355 uint32_t val;
356 PCIBonitoState *s = opaque;
357
358 val = ((uint32_t *)(&s->bonldma))[addr/sizeof(uint32_t)];
359
360 return val;
361 }
362
363 static void bonito_ldma_writel(void *opaque, hwaddr addr,
364 uint64_t val, unsigned size)
365 {
366 PCIBonitoState *s = opaque;
367
368 ((uint32_t *)(&s->bonldma))[addr/sizeof(uint32_t)] = val & 0xffffffff;
369 }
370
371 static const MemoryRegionOps bonito_ldma_ops = {
372 .read = bonito_ldma_readl,
373 .write = bonito_ldma_writel,
374 .endianness = DEVICE_NATIVE_ENDIAN,
375 .valid = {
376 .min_access_size = 4,
377 .max_access_size = 4,
378 },
379 };
380
381 static uint64_t bonito_cop_readl(void *opaque, hwaddr addr,
382 unsigned size)
383 {
384 uint32_t val;
385 PCIBonitoState *s = opaque;
386
387 val = ((uint32_t *)(&s->boncop))[addr/sizeof(uint32_t)];
388
389 return val;
390 }
391
392 static void bonito_cop_writel(void *opaque, hwaddr addr,
393 uint64_t val, unsigned size)
394 {
395 PCIBonitoState *s = opaque;
396
397 ((uint32_t *)(&s->boncop))[addr/sizeof(uint32_t)] = val & 0xffffffff;
398 }
399
400 static const MemoryRegionOps bonito_cop_ops = {
401 .read = bonito_cop_readl,
402 .write = bonito_cop_writel,
403 .endianness = DEVICE_NATIVE_ENDIAN,
404 .valid = {
405 .min_access_size = 4,
406 .max_access_size = 4,
407 },
408 };
409
410 static uint32_t bonito_sbridge_pciaddr(void *opaque, hwaddr addr)
411 {
412 PCIBonitoState *s = opaque;
413 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
414 uint32_t cfgaddr;
415 uint32_t idsel;
416 uint32_t devno;
417 uint32_t funno;
418 uint32_t regno;
419 uint32_t pciaddr;
420
421 /* support type0 pci config */
422 if ((s->regs[BONITO_PCIMAP_CFG] & 0x10000) != 0x0) {
423 return 0xffffffff;
424 }
425
426 cfgaddr = addr & 0xffff;
427 cfgaddr |= (s->regs[BONITO_PCIMAP_CFG] & 0xffff) << 16;
428
429 idsel = (cfgaddr & BONITO_PCICONF_IDSEL_MASK) >> BONITO_PCICONF_IDSEL_OFFSET;
430 devno = ffs(idsel) - 1;
431 funno = (cfgaddr & BONITO_PCICONF_FUN_MASK) >> BONITO_PCICONF_FUN_OFFSET;
432 regno = (cfgaddr & BONITO_PCICONF_REG_MASK) >> BONITO_PCICONF_REG_OFFSET;
433
434 if (idsel == 0) {
435 fprintf(stderr, "error in bonito pci config address " TARGET_FMT_plx
436 ",pcimap_cfg=%x\n", addr, s->regs[BONITO_PCIMAP_CFG]);
437 exit(1);
438 }
439 pciaddr = PCI_ADDR(pci_bus_num(phb->bus), devno, funno, regno);
440 DPRINTF("cfgaddr %x pciaddr %x busno %x devno %d funno %d regno %d\n",
441 cfgaddr, pciaddr, pci_bus_num(phb->bus), devno, funno, regno);
442
443 return pciaddr;
444 }
445
446 static void bonito_spciconf_writeb(void *opaque, hwaddr addr,
447 uint32_t val)
448 {
449 PCIBonitoState *s = opaque;
450 PCIDevice *d = PCI_DEVICE(s);
451 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
452 uint32_t pciaddr;
453 uint16_t status;
454
455 DPRINTF("bonito_spciconf_writeb "TARGET_FMT_plx" val %x\n", addr, val);
456 pciaddr = bonito_sbridge_pciaddr(s, addr);
457
458 if (pciaddr == 0xffffffff) {
459 return;
460 }
461
462 /* set the pci address in s->config_reg */
463 phb->config_reg = (pciaddr) | (1u << 31);
464 pci_data_write(phb->bus, phb->config_reg, val & 0xff, 1);
465
466 /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
467 status = pci_get_word(d->config + PCI_STATUS);
468 status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
469 pci_set_word(d->config + PCI_STATUS, status);
470 }
471
472 static void bonito_spciconf_writew(void *opaque, hwaddr addr,
473 uint32_t val)
474 {
475 PCIBonitoState *s = opaque;
476 PCIDevice *d = PCI_DEVICE(s);
477 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
478 uint32_t pciaddr;
479 uint16_t status;
480
481 DPRINTF("bonito_spciconf_writew "TARGET_FMT_plx" val %x\n", addr, val);
482 assert((addr & 0x1) == 0);
483
484 pciaddr = bonito_sbridge_pciaddr(s, addr);
485
486 if (pciaddr == 0xffffffff) {
487 return;
488 }
489
490 /* set the pci address in s->config_reg */
491 phb->config_reg = (pciaddr) | (1u << 31);
492 pci_data_write(phb->bus, phb->config_reg, val, 2);
493
494 /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
495 status = pci_get_word(d->config + PCI_STATUS);
496 status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
497 pci_set_word(d->config + PCI_STATUS, status);
498 }
499
500 static void bonito_spciconf_writel(void *opaque, hwaddr addr,
501 uint32_t val)
502 {
503 PCIBonitoState *s = opaque;
504 PCIDevice *d = PCI_DEVICE(s);
505 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
506 uint32_t pciaddr;
507 uint16_t status;
508
509 DPRINTF("bonito_spciconf_writel "TARGET_FMT_plx" val %x\n", addr, val);
510 assert((addr & 0x3) == 0);
511
512 pciaddr = bonito_sbridge_pciaddr(s, addr);
513
514 if (pciaddr == 0xffffffff) {
515 return;
516 }
517
518 /* set the pci address in s->config_reg */
519 phb->config_reg = (pciaddr) | (1u << 31);
520 pci_data_write(phb->bus, phb->config_reg, val, 4);
521
522 /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
523 status = pci_get_word(d->config + PCI_STATUS);
524 status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
525 pci_set_word(d->config + PCI_STATUS, status);
526 }
527
528 static uint32_t bonito_spciconf_readb(void *opaque, hwaddr addr)
529 {
530 PCIBonitoState *s = opaque;
531 PCIDevice *d = PCI_DEVICE(s);
532 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
533 uint32_t pciaddr;
534 uint16_t status;
535
536 DPRINTF("bonito_spciconf_readb "TARGET_FMT_plx"\n", addr);
537 pciaddr = bonito_sbridge_pciaddr(s, addr);
538
539 if (pciaddr == 0xffffffff) {
540 return 0xff;
541 }
542
543 /* set the pci address in s->config_reg */
544 phb->config_reg = (pciaddr) | (1u << 31);
545
546 /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
547 status = pci_get_word(d->config + PCI_STATUS);
548 status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
549 pci_set_word(d->config + PCI_STATUS, status);
550
551 return pci_data_read(phb->bus, phb->config_reg, 1);
552 }
553
554 static uint32_t bonito_spciconf_readw(void *opaque, hwaddr addr)
555 {
556 PCIBonitoState *s = opaque;
557 PCIDevice *d = PCI_DEVICE(s);
558 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
559 uint32_t pciaddr;
560 uint16_t status;
561
562 DPRINTF("bonito_spciconf_readw "TARGET_FMT_plx"\n", addr);
563 assert((addr & 0x1) == 0);
564
565 pciaddr = bonito_sbridge_pciaddr(s, addr);
566
567 if (pciaddr == 0xffffffff) {
568 return 0xffff;
569 }
570
571 /* set the pci address in s->config_reg */
572 phb->config_reg = (pciaddr) | (1u << 31);
573
574 /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
575 status = pci_get_word(d->config + PCI_STATUS);
576 status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
577 pci_set_word(d->config + PCI_STATUS, status);
578
579 return pci_data_read(phb->bus, phb->config_reg, 2);
580 }
581
582 static uint32_t bonito_spciconf_readl(void *opaque, hwaddr addr)
583 {
584 PCIBonitoState *s = opaque;
585 PCIDevice *d = PCI_DEVICE(s);
586 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
587 uint32_t pciaddr;
588 uint16_t status;
589
590 DPRINTF("bonito_spciconf_readl "TARGET_FMT_plx"\n", addr);
591 assert((addr & 0x3) == 0);
592
593 pciaddr = bonito_sbridge_pciaddr(s, addr);
594
595 if (pciaddr == 0xffffffff) {
596 return 0xffffffff;
597 }
598
599 /* set the pci address in s->config_reg */
600 phb->config_reg = (pciaddr) | (1u << 31);
601
602 /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
603 status = pci_get_word(d->config + PCI_STATUS);
604 status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
605 pci_set_word(d->config + PCI_STATUS, status);
606
607 return pci_data_read(phb->bus, phb->config_reg, 4);
608 }
609
610 /* south bridge PCI configure space. 0x1fe8 0000 - 0x1fef ffff */
611 static const MemoryRegionOps bonito_spciconf_ops = {
612 .old_mmio = {
613 .read = {
614 bonito_spciconf_readb,
615 bonito_spciconf_readw,
616 bonito_spciconf_readl,
617 },
618 .write = {
619 bonito_spciconf_writeb,
620 bonito_spciconf_writew,
621 bonito_spciconf_writel,
622 },
623 },
624 .endianness = DEVICE_NATIVE_ENDIAN,
625 };
626
627 #define BONITO_IRQ_BASE 32
628
629 static void pci_bonito_set_irq(void *opaque, int irq_num, int level)
630 {
631 BonitoState *s = opaque;
632 qemu_irq *pic = s->pic;
633 PCIBonitoState *bonito_state = s->pci_dev;
634 int internal_irq = irq_num - BONITO_IRQ_BASE;
635
636 if (bonito_state->regs[BONITO_INTEDGE] & (1 << internal_irq)) {
637 qemu_irq_pulse(*pic);
638 } else { /* level triggered */
639 if (bonito_state->regs[BONITO_INTPOL] & (1 << internal_irq)) {
640 qemu_irq_raise(*pic);
641 } else {
642 qemu_irq_lower(*pic);
643 }
644 }
645 }
646
647 /* map the original irq (0~3) to bonito irq (16~47, but 16~31 are unused) */
648 static int pci_bonito_map_irq(PCIDevice * pci_dev, int irq_num)
649 {
650 int slot;
651
652 slot = (pci_dev->devfn >> 3);
653
654 switch (slot) {
655 case 5: /* FULONG2E_VIA_SLOT, SouthBridge, IDE, USB, ACPI, AC97, MC97 */
656 return irq_num % 4 + BONITO_IRQ_BASE;
657 case 6: /* FULONG2E_ATI_SLOT, VGA */
658 return 4 + BONITO_IRQ_BASE;
659 case 7: /* FULONG2E_RTL_SLOT, RTL8139 */
660 return 5 + BONITO_IRQ_BASE;
661 case 8 ... 12: /* PCI slot 1 to 4 */
662 return (slot - 8 + irq_num) + 6 + BONITO_IRQ_BASE;
663 default: /* Unknown device, don't do any translation */
664 return irq_num;
665 }
666 }
667
668 static void bonito_reset(void *opaque)
669 {
670 PCIBonitoState *s = opaque;
671
672 /* set the default value of north bridge registers */
673
674 s->regs[BONITO_BONPONCFG] = 0xc40;
675 s->regs[BONITO_BONGENCFG] = 0x1384;
676 s->regs[BONITO_IODEVCFG] = 0x2bff8010;
677 s->regs[BONITO_SDCFG] = 0x255e0091;
678
679 s->regs[BONITO_GPIODATA] = 0x1ff;
680 s->regs[BONITO_GPIOIE] = 0x1ff;
681 s->regs[BONITO_DQCFG] = 0x8;
682 s->regs[BONITO_MEMSIZE] = 0x10000000;
683 s->regs[BONITO_PCIMAP] = 0x6140;
684 }
685
686 static const VMStateDescription vmstate_bonito = {
687 .name = "Bonito",
688 .version_id = 1,
689 .minimum_version_id = 1,
690 .minimum_version_id_old = 1,
691 .fields = (VMStateField []) {
692 VMSTATE_PCI_DEVICE(dev, PCIBonitoState),
693 VMSTATE_END_OF_LIST()
694 }
695 };
696
697 static int bonito_pcihost_initfn(SysBusDevice *dev)
698 {
699 PCIHostState *phb = PCI_HOST_BRIDGE(dev);
700
701 phb->bus = pci_register_bus(DEVICE(dev), "pci",
702 pci_bonito_set_irq, pci_bonito_map_irq, dev,
703 get_system_memory(), get_system_io(),
704 0x28, 32, TYPE_PCI_BUS);
705
706 return 0;
707 }
708
709 static int bonito_initfn(PCIDevice *dev)
710 {
711 PCIBonitoState *s = DO_UPCAST(PCIBonitoState, dev, dev);
712 SysBusDevice *sysbus = SYS_BUS_DEVICE(s->pcihost);
713 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
714
715 /* Bonito North Bridge, built on FPGA, VENDOR_ID/DEVICE_ID are "undefined" */
716 pci_config_set_prog_interface(dev->config, 0x00);
717
718 /* set the north bridge register mapping */
719 memory_region_init_io(&s->iomem, OBJECT(s), &bonito_ops, s,
720 "north-bridge-register", BONITO_INTERNAL_REG_SIZE);
721 sysbus_init_mmio(sysbus, &s->iomem);
722 sysbus_mmio_map(sysbus, 0, BONITO_INTERNAL_REG_BASE);
723
724 /* set the north bridge pci configure mapping */
725 memory_region_init_io(&phb->conf_mem, OBJECT(s), &bonito_pciconf_ops, s,
726 "north-bridge-pci-config", BONITO_PCICONFIG_SIZE);
727 sysbus_init_mmio(sysbus, &phb->conf_mem);
728 sysbus_mmio_map(sysbus, 1, BONITO_PCICONFIG_BASE);
729
730 /* set the south bridge pci configure mapping */
731 memory_region_init_io(&phb->data_mem, OBJECT(s), &bonito_spciconf_ops, s,
732 "south-bridge-pci-config", BONITO_SPCICONFIG_SIZE);
733 sysbus_init_mmio(sysbus, &phb->data_mem);
734 sysbus_mmio_map(sysbus, 2, BONITO_SPCICONFIG_BASE);
735
736 memory_region_init_io(&s->iomem_ldma, OBJECT(s), &bonito_ldma_ops, s,
737 "ldma", 0x100);
738 sysbus_init_mmio(sysbus, &s->iomem_ldma);
739 sysbus_mmio_map(sysbus, 3, 0xbfe00200);
740
741 memory_region_init_io(&s->iomem_cop, OBJECT(s), &bonito_cop_ops, s,
742 "cop", 0x100);
743 sysbus_init_mmio(sysbus, &s->iomem_cop);
744 sysbus_mmio_map(sysbus, 4, 0xbfe00300);
745
746 /* Map PCI IO Space 0x1fd0 0000 - 0x1fd1 0000 */
747 memory_region_init_alias(&s->bonito_pciio, OBJECT(s), "isa_mmio",
748 get_system_io(), 0, BONITO_PCIIO_SIZE);
749 sysbus_init_mmio(sysbus, &s->bonito_pciio);
750 sysbus_mmio_map(sysbus, 5, BONITO_PCIIO_BASE);
751
752 /* add pci local io mapping */
753 memory_region_init_alias(&s->bonito_localio, OBJECT(s), "isa_mmio",
754 get_system_io(), 0, BONITO_DEV_SIZE);
755 sysbus_init_mmio(sysbus, &s->bonito_localio);
756 sysbus_mmio_map(sysbus, 6, BONITO_DEV_BASE);
757
758 /* set the default value of north bridge pci config */
759 pci_set_word(dev->config + PCI_COMMAND, 0x0000);
760 pci_set_word(dev->config + PCI_STATUS, 0x0000);
761 pci_set_word(dev->config + PCI_SUBSYSTEM_VENDOR_ID, 0x0000);
762 pci_set_word(dev->config + PCI_SUBSYSTEM_ID, 0x0000);
763
764 pci_set_byte(dev->config + PCI_INTERRUPT_LINE, 0x00);
765 pci_set_byte(dev->config + PCI_INTERRUPT_PIN, 0x01);
766 pci_set_byte(dev->config + PCI_MIN_GNT, 0x3c);
767 pci_set_byte(dev->config + PCI_MAX_LAT, 0x00);
768
769 qemu_register_reset(bonito_reset, s);
770
771 return 0;
772 }
773
774 PCIBus *bonito_init(qemu_irq *pic)
775 {
776 DeviceState *dev;
777 BonitoState *pcihost;
778 PCIHostState *phb;
779 PCIBonitoState *s;
780 PCIDevice *d;
781
782 dev = qdev_create(NULL, TYPE_BONITO_PCI_HOST_BRIDGE);
783 phb = PCI_HOST_BRIDGE(dev);
784 pcihost = BONITO_PCI_HOST_BRIDGE(dev);
785 pcihost->pic = pic;
786 qdev_init_nofail(dev);
787
788 /* set the pcihost pointer before bonito_initfn is called */
789 d = pci_create(phb->bus, PCI_DEVFN(0, 0), "Bonito");
790 s = DO_UPCAST(PCIBonitoState, dev, d);
791 s->pcihost = pcihost;
792 pcihost->pci_dev = s;
793 qdev_init_nofail(DEVICE(d));
794
795 return phb->bus;
796 }
797
798 static void bonito_class_init(ObjectClass *klass, void *data)
799 {
800 DeviceClass *dc = DEVICE_CLASS(klass);
801 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
802
803 k->init = bonito_initfn;
804 k->vendor_id = 0xdf53;
805 k->device_id = 0x00d5;
806 k->revision = 0x01;
807 k->class_id = PCI_CLASS_BRIDGE_HOST;
808 dc->desc = "Host bridge";
809 dc->vmsd = &vmstate_bonito;
810 /*
811 * PCI-facing part of the host bridge, not usable without the
812 * host-facing part, which can't be device_add'ed, yet.
813 */
814 dc->cannot_instantiate_with_device_add_yet = true;
815 }
816
817 static const TypeInfo bonito_info = {
818 .name = "Bonito",
819 .parent = TYPE_PCI_DEVICE,
820 .instance_size = sizeof(PCIBonitoState),
821 .class_init = bonito_class_init,
822 };
823
824 static void bonito_pcihost_class_init(ObjectClass *klass, void *data)
825 {
826 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
827
828 k->init = bonito_pcihost_initfn;
829 }
830
831 static const TypeInfo bonito_pcihost_info = {
832 .name = TYPE_BONITO_PCI_HOST_BRIDGE,
833 .parent = TYPE_PCI_HOST_BRIDGE,
834 .instance_size = sizeof(BonitoState),
835 .class_init = bonito_pcihost_class_init,
836 };
837
838 static void bonito_register_types(void)
839 {
840 type_register_static(&bonito_pcihost_info);
841 type_register_static(&bonito_info);
842 }
843
844 type_init(bonito_register_types)
QEmu