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net: cadence_gem: Make phy respond to broadcast
[qemu.git] / hw / arm / pxa2xx.c
blob04291488e43edae69c077f9e6b90d3c549de1cb2
1 /*
2 * Intel XScale PXA255/270 processor support.
3 *
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
6 *
7 * This code is licensed under the GPL.
8 */
9
10 #include "hw/sysbus.h"
11 #include "hw/arm/pxa.h"
12 #include "sysemu/sysemu.h"
13 #include "hw/char/serial.h"
14 #include "hw/i2c/i2c.h"
15 #include "hw/ssi.h"
16 #include "sysemu/char.h"
17 #include "sysemu/blockdev.h"
18
19 static struct {
20 hwaddr io_base;
21 int irqn;
22 } pxa255_serial[] = {
23 { 0x40100000, PXA2XX_PIC_FFUART },
24 { 0x40200000, PXA2XX_PIC_BTUART },
25 { 0x40700000, PXA2XX_PIC_STUART },
26 { 0x41600000, PXA25X_PIC_HWUART },
27 { 0, 0 }
28 }, pxa270_serial[] = {
29 { 0x40100000, PXA2XX_PIC_FFUART },
30 { 0x40200000, PXA2XX_PIC_BTUART },
31 { 0x40700000, PXA2XX_PIC_STUART },
32 { 0, 0 }
33 };
34
35 typedef struct PXASSPDef {
36 hwaddr io_base;
37 int irqn;
38 } PXASSPDef;
39
40 #if 0
41 static PXASSPDef pxa250_ssp[] = {
42 { 0x41000000, PXA2XX_PIC_SSP },
43 { 0, 0 }
44 };
45 #endif
46
47 static PXASSPDef pxa255_ssp[] = {
48 { 0x41000000, PXA2XX_PIC_SSP },
49 { 0x41400000, PXA25X_PIC_NSSP },
50 { 0, 0 }
51 };
52
53 #if 0
54 static PXASSPDef pxa26x_ssp[] = {
55 { 0x41000000, PXA2XX_PIC_SSP },
56 { 0x41400000, PXA25X_PIC_NSSP },
57 { 0x41500000, PXA26X_PIC_ASSP },
58 { 0, 0 }
59 };
60 #endif
61
62 static PXASSPDef pxa27x_ssp[] = {
63 { 0x41000000, PXA2XX_PIC_SSP },
64 { 0x41700000, PXA27X_PIC_SSP2 },
65 { 0x41900000, PXA2XX_PIC_SSP3 },
66 { 0, 0 }
67 };
68
69 #define PMCR 0x00 /* Power Manager Control register */
70 #define PSSR 0x04 /* Power Manager Sleep Status register */
71 #define PSPR 0x08 /* Power Manager Scratch-Pad register */
72 #define PWER 0x0c /* Power Manager Wake-Up Enable register */
73 #define PRER 0x10 /* Power Manager Rising-Edge Detect Enable register */
74 #define PFER 0x14 /* Power Manager Falling-Edge Detect Enable register */
75 #define PEDR 0x18 /* Power Manager Edge-Detect Status register */
76 #define PCFR 0x1c /* Power Manager General Configuration register */
77 #define PGSR0 0x20 /* Power Manager GPIO Sleep-State register 0 */
78 #define PGSR1 0x24 /* Power Manager GPIO Sleep-State register 1 */
79 #define PGSR2 0x28 /* Power Manager GPIO Sleep-State register 2 */
80 #define PGSR3 0x2c /* Power Manager GPIO Sleep-State register 3 */
81 #define RCSR 0x30 /* Reset Controller Status register */
82 #define PSLR 0x34 /* Power Manager Sleep Configuration register */
83 #define PTSR 0x38 /* Power Manager Standby Configuration register */
84 #define PVCR 0x40 /* Power Manager Voltage Change Control register */
85 #define PUCR 0x4c /* Power Manager USIM Card Control/Status register */
86 #define PKWR 0x50 /* Power Manager Keyboard Wake-Up Enable register */
87 #define PKSR 0x54 /* Power Manager Keyboard Level-Detect Status */
88 #define PCMD0 0x80 /* Power Manager I2C Command register File 0 */
89 #define PCMD31 0xfc /* Power Manager I2C Command register File 31 */
90
91 static uint64_t pxa2xx_pm_read(void *opaque, hwaddr addr,
92 unsigned size)
93 {
94 PXA2xxState *s = (PXA2xxState *) opaque;
95
96 switch (addr) {
97 case PMCR ... PCMD31:
98 if (addr & 3)
99 goto fail;
100
101 return s->pm_regs[addr >> 2];
102 default:
103 fail:
104 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
105 break;
106 }
107 return 0;
108 }
109
110 static void pxa2xx_pm_write(void *opaque, hwaddr addr,
111 uint64_t value, unsigned size)
112 {
113 PXA2xxState *s = (PXA2xxState *) opaque;
114
115 switch (addr) {
116 case PMCR:
117 /* Clear the write-one-to-clear bits... */
118 s->pm_regs[addr >> 2] &= ~(value & 0x2a);
119 /* ...and set the plain r/w bits */
120 s->pm_regs[addr >> 2] &= ~0x15;
121 s->pm_regs[addr >> 2] |= value & 0x15;
122 break;
123
124 case PSSR: /* Read-clean registers */
125 case RCSR:
126 case PKSR:
127 s->pm_regs[addr >> 2] &= ~value;
128 break;
129
130 default: /* Read-write registers */
131 if (!(addr & 3)) {
132 s->pm_regs[addr >> 2] = value;
133 break;
134 }
135
136 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
137 break;
138 }
139 }
140
141 static const MemoryRegionOps pxa2xx_pm_ops = {
142 .read = pxa2xx_pm_read,
143 .write = pxa2xx_pm_write,
144 .endianness = DEVICE_NATIVE_ENDIAN,
145 };
146
147 static const VMStateDescription vmstate_pxa2xx_pm = {
148 .name = "pxa2xx_pm",
149 .version_id = 0,
150 .minimum_version_id = 0,
151 .minimum_version_id_old = 0,
152 .fields = (VMStateField[]) {
153 VMSTATE_UINT32_ARRAY(pm_regs, PXA2xxState, 0x40),
154 VMSTATE_END_OF_LIST()
155 }
156 };
157
158 #define CCCR 0x00 /* Core Clock Configuration register */
159 #define CKEN 0x04 /* Clock Enable register */
160 #define OSCC 0x08 /* Oscillator Configuration register */
161 #define CCSR 0x0c /* Core Clock Status register */
162
163 static uint64_t pxa2xx_cm_read(void *opaque, hwaddr addr,
164 unsigned size)
165 {
166 PXA2xxState *s = (PXA2xxState *) opaque;
167
168 switch (addr) {
169 case CCCR:
170 case CKEN:
171 case OSCC:
172 return s->cm_regs[addr >> 2];
173
174 case CCSR:
175 return s->cm_regs[CCCR >> 2] | (3 << 28);
176
177 default:
178 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
179 break;
180 }
181 return 0;
182 }
183
184 static void pxa2xx_cm_write(void *opaque, hwaddr addr,
185 uint64_t value, unsigned size)
186 {
187 PXA2xxState *s = (PXA2xxState *) opaque;
188
189 switch (addr) {
190 case CCCR:
191 case CKEN:
192 s->cm_regs[addr >> 2] = value;
193 break;
194
195 case OSCC:
196 s->cm_regs[addr >> 2] &= ~0x6c;
197 s->cm_regs[addr >> 2] |= value & 0x6e;
198 if ((value >> 1) & 1) /* OON */
199 s->cm_regs[addr >> 2] |= 1 << 0; /* Oscillator is now stable */
200 break;
201
202 default:
203 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
204 break;
205 }
206 }
207
208 static const MemoryRegionOps pxa2xx_cm_ops = {
209 .read = pxa2xx_cm_read,
210 .write = pxa2xx_cm_write,
211 .endianness = DEVICE_NATIVE_ENDIAN,
212 };
213
214 static const VMStateDescription vmstate_pxa2xx_cm = {
215 .name = "pxa2xx_cm",
216 .version_id = 0,
217 .minimum_version_id = 0,
218 .minimum_version_id_old = 0,
219 .fields = (VMStateField[]) {
220 VMSTATE_UINT32_ARRAY(cm_regs, PXA2xxState, 4),
221 VMSTATE_UINT32(clkcfg, PXA2xxState),
222 VMSTATE_UINT32(pmnc, PXA2xxState),
223 VMSTATE_END_OF_LIST()
224 }
225 };
226
227 static uint64_t pxa2xx_clkcfg_read(CPUARMState *env, const ARMCPRegInfo *ri)
228 {
229 PXA2xxState *s = (PXA2xxState *)ri->opaque;
230 return s->clkcfg;
231 }
232
233 static void pxa2xx_clkcfg_write(CPUARMState *env, const ARMCPRegInfo *ri,
234 uint64_t value)
235 {
236 PXA2xxState *s = (PXA2xxState *)ri->opaque;
237 s->clkcfg = value & 0xf;
238 if (value & 2) {
239 printf("%s: CPU frequency change attempt\n", __func__);
240 }
241 }
242
243 static void pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri,
244 uint64_t value)
245 {
246 PXA2xxState *s = (PXA2xxState *)ri->opaque;
247 static const char *pwrmode[8] = {
248 "Normal", "Idle", "Deep-idle", "Standby",
249 "Sleep", "reserved (!)", "reserved (!)", "Deep-sleep",
250 };
251
252 if (value & 8) {
253 printf("%s: CPU voltage change attempt\n", __func__);
254 }
255 switch (value & 7) {
256 case 0:
257 /* Do nothing */
258 break;
259
260 case 1:
261 /* Idle */
262 if (!(s->cm_regs[CCCR >> 2] & (1U << 31))) { /* CPDIS */
263 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT);
264 break;
265 }
266 /* Fall through. */
267
268 case 2:
269 /* Deep-Idle */
270 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT);
271 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
272 goto message;
273
274 case 3:
275 s->cpu->env.uncached_cpsr = ARM_CPU_MODE_SVC;
276 s->cpu->env.daif = PSTATE_A | PSTATE_F | PSTATE_I;
277 s->cpu->env.cp15.c1_sys = 0;
278 s->cpu->env.cp15.c1_coproc = 0;
279 s->cpu->env.cp15.ttbr0_el1 = 0;
280 s->cpu->env.cp15.c3 = 0;
281 s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */
282 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
283
284 /*
285 * The scratch-pad register is almost universally used
286 * for storing the return address on suspend. For the
287 * lack of a resuming bootloader, perform a jump
288 * directly to that address.
289 */
290 memset(s->cpu->env.regs, 0, 4 * 15);
291 s->cpu->env.regs[15] = s->pm_regs[PSPR >> 2];
292
293 #if 0
294 buffer = 0xe59ff000; /* ldr pc, [pc, #0] */
295 cpu_physical_memory_write(0, &buffer, 4);
296 buffer = s->pm_regs[PSPR >> 2];
297 cpu_physical_memory_write(8, &buffer, 4);
298 #endif
299
300 /* Suspend */
301 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT);
302
303 goto message;
304
305 default:
306 message:
307 printf("%s: machine entered %s mode\n", __func__,
308 pwrmode[value & 7]);
309 }
310 }
311
312 static uint64_t pxa2xx_cppmnc_read(CPUARMState *env, const ARMCPRegInfo *ri)
313 {
314 PXA2xxState *s = (PXA2xxState *)ri->opaque;
315 return s->pmnc;
316 }
317
318 static void pxa2xx_cppmnc_write(CPUARMState *env, const ARMCPRegInfo *ri,
319 uint64_t value)
320 {
321 PXA2xxState *s = (PXA2xxState *)ri->opaque;
322 s->pmnc = value;
323 }
324
325 static uint64_t pxa2xx_cpccnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
326 {
327 PXA2xxState *s = (PXA2xxState *)ri->opaque;
328 if (s->pmnc & 1) {
329 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
330 } else {
331 return 0;
332 }
333 }
334
335 static const ARMCPRegInfo pxa_cp_reginfo[] = {
336 /* cp14 crm==1: perf registers */
337 { .name = "CPPMNC", .cp = 14, .crn = 0, .crm = 1, .opc1 = 0, .opc2 = 0,
338 .access = PL1_RW,
339 .readfn = pxa2xx_cppmnc_read, .writefn = pxa2xx_cppmnc_write },
340 { .name = "CPCCNT", .cp = 14, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
341 .access = PL1_RW,
342 .readfn = pxa2xx_cpccnt_read, .writefn = arm_cp_write_ignore },
343 { .name = "CPINTEN", .cp = 14, .crn = 4, .crm = 1, .opc1 = 0, .opc2 = 0,
344 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
345 { .name = "CPFLAG", .cp = 14, .crn = 5, .crm = 1, .opc1 = 0, .opc2 = 0,
346 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
347 { .name = "CPEVTSEL", .cp = 14, .crn = 8, .crm = 1, .opc1 = 0, .opc2 = 0,
348 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
349 /* cp14 crm==2: performance count registers */
350 { .name = "CPPMN0", .cp = 14, .crn = 0, .crm = 2, .opc1 = 0, .opc2 = 0,
351 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
352 { .name = "CPPMN1", .cp = 14, .crn = 1, .crm = 2, .opc1 = 0, .opc2 = 0,
353 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
354 { .name = "CPPMN2", .cp = 14, .crn = 2, .crm = 2, .opc1 = 0, .opc2 = 0,
355 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
356 { .name = "CPPMN3", .cp = 14, .crn = 2, .crm = 3, .opc1 = 0, .opc2 = 0,
357 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
358 /* cp14 crn==6: CLKCFG */
359 { .name = "CLKCFG", .cp = 14, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
360 .access = PL1_RW,
361 .readfn = pxa2xx_clkcfg_read, .writefn = pxa2xx_clkcfg_write },
362 /* cp14 crn==7: PWRMODE */
363 { .name = "PWRMODE", .cp = 14, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 0,
364 .access = PL1_RW,
365 .readfn = arm_cp_read_zero, .writefn = pxa2xx_pwrmode_write },
366 REGINFO_SENTINEL
367 };
368
369 static void pxa2xx_setup_cp14(PXA2xxState *s)
370 {
371 define_arm_cp_regs_with_opaque(s->cpu, pxa_cp_reginfo, s);
372 }
373
374 #define MDCNFG 0x00 /* SDRAM Configuration register */
375 #define MDREFR 0x04 /* SDRAM Refresh Control register */
376 #define MSC0 0x08 /* Static Memory Control register 0 */
377 #define MSC1 0x0c /* Static Memory Control register 1 */
378 #define MSC2 0x10 /* Static Memory Control register 2 */
379 #define MECR 0x14 /* Expansion Memory Bus Config register */
380 #define SXCNFG 0x1c /* Synchronous Static Memory Config register */
381 #define MCMEM0 0x28 /* PC Card Memory Socket 0 Timing register */
382 #define MCMEM1 0x2c /* PC Card Memory Socket 1 Timing register */
383 #define MCATT0 0x30 /* PC Card Attribute Socket 0 register */
384 #define MCATT1 0x34 /* PC Card Attribute Socket 1 register */
385 #define MCIO0 0x38 /* PC Card I/O Socket 0 Timing register */
386 #define MCIO1 0x3c /* PC Card I/O Socket 1 Timing register */
387 #define MDMRS 0x40 /* SDRAM Mode Register Set Config register */
388 #define BOOT_DEF 0x44 /* Boot-time Default Configuration register */
389 #define ARB_CNTL 0x48 /* Arbiter Control register */
390 #define BSCNTR0 0x4c /* Memory Buffer Strength Control register 0 */
391 #define BSCNTR1 0x50 /* Memory Buffer Strength Control register 1 */
392 #define LCDBSCNTR 0x54 /* LCD Buffer Strength Control register */
393 #define MDMRSLP 0x58 /* Low Power SDRAM Mode Set Config register */
394 #define BSCNTR2 0x5c /* Memory Buffer Strength Control register 2 */
395 #define BSCNTR3 0x60 /* Memory Buffer Strength Control register 3 */
396 #define SA1110 0x64 /* SA-1110 Memory Compatibility register */
397
398 static uint64_t pxa2xx_mm_read(void *opaque, hwaddr addr,
399 unsigned size)
400 {
401 PXA2xxState *s = (PXA2xxState *) opaque;
402
403 switch (addr) {
404 case MDCNFG ... SA1110:
405 if ((addr & 3) == 0)
406 return s->mm_regs[addr >> 2];
407
408 default:
409 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
410 break;
411 }
412 return 0;
413 }
414
415 static void pxa2xx_mm_write(void *opaque, hwaddr addr,
416 uint64_t value, unsigned size)
417 {
418 PXA2xxState *s = (PXA2xxState *) opaque;
419
420 switch (addr) {
421 case MDCNFG ... SA1110:
422 if ((addr & 3) == 0) {
423 s->mm_regs[addr >> 2] = value;
424 break;
425 }
426
427 default:
428 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
429 break;
430 }
431 }
432
433 static const MemoryRegionOps pxa2xx_mm_ops = {
434 .read = pxa2xx_mm_read,
435 .write = pxa2xx_mm_write,
436 .endianness = DEVICE_NATIVE_ENDIAN,
437 };
438
439 static const VMStateDescription vmstate_pxa2xx_mm = {
440 .name = "pxa2xx_mm",
441 .version_id = 0,
442 .minimum_version_id = 0,
443 .minimum_version_id_old = 0,
444 .fields = (VMStateField[]) {
445 VMSTATE_UINT32_ARRAY(mm_regs, PXA2xxState, 0x1a),
446 VMSTATE_END_OF_LIST()
447 }
448 };
449
450 #define TYPE_PXA2XX_SSP "pxa2xx-ssp"
451 #define PXA2XX_SSP(obj) \
452 OBJECT_CHECK(PXA2xxSSPState, (obj), TYPE_PXA2XX_SSP)
453
454 /* Synchronous Serial Ports */
455 typedef struct {
456 /*< private >*/
457 SysBusDevice parent_obj;
458 /*< public >*/
459
460 MemoryRegion iomem;
461 qemu_irq irq;
462 int enable;
463 SSIBus *bus;
464
465 uint32_t sscr[2];
466 uint32_t sspsp;
467 uint32_t ssto;
468 uint32_t ssitr;
469 uint32_t sssr;
470 uint8_t sstsa;
471 uint8_t ssrsa;
472 uint8_t ssacd;
473
474 uint32_t rx_fifo[16];
475 int rx_level;
476 int rx_start;
477 } PXA2xxSSPState;
478
479 #define SSCR0 0x00 /* SSP Control register 0 */
480 #define SSCR1 0x04 /* SSP Control register 1 */
481 #define SSSR 0x08 /* SSP Status register */
482 #define SSITR 0x0c /* SSP Interrupt Test register */
483 #define SSDR 0x10 /* SSP Data register */
484 #define SSTO 0x28 /* SSP Time-Out register */
485 #define SSPSP 0x2c /* SSP Programmable Serial Protocol register */
486 #define SSTSA 0x30 /* SSP TX Time Slot Active register */
487 #define SSRSA 0x34 /* SSP RX Time Slot Active register */
488 #define SSTSS 0x38 /* SSP Time Slot Status register */
489 #define SSACD 0x3c /* SSP Audio Clock Divider register */
490
491 /* Bitfields for above registers */
492 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00)
493 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10)
494 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20)
495 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30)
496 #define SSCR0_SSE (1 << 7)
497 #define SSCR0_RIM (1 << 22)
498 #define SSCR0_TIM (1 << 23)
499 #define SSCR0_MOD (1U << 31)
500 #define SSCR0_DSS(x) (((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1)
501 #define SSCR1_RIE (1 << 0)
502 #define SSCR1_TIE (1 << 1)
503 #define SSCR1_LBM (1 << 2)
504 #define SSCR1_MWDS (1 << 5)
505 #define SSCR1_TFT(x) ((((x) >> 6) & 0xf) + 1)
506 #define SSCR1_RFT(x) ((((x) >> 10) & 0xf) + 1)
507 #define SSCR1_EFWR (1 << 14)
508 #define SSCR1_PINTE (1 << 18)
509 #define SSCR1_TINTE (1 << 19)
510 #define SSCR1_RSRE (1 << 20)
511 #define SSCR1_TSRE (1 << 21)
512 #define SSCR1_EBCEI (1 << 29)
513 #define SSITR_INT (7 << 5)
514 #define SSSR_TNF (1 << 2)
515 #define SSSR_RNE (1 << 3)
516 #define SSSR_TFS (1 << 5)
517 #define SSSR_RFS (1 << 6)
518 #define SSSR_ROR (1 << 7)
519 #define SSSR_PINT (1 << 18)
520 #define SSSR_TINT (1 << 19)
521 #define SSSR_EOC (1 << 20)
522 #define SSSR_TUR (1 << 21)
523 #define SSSR_BCE (1 << 23)
524 #define SSSR_RW 0x00bc0080
525
526 static void pxa2xx_ssp_int_update(PXA2xxSSPState *s)
527 {
528 int level = 0;
529
530 level |= s->ssitr & SSITR_INT;
531 level |= (s->sssr & SSSR_BCE) && (s->sscr[1] & SSCR1_EBCEI);
532 level |= (s->sssr & SSSR_TUR) && !(s->sscr[0] & SSCR0_TIM);
533 level |= (s->sssr & SSSR_EOC) && (s->sssr & (SSSR_TINT | SSSR_PINT));
534 level |= (s->sssr & SSSR_TINT) && (s->sscr[1] & SSCR1_TINTE);
535 level |= (s->sssr & SSSR_PINT) && (s->sscr[1] & SSCR1_PINTE);
536 level |= (s->sssr & SSSR_ROR) && !(s->sscr[0] & SSCR0_RIM);
537 level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE);
538 level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE);
539 qemu_set_irq(s->irq, !!level);
540 }
541
542 static void pxa2xx_ssp_fifo_update(PXA2xxSSPState *s)
543 {
544 s->sssr &= ~(0xf << 12); /* Clear RFL */
545 s->sssr &= ~(0xf << 8); /* Clear TFL */
546 s->sssr &= ~SSSR_TFS;
547 s->sssr &= ~SSSR_TNF;
548 if (s->enable) {
549 s->sssr |= ((s->rx_level - 1) & 0xf) << 12;
550 if (s->rx_level >= SSCR1_RFT(s->sscr[1]))
551 s->sssr |= SSSR_RFS;
552 else
553 s->sssr &= ~SSSR_RFS;
554 if (s->rx_level)
555 s->sssr |= SSSR_RNE;
556 else
557 s->sssr &= ~SSSR_RNE;
558 /* TX FIFO is never filled, so it is always in underrun
559 condition if SSP is enabled */
560 s->sssr |= SSSR_TFS;
561 s->sssr |= SSSR_TNF;
562 }
563
564 pxa2xx_ssp_int_update(s);
565 }
566
567 static uint64_t pxa2xx_ssp_read(void *opaque, hwaddr addr,
568 unsigned size)
569 {
570 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
571 uint32_t retval;
572
573 switch (addr) {
574 case SSCR0:
575 return s->sscr[0];
576 case SSCR1:
577 return s->sscr[1];
578 case SSPSP:
579 return s->sspsp;
580 case SSTO:
581 return s->ssto;
582 case SSITR:
583 return s->ssitr;
584 case SSSR:
585 return s->sssr | s->ssitr;
586 case SSDR:
587 if (!s->enable)
588 return 0xffffffff;
589 if (s->rx_level < 1) {
590 printf("%s: SSP Rx Underrun\n", __FUNCTION__);
591 return 0xffffffff;
592 }
593 s->rx_level --;
594 retval = s->rx_fifo[s->rx_start ++];
595 s->rx_start &= 0xf;
596 pxa2xx_ssp_fifo_update(s);
597 return retval;
598 case SSTSA:
599 return s->sstsa;
600 case SSRSA:
601 return s->ssrsa;
602 case SSTSS:
603 return 0;
604 case SSACD:
605 return s->ssacd;
606 default:
607 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
608 break;
609 }
610 return 0;
611 }
612
613 static void pxa2xx_ssp_write(void *opaque, hwaddr addr,
614 uint64_t value64, unsigned size)
615 {
616 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
617 uint32_t value = value64;
618
619 switch (addr) {
620 case SSCR0:
621 s->sscr[0] = value & 0xc7ffffff;
622 s->enable = value & SSCR0_SSE;
623 if (value & SSCR0_MOD)
624 printf("%s: Attempt to use network mode\n", __FUNCTION__);
625 if (s->enable && SSCR0_DSS(value) < 4)
626 printf("%s: Wrong data size: %i bits\n", __FUNCTION__,
627 SSCR0_DSS(value));
628 if (!(value & SSCR0_SSE)) {
629 s->sssr = 0;
630 s->ssitr = 0;
631 s->rx_level = 0;
632 }
633 pxa2xx_ssp_fifo_update(s);
634 break;
635
636 case SSCR1:
637 s->sscr[1] = value;
638 if (value & (SSCR1_LBM | SSCR1_EFWR))
639 printf("%s: Attempt to use SSP test mode\n", __FUNCTION__);
640 pxa2xx_ssp_fifo_update(s);
641 break;
642
643 case SSPSP:
644 s->sspsp = value;
645 break;
646
647 case SSTO:
648 s->ssto = value;
649 break;
650
651 case SSITR:
652 s->ssitr = value & SSITR_INT;
653 pxa2xx_ssp_int_update(s);
654 break;
655
656 case SSSR:
657 s->sssr &= ~(value & SSSR_RW);
658 pxa2xx_ssp_int_update(s);
659 break;
660
661 case SSDR:
662 if (SSCR0_UWIRE(s->sscr[0])) {
663 if (s->sscr[1] & SSCR1_MWDS)
664 value &= 0xffff;
665 else
666 value &= 0xff;
667 } else
668 /* Note how 32bits overflow does no harm here */
669 value &= (1 << SSCR0_DSS(s->sscr[0])) - 1;
670
671 /* Data goes from here to the Tx FIFO and is shifted out from
672 * there directly to the slave, no need to buffer it.
673 */
674 if (s->enable) {
675 uint32_t readval;
676 readval = ssi_transfer(s->bus, value);
677 if (s->rx_level < 0x10) {
678 s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] = readval;
679 } else {
680 s->sssr |= SSSR_ROR;
681 }
682 }
683 pxa2xx_ssp_fifo_update(s);
684 break;
685
686 case SSTSA:
687 s->sstsa = value;
688 break;
689
690 case SSRSA:
691 s->ssrsa = value;
692 break;
693
694 case SSACD:
695 s->ssacd = value;
696 break;
697
698 default:
699 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
700 break;
701 }
702 }
703
704 static const MemoryRegionOps pxa2xx_ssp_ops = {
705 .read = pxa2xx_ssp_read,
706 .write = pxa2xx_ssp_write,
707 .endianness = DEVICE_NATIVE_ENDIAN,
708 };
709
710 static void pxa2xx_ssp_save(QEMUFile *f, void *opaque)
711 {
712 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
713 int i;
714
715 qemu_put_be32(f, s->enable);
716
717 qemu_put_be32s(f, &s->sscr[0]);
718 qemu_put_be32s(f, &s->sscr[1]);
719 qemu_put_be32s(f, &s->sspsp);
720 qemu_put_be32s(f, &s->ssto);
721 qemu_put_be32s(f, &s->ssitr);
722 qemu_put_be32s(f, &s->sssr);
723 qemu_put_8s(f, &s->sstsa);
724 qemu_put_8s(f, &s->ssrsa);
725 qemu_put_8s(f, &s->ssacd);
726
727 qemu_put_byte(f, s->rx_level);
728 for (i = 0; i < s->rx_level; i ++)
729 qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 0xf]);
730 }
731
732 static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id)
733 {
734 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
735 int i;
736
737 s->enable = qemu_get_be32(f);
738
739 qemu_get_be32s(f, &s->sscr[0]);
740 qemu_get_be32s(f, &s->sscr[1]);
741 qemu_get_be32s(f, &s->sspsp);
742 qemu_get_be32s(f, &s->ssto);
743 qemu_get_be32s(f, &s->ssitr);
744 qemu_get_be32s(f, &s->sssr);
745 qemu_get_8s(f, &s->sstsa);
746 qemu_get_8s(f, &s->ssrsa);
747 qemu_get_8s(f, &s->ssacd);
748
749 s->rx_level = qemu_get_byte(f);
750 s->rx_start = 0;
751 for (i = 0; i < s->rx_level; i ++)
752 s->rx_fifo[i] = qemu_get_byte(f);
753
754 return 0;
755 }
756
757 static int pxa2xx_ssp_init(SysBusDevice *sbd)
758 {
759 DeviceState *dev = DEVICE(sbd);
760 PXA2xxSSPState *s = PXA2XX_SSP(dev);
761
762 sysbus_init_irq(sbd, &s->irq);
763
764 memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_ssp_ops, s,
765 "pxa2xx-ssp", 0x1000);
766 sysbus_init_mmio(sbd, &s->iomem);
767 register_savevm(dev, "pxa2xx_ssp", -1, 0,
768 pxa2xx_ssp_save, pxa2xx_ssp_load, s);
769
770 s->bus = ssi_create_bus(dev, "ssi");
771 return 0;
772 }
773
774 /* Real-Time Clock */
775 #define RCNR 0x00 /* RTC Counter register */
776 #define RTAR 0x04 /* RTC Alarm register */
777 #define RTSR 0x08 /* RTC Status register */
778 #define RTTR 0x0c /* RTC Timer Trim register */
779 #define RDCR 0x10 /* RTC Day Counter register */
780 #define RYCR 0x14 /* RTC Year Counter register */
781 #define RDAR1 0x18 /* RTC Wristwatch Day Alarm register 1 */
782 #define RYAR1 0x1c /* RTC Wristwatch Year Alarm register 1 */
783 #define RDAR2 0x20 /* RTC Wristwatch Day Alarm register 2 */
784 #define RYAR2 0x24 /* RTC Wristwatch Year Alarm register 2 */
785 #define SWCR 0x28 /* RTC Stopwatch Counter register */
786 #define SWAR1 0x2c /* RTC Stopwatch Alarm register 1 */
787 #define SWAR2 0x30 /* RTC Stopwatch Alarm register 2 */
788 #define RTCPICR 0x34 /* RTC Periodic Interrupt Counter register */
789 #define PIAR 0x38 /* RTC Periodic Interrupt Alarm register */
790
791 #define TYPE_PXA2XX_RTC "pxa2xx_rtc"
792 #define PXA2XX_RTC(obj) \
793 OBJECT_CHECK(PXA2xxRTCState, (obj), TYPE_PXA2XX_RTC)
794
795 typedef struct {
796 /*< private >*/
797 SysBusDevice parent_obj;
798 /*< public >*/
799
800 MemoryRegion iomem;
801 uint32_t rttr;
802 uint32_t rtsr;
803 uint32_t rtar;
804 uint32_t rdar1;
805 uint32_t rdar2;
806 uint32_t ryar1;
807 uint32_t ryar2;
808 uint32_t swar1;
809 uint32_t swar2;
810 uint32_t piar;
811 uint32_t last_rcnr;
812 uint32_t last_rdcr;
813 uint32_t last_rycr;
814 uint32_t last_swcr;
815 uint32_t last_rtcpicr;
816 int64_t last_hz;
817 int64_t last_sw;
818 int64_t last_pi;
819 QEMUTimer *rtc_hz;
820 QEMUTimer *rtc_rdal1;
821 QEMUTimer *rtc_rdal2;
822 QEMUTimer *rtc_swal1;
823 QEMUTimer *rtc_swal2;
824 QEMUTimer *rtc_pi;
825 qemu_irq rtc_irq;
826 } PXA2xxRTCState;
827
828 static inline void pxa2xx_rtc_int_update(PXA2xxRTCState *s)
829 {
830 qemu_set_irq(s->rtc_irq, !!(s->rtsr & 0x2553));
831 }
832
833 static void pxa2xx_rtc_hzupdate(PXA2xxRTCState *s)
834 {
835 int64_t rt = qemu_clock_get_ms(rtc_clock);
836 s->last_rcnr += ((rt - s->last_hz) << 15) /
837 (1000 * ((s->rttr & 0xffff) + 1));
838 s->last_rdcr += ((rt - s->last_hz) << 15) /
839 (1000 * ((s->rttr & 0xffff) + 1));
840 s->last_hz = rt;
841 }
842
843 static void pxa2xx_rtc_swupdate(PXA2xxRTCState *s)
844 {
845 int64_t rt = qemu_clock_get_ms(rtc_clock);
846 if (s->rtsr & (1 << 12))
847 s->last_swcr += (rt - s->last_sw) / 10;
848 s->last_sw = rt;
849 }
850
851 static void pxa2xx_rtc_piupdate(PXA2xxRTCState *s)
852 {
853 int64_t rt = qemu_clock_get_ms(rtc_clock);
854 if (s->rtsr & (1 << 15))
855 s->last_swcr += rt - s->last_pi;
856 s->last_pi = rt;
857 }
858
859 static inline void pxa2xx_rtc_alarm_update(PXA2xxRTCState *s,
860 uint32_t rtsr)
861 {
862 if ((rtsr & (1 << 2)) && !(rtsr & (1 << 0)))
863 timer_mod(s->rtc_hz, s->last_hz +
864 (((s->rtar - s->last_rcnr) * 1000 *
865 ((s->rttr & 0xffff) + 1)) >> 15));
866 else
867 timer_del(s->rtc_hz);
868
869 if ((rtsr & (1 << 5)) && !(rtsr & (1 << 4)))
870 timer_mod(s->rtc_rdal1, s->last_hz +
871 (((s->rdar1 - s->last_rdcr) * 1000 *
872 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */
873 else
874 timer_del(s->rtc_rdal1);
875
876 if ((rtsr & (1 << 7)) && !(rtsr & (1 << 6)))
877 timer_mod(s->rtc_rdal2, s->last_hz +
878 (((s->rdar2 - s->last_rdcr) * 1000 *
879 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */
880 else
881 timer_del(s->rtc_rdal2);
882
883 if ((rtsr & 0x1200) == 0x1200 && !(rtsr & (1 << 8)))
884 timer_mod(s->rtc_swal1, s->last_sw +
885 (s->swar1 - s->last_swcr) * 10); /* TODO: fixup */
886 else
887 timer_del(s->rtc_swal1);
888
889 if ((rtsr & 0x1800) == 0x1800 && !(rtsr & (1 << 10)))
890 timer_mod(s->rtc_swal2, s->last_sw +
891 (s->swar2 - s->last_swcr) * 10); /* TODO: fixup */
892 else
893 timer_del(s->rtc_swal2);
894
895 if ((rtsr & 0xc000) == 0xc000 && !(rtsr & (1 << 13)))
896 timer_mod(s->rtc_pi, s->last_pi +
897 (s->piar & 0xffff) - s->last_rtcpicr);
898 else
899 timer_del(s->rtc_pi);
900 }
901
902 static inline void pxa2xx_rtc_hz_tick(void *opaque)
903 {
904 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
905 s->rtsr |= (1 << 0);
906 pxa2xx_rtc_alarm_update(s, s->rtsr);
907 pxa2xx_rtc_int_update(s);
908 }
909
910 static inline void pxa2xx_rtc_rdal1_tick(void *opaque)
911 {
912 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
913 s->rtsr |= (1 << 4);
914 pxa2xx_rtc_alarm_update(s, s->rtsr);
915 pxa2xx_rtc_int_update(s);
916 }
917
918 static inline void pxa2xx_rtc_rdal2_tick(void *opaque)
919 {
920 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
921 s->rtsr |= (1 << 6);
922 pxa2xx_rtc_alarm_update(s, s->rtsr);
923 pxa2xx_rtc_int_update(s);
924 }
925
926 static inline void pxa2xx_rtc_swal1_tick(void *opaque)
927 {
928 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
929 s->rtsr |= (1 << 8);
930 pxa2xx_rtc_alarm_update(s, s->rtsr);
931 pxa2xx_rtc_int_update(s);
932 }
933
934 static inline void pxa2xx_rtc_swal2_tick(void *opaque)
935 {
936 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
937 s->rtsr |= (1 << 10);
938 pxa2xx_rtc_alarm_update(s, s->rtsr);
939 pxa2xx_rtc_int_update(s);
940 }
941
942 static inline void pxa2xx_rtc_pi_tick(void *opaque)
943 {
944 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
945 s->rtsr |= (1 << 13);
946 pxa2xx_rtc_piupdate(s);
947 s->last_rtcpicr = 0;
948 pxa2xx_rtc_alarm_update(s, s->rtsr);
949 pxa2xx_rtc_int_update(s);
950 }
951
952 static uint64_t pxa2xx_rtc_read(void *opaque, hwaddr addr,
953 unsigned size)
954 {
955 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
956
957 switch (addr) {
958 case RTTR:
959 return s->rttr;
960 case RTSR:
961 return s->rtsr;
962 case RTAR:
963 return s->rtar;
964 case RDAR1:
965 return s->rdar1;
966 case RDAR2:
967 return s->rdar2;
968 case RYAR1:
969 return s->ryar1;
970 case RYAR2:
971 return s->ryar2;
972 case SWAR1:
973 return s->swar1;
974 case SWAR2:
975 return s->swar2;
976 case PIAR:
977 return s->piar;
978 case RCNR:
979 return s->last_rcnr +
980 ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) /
981 (1000 * ((s->rttr & 0xffff) + 1));
982 case RDCR:
983 return s->last_rdcr +
984 ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) /
985 (1000 * ((s->rttr & 0xffff) + 1));
986 case RYCR:
987 return s->last_rycr;
988 case SWCR:
989 if (s->rtsr & (1 << 12))
990 return s->last_swcr +
991 (qemu_clock_get_ms(rtc_clock) - s->last_sw) / 10;
992 else
993 return s->last_swcr;
994 default:
995 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
996 break;
997 }
998 return 0;
999 }
1000
1001 static void pxa2xx_rtc_write(void *opaque, hwaddr addr,
1002 uint64_t value64, unsigned size)
1003 {
1004 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1005 uint32_t value = value64;
1006
1007 switch (addr) {
1008 case RTTR:
1009 if (!(s->rttr & (1U << 31))) {
1010 pxa2xx_rtc_hzupdate(s);
1011 s->rttr = value;
1012 pxa2xx_rtc_alarm_update(s, s->rtsr);
1013 }
1014 break;
1015
1016 case RTSR:
1017 if ((s->rtsr ^ value) & (1 << 15))
1018 pxa2xx_rtc_piupdate(s);
1019
1020 if ((s->rtsr ^ value) & (1 << 12))
1021 pxa2xx_rtc_swupdate(s);
1022
1023 if (((s->rtsr ^ value) & 0x4aac) | (value & ~0xdaac))
1024 pxa2xx_rtc_alarm_update(s, value);
1025
1026 s->rtsr = (value & 0xdaac) | (s->rtsr & ~(value & ~0xdaac));
1027 pxa2xx_rtc_int_update(s);
1028 break;
1029
1030 case RTAR:
1031 s->rtar = value;
1032 pxa2xx_rtc_alarm_update(s, s->rtsr);
1033 break;
1034
1035 case RDAR1:
1036 s->rdar1 = value;
1037 pxa2xx_rtc_alarm_update(s, s->rtsr);
1038 break;
1039
1040 case RDAR2:
1041 s->rdar2 = value;
1042 pxa2xx_rtc_alarm_update(s, s->rtsr);
1043 break;
1044
1045 case RYAR1:
1046 s->ryar1 = value;
1047 pxa2xx_rtc_alarm_update(s, s->rtsr);
1048 break;
1049
1050 case RYAR2:
1051 s->ryar2 = value;
1052 pxa2xx_rtc_alarm_update(s, s->rtsr);
1053 break;
1054
1055 case SWAR1:
1056 pxa2xx_rtc_swupdate(s);
1057 s->swar1 = value;
1058 s->last_swcr = 0;
1059 pxa2xx_rtc_alarm_update(s, s->rtsr);
1060 break;
1061
1062 case SWAR2:
1063 s->swar2 = value;
1064 pxa2xx_rtc_alarm_update(s, s->rtsr);
1065 break;
1066
1067 case PIAR:
1068 s->piar = value;
1069 pxa2xx_rtc_alarm_update(s, s->rtsr);
1070 break;
1071
1072 case RCNR:
1073 pxa2xx_rtc_hzupdate(s);
1074 s->last_rcnr = value;
1075 pxa2xx_rtc_alarm_update(s, s->rtsr);
1076 break;
1077
1078 case RDCR:
1079 pxa2xx_rtc_hzupdate(s);
1080 s->last_rdcr = value;
1081 pxa2xx_rtc_alarm_update(s, s->rtsr);
1082 break;
1083
1084 case RYCR:
1085 s->last_rycr = value;
1086 break;
1087
1088 case SWCR:
1089 pxa2xx_rtc_swupdate(s);
1090 s->last_swcr = value;
1091 pxa2xx_rtc_alarm_update(s, s->rtsr);
1092 break;
1093
1094 case RTCPICR:
1095 pxa2xx_rtc_piupdate(s);
1096 s->last_rtcpicr = value & 0xffff;
1097 pxa2xx_rtc_alarm_update(s, s->rtsr);
1098 break;
1099
1100 default:
1101 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1102 }
1103 }
1104
1105 static const MemoryRegionOps pxa2xx_rtc_ops = {
1106 .read = pxa2xx_rtc_read,
1107 .write = pxa2xx_rtc_write,
1108 .endianness = DEVICE_NATIVE_ENDIAN,
1109 };
1110
1111 static int pxa2xx_rtc_init(SysBusDevice *dev)
1112 {
1113 PXA2xxRTCState *s = PXA2XX_RTC(dev);
1114 struct tm tm;
1115 int wom;
1116
1117 s->rttr = 0x7fff;
1118 s->rtsr = 0;
1119
1120 qemu_get_timedate(&tm, 0);
1121 wom = ((tm.tm_mday - 1) / 7) + 1;
1122
1123 s->last_rcnr = (uint32_t) mktimegm(&tm);
1124 s->last_rdcr = (wom << 20) | ((tm.tm_wday + 1) << 17) |
1125 (tm.tm_hour << 12) | (tm.tm_min << 6) | tm.tm_sec;
1126 s->last_rycr = ((tm.tm_year + 1900) << 9) |
1127 ((tm.tm_mon + 1) << 5) | tm.tm_mday;
1128 s->last_swcr = (tm.tm_hour << 19) |
1129 (tm.tm_min << 13) | (tm.tm_sec << 7);
1130 s->last_rtcpicr = 0;
1131 s->last_hz = s->last_sw = s->last_pi = qemu_clock_get_ms(rtc_clock);
1132
1133 s->rtc_hz = timer_new_ms(rtc_clock, pxa2xx_rtc_hz_tick, s);
1134 s->rtc_rdal1 = timer_new_ms(rtc_clock, pxa2xx_rtc_rdal1_tick, s);
1135 s->rtc_rdal2 = timer_new_ms(rtc_clock, pxa2xx_rtc_rdal2_tick, s);
1136 s->rtc_swal1 = timer_new_ms(rtc_clock, pxa2xx_rtc_swal1_tick, s);
1137 s->rtc_swal2 = timer_new_ms(rtc_clock, pxa2xx_rtc_swal2_tick, s);
1138 s->rtc_pi = timer_new_ms(rtc_clock, pxa2xx_rtc_pi_tick, s);
1139
1140 sysbus_init_irq(dev, &s->rtc_irq);
1141
1142 memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_rtc_ops, s,
1143 "pxa2xx-rtc", 0x10000);
1144 sysbus_init_mmio(dev, &s->iomem);
1145
1146 return 0;
1147 }
1148
1149 static void pxa2xx_rtc_pre_save(void *opaque)
1150 {
1151 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1152
1153 pxa2xx_rtc_hzupdate(s);
1154 pxa2xx_rtc_piupdate(s);
1155 pxa2xx_rtc_swupdate(s);
1156 }
1157
1158 static int pxa2xx_rtc_post_load(void *opaque, int version_id)
1159 {
1160 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1161
1162 pxa2xx_rtc_alarm_update(s, s->rtsr);
1163
1164 return 0;
1165 }
1166
1167 static const VMStateDescription vmstate_pxa2xx_rtc_regs = {
1168 .name = "pxa2xx_rtc",
1169 .version_id = 0,
1170 .minimum_version_id = 0,
1171 .minimum_version_id_old = 0,
1172 .pre_save = pxa2xx_rtc_pre_save,
1173 .post_load = pxa2xx_rtc_post_load,
1174 .fields = (VMStateField[]) {
1175 VMSTATE_UINT32(rttr, PXA2xxRTCState),
1176 VMSTATE_UINT32(rtsr, PXA2xxRTCState),
1177 VMSTATE_UINT32(rtar, PXA2xxRTCState),
1178 VMSTATE_UINT32(rdar1, PXA2xxRTCState),
1179 VMSTATE_UINT32(rdar2, PXA2xxRTCState),
1180 VMSTATE_UINT32(ryar1, PXA2xxRTCState),
1181 VMSTATE_UINT32(ryar2, PXA2xxRTCState),
1182 VMSTATE_UINT32(swar1, PXA2xxRTCState),
1183 VMSTATE_UINT32(swar2, PXA2xxRTCState),
1184 VMSTATE_UINT32(piar, PXA2xxRTCState),
1185 VMSTATE_UINT32(last_rcnr, PXA2xxRTCState),
1186 VMSTATE_UINT32(last_rdcr, PXA2xxRTCState),
1187 VMSTATE_UINT32(last_rycr, PXA2xxRTCState),
1188 VMSTATE_UINT32(last_swcr, PXA2xxRTCState),
1189 VMSTATE_UINT32(last_rtcpicr, PXA2xxRTCState),
1190 VMSTATE_INT64(last_hz, PXA2xxRTCState),
1191 VMSTATE_INT64(last_sw, PXA2xxRTCState),
1192 VMSTATE_INT64(last_pi, PXA2xxRTCState),
1193 VMSTATE_END_OF_LIST(),
1194 },
1195 };
1196
1197 static void pxa2xx_rtc_sysbus_class_init(ObjectClass *klass, void *data)
1198 {
1199 DeviceClass *dc = DEVICE_CLASS(klass);
1200 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
1201
1202 k->init = pxa2xx_rtc_init;
1203 dc->desc = "PXA2xx RTC Controller";
1204 dc->vmsd = &vmstate_pxa2xx_rtc_regs;
1205 }
1206
1207 static const TypeInfo pxa2xx_rtc_sysbus_info = {
1208 .name = TYPE_PXA2XX_RTC,
1209 .parent = TYPE_SYS_BUS_DEVICE,
1210 .instance_size = sizeof(PXA2xxRTCState),
1211 .class_init = pxa2xx_rtc_sysbus_class_init,
1212 };
1213
1214 /* I2C Interface */
1215
1216 #define TYPE_PXA2XX_I2C_SLAVE "pxa2xx-i2c-slave"
1217 #define PXA2XX_I2C_SLAVE(obj) \
1218 OBJECT_CHECK(PXA2xxI2CSlaveState, (obj), TYPE_PXA2XX_I2C_SLAVE)
1219
1220 typedef struct PXA2xxI2CSlaveState {
1221 I2CSlave parent_obj;
1222
1223 PXA2xxI2CState *host;
1224 } PXA2xxI2CSlaveState;
1225
1226 #define TYPE_PXA2XX_I2C "pxa2xx_i2c"
1227 #define PXA2XX_I2C(obj) \
1228 OBJECT_CHECK(PXA2xxI2CState, (obj), TYPE_PXA2XX_I2C)
1229
1230 struct PXA2xxI2CState {
1231 /*< private >*/
1232 SysBusDevice parent_obj;
1233 /*< public >*/
1234
1235 MemoryRegion iomem;
1236 PXA2xxI2CSlaveState *slave;
1237 I2CBus *bus;
1238 qemu_irq irq;
1239 uint32_t offset;
1240 uint32_t region_size;
1241
1242 uint16_t control;
1243 uint16_t status;
1244 uint8_t ibmr;
1245 uint8_t data;
1246 };
1247
1248 #define IBMR 0x80 /* I2C Bus Monitor register */
1249 #define IDBR 0x88 /* I2C Data Buffer register */
1250 #define ICR 0x90 /* I2C Control register */
1251 #define ISR 0x98 /* I2C Status register */
1252 #define ISAR 0xa0 /* I2C Slave Address register */
1253
1254 static void pxa2xx_i2c_update(PXA2xxI2CState *s)
1255 {
1256 uint16_t level = 0;
1257 level |= s->status & s->control & (1 << 10); /* BED */
1258 level |= (s->status & (1 << 7)) && (s->control & (1 << 9)); /* IRF */
1259 level |= (s->status & (1 << 6)) && (s->control & (1 << 8)); /* ITE */
1260 level |= s->status & (1 << 9); /* SAD */
1261 qemu_set_irq(s->irq, !!level);
1262 }
1263
1264 /* These are only stubs now. */
1265 static void pxa2xx_i2c_event(I2CSlave *i2c, enum i2c_event event)
1266 {
1267 PXA2xxI2CSlaveState *slave = PXA2XX_I2C_SLAVE(i2c);
1268 PXA2xxI2CState *s = slave->host;
1269
1270 switch (event) {
1271 case I2C_START_SEND:
1272 s->status |= (1 << 9); /* set SAD */
1273 s->status &= ~(1 << 0); /* clear RWM */
1274 break;
1275 case I2C_START_RECV:
1276 s->status |= (1 << 9); /* set SAD */
1277 s->status |= 1 << 0; /* set RWM */
1278 break;
1279 case I2C_FINISH:
1280 s->status |= (1 << 4); /* set SSD */
1281 break;
1282 case I2C_NACK:
1283 s->status |= 1 << 1; /* set ACKNAK */
1284 break;
1285 }
1286 pxa2xx_i2c_update(s);
1287 }
1288
1289 static int pxa2xx_i2c_rx(I2CSlave *i2c)
1290 {
1291 PXA2xxI2CSlaveState *slave = PXA2XX_I2C_SLAVE(i2c);
1292 PXA2xxI2CState *s = slave->host;
1293
1294 if ((s->control & (1 << 14)) || !(s->control & (1 << 6))) {
1295 return 0;
1296 }
1297
1298 if (s->status & (1 << 0)) { /* RWM */
1299 s->status |= 1 << 6; /* set ITE */
1300 }
1301 pxa2xx_i2c_update(s);
1302
1303 return s->data;
1304 }
1305
1306 static int pxa2xx_i2c_tx(I2CSlave *i2c, uint8_t data)
1307 {
1308 PXA2xxI2CSlaveState *slave = PXA2XX_I2C_SLAVE(i2c);
1309 PXA2xxI2CState *s = slave->host;
1310
1311 if ((s->control & (1 << 14)) || !(s->control & (1 << 6))) {
1312 return 1;
1313 }
1314
1315 if (!(s->status & (1 << 0))) { /* RWM */
1316 s->status |= 1 << 7; /* set IRF */
1317 s->data = data;
1318 }
1319 pxa2xx_i2c_update(s);
1320
1321 return 1;
1322 }
1323
1324 static uint64_t pxa2xx_i2c_read(void *opaque, hwaddr addr,
1325 unsigned size)
1326 {
1327 PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
1328 I2CSlave *slave;
1329
1330 addr -= s->offset;
1331 switch (addr) {
1332 case ICR:
1333 return s->control;
1334 case ISR:
1335 return s->status | (i2c_bus_busy(s->bus) << 2);
1336 case ISAR:
1337 slave = I2C_SLAVE(s->slave);
1338 return slave->address;
1339 case IDBR:
1340 return s->data;
1341 case IBMR:
1342 if (s->status & (1 << 2))
1343 s->ibmr ^= 3; /* Fake SCL and SDA pin changes */
1344 else
1345 s->ibmr = 0;
1346 return s->ibmr;
1347 default:
1348 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1349 break;
1350 }
1351 return 0;
1352 }
1353
1354 static void pxa2xx_i2c_write(void *opaque, hwaddr addr,
1355 uint64_t value64, unsigned size)
1356 {
1357 PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
1358 uint32_t value = value64;
1359 int ack;
1360
1361 addr -= s->offset;
1362 switch (addr) {
1363 case ICR:
1364 s->control = value & 0xfff7;
1365 if ((value & (1 << 3)) && (value & (1 << 6))) { /* TB and IUE */
1366 /* TODO: slave mode */
1367 if (value & (1 << 0)) { /* START condition */
1368 if (s->data & 1)
1369 s->status |= 1 << 0; /* set RWM */
1370 else
1371 s->status &= ~(1 << 0); /* clear RWM */
1372 ack = !i2c_start_transfer(s->bus, s->data >> 1, s->data & 1);
1373 } else {
1374 if (s->status & (1 << 0)) { /* RWM */
1375 s->data = i2c_recv(s->bus);
1376 if (value & (1 << 2)) /* ACKNAK */
1377 i2c_nack(s->bus);
1378 ack = 1;
1379 } else
1380 ack = !i2c_send(s->bus, s->data);
1381 }
1382
1383 if (value & (1 << 1)) /* STOP condition */
1384 i2c_end_transfer(s->bus);
1385
1386 if (ack) {
1387 if (value & (1 << 0)) /* START condition */
1388 s->status |= 1 << 6; /* set ITE */
1389 else
1390 if (s->status & (1 << 0)) /* RWM */
1391 s->status |= 1 << 7; /* set IRF */
1392 else
1393 s->status |= 1 << 6; /* set ITE */
1394 s->status &= ~(1 << 1); /* clear ACKNAK */
1395 } else {
1396 s->status |= 1 << 6; /* set ITE */
1397 s->status |= 1 << 10; /* set BED */
1398 s->status |= 1 << 1; /* set ACKNAK */
1399 }
1400 }
1401 if (!(value & (1 << 3)) && (value & (1 << 6))) /* !TB and IUE */
1402 if (value & (1 << 4)) /* MA */
1403 i2c_end_transfer(s->bus);
1404 pxa2xx_i2c_update(s);
1405 break;
1406
1407 case ISR:
1408 s->status &= ~(value & 0x07f0);
1409 pxa2xx_i2c_update(s);
1410 break;
1411
1412 case ISAR:
1413 i2c_set_slave_address(I2C_SLAVE(s->slave), value & 0x7f);
1414 break;
1415
1416 case IDBR:
1417 s->data = value & 0xff;
1418 break;
1419
1420 default:
1421 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1422 }
1423 }
1424
1425 static const MemoryRegionOps pxa2xx_i2c_ops = {
1426 .read = pxa2xx_i2c_read,
1427 .write = pxa2xx_i2c_write,
1428 .endianness = DEVICE_NATIVE_ENDIAN,
1429 };
1430
1431 static const VMStateDescription vmstate_pxa2xx_i2c_slave = {
1432 .name = "pxa2xx_i2c_slave",
1433 .version_id = 1,
1434 .minimum_version_id = 1,
1435 .minimum_version_id_old = 1,
1436 .fields = (VMStateField []) {
1437 VMSTATE_I2C_SLAVE(parent_obj, PXA2xxI2CSlaveState),
1438 VMSTATE_END_OF_LIST()
1439 }
1440 };
1441
1442 static const VMStateDescription vmstate_pxa2xx_i2c = {
1443 .name = "pxa2xx_i2c",
1444 .version_id = 1,
1445 .minimum_version_id = 1,
1446 .minimum_version_id_old = 1,
1447 .fields = (VMStateField []) {
1448 VMSTATE_UINT16(control, PXA2xxI2CState),
1449 VMSTATE_UINT16(status, PXA2xxI2CState),
1450 VMSTATE_UINT8(ibmr, PXA2xxI2CState),
1451 VMSTATE_UINT8(data, PXA2xxI2CState),
1452 VMSTATE_STRUCT_POINTER(slave, PXA2xxI2CState,
1453 vmstate_pxa2xx_i2c_slave, PXA2xxI2CSlaveState),
1454 VMSTATE_END_OF_LIST()
1455 }
1456 };
1457
1458 static int pxa2xx_i2c_slave_init(I2CSlave *i2c)
1459 {
1460 /* Nothing to do. */
1461 return 0;
1462 }
1463
1464 static void pxa2xx_i2c_slave_class_init(ObjectClass *klass, void *data)
1465 {
1466 I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
1467
1468 k->init = pxa2xx_i2c_slave_init;
1469 k->event = pxa2xx_i2c_event;
1470 k->recv = pxa2xx_i2c_rx;
1471 k->send = pxa2xx_i2c_tx;
1472 }
1473
1474 static const TypeInfo pxa2xx_i2c_slave_info = {
1475 .name = TYPE_PXA2XX_I2C_SLAVE,
1476 .parent = TYPE_I2C_SLAVE,
1477 .instance_size = sizeof(PXA2xxI2CSlaveState),
1478 .class_init = pxa2xx_i2c_slave_class_init,
1479 };
1480
1481 PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base,
1482 qemu_irq irq, uint32_t region_size)
1483 {
1484 DeviceState *dev;
1485 SysBusDevice *i2c_dev;
1486 PXA2xxI2CState *s;
1487 I2CBus *i2cbus;
1488
1489 dev = qdev_create(NULL, TYPE_PXA2XX_I2C);
1490 qdev_prop_set_uint32(dev, "size", region_size + 1);
1491 qdev_prop_set_uint32(dev, "offset", base & region_size);
1492 qdev_init_nofail(dev);
1493
1494 i2c_dev = SYS_BUS_DEVICE(dev);
1495 sysbus_mmio_map(i2c_dev, 0, base & ~region_size);
1496 sysbus_connect_irq(i2c_dev, 0, irq);
1497
1498 s = PXA2XX_I2C(i2c_dev);
1499 /* FIXME: Should the slave device really be on a separate bus? */
1500 i2cbus = i2c_init_bus(dev, "dummy");
1501 dev = i2c_create_slave(i2cbus, TYPE_PXA2XX_I2C_SLAVE, 0);
1502 s->slave = PXA2XX_I2C_SLAVE(dev);
1503 s->slave->host = s;
1504
1505 return s;
1506 }
1507
1508 static int pxa2xx_i2c_initfn(SysBusDevice *sbd)
1509 {
1510 DeviceState *dev = DEVICE(sbd);
1511 PXA2xxI2CState *s = PXA2XX_I2C(dev);
1512
1513 s->bus = i2c_init_bus(dev, "i2c");
1514
1515 memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_i2c_ops, s,
1516 "pxa2xx-i2c", s->region_size);
1517 sysbus_init_mmio(sbd, &s->iomem);
1518 sysbus_init_irq(sbd, &s->irq);
1519
1520 return 0;
1521 }
1522
1523 I2CBus *pxa2xx_i2c_bus(PXA2xxI2CState *s)
1524 {
1525 return s->bus;
1526 }
1527
1528 static Property pxa2xx_i2c_properties[] = {
1529 DEFINE_PROP_UINT32("size", PXA2xxI2CState, region_size, 0x10000),
1530 DEFINE_PROP_UINT32("offset", PXA2xxI2CState, offset, 0),
1531 DEFINE_PROP_END_OF_LIST(),
1532 };
1533
1534 static void pxa2xx_i2c_class_init(ObjectClass *klass, void *data)
1535 {
1536 DeviceClass *dc = DEVICE_CLASS(klass);
1537 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
1538
1539 k->init = pxa2xx_i2c_initfn;
1540 dc->desc = "PXA2xx I2C Bus Controller";
1541 dc->vmsd = &vmstate_pxa2xx_i2c;
1542 dc->props = pxa2xx_i2c_properties;
1543 }
1544
1545 static const TypeInfo pxa2xx_i2c_info = {
1546 .name = TYPE_PXA2XX_I2C,
1547 .parent = TYPE_SYS_BUS_DEVICE,
1548 .instance_size = sizeof(PXA2xxI2CState),
1549 .class_init = pxa2xx_i2c_class_init,
1550 };
1551
1552 /* PXA Inter-IC Sound Controller */
1553 static void pxa2xx_i2s_reset(PXA2xxI2SState *i2s)
1554 {
1555 i2s->rx_len = 0;
1556 i2s->tx_len = 0;
1557 i2s->fifo_len = 0;
1558 i2s->clk = 0x1a;
1559 i2s->control[0] = 0x00;
1560 i2s->control[1] = 0x00;
1561 i2s->status = 0x00;
1562 i2s->mask = 0x00;
1563 }
1564
1565 #define SACR_TFTH(val) ((val >> 8) & 0xf)
1566 #define SACR_RFTH(val) ((val >> 12) & 0xf)
1567 #define SACR_DREC(val) (val & (1 << 3))
1568 #define SACR_DPRL(val) (val & (1 << 4))
1569
1570 static inline void pxa2xx_i2s_update(PXA2xxI2SState *i2s)
1571 {
1572 int rfs, tfs;
1573 rfs = SACR_RFTH(i2s->control[0]) < i2s->rx_len &&
1574 !SACR_DREC(i2s->control[1]);
1575 tfs = (i2s->tx_len || i2s->fifo_len < SACR_TFTH(i2s->control[0])) &&
1576 i2s->enable && !SACR_DPRL(i2s->control[1]);
1577
1578 qemu_set_irq(i2s->rx_dma, rfs);
1579 qemu_set_irq(i2s->tx_dma, tfs);
1580
1581 i2s->status &= 0xe0;
1582 if (i2s->fifo_len < 16 || !i2s->enable)
1583 i2s->status |= 1 << 0; /* TNF */
1584 if (i2s->rx_len)
1585 i2s->status |= 1 << 1; /* RNE */
1586 if (i2s->enable)
1587 i2s->status |= 1 << 2; /* BSY */
1588 if (tfs)
1589 i2s->status |= 1 << 3; /* TFS */
1590 if (rfs)
1591 i2s->status |= 1 << 4; /* RFS */
1592 if (!(i2s->tx_len && i2s->enable))
1593 i2s->status |= i2s->fifo_len << 8; /* TFL */
1594 i2s->status |= MAX(i2s->rx_len, 0xf) << 12; /* RFL */
1595
1596 qemu_set_irq(i2s->irq, i2s->status & i2s->mask);
1597 }
1598
1599 #define SACR0 0x00 /* Serial Audio Global Control register */
1600 #define SACR1 0x04 /* Serial Audio I2S/MSB-Justified Control register */
1601 #define SASR0 0x0c /* Serial Audio Interface and FIFO Status register */
1602 #define SAIMR 0x14 /* Serial Audio Interrupt Mask register */
1603 #define SAICR 0x18 /* Serial Audio Interrupt Clear register */
1604 #define SADIV 0x60 /* Serial Audio Clock Divider register */
1605 #define SADR 0x80 /* Serial Audio Data register */
1606
1607 static uint64_t pxa2xx_i2s_read(void *opaque, hwaddr addr,
1608 unsigned size)
1609 {
1610 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1611
1612 switch (addr) {
1613 case SACR0:
1614 return s->control[0];
1615 case SACR1:
1616 return s->control[1];
1617 case SASR0:
1618 return s->status;
1619 case SAIMR:
1620 return s->mask;
1621 case SAICR:
1622 return 0;
1623 case SADIV:
1624 return s->clk;
1625 case SADR:
1626 if (s->rx_len > 0) {
1627 s->rx_len --;
1628 pxa2xx_i2s_update(s);
1629 return s->codec_in(s->opaque);
1630 }
1631 return 0;
1632 default:
1633 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1634 break;
1635 }
1636 return 0;
1637 }
1638
1639 static void pxa2xx_i2s_write(void *opaque, hwaddr addr,
1640 uint64_t value, unsigned size)
1641 {
1642 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1643 uint32_t *sample;
1644
1645 switch (addr) {
1646 case SACR0:
1647 if (value & (1 << 3)) /* RST */
1648 pxa2xx_i2s_reset(s);
1649 s->control[0] = value & 0xff3d;
1650 if (!s->enable && (value & 1) && s->tx_len) { /* ENB */
1651 for (sample = s->fifo; s->fifo_len > 0; s->fifo_len --, sample ++)
1652 s->codec_out(s->opaque, *sample);
1653 s->status &= ~(1 << 7); /* I2SOFF */
1654 }
1655 if (value & (1 << 4)) /* EFWR */
1656 printf("%s: Attempt to use special function\n", __FUNCTION__);
1657 s->enable = (value & 9) == 1; /* ENB && !RST*/
1658 pxa2xx_i2s_update(s);
1659 break;
1660 case SACR1:
1661 s->control[1] = value & 0x0039;
1662 if (value & (1 << 5)) /* ENLBF */
1663 printf("%s: Attempt to use loopback function\n", __FUNCTION__);
1664 if (value & (1 << 4)) /* DPRL */
1665 s->fifo_len = 0;
1666 pxa2xx_i2s_update(s);
1667 break;
1668 case SAIMR:
1669 s->mask = value & 0x0078;
1670 pxa2xx_i2s_update(s);
1671 break;
1672 case SAICR:
1673 s->status &= ~(value & (3 << 5));
1674 pxa2xx_i2s_update(s);
1675 break;
1676 case SADIV:
1677 s->clk = value & 0x007f;
1678 break;
1679 case SADR:
1680 if (s->tx_len && s->enable) {
1681 s->tx_len --;
1682 pxa2xx_i2s_update(s);
1683 s->codec_out(s->opaque, value);
1684 } else if (s->fifo_len < 16) {
1685 s->fifo[s->fifo_len ++] = value;
1686 pxa2xx_i2s_update(s);
1687 }
1688 break;
1689 default:
1690 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1691 }
1692 }
1693
1694 static const MemoryRegionOps pxa2xx_i2s_ops = {
1695 .read = pxa2xx_i2s_read,
1696 .write = pxa2xx_i2s_write,
1697 .endianness = DEVICE_NATIVE_ENDIAN,
1698 };
1699
1700 static const VMStateDescription vmstate_pxa2xx_i2s = {
1701 .name = "pxa2xx_i2s",
1702 .version_id = 0,
1703 .minimum_version_id = 0,
1704 .minimum_version_id_old = 0,
1705 .fields = (VMStateField[]) {
1706 VMSTATE_UINT32_ARRAY(control, PXA2xxI2SState, 2),
1707 VMSTATE_UINT32(status, PXA2xxI2SState),
1708 VMSTATE_UINT32(mask, PXA2xxI2SState),
1709 VMSTATE_UINT32(clk, PXA2xxI2SState),
1710 VMSTATE_INT32(enable, PXA2xxI2SState),
1711 VMSTATE_INT32(rx_len, PXA2xxI2SState),
1712 VMSTATE_INT32(tx_len, PXA2xxI2SState),
1713 VMSTATE_INT32(fifo_len, PXA2xxI2SState),
1714 VMSTATE_END_OF_LIST()
1715 }
1716 };
1717
1718 static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx)
1719 {
1720 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1721 uint32_t *sample;
1722
1723 /* Signal FIFO errors */
1724 if (s->enable && s->tx_len)
1725 s->status |= 1 << 5; /* TUR */
1726 if (s->enable && s->rx_len)
1727 s->status |= 1 << 6; /* ROR */
1728
1729 /* Should be tx - MIN(tx, s->fifo_len) but we don't really need to
1730 * handle the cases where it makes a difference. */
1731 s->tx_len = tx - s->fifo_len;
1732 s->rx_len = rx;
1733 /* Note that is s->codec_out wasn't set, we wouldn't get called. */
1734 if (s->enable)
1735 for (sample = s->fifo; s->fifo_len; s->fifo_len --, sample ++)
1736 s->codec_out(s->opaque, *sample);
1737 pxa2xx_i2s_update(s);
1738 }
1739
1740 static PXA2xxI2SState *pxa2xx_i2s_init(MemoryRegion *sysmem,
1741 hwaddr base,
1742 qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma)
1743 {
1744 PXA2xxI2SState *s = (PXA2xxI2SState *)
1745 g_malloc0(sizeof(PXA2xxI2SState));
1746
1747 s->irq = irq;
1748 s->rx_dma = rx_dma;
1749 s->tx_dma = tx_dma;
1750 s->data_req = pxa2xx_i2s_data_req;
1751
1752 pxa2xx_i2s_reset(s);
1753
1754 memory_region_init_io(&s->iomem, NULL, &pxa2xx_i2s_ops, s,
1755 "pxa2xx-i2s", 0x100000);
1756 memory_region_add_subregion(sysmem, base, &s->iomem);
1757
1758 vmstate_register(NULL, base, &vmstate_pxa2xx_i2s, s);
1759
1760 return s;
1761 }
1762
1763 /* PXA Fast Infra-red Communications Port */
1764 struct PXA2xxFIrState {
1765 MemoryRegion iomem;
1766 qemu_irq irq;
1767 qemu_irq rx_dma;
1768 qemu_irq tx_dma;
1769 int enable;
1770 CharDriverState *chr;
1771
1772 uint8_t control[3];
1773 uint8_t status[2];
1774
1775 int rx_len;
1776 int rx_start;
1777 uint8_t rx_fifo[64];
1778 };
1779
1780 static void pxa2xx_fir_reset(PXA2xxFIrState *s)
1781 {
1782 s->control[0] = 0x00;
1783 s->control[1] = 0x00;
1784 s->control[2] = 0x00;
1785 s->status[0] = 0x00;
1786 s->status[1] = 0x00;
1787 s->enable = 0;
1788 }
1789
1790 static inline void pxa2xx_fir_update(PXA2xxFIrState *s)
1791 {
1792 static const int tresh[4] = { 8, 16, 32, 0 };
1793 int intr = 0;
1794 if ((s->control[0] & (1 << 4)) && /* RXE */
1795 s->rx_len >= tresh[s->control[2] & 3]) /* TRIG */
1796 s->status[0] |= 1 << 4; /* RFS */
1797 else
1798 s->status[0] &= ~(1 << 4); /* RFS */
1799 if (s->control[0] & (1 << 3)) /* TXE */
1800 s->status[0] |= 1 << 3; /* TFS */
1801 else
1802 s->status[0] &= ~(1 << 3); /* TFS */
1803 if (s->rx_len)
1804 s->status[1] |= 1 << 2; /* RNE */
1805 else
1806 s->status[1] &= ~(1 << 2); /* RNE */
1807 if (s->control[0] & (1 << 4)) /* RXE */
1808 s->status[1] |= 1 << 0; /* RSY */
1809 else
1810 s->status[1] &= ~(1 << 0); /* RSY */
1811
1812 intr |= (s->control[0] & (1 << 5)) && /* RIE */
1813 (s->status[0] & (1 << 4)); /* RFS */
1814 intr |= (s->control[0] & (1 << 6)) && /* TIE */
1815 (s->status[0] & (1 << 3)); /* TFS */
1816 intr |= (s->control[2] & (1 << 4)) && /* TRAIL */
1817 (s->status[0] & (1 << 6)); /* EOC */
1818 intr |= (s->control[0] & (1 << 2)) && /* TUS */
1819 (s->status[0] & (1 << 1)); /* TUR */
1820 intr |= s->status[0] & 0x25; /* FRE, RAB, EIF */
1821
1822 qemu_set_irq(s->rx_dma, (s->status[0] >> 4) & 1);
1823 qemu_set_irq(s->tx_dma, (s->status[0] >> 3) & 1);
1824
1825 qemu_set_irq(s->irq, intr && s->enable);
1826 }
1827
1828 #define ICCR0 0x00 /* FICP Control register 0 */
1829 #define ICCR1 0x04 /* FICP Control register 1 */
1830 #define ICCR2 0x08 /* FICP Control register 2 */
1831 #define ICDR 0x0c /* FICP Data register */
1832 #define ICSR0 0x14 /* FICP Status register 0 */
1833 #define ICSR1 0x18 /* FICP Status register 1 */
1834 #define ICFOR 0x1c /* FICP FIFO Occupancy Status register */
1835
1836 static uint64_t pxa2xx_fir_read(void *opaque, hwaddr addr,
1837 unsigned size)
1838 {
1839 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1840 uint8_t ret;
1841
1842 switch (addr) {
1843 case ICCR0:
1844 return s->control[0];
1845 case ICCR1:
1846 return s->control[1];
1847 case ICCR2:
1848 return s->control[2];
1849 case ICDR:
1850 s->status[0] &= ~0x01;
1851 s->status[1] &= ~0x72;
1852 if (s->rx_len) {
1853 s->rx_len --;
1854 ret = s->rx_fifo[s->rx_start ++];
1855 s->rx_start &= 63;
1856 pxa2xx_fir_update(s);
1857 return ret;
1858 }
1859 printf("%s: Rx FIFO underrun.\n", __FUNCTION__);
1860 break;
1861 case ICSR0:
1862 return s->status[0];
1863 case ICSR1:
1864 return s->status[1] | (1 << 3); /* TNF */
1865 case ICFOR:
1866 return s->rx_len;
1867 default:
1868 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1869 break;
1870 }
1871 return 0;
1872 }
1873
1874 static void pxa2xx_fir_write(void *opaque, hwaddr addr,
1875 uint64_t value64, unsigned size)
1876 {
1877 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1878 uint32_t value = value64;
1879 uint8_t ch;
1880
1881 switch (addr) {
1882 case ICCR0:
1883 s->control[0] = value;
1884 if (!(value & (1 << 4))) /* RXE */
1885 s->rx_len = s->rx_start = 0;
1886 if (!(value & (1 << 3))) { /* TXE */
1887 /* Nop */
1888 }
1889 s->enable = value & 1; /* ITR */
1890 if (!s->enable)
1891 s->status[0] = 0;
1892 pxa2xx_fir_update(s);
1893 break;
1894 case ICCR1:
1895 s->control[1] = value;
1896 break;
1897 case ICCR2:
1898 s->control[2] = value & 0x3f;
1899 pxa2xx_fir_update(s);
1900 break;
1901 case ICDR:
1902 if (s->control[2] & (1 << 2)) /* TXP */
1903 ch = value;
1904 else
1905 ch = ~value;
1906 if (s->chr && s->enable && (s->control[0] & (1 << 3))) /* TXE */
1907 qemu_chr_fe_write(s->chr, &ch, 1);
1908 break;
1909 case ICSR0:
1910 s->status[0] &= ~(value & 0x66);
1911 pxa2xx_fir_update(s);
1912 break;
1913 case ICFOR:
1914 break;
1915 default:
1916 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1917 }
1918 }
1919
1920 static const MemoryRegionOps pxa2xx_fir_ops = {
1921 .read = pxa2xx_fir_read,
1922 .write = pxa2xx_fir_write,
1923 .endianness = DEVICE_NATIVE_ENDIAN,
1924 };
1925
1926 static int pxa2xx_fir_is_empty(void *opaque)
1927 {
1928 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1929 return (s->rx_len < 64);
1930 }
1931
1932 static void pxa2xx_fir_rx(void *opaque, const uint8_t *buf, int size)
1933 {
1934 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1935 if (!(s->control[0] & (1 << 4))) /* RXE */
1936 return;
1937
1938 while (size --) {
1939 s->status[1] |= 1 << 4; /* EOF */
1940 if (s->rx_len >= 64) {
1941 s->status[1] |= 1 << 6; /* ROR */
1942 break;
1943 }
1944
1945 if (s->control[2] & (1 << 3)) /* RXP */
1946 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = *(buf ++);
1947 else
1948 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = ~*(buf ++);
1949 }
1950
1951 pxa2xx_fir_update(s);
1952 }
1953
1954 static void pxa2xx_fir_event(void *opaque, int event)
1955 {
1956 }
1957
1958 static void pxa2xx_fir_save(QEMUFile *f, void *opaque)
1959 {
1960 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1961 int i;
1962
1963 qemu_put_be32(f, s->enable);
1964
1965 qemu_put_8s(f, &s->control[0]);
1966 qemu_put_8s(f, &s->control[1]);
1967 qemu_put_8s(f, &s->control[2]);
1968 qemu_put_8s(f, &s->status[0]);
1969 qemu_put_8s(f, &s->status[1]);
1970
1971 qemu_put_byte(f, s->rx_len);
1972 for (i = 0; i < s->rx_len; i ++)
1973 qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 63]);
1974 }
1975
1976 static int pxa2xx_fir_load(QEMUFile *f, void *opaque, int version_id)
1977 {
1978 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1979 int i;
1980
1981 s->enable = qemu_get_be32(f);
1982
1983 qemu_get_8s(f, &s->control[0]);
1984 qemu_get_8s(f, &s->control[1]);
1985 qemu_get_8s(f, &s->control[2]);
1986 qemu_get_8s(f, &s->status[0]);
1987 qemu_get_8s(f, &s->status[1]);
1988
1989 s->rx_len = qemu_get_byte(f);
1990 s->rx_start = 0;
1991 for (i = 0; i < s->rx_len; i ++)
1992 s->rx_fifo[i] = qemu_get_byte(f);
1993
1994 return 0;
1995 }
1996
1997 static PXA2xxFIrState *pxa2xx_fir_init(MemoryRegion *sysmem,
1998 hwaddr base,
1999 qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma,
2000 CharDriverState *chr)
2001 {
2002 PXA2xxFIrState *s = (PXA2xxFIrState *)
2003 g_malloc0(sizeof(PXA2xxFIrState));
2004
2005 s->irq = irq;
2006 s->rx_dma = rx_dma;
2007 s->tx_dma = tx_dma;
2008 s->chr = chr;
2009
2010 pxa2xx_fir_reset(s);
2011
2012 memory_region_init_io(&s->iomem, NULL, &pxa2xx_fir_ops, s, "pxa2xx-fir", 0x1000);
2013 memory_region_add_subregion(sysmem, base, &s->iomem);
2014
2015 if (chr) {
2016 qemu_chr_fe_claim_no_fail(chr);
2017 qemu_chr_add_handlers(chr, pxa2xx_fir_is_empty,
2018 pxa2xx_fir_rx, pxa2xx_fir_event, s);
2019 }
2020
2021 register_savevm(NULL, "pxa2xx_fir", 0, 0, pxa2xx_fir_save,
2022 pxa2xx_fir_load, s);
2023
2024 return s;
2025 }
2026
2027 static void pxa2xx_reset(void *opaque, int line, int level)
2028 {
2029 PXA2xxState *s = (PXA2xxState *) opaque;
2030
2031 if (level && (s->pm_regs[PCFR >> 2] & 0x10)) { /* GPR_EN */
2032 cpu_reset(CPU(s->cpu));
2033 /* TODO: reset peripherals */
2034 }
2035 }
2036
2037 /* Initialise a PXA270 integrated chip (ARM based core). */
2038 PXA2xxState *pxa270_init(MemoryRegion *address_space,
2039 unsigned int sdram_size, const char *revision)
2040 {
2041 PXA2xxState *s;
2042 int i;
2043 DriveInfo *dinfo;
2044 s = (PXA2xxState *) g_malloc0(sizeof(PXA2xxState));
2045
2046 if (revision && strncmp(revision, "pxa27", 5)) {
2047 fprintf(stderr, "Machine requires a PXA27x processor.\n");
2048 exit(1);
2049 }
2050 if (!revision)
2051 revision = "pxa270";
2052
2053 s->cpu = cpu_arm_init(revision);
2054 if (s->cpu == NULL) {
2055 fprintf(stderr, "Unable to find CPU definition\n");
2056 exit(1);
2057 }
2058 s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0];
2059
2060 /* SDRAM & Internal Memory Storage */
2061 memory_region_init_ram(&s->sdram, NULL, "pxa270.sdram", sdram_size);
2062 vmstate_register_ram_global(&s->sdram);
2063 memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram);
2064 memory_region_init_ram(&s->internal, NULL, "pxa270.internal", 0x40000);
2065 vmstate_register_ram_global(&s->internal);
2066 memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE,
2067 &s->internal);
2068
2069 s->pic = pxa2xx_pic_init(0x40d00000, s->cpu);
2070
2071 s->dma = pxa27x_dma_init(0x40000000,
2072 qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA));
2073
2074 sysbus_create_varargs("pxa27x-timer", 0x40a00000,
2075 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0),
2076 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1),
2077 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2),
2078 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3),
2079 qdev_get_gpio_in(s->pic, PXA27X_PIC_OST_4_11),
2080 NULL);
2081
2082 s->gpio = pxa2xx_gpio_init(0x40e00000, s->cpu, s->pic, 121);
2083
2084 dinfo = drive_get(IF_SD, 0, 0);
2085 if (!dinfo) {
2086 fprintf(stderr, "qemu: missing SecureDigital device\n");
2087 exit(1);
2088 }
2089 s->mmc = pxa2xx_mmci_init(address_space, 0x41100000, dinfo->bdrv,
2090 qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC),
2091 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI),
2092 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI));
2093
2094 for (i = 0; pxa270_serial[i].io_base; i++) {
2095 if (serial_hds[i]) {
2096 serial_mm_init(address_space, pxa270_serial[i].io_base, 2,
2097 qdev_get_gpio_in(s->pic, pxa270_serial[i].irqn),
2098 14857000 / 16, serial_hds[i],
2099 DEVICE_NATIVE_ENDIAN);
2100 } else {
2101 break;
2102 }
2103 }
2104 if (serial_hds[i])
2105 s->fir = pxa2xx_fir_init(address_space, 0x40800000,
2106 qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP),
2107 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP),
2108 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP),
2109 serial_hds[i]);
2110
2111 s->lcd = pxa2xx_lcdc_init(address_space, 0x44000000,
2112 qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD));
2113
2114 s->cm_base = 0x41300000;
2115 s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
2116 s->clkcfg = 0x00000009; /* Turbo mode active */
2117 memory_region_init_io(&s->cm_iomem, NULL, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000);
2118 memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem);
2119 vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s);
2120
2121 pxa2xx_setup_cp14(s);
2122
2123 s->mm_base = 0x48000000;
2124 s->mm_regs[MDMRS >> 2] = 0x00020002;
2125 s->mm_regs[MDREFR >> 2] = 0x03ca4000;
2126 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
2127 memory_region_init_io(&s->mm_iomem, NULL, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000);
2128 memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem);
2129 vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s);
2130
2131 s->pm_base = 0x40f00000;
2132 memory_region_init_io(&s->pm_iomem, NULL, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100);
2133 memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem);
2134 vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s);
2135
2136 for (i = 0; pxa27x_ssp[i].io_base; i ++);
2137 s->ssp = (SSIBus **)g_malloc0(sizeof(SSIBus *) * i);
2138 for (i = 0; pxa27x_ssp[i].io_base; i ++) {
2139 DeviceState *dev;
2140 dev = sysbus_create_simple(TYPE_PXA2XX_SSP, pxa27x_ssp[i].io_base,
2141 qdev_get_gpio_in(s->pic, pxa27x_ssp[i].irqn));
2142 s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
2143 }
2144
2145 if (usb_enabled(false)) {
2146 sysbus_create_simple("sysbus-ohci", 0x4c000000,
2147 qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1));
2148 }
2149
2150 s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000);
2151 s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000);
2152
2153 sysbus_create_simple(TYPE_PXA2XX_RTC, 0x40900000,
2154 qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM));
2155
2156 s->i2c[0] = pxa2xx_i2c_init(0x40301600,
2157 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff);
2158 s->i2c[1] = pxa2xx_i2c_init(0x40f00100,
2159 qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff);
2160
2161 s->i2s = pxa2xx_i2s_init(address_space, 0x40400000,
2162 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S),
2163 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S),
2164 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S));
2165
2166 s->kp = pxa27x_keypad_init(address_space, 0x41500000,
2167 qdev_get_gpio_in(s->pic, PXA2XX_PIC_KEYPAD));
2168
2169 /* GPIO1 resets the processor */
2170 /* The handler can be overridden by board-specific code */
2171 qdev_connect_gpio_out(s->gpio, 1, s->reset);
2172 return s;
2173 }
2174
2175 /* Initialise a PXA255 integrated chip (ARM based core). */
2176 PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size)
2177 {
2178 PXA2xxState *s;
2179 int i;
2180 DriveInfo *dinfo;
2181
2182 s = (PXA2xxState *) g_malloc0(sizeof(PXA2xxState));
2183
2184 s->cpu = cpu_arm_init("pxa255");
2185 if (s->cpu == NULL) {
2186 fprintf(stderr, "Unable to find CPU definition\n");
2187 exit(1);
2188 }
2189 s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0];
2190
2191 /* SDRAM & Internal Memory Storage */
2192 memory_region_init_ram(&s->sdram, NULL, "pxa255.sdram", sdram_size);
2193 vmstate_register_ram_global(&s->sdram);
2194 memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram);
2195 memory_region_init_ram(&s->internal, NULL, "pxa255.internal",
2196 PXA2XX_INTERNAL_SIZE);
2197 vmstate_register_ram_global(&s->internal);
2198 memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE,
2199 &s->internal);
2200
2201 s->pic = pxa2xx_pic_init(0x40d00000, s->cpu);
2202
2203 s->dma = pxa255_dma_init(0x40000000,
2204 qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA));
2205
2206 sysbus_create_varargs("pxa25x-timer", 0x40a00000,
2207 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0),
2208 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1),
2209 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2),
2210 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3),
2211 NULL);
2212
2213 s->gpio = pxa2xx_gpio_init(0x40e00000, s->cpu, s->pic, 85);
2214
2215 dinfo = drive_get(IF_SD, 0, 0);
2216 if (!dinfo) {
2217 fprintf(stderr, "qemu: missing SecureDigital device\n");
2218 exit(1);
2219 }
2220 s->mmc = pxa2xx_mmci_init(address_space, 0x41100000, dinfo->bdrv,
2221 qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC),
2222 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI),
2223 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI));
2224
2225 for (i = 0; pxa255_serial[i].io_base; i++) {
2226 if (serial_hds[i]) {
2227 serial_mm_init(address_space, pxa255_serial[i].io_base, 2,
2228 qdev_get_gpio_in(s->pic, pxa255_serial[i].irqn),
2229 14745600 / 16, serial_hds[i],
2230 DEVICE_NATIVE_ENDIAN);
2231 } else {
2232 break;
2233 }
2234 }
2235 if (serial_hds[i])
2236 s->fir = pxa2xx_fir_init(address_space, 0x40800000,
2237 qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP),
2238 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP),
2239 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP),
2240 serial_hds[i]);
2241
2242 s->lcd = pxa2xx_lcdc_init(address_space, 0x44000000,
2243 qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD));
2244
2245 s->cm_base = 0x41300000;
2246 s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
2247 s->clkcfg = 0x00000009; /* Turbo mode active */
2248 memory_region_init_io(&s->cm_iomem, NULL, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000);
2249 memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem);
2250 vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s);
2251
2252 pxa2xx_setup_cp14(s);
2253
2254 s->mm_base = 0x48000000;
2255 s->mm_regs[MDMRS >> 2] = 0x00020002;
2256 s->mm_regs[MDREFR >> 2] = 0x03ca4000;
2257 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
2258 memory_region_init_io(&s->mm_iomem, NULL, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000);
2259 memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem);
2260 vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s);
2261
2262 s->pm_base = 0x40f00000;
2263 memory_region_init_io(&s->pm_iomem, NULL, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100);
2264 memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem);
2265 vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s);
2266
2267 for (i = 0; pxa255_ssp[i].io_base; i ++);
2268 s->ssp = (SSIBus **)g_malloc0(sizeof(SSIBus *) * i);
2269 for (i = 0; pxa255_ssp[i].io_base; i ++) {
2270 DeviceState *dev;
2271 dev = sysbus_create_simple(TYPE_PXA2XX_SSP, pxa255_ssp[i].io_base,
2272 qdev_get_gpio_in(s->pic, pxa255_ssp[i].irqn));
2273 s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
2274 }
2275
2276 if (usb_enabled(false)) {
2277 sysbus_create_simple("sysbus-ohci", 0x4c000000,
2278 qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1));
2279 }
2280
2281 s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000);
2282 s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000);
2283
2284 sysbus_create_simple(TYPE_PXA2XX_RTC, 0x40900000,
2285 qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM));
2286
2287 s->i2c[0] = pxa2xx_i2c_init(0x40301600,
2288 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff);
2289 s->i2c[1] = pxa2xx_i2c_init(0x40f00100,
2290 qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff);
2291
2292 s->i2s = pxa2xx_i2s_init(address_space, 0x40400000,
2293 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S),
2294 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S),
2295 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S));
2296
2297 /* GPIO1 resets the processor */
2298 /* The handler can be overridden by board-specific code */
2299 qdev_connect_gpio_out(s->gpio, 1, s->reset);
2300 return s;
2301 }
2302
2303 static void pxa2xx_ssp_class_init(ObjectClass *klass, void *data)
2304 {
2305 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
2306
2307 sdc->init = pxa2xx_ssp_init;
2308 }
2309
2310 static const TypeInfo pxa2xx_ssp_info = {
2311 .name = TYPE_PXA2XX_SSP,
2312 .parent = TYPE_SYS_BUS_DEVICE,
2313 .instance_size = sizeof(PXA2xxSSPState),
2314 .class_init = pxa2xx_ssp_class_init,
2315 };
2316
2317 static void pxa2xx_register_types(void)
2318 {
2319 type_register_static(&pxa2xx_i2c_slave_info);
2320 type_register_static(&pxa2xx_ssp_info);
2321 type_register_static(&pxa2xx_i2c_info);
2322 type_register_static(&pxa2xx_rtc_sysbus_info);
2323 }
2324
2325 type_init(pxa2xx_register_types)
QEmu