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Register reset functions for e1000 and rtl8139
[qemu.git] / hw / rtl8139.c
blobea2ca25182257507f10d14441646e1f901e34ea3
1 /**
2 * QEMU RTL8139 emulation
3 *
4 * Copyright (c) 2006 Igor Kovalenko
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23
24 * Modifications:
25 * 2006-Jan-28 Mark Malakanov : TSAD and CSCR implementation (for Windows driver)
26 *
27 * 2006-Apr-28 Juergen Lock : EEPROM emulation changes for FreeBSD driver
28 * HW revision ID changes for FreeBSD driver
29 *
30 * 2006-Jul-01 Igor Kovalenko : Implemented loopback mode for FreeBSD driver
31 * Corrected packet transfer reassembly routine for 8139C+ mode
32 * Rearranged debugging print statements
33 * Implemented PCI timer interrupt (disabled by default)
34 * Implemented Tally Counters, increased VM load/save version
35 * Implemented IP/TCP/UDP checksum task offloading
36 *
37 * 2006-Jul-04 Igor Kovalenko : Implemented TCP segmentation offloading
38 * Fixed MTU=1500 for produced ethernet frames
39 *
40 * 2006-Jul-09 Igor Kovalenko : Fixed TCP header length calculation while processing
41 * segmentation offloading
42 * Removed slirp.h dependency
43 * Added rx/tx buffer reset when enabling rx/tx operation
44 */
45
46 #include "hw.h"
47 #include "pci.h"
48 #include "qemu-timer.h"
49 #include "net.h"
50
51 /* debug RTL8139 card */
52 //#define DEBUG_RTL8139 1
53
54 #define PCI_FREQUENCY 33000000L
55
56 /* debug RTL8139 card C+ mode only */
57 //#define DEBUG_RTL8139CP 1
58
59 /* Calculate CRCs properly on Rx packets */
60 #define RTL8139_CALCULATE_RXCRC 1
61
62 /* Uncomment to enable on-board timer interrupts */
63 //#define RTL8139_ONBOARD_TIMER 1
64
65 #if defined(RTL8139_CALCULATE_RXCRC)
66 /* For crc32 */
67 #include <zlib.h>
68 #endif
69
70 #define SET_MASKED(input, mask, curr) \
71 ( ( (input) & ~(mask) ) | ( (curr) & (mask) ) )
72
73 /* arg % size for size which is a power of 2 */
74 #define MOD2(input, size) \
75 ( ( input ) & ( size - 1 ) )
76
77 #if defined (DEBUG_RTL8139)
78 # define DEBUG_PRINT(x) do { printf x ; } while (0)
79 #else
80 # define DEBUG_PRINT(x)
81 #endif
82
83 /* Symbolic offsets to registers. */
84 enum RTL8139_registers {
85 MAC0 = 0, /* Ethernet hardware address. */
86 MAR0 = 8, /* Multicast filter. */
87 TxStatus0 = 0x10,/* Transmit status (Four 32bit registers). C mode only */
88 /* Dump Tally Conter control register(64bit). C+ mode only */
89 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
90 RxBuf = 0x30,
91 ChipCmd = 0x37,
92 RxBufPtr = 0x38,
93 RxBufAddr = 0x3A,
94 IntrMask = 0x3C,
95 IntrStatus = 0x3E,
96 TxConfig = 0x40,
97 RxConfig = 0x44,
98 Timer = 0x48, /* A general-purpose counter. */
99 RxMissed = 0x4C, /* 24 bits valid, write clears. */
100 Cfg9346 = 0x50,
101 Config0 = 0x51,
102 Config1 = 0x52,
103 FlashReg = 0x54,
104 MediaStatus = 0x58,
105 Config3 = 0x59,
106 Config4 = 0x5A, /* absent on RTL-8139A */
107 HltClk = 0x5B,
108 MultiIntr = 0x5C,
109 PCIRevisionID = 0x5E,
110 TxSummary = 0x60, /* TSAD register. Transmit Status of All Descriptors*/
111 BasicModeCtrl = 0x62,
112 BasicModeStatus = 0x64,
113 NWayAdvert = 0x66,
114 NWayLPAR = 0x68,
115 NWayExpansion = 0x6A,
116 /* Undocumented registers, but required for proper operation. */
117 FIFOTMS = 0x70, /* FIFO Control and test. */
118 CSCR = 0x74, /* Chip Status and Configuration Register. */
119 PARA78 = 0x78,
120 PARA7c = 0x7c, /* Magic transceiver parameter register. */
121 Config5 = 0xD8, /* absent on RTL-8139A */
122 /* C+ mode */
123 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
124 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
125 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
126 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
127 RxRingAddrLO = 0xE4, /* 64-bit start addr of Rx ring */
128 RxRingAddrHI = 0xE8, /* 64-bit start addr of Rx ring */
129 TxThresh = 0xEC, /* Early Tx threshold */
130 };
131
132 enum ClearBitMasks {
133 MultiIntrClear = 0xF000,
134 ChipCmdClear = 0xE2,
135 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
136 };
137
138 enum ChipCmdBits {
139 CmdReset = 0x10,
140 CmdRxEnb = 0x08,
141 CmdTxEnb = 0x04,
142 RxBufEmpty = 0x01,
143 };
144
145 /* C+ mode */
146 enum CplusCmdBits {
147 CPlusRxVLAN = 0x0040, /* enable receive VLAN detagging */
148 CPlusRxChkSum = 0x0020, /* enable receive checksum offloading */
149 CPlusRxEnb = 0x0002,
150 CPlusTxEnb = 0x0001,
151 };
152
153 /* Interrupt register bits, using my own meaningful names. */
154 enum IntrStatusBits {
155 PCIErr = 0x8000,
156 PCSTimeout = 0x4000,
157 RxFIFOOver = 0x40,
158 RxUnderrun = 0x20,
159 RxOverflow = 0x10,
160 TxErr = 0x08,
161 TxOK = 0x04,
162 RxErr = 0x02,
163 RxOK = 0x01,
164
165 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
166 };
167
168 enum TxStatusBits {
169 TxHostOwns = 0x2000,
170 TxUnderrun = 0x4000,
171 TxStatOK = 0x8000,
172 TxOutOfWindow = 0x20000000,
173 TxAborted = 0x40000000,
174 TxCarrierLost = 0x80000000,
175 };
176 enum RxStatusBits {
177 RxMulticast = 0x8000,
178 RxPhysical = 0x4000,
179 RxBroadcast = 0x2000,
180 RxBadSymbol = 0x0020,
181 RxRunt = 0x0010,
182 RxTooLong = 0x0008,
183 RxCRCErr = 0x0004,
184 RxBadAlign = 0x0002,
185 RxStatusOK = 0x0001,
186 };
187
188 /* Bits in RxConfig. */
189 enum rx_mode_bits {
190 AcceptErr = 0x20,
191 AcceptRunt = 0x10,
192 AcceptBroadcast = 0x08,
193 AcceptMulticast = 0x04,
194 AcceptMyPhys = 0x02,
195 AcceptAllPhys = 0x01,
196 };
197
198 /* Bits in TxConfig. */
199 enum tx_config_bits {
200
201 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
202 TxIFGShift = 24,
203 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
204 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
205 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
206 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
207
208 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
209 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
210 TxClearAbt = (1 << 0), /* Clear abort (WO) */
211 TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */
212 TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */
213
214 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
215 };
216
217
218 /* Transmit Status of All Descriptors (TSAD) Register */
219 enum TSAD_bits {
220 TSAD_TOK3 = 1<<15, // TOK bit of Descriptor 3
221 TSAD_TOK2 = 1<<14, // TOK bit of Descriptor 2
222 TSAD_TOK1 = 1<<13, // TOK bit of Descriptor 1
223 TSAD_TOK0 = 1<<12, // TOK bit of Descriptor 0
224 TSAD_TUN3 = 1<<11, // TUN bit of Descriptor 3
225 TSAD_TUN2 = 1<<10, // TUN bit of Descriptor 2
226 TSAD_TUN1 = 1<<9, // TUN bit of Descriptor 1
227 TSAD_TUN0 = 1<<8, // TUN bit of Descriptor 0
228 TSAD_TABT3 = 1<<07, // TABT bit of Descriptor 3
229 TSAD_TABT2 = 1<<06, // TABT bit of Descriptor 2
230 TSAD_TABT1 = 1<<05, // TABT bit of Descriptor 1
231 TSAD_TABT0 = 1<<04, // TABT bit of Descriptor 0
232 TSAD_OWN3 = 1<<03, // OWN bit of Descriptor 3
233 TSAD_OWN2 = 1<<02, // OWN bit of Descriptor 2
234 TSAD_OWN1 = 1<<01, // OWN bit of Descriptor 1
235 TSAD_OWN0 = 1<<00, // OWN bit of Descriptor 0
236 };
237
238
239 /* Bits in Config1 */
240 enum Config1Bits {
241 Cfg1_PM_Enable = 0x01,
242 Cfg1_VPD_Enable = 0x02,
243 Cfg1_PIO = 0x04,
244 Cfg1_MMIO = 0x08,
245 LWAKE = 0x10, /* not on 8139, 8139A */
246 Cfg1_Driver_Load = 0x20,
247 Cfg1_LED0 = 0x40,
248 Cfg1_LED1 = 0x80,
249 SLEEP = (1 << 1), /* only on 8139, 8139A */
250 PWRDN = (1 << 0), /* only on 8139, 8139A */
251 };
252
253 /* Bits in Config3 */
254 enum Config3Bits {
255 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
256 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
257 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
258 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
259 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
260 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
261 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
262 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
263 };
264
265 /* Bits in Config4 */
266 enum Config4Bits {
267 LWPTN = (1 << 2), /* not on 8139, 8139A */
268 };
269
270 /* Bits in Config5 */
271 enum Config5Bits {
272 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
273 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
274 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
275 Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */
276 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
277 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
278 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
279 };
280
281 enum RxConfigBits {
282 /* rx fifo threshold */
283 RxCfgFIFOShift = 13,
284 RxCfgFIFONone = (7 << RxCfgFIFOShift),
285
286 /* Max DMA burst */
287 RxCfgDMAShift = 8,
288 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
289
290 /* rx ring buffer length */
291 RxCfgRcv8K = 0,
292 RxCfgRcv16K = (1 << 11),
293 RxCfgRcv32K = (1 << 12),
294 RxCfgRcv64K = (1 << 11) | (1 << 12),
295
296 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
297 RxNoWrap = (1 << 7),
298 };
299
300 /* Twister tuning parameters from RealTek.
301 Completely undocumented, but required to tune bad links on some boards. */
302 /*
303 enum CSCRBits {
304 CSCR_LinkOKBit = 0x0400,
305 CSCR_LinkChangeBit = 0x0800,
306 CSCR_LinkStatusBits = 0x0f000,
307 CSCR_LinkDownOffCmd = 0x003c0,
308 CSCR_LinkDownCmd = 0x0f3c0,
309 */
310 enum CSCRBits {
311 CSCR_Testfun = 1<<15, /* 1 = Auto-neg speeds up internal timer, WO, def 0 */
312 CSCR_LD = 1<<9, /* Active low TPI link disable signal. When low, TPI still transmits link pulses and TPI stays in good link state. def 1*/
313 CSCR_HEART_BIT = 1<<8, /* 1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART BEAT function is only valid in 10Mbps mode. def 1*/
314 CSCR_JBEN = 1<<7, /* 1 = enable jabber function. 0 = disable jabber function, def 1*/
315 CSCR_F_LINK_100 = 1<<6, /* Used to login force good link in 100Mbps for diagnostic purposes. 1 = DISABLE, 0 = ENABLE. def 1*/
316 CSCR_F_Connect = 1<<5, /* Assertion of this bit forces the disconnect function to be bypassed. def 0*/
317 CSCR_Con_status = 1<<3, /* This bit indicates the status of the connection. 1 = valid connected link detected; 0 = disconnected link detected. RO def 0*/
318 CSCR_Con_status_En = 1<<2, /* Assertion of this bit configures LED1 pin to indicate connection status. def 0*/
319 CSCR_PASS_SCR = 1<<0, /* Bypass Scramble, def 0*/
320 };
321
322 enum Cfg9346Bits {
323 Cfg9346_Lock = 0x00,
324 Cfg9346_Unlock = 0xC0,
325 };
326
327 typedef enum {
328 CH_8139 = 0,
329 CH_8139_K,
330 CH_8139A,
331 CH_8139A_G,
332 CH_8139B,
333 CH_8130,
334 CH_8139C,
335 CH_8100,
336 CH_8100B_8139D,
337 CH_8101,
338 } chip_t;
339
340 enum chip_flags {
341 HasHltClk = (1 << 0),
342 HasLWake = (1 << 1),
343 };
344
345 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
346 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
347 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
348
349 #define RTL8139_PCI_REVID_8139 0x10
350 #define RTL8139_PCI_REVID_8139CPLUS 0x20
351
352 #define RTL8139_PCI_REVID RTL8139_PCI_REVID_8139CPLUS
353
354 /* Size is 64 * 16bit words */
355 #define EEPROM_9346_ADDR_BITS 6
356 #define EEPROM_9346_SIZE (1 << EEPROM_9346_ADDR_BITS)
357 #define EEPROM_9346_ADDR_MASK (EEPROM_9346_SIZE - 1)
358
359 enum Chip9346Operation
360 {
361 Chip9346_op_mask = 0xc0, /* 10 zzzzzz */
362 Chip9346_op_read = 0x80, /* 10 AAAAAA */
363 Chip9346_op_write = 0x40, /* 01 AAAAAA D(15)..D(0) */
364 Chip9346_op_ext_mask = 0xf0, /* 11 zzzzzz */
365 Chip9346_op_write_enable = 0x30, /* 00 11zzzz */
366 Chip9346_op_write_all = 0x10, /* 00 01zzzz */
367 Chip9346_op_write_disable = 0x00, /* 00 00zzzz */
368 };
369
370 enum Chip9346Mode
371 {
372 Chip9346_none = 0,
373 Chip9346_enter_command_mode,
374 Chip9346_read_command,
375 Chip9346_data_read, /* from output register */
376 Chip9346_data_write, /* to input register, then to contents at specified address */
377 Chip9346_data_write_all, /* to input register, then filling contents */
378 };
379
380 typedef struct EEprom9346
381 {
382 uint16_t contents[EEPROM_9346_SIZE];
383 int mode;
384 uint32_t tick;
385 uint8_t address;
386 uint16_t input;
387 uint16_t output;
388
389 uint8_t eecs;
390 uint8_t eesk;
391 uint8_t eedi;
392 uint8_t eedo;
393 } EEprom9346;
394
395 typedef struct RTL8139TallyCounters
396 {
397 /* Tally counters */
398 uint64_t TxOk;
399 uint64_t RxOk;
400 uint64_t TxERR;
401 uint32_t RxERR;
402 uint16_t MissPkt;
403 uint16_t FAE;
404 uint32_t Tx1Col;
405 uint32_t TxMCol;
406 uint64_t RxOkPhy;
407 uint64_t RxOkBrd;
408 uint32_t RxOkMul;
409 uint16_t TxAbt;
410 uint16_t TxUndrn;
411 } RTL8139TallyCounters;
412
413 /* Clears all tally counters */
414 static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters);
415
416 /* Writes tally counters to specified physical memory address */
417 static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr, RTL8139TallyCounters* counters);
418
419 /* Loads values of tally counters from VM state file */
420 static void RTL8139TallyCounters_load(QEMUFile* f, RTL8139TallyCounters *tally_counters);
421
422 /* Saves values of tally counters to VM state file */
423 static void RTL8139TallyCounters_save(QEMUFile* f, RTL8139TallyCounters *tally_counters);
424
425 typedef struct RTL8139State {
426 uint8_t phys[8]; /* mac address */
427 uint8_t mult[8]; /* multicast mask array */
428
429 uint32_t TxStatus[4]; /* TxStatus0 in C mode*/ /* also DTCCR[0] and DTCCR[1] in C+ mode */
430 uint32_t TxAddr[4]; /* TxAddr0 */
431 uint32_t RxBuf; /* Receive buffer */
432 uint32_t RxBufferSize;/* internal variable, receive ring buffer size in C mode */
433 uint32_t RxBufPtr;
434 uint32_t RxBufAddr;
435
436 uint16_t IntrStatus;
437 uint16_t IntrMask;
438
439 uint32_t TxConfig;
440 uint32_t RxConfig;
441 uint32_t RxMissed;
442
443 uint16_t CSCR;
444
445 uint8_t Cfg9346;
446 uint8_t Config0;
447 uint8_t Config1;
448 uint8_t Config3;
449 uint8_t Config4;
450 uint8_t Config5;
451
452 uint8_t clock_enabled;
453 uint8_t bChipCmdState;
454
455 uint16_t MultiIntr;
456
457 uint16_t BasicModeCtrl;
458 uint16_t BasicModeStatus;
459 uint16_t NWayAdvert;
460 uint16_t NWayLPAR;
461 uint16_t NWayExpansion;
462
463 uint16_t CpCmd;
464 uint8_t TxThresh;
465
466 PCIDevice *pci_dev;
467 VLANClientState *vc;
468 uint8_t macaddr[6];
469 int rtl8139_mmio_io_addr;
470
471 /* C ring mode */
472 uint32_t currTxDesc;
473
474 /* C+ mode */
475 uint32_t cplus_enabled;
476
477 uint32_t currCPlusRxDesc;
478 uint32_t currCPlusTxDesc;
479
480 uint32_t RxRingAddrLO;
481 uint32_t RxRingAddrHI;
482
483 EEprom9346 eeprom;
484
485 uint32_t TCTR;
486 uint32_t TimerInt;
487 int64_t TCTR_base;
488
489 /* Tally counters */
490 RTL8139TallyCounters tally_counters;
491
492 /* Non-persistent data */
493 uint8_t *cplus_txbuffer;
494 int cplus_txbuffer_len;
495 int cplus_txbuffer_offset;
496
497 /* PCI interrupt timer */
498 QEMUTimer *timer;
499
500 } RTL8139State;
501
502 static void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command)
503 {
504 DEBUG_PRINT(("RTL8139: eeprom command 0x%02x\n", command));
505
506 switch (command & Chip9346_op_mask)
507 {
508 case Chip9346_op_read:
509 {
510 eeprom->address = command & EEPROM_9346_ADDR_MASK;
511 eeprom->output = eeprom->contents[eeprom->address];
512 eeprom->eedo = 0;
513 eeprom->tick = 0;
514 eeprom->mode = Chip9346_data_read;
515 DEBUG_PRINT(("RTL8139: eeprom read from address 0x%02x data=0x%04x\n",
516 eeprom->address, eeprom->output));
517 }
518 break;
519
520 case Chip9346_op_write:
521 {
522 eeprom->address = command & EEPROM_9346_ADDR_MASK;
523 eeprom->input = 0;
524 eeprom->tick = 0;
525 eeprom->mode = Chip9346_none; /* Chip9346_data_write */
526 DEBUG_PRINT(("RTL8139: eeprom begin write to address 0x%02x\n",
527 eeprom->address));
528 }
529 break;
530 default:
531 eeprom->mode = Chip9346_none;
532 switch (command & Chip9346_op_ext_mask)
533 {
534 case Chip9346_op_write_enable:
535 DEBUG_PRINT(("RTL8139: eeprom write enabled\n"));
536 break;
537 case Chip9346_op_write_all:
538 DEBUG_PRINT(("RTL8139: eeprom begin write all\n"));
539 break;
540 case Chip9346_op_write_disable:
541 DEBUG_PRINT(("RTL8139: eeprom write disabled\n"));
542 break;
543 }
544 break;
545 }
546 }
547
548 static void prom9346_shift_clock(EEprom9346 *eeprom)
549 {
550 int bit = eeprom->eedi?1:0;
551
552 ++ eeprom->tick;
553
554 DEBUG_PRINT(("eeprom: tick %d eedi=%d eedo=%d\n", eeprom->tick, eeprom->eedi, eeprom->eedo));
555
556 switch (eeprom->mode)
557 {
558 case Chip9346_enter_command_mode:
559 if (bit)
560 {
561 eeprom->mode = Chip9346_read_command;
562 eeprom->tick = 0;
563 eeprom->input = 0;
564 DEBUG_PRINT(("eeprom: +++ synchronized, begin command read\n"));
565 }
566 break;
567
568 case Chip9346_read_command:
569 eeprom->input = (eeprom->input << 1) | (bit & 1);
570 if (eeprom->tick == 8)
571 {
572 prom9346_decode_command(eeprom, eeprom->input & 0xff);
573 }
574 break;
575
576 case Chip9346_data_read:
577 eeprom->eedo = (eeprom->output & 0x8000)?1:0;
578 eeprom->output <<= 1;
579 if (eeprom->tick == 16)
580 {
581 #if 1
582 // the FreeBSD drivers (rl and re) don't explicitly toggle
583 // CS between reads (or does setting Cfg9346 to 0 count too?),
584 // so we need to enter wait-for-command state here
585 eeprom->mode = Chip9346_enter_command_mode;
586 eeprom->input = 0;
587 eeprom->tick = 0;
588
589 DEBUG_PRINT(("eeprom: +++ end of read, awaiting next command\n"));
590 #else
591 // original behaviour
592 ++eeprom->address;
593 eeprom->address &= EEPROM_9346_ADDR_MASK;
594 eeprom->output = eeprom->contents[eeprom->address];
595 eeprom->tick = 0;
596
597 DEBUG_PRINT(("eeprom: +++ read next address 0x%02x data=0x%04x\n",
598 eeprom->address, eeprom->output));
599 #endif
600 }
601 break;
602
603 case Chip9346_data_write:
604 eeprom->input = (eeprom->input << 1) | (bit & 1);
605 if (eeprom->tick == 16)
606 {
607 DEBUG_PRINT(("RTL8139: eeprom write to address 0x%02x data=0x%04x\n",
608 eeprom->address, eeprom->input));
609
610 eeprom->contents[eeprom->address] = eeprom->input;
611 eeprom->mode = Chip9346_none; /* waiting for next command after CS cycle */
612 eeprom->tick = 0;
613 eeprom->input = 0;
614 }
615 break;
616
617 case Chip9346_data_write_all:
618 eeprom->input = (eeprom->input << 1) | (bit & 1);
619 if (eeprom->tick == 16)
620 {
621 int i;
622 for (i = 0; i < EEPROM_9346_SIZE; i++)
623 {
624 eeprom->contents[i] = eeprom->input;
625 }
626 DEBUG_PRINT(("RTL8139: eeprom filled with data=0x%04x\n",
627 eeprom->input));
628
629 eeprom->mode = Chip9346_enter_command_mode;
630 eeprom->tick = 0;
631 eeprom->input = 0;
632 }
633 break;
634
635 default:
636 break;
637 }
638 }
639
640 static int prom9346_get_wire(RTL8139State *s)
641 {
642 EEprom9346 *eeprom = &s->eeprom;
643 if (!eeprom->eecs)
644 return 0;
645
646 return eeprom->eedo;
647 }
648
649 /* FIXME: This should be merged into/replaced by eeprom93xx.c. */
650 static void prom9346_set_wire(RTL8139State *s, int eecs, int eesk, int eedi)
651 {
652 EEprom9346 *eeprom = &s->eeprom;
653 uint8_t old_eecs = eeprom->eecs;
654 uint8_t old_eesk = eeprom->eesk;
655
656 eeprom->eecs = eecs;
657 eeprom->eesk = eesk;
658 eeprom->eedi = eedi;
659
660 DEBUG_PRINT(("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n",
661 eeprom->eecs, eeprom->eesk, eeprom->eedi, eeprom->eedo));
662
663 if (!old_eecs && eecs)
664 {
665 /* Synchronize start */
666 eeprom->tick = 0;
667 eeprom->input = 0;
668 eeprom->output = 0;
669 eeprom->mode = Chip9346_enter_command_mode;
670
671 DEBUG_PRINT(("=== eeprom: begin access, enter command mode\n"));
672 }
673
674 if (!eecs)
675 {
676 DEBUG_PRINT(("=== eeprom: end access\n"));
677 return;
678 }
679
680 if (!old_eesk && eesk)
681 {
682 /* SK front rules */
683 prom9346_shift_clock(eeprom);
684 }
685 }
686
687 static void rtl8139_update_irq(RTL8139State *s)
688 {
689 int isr;
690 isr = (s->IntrStatus & s->IntrMask) & 0xffff;
691
692 DEBUG_PRINT(("RTL8139: Set IRQ to %d (%04x %04x)\n",
693 isr ? 1 : 0, s->IntrStatus, s->IntrMask));
694
695 qemu_set_irq(s->pci_dev->irq[0], (isr != 0));
696 }
697
698 #define POLYNOMIAL 0x04c11db6
699
700 /* From FreeBSD */
701 /* XXX: optimize */
702 static int compute_mcast_idx(const uint8_t *ep)
703 {
704 uint32_t crc;
705 int carry, i, j;
706 uint8_t b;
707
708 crc = 0xffffffff;
709 for (i = 0; i < 6; i++) {
710 b = *ep++;
711 for (j = 0; j < 8; j++) {
712 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
713 crc <<= 1;
714 b >>= 1;
715 if (carry)
716 crc = ((crc ^ POLYNOMIAL) | carry);
717 }
718 }
719 return (crc >> 26);
720 }
721
722 static int rtl8139_RxWrap(RTL8139State *s)
723 {
724 /* wrapping enabled; assume 1.5k more buffer space if size < 65536 */
725 return (s->RxConfig & (1 << 7));
726 }
727
728 static int rtl8139_receiver_enabled(RTL8139State *s)
729 {
730 return s->bChipCmdState & CmdRxEnb;
731 }
732
733 static int rtl8139_transmitter_enabled(RTL8139State *s)
734 {
735 return s->bChipCmdState & CmdTxEnb;
736 }
737
738 static int rtl8139_cp_receiver_enabled(RTL8139State *s)
739 {
740 return s->CpCmd & CPlusRxEnb;
741 }
742
743 static int rtl8139_cp_transmitter_enabled(RTL8139State *s)
744 {
745 return s->CpCmd & CPlusTxEnb;
746 }
747
748 static void rtl8139_write_buffer(RTL8139State *s, const void *buf, int size)
749 {
750 if (s->RxBufAddr + size > s->RxBufferSize)
751 {
752 int wrapped = MOD2(s->RxBufAddr + size, s->RxBufferSize);
753
754 /* write packet data */
755 if (wrapped && !(s->RxBufferSize < 65536 && rtl8139_RxWrap(s)))
756 {
757 DEBUG_PRINT((">>> RTL8139: rx packet wrapped in buffer at %d\n", size-wrapped));
758
759 if (size > wrapped)
760 {
761 cpu_physical_memory_write( s->RxBuf + s->RxBufAddr,
762 buf, size-wrapped );
763 }
764
765 /* reset buffer pointer */
766 s->RxBufAddr = 0;
767
768 cpu_physical_memory_write( s->RxBuf + s->RxBufAddr,
769 buf + (size-wrapped), wrapped );
770
771 s->RxBufAddr = wrapped;
772
773 return;
774 }
775 }
776
777 /* non-wrapping path or overwrapping enabled */
778 cpu_physical_memory_write( s->RxBuf + s->RxBufAddr, buf, size );
779
780 s->RxBufAddr += size;
781 }
782
783 #define MIN_BUF_SIZE 60
784 static inline target_phys_addr_t rtl8139_addr64(uint32_t low, uint32_t high)
785 {
786 #if TARGET_PHYS_ADDR_BITS > 32
787 return low | ((target_phys_addr_t)high << 32);
788 #else
789 return low;
790 #endif
791 }
792
793 static int rtl8139_can_receive(void *opaque)
794 {
795 RTL8139State *s = opaque;
796 int avail;
797
798 /* Receive (drop) packets if card is disabled. */
799 if (!s->clock_enabled)
800 return 1;
801 if (!rtl8139_receiver_enabled(s))
802 return 1;
803
804 if (rtl8139_cp_receiver_enabled(s)) {
805 /* ??? Flow control not implemented in c+ mode.
806 This is a hack to work around slirp deficiencies anyway. */
807 return 1;
808 } else {
809 avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr,
810 s->RxBufferSize);
811 return (avail == 0 || avail >= 1514);
812 }
813 }
814
815 static void rtl8139_do_receive(void *opaque, const uint8_t *buf, int size, int do_interrupt)
816 {
817 RTL8139State *s = opaque;
818
819 uint32_t packet_header = 0;
820
821 uint8_t buf1[60];
822 static const uint8_t broadcast_macaddr[6] =
823 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
824
825 DEBUG_PRINT((">>> RTL8139: received len=%d\n", size));
826
827 /* test if board clock is stopped */
828 if (!s->clock_enabled)
829 {
830 DEBUG_PRINT(("RTL8139: stopped ==========================\n"));
831 return;
832 }
833
834 /* first check if receiver is enabled */
835
836 if (!rtl8139_receiver_enabled(s))
837 {
838 DEBUG_PRINT(("RTL8139: receiver disabled ================\n"));
839 return;
840 }
841
842 /* XXX: check this */
843 if (s->RxConfig & AcceptAllPhys) {
844 /* promiscuous: receive all */
845 DEBUG_PRINT((">>> RTL8139: packet received in promiscuous mode\n"));
846
847 } else {
848 if (!memcmp(buf, broadcast_macaddr, 6)) {
849 /* broadcast address */
850 if (!(s->RxConfig & AcceptBroadcast))
851 {
852 DEBUG_PRINT((">>> RTL8139: broadcast packet rejected\n"));
853
854 /* update tally counter */
855 ++s->tally_counters.RxERR;
856
857 return;
858 }
859
860 packet_header |= RxBroadcast;
861
862 DEBUG_PRINT((">>> RTL8139: broadcast packet received\n"));
863
864 /* update tally counter */
865 ++s->tally_counters.RxOkBrd;
866
867 } else if (buf[0] & 0x01) {
868 /* multicast */
869 if (!(s->RxConfig & AcceptMulticast))
870 {
871 DEBUG_PRINT((">>> RTL8139: multicast packet rejected\n"));
872
873 /* update tally counter */
874 ++s->tally_counters.RxERR;
875
876 return;
877 }
878
879 int mcast_idx = compute_mcast_idx(buf);
880
881 if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
882 {
883 DEBUG_PRINT((">>> RTL8139: multicast address mismatch\n"));
884
885 /* update tally counter */
886 ++s->tally_counters.RxERR;
887
888 return;
889 }
890
891 packet_header |= RxMulticast;
892
893 DEBUG_PRINT((">>> RTL8139: multicast packet received\n"));
894
895 /* update tally counter */
896 ++s->tally_counters.RxOkMul;
897
898 } else if (s->phys[0] == buf[0] &&
899 s->phys[1] == buf[1] &&
900 s->phys[2] == buf[2] &&
901 s->phys[3] == buf[3] &&
902 s->phys[4] == buf[4] &&
903 s->phys[5] == buf[5]) {
904 /* match */
905 if (!(s->RxConfig & AcceptMyPhys))
906 {
907 DEBUG_PRINT((">>> RTL8139: rejecting physical address matching packet\n"));
908
909 /* update tally counter */
910 ++s->tally_counters.RxERR;
911
912 return;
913 }
914
915 packet_header |= RxPhysical;
916
917 DEBUG_PRINT((">>> RTL8139: physical address matching packet received\n"));
918
919 /* update tally counter */
920 ++s->tally_counters.RxOkPhy;
921
922 } else {
923
924 DEBUG_PRINT((">>> RTL8139: unknown packet\n"));
925
926 /* update tally counter */
927 ++s->tally_counters.RxERR;
928
929 return;
930 }
931 }
932
933 /* if too small buffer, then expand it */
934 if (size < MIN_BUF_SIZE) {
935 memcpy(buf1, buf, size);
936 memset(buf1 + size, 0, MIN_BUF_SIZE - size);
937 buf = buf1;
938 size = MIN_BUF_SIZE;
939 }
940
941 if (rtl8139_cp_receiver_enabled(s))
942 {
943 DEBUG_PRINT(("RTL8139: in C+ Rx mode ================\n"));
944
945 /* begin C+ receiver mode */
946
947 /* w0 ownership flag */
948 #define CP_RX_OWN (1<<31)
949 /* w0 end of ring flag */
950 #define CP_RX_EOR (1<<30)
951 /* w0 bits 0...12 : buffer size */
952 #define CP_RX_BUFFER_SIZE_MASK ((1<<13) - 1)
953 /* w1 tag available flag */
954 #define CP_RX_TAVA (1<<16)
955 /* w1 bits 0...15 : VLAN tag */
956 #define CP_RX_VLAN_TAG_MASK ((1<<16) - 1)
957 /* w2 low 32bit of Rx buffer ptr */
958 /* w3 high 32bit of Rx buffer ptr */
959
960 int descriptor = s->currCPlusRxDesc;
961 target_phys_addr_t cplus_rx_ring_desc;
962
963 cplus_rx_ring_desc = rtl8139_addr64(s->RxRingAddrLO, s->RxRingAddrHI);
964 cplus_rx_ring_desc += 16 * descriptor;
965
966 DEBUG_PRINT(("RTL8139: +++ C+ mode reading RX descriptor %d from host memory at %08x %08x = %016" PRIx64 "\n",
967 descriptor, s->RxRingAddrHI, s->RxRingAddrLO, (uint64_t)cplus_rx_ring_desc));
968
969 uint32_t val, rxdw0,rxdw1,rxbufLO,rxbufHI;
970
971 cpu_physical_memory_read(cplus_rx_ring_desc, (uint8_t *)&val, 4);
972 rxdw0 = le32_to_cpu(val);
973 cpu_physical_memory_read(cplus_rx_ring_desc+4, (uint8_t *)&val, 4);
974 rxdw1 = le32_to_cpu(val);
975 cpu_physical_memory_read(cplus_rx_ring_desc+8, (uint8_t *)&val, 4);
976 rxbufLO = le32_to_cpu(val);
977 cpu_physical_memory_read(cplus_rx_ring_desc+12, (uint8_t *)&val, 4);
978 rxbufHI = le32_to_cpu(val);
979
980 DEBUG_PRINT(("RTL8139: +++ C+ mode RX descriptor %d %08x %08x %08x %08x\n",
981 descriptor,
982 rxdw0, rxdw1, rxbufLO, rxbufHI));
983
984 if (!(rxdw0 & CP_RX_OWN))
985 {
986 DEBUG_PRINT(("RTL8139: C+ Rx mode : descriptor %d is owned by host\n", descriptor));
987
988 s->IntrStatus |= RxOverflow;
989 ++s->RxMissed;
990
991 /* update tally counter */
992 ++s->tally_counters.RxERR;
993 ++s->tally_counters.MissPkt;
994
995 rtl8139_update_irq(s);
996 return;
997 }
998
999 uint32_t rx_space = rxdw0 & CP_RX_BUFFER_SIZE_MASK;
1000
1001 /* TODO: scatter the packet over available receive ring descriptors space */
1002
1003 if (size+4 > rx_space)
1004 {
1005 DEBUG_PRINT(("RTL8139: C+ Rx mode : descriptor %d size %d received %d + 4\n",
1006 descriptor, rx_space, size));
1007
1008 s->IntrStatus |= RxOverflow;
1009 ++s->RxMissed;
1010
1011 /* update tally counter */
1012 ++s->tally_counters.RxERR;
1013 ++s->tally_counters.MissPkt;
1014
1015 rtl8139_update_irq(s);
1016 return;
1017 }
1018
1019 target_phys_addr_t rx_addr = rtl8139_addr64(rxbufLO, rxbufHI);
1020
1021 /* receive/copy to target memory */
1022 cpu_physical_memory_write( rx_addr, buf, size );
1023
1024 if (s->CpCmd & CPlusRxChkSum)
1025 {
1026 /* do some packet checksumming */
1027 }
1028
1029 /* write checksum */
1030 #if defined (RTL8139_CALCULATE_RXCRC)
1031 val = cpu_to_le32(crc32(0, buf, size));
1032 #else
1033 val = 0;
1034 #endif
1035 cpu_physical_memory_write( rx_addr+size, (uint8_t *)&val, 4);
1036
1037 /* first segment of received packet flag */
1038 #define CP_RX_STATUS_FS (1<<29)
1039 /* last segment of received packet flag */
1040 #define CP_RX_STATUS_LS (1<<28)
1041 /* multicast packet flag */
1042 #define CP_RX_STATUS_MAR (1<<26)
1043 /* physical-matching packet flag */
1044 #define CP_RX_STATUS_PAM (1<<25)
1045 /* broadcast packet flag */
1046 #define CP_RX_STATUS_BAR (1<<24)
1047 /* runt packet flag */
1048 #define CP_RX_STATUS_RUNT (1<<19)
1049 /* crc error flag */
1050 #define CP_RX_STATUS_CRC (1<<18)
1051 /* IP checksum error flag */
1052 #define CP_RX_STATUS_IPF (1<<15)
1053 /* UDP checksum error flag */
1054 #define CP_RX_STATUS_UDPF (1<<14)
1055 /* TCP checksum error flag */
1056 #define CP_RX_STATUS_TCPF (1<<13)
1057
1058 /* transfer ownership to target */
1059 rxdw0 &= ~CP_RX_OWN;
1060
1061 /* set first segment bit */
1062 rxdw0 |= CP_RX_STATUS_FS;
1063
1064 /* set last segment bit */
1065 rxdw0 |= CP_RX_STATUS_LS;
1066
1067 /* set received packet type flags */
1068 if (packet_header & RxBroadcast)
1069 rxdw0 |= CP_RX_STATUS_BAR;
1070 if (packet_header & RxMulticast)
1071 rxdw0 |= CP_RX_STATUS_MAR;
1072 if (packet_header & RxPhysical)
1073 rxdw0 |= CP_RX_STATUS_PAM;
1074
1075 /* set received size */
1076 rxdw0 &= ~CP_RX_BUFFER_SIZE_MASK;
1077 rxdw0 |= (size+4);
1078
1079 /* reset VLAN tag flag */
1080 rxdw1 &= ~CP_RX_TAVA;
1081
1082 /* update ring data */
1083 val = cpu_to_le32(rxdw0);
1084 cpu_physical_memory_write(cplus_rx_ring_desc, (uint8_t *)&val, 4);
1085 val = cpu_to_le32(rxdw1);
1086 cpu_physical_memory_write(cplus_rx_ring_desc+4, (uint8_t *)&val, 4);
1087
1088 /* update tally counter */
1089 ++s->tally_counters.RxOk;
1090
1091 /* seek to next Rx descriptor */
1092 if (rxdw0 & CP_RX_EOR)
1093 {
1094 s->currCPlusRxDesc = 0;
1095 }
1096 else
1097 {
1098 ++s->currCPlusRxDesc;
1099 }
1100
1101 DEBUG_PRINT(("RTL8139: done C+ Rx mode ----------------\n"));
1102
1103 }
1104 else
1105 {
1106 DEBUG_PRINT(("RTL8139: in ring Rx mode ================\n"));
1107
1108 /* begin ring receiver mode */
1109 int avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, s->RxBufferSize);
1110
1111 /* if receiver buffer is empty then avail == 0 */
1112
1113 if (avail != 0 && size + 8 >= avail)
1114 {
1115 DEBUG_PRINT(("rx overflow: rx buffer length %d head 0x%04x read 0x%04x === available 0x%04x need 0x%04x\n",
1116 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr, avail, size + 8));
1117
1118 s->IntrStatus |= RxOverflow;
1119 ++s->RxMissed;
1120 rtl8139_update_irq(s);
1121 return;
1122 }
1123
1124 packet_header |= RxStatusOK;
1125
1126 packet_header |= (((size+4) << 16) & 0xffff0000);
1127
1128 /* write header */
1129 uint32_t val = cpu_to_le32(packet_header);
1130
1131 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1132
1133 rtl8139_write_buffer(s, buf, size);
1134
1135 /* write checksum */
1136 #if defined (RTL8139_CALCULATE_RXCRC)
1137 val = cpu_to_le32(crc32(0, buf, size));
1138 #else
1139 val = 0;
1140 #endif
1141
1142 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1143
1144 /* correct buffer write pointer */
1145 s->RxBufAddr = MOD2((s->RxBufAddr + 3) & ~0x3, s->RxBufferSize);
1146
1147 /* now we can signal we have received something */
1148
1149 DEBUG_PRINT((" received: rx buffer length %d head 0x%04x read 0x%04x\n",
1150 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr));
1151 }
1152
1153 s->IntrStatus |= RxOK;
1154
1155 if (do_interrupt)
1156 {
1157 rtl8139_update_irq(s);
1158 }
1159 }
1160
1161 static void rtl8139_receive(void *opaque, const uint8_t *buf, int size)
1162 {
1163 rtl8139_do_receive(opaque, buf, size, 1);
1164 }
1165
1166 static void rtl8139_reset_rxring(RTL8139State *s, uint32_t bufferSize)
1167 {
1168 s->RxBufferSize = bufferSize;
1169 s->RxBufPtr = 0;
1170 s->RxBufAddr = 0;
1171 }
1172
1173 static void rtl8139_reset(void *opaque)
1174 {
1175 RTL8139State *s = opaque;
1176 int i;
1177
1178 /* restore MAC address */
1179 memcpy(s->phys, s->macaddr, 6);
1180
1181 /* reset interrupt mask */
1182 s->IntrStatus = 0;
1183 s->IntrMask = 0;
1184
1185 rtl8139_update_irq(s);
1186
1187 /* prepare eeprom */
1188 s->eeprom.contents[0] = 0x8129;
1189 #if 1
1190 // PCI vendor and device ID should be mirrored here
1191 s->eeprom.contents[1] = PCI_VENDOR_ID_REALTEK;
1192 s->eeprom.contents[2] = PCI_DEVICE_ID_REALTEK_8139;
1193 #endif
1194
1195 s->eeprom.contents[7] = s->macaddr[0] | s->macaddr[1] << 8;
1196 s->eeprom.contents[8] = s->macaddr[2] | s->macaddr[3] << 8;
1197 s->eeprom.contents[9] = s->macaddr[4] | s->macaddr[5] << 8;
1198
1199 /* mark all status registers as owned by host */
1200 for (i = 0; i < 4; ++i)
1201 {
1202 s->TxStatus[i] = TxHostOwns;
1203 }
1204
1205 s->currTxDesc = 0;
1206 s->currCPlusRxDesc = 0;
1207 s->currCPlusTxDesc = 0;
1208
1209 s->RxRingAddrLO = 0;
1210 s->RxRingAddrHI = 0;
1211
1212 s->RxBuf = 0;
1213
1214 rtl8139_reset_rxring(s, 8192);
1215
1216 /* ACK the reset */
1217 s->TxConfig = 0;
1218
1219 #if 0
1220 // s->TxConfig |= HW_REVID(1, 0, 0, 0, 0, 0, 0); // RTL-8139 HasHltClk
1221 s->clock_enabled = 0;
1222 #else
1223 s->TxConfig |= HW_REVID(1, 1, 1, 0, 1, 1, 0); // RTL-8139C+ HasLWake
1224 s->clock_enabled = 1;
1225 #endif
1226
1227 s->bChipCmdState = CmdReset; /* RxBufEmpty bit is calculated on read from ChipCmd */;
1228
1229 /* set initial state data */
1230 s->Config0 = 0x0; /* No boot ROM */
1231 s->Config1 = 0xC; /* IO mapped and MEM mapped registers available */
1232 s->Config3 = 0x1; /* fast back-to-back compatible */
1233 s->Config5 = 0x0;
1234
1235 s->CSCR = CSCR_F_LINK_100 | CSCR_HEART_BIT | CSCR_LD;
1236
1237 s->CpCmd = 0x0; /* reset C+ mode */
1238 s->cplus_enabled = 0;
1239
1240
1241 // s->BasicModeCtrl = 0x3100; // 100Mbps, full duplex, autonegotiation
1242 // s->BasicModeCtrl = 0x2100; // 100Mbps, full duplex
1243 s->BasicModeCtrl = 0x1000; // autonegotiation
1244
1245 s->BasicModeStatus = 0x7809;
1246 //s->BasicModeStatus |= 0x0040; /* UTP medium */
1247 s->BasicModeStatus |= 0x0020; /* autonegotiation completed */
1248 s->BasicModeStatus |= 0x0004; /* link is up */
1249
1250 s->NWayAdvert = 0x05e1; /* all modes, full duplex */
1251 s->NWayLPAR = 0x05e1; /* all modes, full duplex */
1252 s->NWayExpansion = 0x0001; /* autonegotiation supported */
1253
1254 /* also reset timer and disable timer interrupt */
1255 s->TCTR = 0;
1256 s->TimerInt = 0;
1257 s->TCTR_base = 0;
1258
1259 /* reset tally counters */
1260 RTL8139TallyCounters_clear(&s->tally_counters);
1261 }
1262
1263 static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters)
1264 {
1265 counters->TxOk = 0;
1266 counters->RxOk = 0;
1267 counters->TxERR = 0;
1268 counters->RxERR = 0;
1269 counters->MissPkt = 0;
1270 counters->FAE = 0;
1271 counters->Tx1Col = 0;
1272 counters->TxMCol = 0;
1273 counters->RxOkPhy = 0;
1274 counters->RxOkBrd = 0;
1275 counters->RxOkMul = 0;
1276 counters->TxAbt = 0;
1277 counters->TxUndrn = 0;
1278 }
1279
1280 static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr, RTL8139TallyCounters* tally_counters)
1281 {
1282 uint16_t val16;
1283 uint32_t val32;
1284 uint64_t val64;
1285
1286 val64 = cpu_to_le64(tally_counters->TxOk);
1287 cpu_physical_memory_write(tc_addr + 0, (uint8_t *)&val64, 8);
1288
1289 val64 = cpu_to_le64(tally_counters->RxOk);
1290 cpu_physical_memory_write(tc_addr + 8, (uint8_t *)&val64, 8);
1291
1292 val64 = cpu_to_le64(tally_counters->TxERR);
1293 cpu_physical_memory_write(tc_addr + 16, (uint8_t *)&val64, 8);
1294
1295 val32 = cpu_to_le32(tally_counters->RxERR);
1296 cpu_physical_memory_write(tc_addr + 24, (uint8_t *)&val32, 4);
1297
1298 val16 = cpu_to_le16(tally_counters->MissPkt);
1299 cpu_physical_memory_write(tc_addr + 28, (uint8_t *)&val16, 2);
1300
1301 val16 = cpu_to_le16(tally_counters->FAE);
1302 cpu_physical_memory_write(tc_addr + 30, (uint8_t *)&val16, 2);
1303
1304 val32 = cpu_to_le32(tally_counters->Tx1Col);
1305 cpu_physical_memory_write(tc_addr + 32, (uint8_t *)&val32, 4);
1306
1307 val32 = cpu_to_le32(tally_counters->TxMCol);
1308 cpu_physical_memory_write(tc_addr + 36, (uint8_t *)&val32, 4);
1309
1310 val64 = cpu_to_le64(tally_counters->RxOkPhy);
1311 cpu_physical_memory_write(tc_addr + 40, (uint8_t *)&val64, 8);
1312
1313 val64 = cpu_to_le64(tally_counters->RxOkBrd);
1314 cpu_physical_memory_write(tc_addr + 48, (uint8_t *)&val64, 8);
1315
1316 val32 = cpu_to_le32(tally_counters->RxOkMul);
1317 cpu_physical_memory_write(tc_addr + 56, (uint8_t *)&val32, 4);
1318
1319 val16 = cpu_to_le16(tally_counters->TxAbt);
1320 cpu_physical_memory_write(tc_addr + 60, (uint8_t *)&val16, 2);
1321
1322 val16 = cpu_to_le16(tally_counters->TxUndrn);
1323 cpu_physical_memory_write(tc_addr + 62, (uint8_t *)&val16, 2);
1324 }
1325
1326 /* Loads values of tally counters from VM state file */
1327 static void RTL8139TallyCounters_load(QEMUFile* f, RTL8139TallyCounters *tally_counters)
1328 {
1329 qemu_get_be64s(f, &tally_counters->TxOk);
1330 qemu_get_be64s(f, &tally_counters->RxOk);
1331 qemu_get_be64s(f, &tally_counters->TxERR);
1332 qemu_get_be32s(f, &tally_counters->RxERR);
1333 qemu_get_be16s(f, &tally_counters->MissPkt);
1334 qemu_get_be16s(f, &tally_counters->FAE);
1335 qemu_get_be32s(f, &tally_counters->Tx1Col);
1336 qemu_get_be32s(f, &tally_counters->TxMCol);
1337 qemu_get_be64s(f, &tally_counters->RxOkPhy);
1338 qemu_get_be64s(f, &tally_counters->RxOkBrd);
1339 qemu_get_be32s(f, &tally_counters->RxOkMul);
1340 qemu_get_be16s(f, &tally_counters->TxAbt);
1341 qemu_get_be16s(f, &tally_counters->TxUndrn);
1342 }
1343
1344 /* Saves values of tally counters to VM state file */
1345 static void RTL8139TallyCounters_save(QEMUFile* f, RTL8139TallyCounters *tally_counters)
1346 {
1347 qemu_put_be64s(f, &tally_counters->TxOk);
1348 qemu_put_be64s(f, &tally_counters->RxOk);
1349 qemu_put_be64s(f, &tally_counters->TxERR);
1350 qemu_put_be32s(f, &tally_counters->RxERR);
1351 qemu_put_be16s(f, &tally_counters->MissPkt);
1352 qemu_put_be16s(f, &tally_counters->FAE);
1353 qemu_put_be32s(f, &tally_counters->Tx1Col);
1354 qemu_put_be32s(f, &tally_counters->TxMCol);
1355 qemu_put_be64s(f, &tally_counters->RxOkPhy);
1356 qemu_put_be64s(f, &tally_counters->RxOkBrd);
1357 qemu_put_be32s(f, &tally_counters->RxOkMul);
1358 qemu_put_be16s(f, &tally_counters->TxAbt);
1359 qemu_put_be16s(f, &tally_counters->TxUndrn);
1360 }
1361
1362 static void rtl8139_ChipCmd_write(RTL8139State *s, uint32_t val)
1363 {
1364 val &= 0xff;
1365
1366 DEBUG_PRINT(("RTL8139: ChipCmd write val=0x%08x\n", val));
1367
1368 if (val & CmdReset)
1369 {
1370 DEBUG_PRINT(("RTL8139: ChipCmd reset\n"));
1371 rtl8139_reset(s);
1372 }
1373 if (val & CmdRxEnb)
1374 {
1375 DEBUG_PRINT(("RTL8139: ChipCmd enable receiver\n"));
1376
1377 s->currCPlusRxDesc = 0;
1378 }
1379 if (val & CmdTxEnb)
1380 {
1381 DEBUG_PRINT(("RTL8139: ChipCmd enable transmitter\n"));
1382
1383 s->currCPlusTxDesc = 0;
1384 }
1385
1386 /* mask unwriteable bits */
1387 val = SET_MASKED(val, 0xe3, s->bChipCmdState);
1388
1389 /* Deassert reset pin before next read */
1390 val &= ~CmdReset;
1391
1392 s->bChipCmdState = val;
1393 }
1394
1395 static int rtl8139_RxBufferEmpty(RTL8139State *s)
1396 {
1397 int unread = MOD2(s->RxBufferSize + s->RxBufAddr - s->RxBufPtr, s->RxBufferSize);
1398
1399 if (unread != 0)
1400 {
1401 DEBUG_PRINT(("RTL8139: receiver buffer data available 0x%04x\n", unread));
1402 return 0;
1403 }
1404
1405 DEBUG_PRINT(("RTL8139: receiver buffer is empty\n"));
1406
1407 return 1;
1408 }
1409
1410 static uint32_t rtl8139_ChipCmd_read(RTL8139State *s)
1411 {
1412 uint32_t ret = s->bChipCmdState;
1413
1414 if (rtl8139_RxBufferEmpty(s))
1415 ret |= RxBufEmpty;
1416
1417 DEBUG_PRINT(("RTL8139: ChipCmd read val=0x%04x\n", ret));
1418
1419 return ret;
1420 }
1421
1422 static void rtl8139_CpCmd_write(RTL8139State *s, uint32_t val)
1423 {
1424 val &= 0xffff;
1425
1426 DEBUG_PRINT(("RTL8139C+ command register write(w) val=0x%04x\n", val));
1427
1428 s->cplus_enabled = 1;
1429
1430 /* mask unwriteable bits */
1431 val = SET_MASKED(val, 0xff84, s->CpCmd);
1432
1433 s->CpCmd = val;
1434 }
1435
1436 static uint32_t rtl8139_CpCmd_read(RTL8139State *s)
1437 {
1438 uint32_t ret = s->CpCmd;
1439
1440 DEBUG_PRINT(("RTL8139C+ command register read(w) val=0x%04x\n", ret));
1441
1442 return ret;
1443 }
1444
1445 static void rtl8139_IntrMitigate_write(RTL8139State *s, uint32_t val)
1446 {
1447 DEBUG_PRINT(("RTL8139C+ IntrMitigate register write(w) val=0x%04x\n", val));
1448 }
1449
1450 static uint32_t rtl8139_IntrMitigate_read(RTL8139State *s)
1451 {
1452 uint32_t ret = 0;
1453
1454 DEBUG_PRINT(("RTL8139C+ IntrMitigate register read(w) val=0x%04x\n", ret));
1455
1456 return ret;
1457 }
1458
1459 static int rtl8139_config_writeable(RTL8139State *s)
1460 {
1461 if (s->Cfg9346 & Cfg9346_Unlock)
1462 {
1463 return 1;
1464 }
1465
1466 DEBUG_PRINT(("RTL8139: Configuration registers are write-protected\n"));
1467
1468 return 0;
1469 }
1470
1471 static void rtl8139_BasicModeCtrl_write(RTL8139State *s, uint32_t val)
1472 {
1473 val &= 0xffff;
1474
1475 DEBUG_PRINT(("RTL8139: BasicModeCtrl register write(w) val=0x%04x\n", val));
1476
1477 /* mask unwriteable bits */
1478 uint32_t mask = 0x4cff;
1479
1480 if (1 || !rtl8139_config_writeable(s))
1481 {
1482 /* Speed setting and autonegotiation enable bits are read-only */
1483 mask |= 0x3000;
1484 /* Duplex mode setting is read-only */
1485 mask |= 0x0100;
1486 }
1487
1488 val = SET_MASKED(val, mask, s->BasicModeCtrl);
1489
1490 s->BasicModeCtrl = val;
1491 }
1492
1493 static uint32_t rtl8139_BasicModeCtrl_read(RTL8139State *s)
1494 {
1495 uint32_t ret = s->BasicModeCtrl;
1496
1497 DEBUG_PRINT(("RTL8139: BasicModeCtrl register read(w) val=0x%04x\n", ret));
1498
1499 return ret;
1500 }
1501
1502 static void rtl8139_BasicModeStatus_write(RTL8139State *s, uint32_t val)
1503 {
1504 val &= 0xffff;
1505
1506 DEBUG_PRINT(("RTL8139: BasicModeStatus register write(w) val=0x%04x\n", val));
1507
1508 /* mask unwriteable bits */
1509 val = SET_MASKED(val, 0xff3f, s->BasicModeStatus);
1510
1511 s->BasicModeStatus = val;
1512 }
1513
1514 static uint32_t rtl8139_BasicModeStatus_read(RTL8139State *s)
1515 {
1516 uint32_t ret = s->BasicModeStatus;
1517
1518 DEBUG_PRINT(("RTL8139: BasicModeStatus register read(w) val=0x%04x\n", ret));
1519
1520 return ret;
1521 }
1522
1523 static void rtl8139_Cfg9346_write(RTL8139State *s, uint32_t val)
1524 {
1525 val &= 0xff;
1526
1527 DEBUG_PRINT(("RTL8139: Cfg9346 write val=0x%02x\n", val));
1528
1529 /* mask unwriteable bits */
1530 val = SET_MASKED(val, 0x31, s->Cfg9346);
1531
1532 uint32_t opmode = val & 0xc0;
1533 uint32_t eeprom_val = val & 0xf;
1534
1535 if (opmode == 0x80) {
1536 /* eeprom access */
1537 int eecs = (eeprom_val & 0x08)?1:0;
1538 int eesk = (eeprom_val & 0x04)?1:0;
1539 int eedi = (eeprom_val & 0x02)?1:0;
1540 prom9346_set_wire(s, eecs, eesk, eedi);
1541 } else if (opmode == 0x40) {
1542 /* Reset. */
1543 val = 0;
1544 rtl8139_reset(s);
1545 }
1546
1547 s->Cfg9346 = val;
1548 }
1549
1550 static uint32_t rtl8139_Cfg9346_read(RTL8139State *s)
1551 {
1552 uint32_t ret = s->Cfg9346;
1553
1554 uint32_t opmode = ret & 0xc0;
1555
1556 if (opmode == 0x80)
1557 {
1558 /* eeprom access */
1559 int eedo = prom9346_get_wire(s);
1560 if (eedo)
1561 {
1562 ret |= 0x01;
1563 }
1564 else
1565 {
1566 ret &= ~0x01;
1567 }
1568 }
1569
1570 DEBUG_PRINT(("RTL8139: Cfg9346 read val=0x%02x\n", ret));
1571
1572 return ret;
1573 }
1574
1575 static void rtl8139_Config0_write(RTL8139State *s, uint32_t val)
1576 {
1577 val &= 0xff;
1578
1579 DEBUG_PRINT(("RTL8139: Config0 write val=0x%02x\n", val));
1580
1581 if (!rtl8139_config_writeable(s))
1582 return;
1583
1584 /* mask unwriteable bits */
1585 val = SET_MASKED(val, 0xf8, s->Config0);
1586
1587 s->Config0 = val;
1588 }
1589
1590 static uint32_t rtl8139_Config0_read(RTL8139State *s)
1591 {
1592 uint32_t ret = s->Config0;
1593
1594 DEBUG_PRINT(("RTL8139: Config0 read val=0x%02x\n", ret));
1595
1596 return ret;
1597 }
1598
1599 static void rtl8139_Config1_write(RTL8139State *s, uint32_t val)
1600 {
1601 val &= 0xff;
1602
1603 DEBUG_PRINT(("RTL8139: Config1 write val=0x%02x\n", val));
1604
1605 if (!rtl8139_config_writeable(s))
1606 return;
1607
1608 /* mask unwriteable bits */
1609 val = SET_MASKED(val, 0xC, s->Config1);
1610
1611 s->Config1 = val;
1612 }
1613
1614 static uint32_t rtl8139_Config1_read(RTL8139State *s)
1615 {
1616 uint32_t ret = s->Config1;
1617
1618 DEBUG_PRINT(("RTL8139: Config1 read val=0x%02x\n", ret));
1619
1620 return ret;
1621 }
1622
1623 static void rtl8139_Config3_write(RTL8139State *s, uint32_t val)
1624 {
1625 val &= 0xff;
1626
1627 DEBUG_PRINT(("RTL8139: Config3 write val=0x%02x\n", val));
1628
1629 if (!rtl8139_config_writeable(s))
1630 return;
1631
1632 /* mask unwriteable bits */
1633 val = SET_MASKED(val, 0x8F, s->Config3);
1634
1635 s->Config3 = val;
1636 }
1637
1638 static uint32_t rtl8139_Config3_read(RTL8139State *s)
1639 {
1640 uint32_t ret = s->Config3;
1641
1642 DEBUG_PRINT(("RTL8139: Config3 read val=0x%02x\n", ret));
1643
1644 return ret;
1645 }
1646
1647 static void rtl8139_Config4_write(RTL8139State *s, uint32_t val)
1648 {
1649 val &= 0xff;
1650
1651 DEBUG_PRINT(("RTL8139: Config4 write val=0x%02x\n", val));
1652
1653 if (!rtl8139_config_writeable(s))
1654 return;
1655
1656 /* mask unwriteable bits */
1657 val = SET_MASKED(val, 0x0a, s->Config4);
1658
1659 s->Config4 = val;
1660 }
1661
1662 static uint32_t rtl8139_Config4_read(RTL8139State *s)
1663 {
1664 uint32_t ret = s->Config4;
1665
1666 DEBUG_PRINT(("RTL8139: Config4 read val=0x%02x\n", ret));
1667
1668 return ret;
1669 }
1670
1671 static void rtl8139_Config5_write(RTL8139State *s, uint32_t val)
1672 {
1673 val &= 0xff;
1674
1675 DEBUG_PRINT(("RTL8139: Config5 write val=0x%02x\n", val));
1676
1677 /* mask unwriteable bits */
1678 val = SET_MASKED(val, 0x80, s->Config5);
1679
1680 s->Config5 = val;
1681 }
1682
1683 static uint32_t rtl8139_Config5_read(RTL8139State *s)
1684 {
1685 uint32_t ret = s->Config5;
1686
1687 DEBUG_PRINT(("RTL8139: Config5 read val=0x%02x\n", ret));
1688
1689 return ret;
1690 }
1691
1692 static void rtl8139_TxConfig_write(RTL8139State *s, uint32_t val)
1693 {
1694 if (!rtl8139_transmitter_enabled(s))
1695 {
1696 DEBUG_PRINT(("RTL8139: transmitter disabled; no TxConfig write val=0x%08x\n", val));
1697 return;
1698 }
1699
1700 DEBUG_PRINT(("RTL8139: TxConfig write val=0x%08x\n", val));
1701
1702 val = SET_MASKED(val, TxVersionMask | 0x8070f80f, s->TxConfig);
1703
1704 s->TxConfig = val;
1705 }
1706
1707 static void rtl8139_TxConfig_writeb(RTL8139State *s, uint32_t val)
1708 {
1709 DEBUG_PRINT(("RTL8139C TxConfig via write(b) val=0x%02x\n", val));
1710
1711 uint32_t tc = s->TxConfig;
1712 tc &= 0xFFFFFF00;
1713 tc |= (val & 0x000000FF);
1714 rtl8139_TxConfig_write(s, tc);
1715 }
1716
1717 static uint32_t rtl8139_TxConfig_read(RTL8139State *s)
1718 {
1719 uint32_t ret = s->TxConfig;
1720
1721 DEBUG_PRINT(("RTL8139: TxConfig read val=0x%04x\n", ret));
1722
1723 return ret;
1724 }
1725
1726 static void rtl8139_RxConfig_write(RTL8139State *s, uint32_t val)
1727 {
1728 DEBUG_PRINT(("RTL8139: RxConfig write val=0x%08x\n", val));
1729
1730 /* mask unwriteable bits */
1731 val = SET_MASKED(val, 0xf0fc0040, s->RxConfig);
1732
1733 s->RxConfig = val;
1734
1735 /* reset buffer size and read/write pointers */
1736 rtl8139_reset_rxring(s, 8192 << ((s->RxConfig >> 11) & 0x3));
1737
1738 DEBUG_PRINT(("RTL8139: RxConfig write reset buffer size to %d\n", s->RxBufferSize));
1739 }
1740
1741 static uint32_t rtl8139_RxConfig_read(RTL8139State *s)
1742 {
1743 uint32_t ret = s->RxConfig;
1744
1745 DEBUG_PRINT(("RTL8139: RxConfig read val=0x%08x\n", ret));
1746
1747 return ret;
1748 }
1749
1750 static void rtl8139_transfer_frame(RTL8139State *s, const uint8_t *buf, int size, int do_interrupt)
1751 {
1752 if (!size)
1753 {
1754 DEBUG_PRINT(("RTL8139: +++ empty ethernet frame\n"));
1755 return;
1756 }
1757
1758 if (TxLoopBack == (s->TxConfig & TxLoopBack))
1759 {
1760 DEBUG_PRINT(("RTL8139: +++ transmit loopback mode\n"));
1761 rtl8139_do_receive(s, buf, size, do_interrupt);
1762 }
1763 else
1764 {
1765 qemu_send_packet(s->vc, buf, size);
1766 }
1767 }
1768
1769 static int rtl8139_transmit_one(RTL8139State *s, int descriptor)
1770 {
1771 if (!rtl8139_transmitter_enabled(s))
1772 {
1773 DEBUG_PRINT(("RTL8139: +++ cannot transmit from descriptor %d: transmitter disabled\n",
1774 descriptor));
1775 return 0;
1776 }
1777
1778 if (s->TxStatus[descriptor] & TxHostOwns)
1779 {
1780 DEBUG_PRINT(("RTL8139: +++ cannot transmit from descriptor %d: owned by host (%08x)\n",
1781 descriptor, s->TxStatus[descriptor]));
1782 return 0;
1783 }
1784
1785 DEBUG_PRINT(("RTL8139: +++ transmitting from descriptor %d\n", descriptor));
1786
1787 int txsize = s->TxStatus[descriptor] & 0x1fff;
1788 uint8_t txbuffer[0x2000];
1789
1790 DEBUG_PRINT(("RTL8139: +++ transmit reading %d bytes from host memory at 0x%08x\n",
1791 txsize, s->TxAddr[descriptor]));
1792
1793 cpu_physical_memory_read(s->TxAddr[descriptor], txbuffer, txsize);
1794
1795 /* Mark descriptor as transferred */
1796 s->TxStatus[descriptor] |= TxHostOwns;
1797 s->TxStatus[descriptor] |= TxStatOK;
1798
1799 rtl8139_transfer_frame(s, txbuffer, txsize, 0);
1800
1801 DEBUG_PRINT(("RTL8139: +++ transmitted %d bytes from descriptor %d\n", txsize, descriptor));
1802
1803 /* update interrupt */
1804 s->IntrStatus |= TxOK;
1805 rtl8139_update_irq(s);
1806
1807 return 1;
1808 }
1809
1810 /* structures and macros for task offloading */
1811 typedef struct ip_header
1812 {
1813 uint8_t ip_ver_len; /* version and header length */
1814 uint8_t ip_tos; /* type of service */
1815 uint16_t ip_len; /* total length */
1816 uint16_t ip_id; /* identification */
1817 uint16_t ip_off; /* fragment offset field */
1818 uint8_t ip_ttl; /* time to live */
1819 uint8_t ip_p; /* protocol */
1820 uint16_t ip_sum; /* checksum */
1821 uint32_t ip_src,ip_dst; /* source and dest address */
1822 } ip_header;
1823
1824 #define IP_HEADER_VERSION_4 4
1825 #define IP_HEADER_VERSION(ip) ((ip->ip_ver_len >> 4)&0xf)
1826 #define IP_HEADER_LENGTH(ip) (((ip->ip_ver_len)&0xf) << 2)
1827
1828 typedef struct tcp_header
1829 {
1830 uint16_t th_sport; /* source port */
1831 uint16_t th_dport; /* destination port */
1832 uint32_t th_seq; /* sequence number */
1833 uint32_t th_ack; /* acknowledgement number */
1834 uint16_t th_offset_flags; /* data offset, reserved 6 bits, TCP protocol flags */
1835 uint16_t th_win; /* window */
1836 uint16_t th_sum; /* checksum */
1837 uint16_t th_urp; /* urgent pointer */
1838 } tcp_header;
1839
1840 typedef struct udp_header
1841 {
1842 uint16_t uh_sport; /* source port */
1843 uint16_t uh_dport; /* destination port */
1844 uint16_t uh_ulen; /* udp length */
1845 uint16_t uh_sum; /* udp checksum */
1846 } udp_header;
1847
1848 typedef struct ip_pseudo_header
1849 {
1850 uint32_t ip_src;
1851 uint32_t ip_dst;
1852 uint8_t zeros;
1853 uint8_t ip_proto;
1854 uint16_t ip_payload;
1855 } ip_pseudo_header;
1856
1857 #define IP_PROTO_TCP 6
1858 #define IP_PROTO_UDP 17
1859
1860 #define TCP_HEADER_DATA_OFFSET(tcp) (((be16_to_cpu(tcp->th_offset_flags) >> 12)&0xf) << 2)
1861 #define TCP_FLAGS_ONLY(flags) ((flags)&0x3f)
1862 #define TCP_HEADER_FLAGS(tcp) TCP_FLAGS_ONLY(be16_to_cpu(tcp->th_offset_flags))
1863
1864 #define TCP_HEADER_CLEAR_FLAGS(tcp, off) ((tcp)->th_offset_flags &= cpu_to_be16(~TCP_FLAGS_ONLY(off)))
1865
1866 #define TCP_FLAG_FIN 0x01
1867 #define TCP_FLAG_PUSH 0x08
1868
1869 /* produces ones' complement sum of data */
1870 static uint16_t ones_complement_sum(uint8_t *data, size_t len)
1871 {
1872 uint32_t result = 0;
1873
1874 for (; len > 1; data+=2, len-=2)
1875 {
1876 result += *(uint16_t*)data;
1877 }
1878
1879 /* add the remainder byte */
1880 if (len)
1881 {
1882 uint8_t odd[2] = {*data, 0};
1883 result += *(uint16_t*)odd;
1884 }
1885
1886 while (result>>16)
1887 result = (result & 0xffff) + (result >> 16);
1888
1889 return result;
1890 }
1891
1892 static uint16_t ip_checksum(void *data, size_t len)
1893 {
1894 return ~ones_complement_sum((uint8_t*)data, len);
1895 }
1896
1897 static int rtl8139_cplus_transmit_one(RTL8139State *s)
1898 {
1899 if (!rtl8139_transmitter_enabled(s))
1900 {
1901 DEBUG_PRINT(("RTL8139: +++ C+ mode: transmitter disabled\n"));
1902 return 0;
1903 }
1904
1905 if (!rtl8139_cp_transmitter_enabled(s))
1906 {
1907 DEBUG_PRINT(("RTL8139: +++ C+ mode: C+ transmitter disabled\n"));
1908 return 0 ;
1909 }
1910
1911 int descriptor = s->currCPlusTxDesc;
1912
1913 target_phys_addr_t cplus_tx_ring_desc =
1914 rtl8139_addr64(s->TxAddr[0], s->TxAddr[1]);
1915
1916 /* Normal priority ring */
1917 cplus_tx_ring_desc += 16 * descriptor;
1918
1919 DEBUG_PRINT(("RTL8139: +++ C+ mode reading TX descriptor %d from host memory at %08x0x%08x = 0x%8lx\n",
1920 descriptor, s->TxAddr[1], s->TxAddr[0], cplus_tx_ring_desc));
1921
1922 uint32_t val, txdw0,txdw1,txbufLO,txbufHI;
1923
1924 cpu_physical_memory_read(cplus_tx_ring_desc, (uint8_t *)&val, 4);
1925 txdw0 = le32_to_cpu(val);
1926 cpu_physical_memory_read(cplus_tx_ring_desc+4, (uint8_t *)&val, 4);
1927 txdw1 = le32_to_cpu(val);
1928 cpu_physical_memory_read(cplus_tx_ring_desc+8, (uint8_t *)&val, 4);
1929 txbufLO = le32_to_cpu(val);
1930 cpu_physical_memory_read(cplus_tx_ring_desc+12, (uint8_t *)&val, 4);
1931 txbufHI = le32_to_cpu(val);
1932
1933 DEBUG_PRINT(("RTL8139: +++ C+ mode TX descriptor %d %08x %08x %08x %08x\n",
1934 descriptor,
1935 txdw0, txdw1, txbufLO, txbufHI));
1936
1937 /* w0 ownership flag */
1938 #define CP_TX_OWN (1<<31)
1939 /* w0 end of ring flag */
1940 #define CP_TX_EOR (1<<30)
1941 /* first segment of received packet flag */
1942 #define CP_TX_FS (1<<29)
1943 /* last segment of received packet flag */
1944 #define CP_TX_LS (1<<28)
1945 /* large send packet flag */
1946 #define CP_TX_LGSEN (1<<27)
1947 /* large send MSS mask, bits 16...25 */
1948 #define CP_TC_LGSEN_MSS_MASK ((1 << 12) - 1)
1949
1950 /* IP checksum offload flag */
1951 #define CP_TX_IPCS (1<<18)
1952 /* UDP checksum offload flag */
1953 #define CP_TX_UDPCS (1<<17)
1954 /* TCP checksum offload flag */
1955 #define CP_TX_TCPCS (1<<16)
1956
1957 /* w0 bits 0...15 : buffer size */
1958 #define CP_TX_BUFFER_SIZE (1<<16)
1959 #define CP_TX_BUFFER_SIZE_MASK (CP_TX_BUFFER_SIZE - 1)
1960 /* w1 tag available flag */
1961 #define CP_RX_TAGC (1<<17)
1962 /* w1 bits 0...15 : VLAN tag */
1963 #define CP_TX_VLAN_TAG_MASK ((1<<16) - 1)
1964 /* w2 low 32bit of Rx buffer ptr */
1965 /* w3 high 32bit of Rx buffer ptr */
1966
1967 /* set after transmission */
1968 /* FIFO underrun flag */
1969 #define CP_TX_STATUS_UNF (1<<25)
1970 /* transmit error summary flag, valid if set any of three below */
1971 #define CP_TX_STATUS_TES (1<<23)
1972 /* out-of-window collision flag */
1973 #define CP_TX_STATUS_OWC (1<<22)
1974 /* link failure flag */
1975 #define CP_TX_STATUS_LNKF (1<<21)
1976 /* excessive collisions flag */
1977 #define CP_TX_STATUS_EXC (1<<20)
1978
1979 if (!(txdw0 & CP_TX_OWN))
1980 {
1981 DEBUG_PRINT(("RTL8139: C+ Tx mode : descriptor %d is owned by host\n", descriptor));
1982 return 0 ;
1983 }
1984
1985 DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : transmitting from descriptor %d\n", descriptor));
1986
1987 if (txdw0 & CP_TX_FS)
1988 {
1989 DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : descriptor %d is first segment descriptor\n", descriptor));
1990
1991 /* reset internal buffer offset */
1992 s->cplus_txbuffer_offset = 0;
1993 }
1994
1995 int txsize = txdw0 & CP_TX_BUFFER_SIZE_MASK;
1996 target_phys_addr_t tx_addr = rtl8139_addr64(txbufLO, txbufHI);
1997
1998 /* make sure we have enough space to assemble the packet */
1999 if (!s->cplus_txbuffer)
2000 {
2001 s->cplus_txbuffer_len = CP_TX_BUFFER_SIZE;
2002 s->cplus_txbuffer = malloc(s->cplus_txbuffer_len);
2003 s->cplus_txbuffer_offset = 0;
2004
2005 DEBUG_PRINT(("RTL8139: +++ C+ mode transmission buffer allocated space %d\n", s->cplus_txbuffer_len));
2006 }
2007
2008 while (s->cplus_txbuffer && s->cplus_txbuffer_offset + txsize >= s->cplus_txbuffer_len)
2009 {
2010 s->cplus_txbuffer_len += CP_TX_BUFFER_SIZE;
2011 s->cplus_txbuffer = qemu_realloc(s->cplus_txbuffer, s->cplus_txbuffer_len);
2012
2013 DEBUG_PRINT(("RTL8139: +++ C+ mode transmission buffer space changed to %d\n", s->cplus_txbuffer_len));
2014 }
2015
2016 if (!s->cplus_txbuffer)
2017 {
2018 /* out of memory */
2019
2020 DEBUG_PRINT(("RTL8139: +++ C+ mode transmiter failed to reallocate %d bytes\n", s->cplus_txbuffer_len));
2021
2022 /* update tally counter */
2023 ++s->tally_counters.TxERR;
2024 ++s->tally_counters.TxAbt;
2025
2026 return 0;
2027 }
2028
2029 /* append more data to the packet */
2030
2031 DEBUG_PRINT(("RTL8139: +++ C+ mode transmit reading %d bytes from host memory at %016" PRIx64 " to offset %d\n",
2032 txsize, (uint64_t)tx_addr, s->cplus_txbuffer_offset));
2033
2034 cpu_physical_memory_read(tx_addr, s->cplus_txbuffer + s->cplus_txbuffer_offset, txsize);
2035 s->cplus_txbuffer_offset += txsize;
2036
2037 /* seek to next Rx descriptor */
2038 if (txdw0 & CP_TX_EOR)
2039 {
2040 s->currCPlusTxDesc = 0;
2041 }
2042 else
2043 {
2044 ++s->currCPlusTxDesc;
2045 if (s->currCPlusTxDesc >= 64)
2046 s->currCPlusTxDesc = 0;
2047 }
2048
2049 /* transfer ownership to target */
2050 txdw0 &= ~CP_RX_OWN;
2051
2052 /* reset error indicator bits */
2053 txdw0 &= ~CP_TX_STATUS_UNF;
2054 txdw0 &= ~CP_TX_STATUS_TES;
2055 txdw0 &= ~CP_TX_STATUS_OWC;
2056 txdw0 &= ~CP_TX_STATUS_LNKF;
2057 txdw0 &= ~CP_TX_STATUS_EXC;
2058
2059 /* update ring data */
2060 val = cpu_to_le32(txdw0);
2061 cpu_physical_memory_write(cplus_tx_ring_desc, (uint8_t *)&val, 4);
2062 // val = cpu_to_le32(txdw1);
2063 // cpu_physical_memory_write(cplus_tx_ring_desc+4, &val, 4);
2064
2065 /* Now decide if descriptor being processed is holding the last segment of packet */
2066 if (txdw0 & CP_TX_LS)
2067 {
2068 DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : descriptor %d is last segment descriptor\n", descriptor));
2069
2070 /* can transfer fully assembled packet */
2071
2072 uint8_t *saved_buffer = s->cplus_txbuffer;
2073 int saved_size = s->cplus_txbuffer_offset;
2074 int saved_buffer_len = s->cplus_txbuffer_len;
2075
2076 /* reset the card space to protect from recursive call */
2077 s->cplus_txbuffer = NULL;
2078 s->cplus_txbuffer_offset = 0;
2079 s->cplus_txbuffer_len = 0;
2080
2081 if (txdw0 & (CP_TX_IPCS | CP_TX_UDPCS | CP_TX_TCPCS | CP_TX_LGSEN))
2082 {
2083 DEBUG_PRINT(("RTL8139: +++ C+ mode offloaded task checksum\n"));
2084
2085 #define ETH_P_IP 0x0800 /* Internet Protocol packet */
2086 #define ETH_HLEN 14
2087 #define ETH_MTU 1500
2088
2089 /* ip packet header */
2090 ip_header *ip = 0;
2091 int hlen = 0;
2092 uint8_t ip_protocol = 0;
2093 uint16_t ip_data_len = 0;
2094
2095 uint8_t *eth_payload_data = 0;
2096 size_t eth_payload_len = 0;
2097
2098 int proto = be16_to_cpu(*(uint16_t *)(saved_buffer + 12));
2099 if (proto == ETH_P_IP)
2100 {
2101 DEBUG_PRINT(("RTL8139: +++ C+ mode has IP packet\n"));
2102
2103 /* not aligned */
2104 eth_payload_data = saved_buffer + ETH_HLEN;
2105 eth_payload_len = saved_size - ETH_HLEN;
2106
2107 ip = (ip_header*)eth_payload_data;
2108
2109 if (IP_HEADER_VERSION(ip) != IP_HEADER_VERSION_4) {
2110 DEBUG_PRINT(("RTL8139: +++ C+ mode packet has bad IP version %d expected %d\n", IP_HEADER_VERSION(ip), IP_HEADER_VERSION_4));
2111 ip = NULL;
2112 } else {
2113 hlen = IP_HEADER_LENGTH(ip);
2114 ip_protocol = ip->ip_p;
2115 ip_data_len = be16_to_cpu(ip->ip_len) - hlen;
2116 }
2117 }
2118
2119 if (ip)
2120 {
2121 if (txdw0 & CP_TX_IPCS)
2122 {
2123 DEBUG_PRINT(("RTL8139: +++ C+ mode need IP checksum\n"));
2124
2125 if (hlen<sizeof(ip_header) || hlen>eth_payload_len) {/* min header length */
2126 /* bad packet header len */
2127 /* or packet too short */
2128 }
2129 else
2130 {
2131 ip->ip_sum = 0;
2132 ip->ip_sum = ip_checksum(ip, hlen);
2133 DEBUG_PRINT(("RTL8139: +++ C+ mode IP header len=%d checksum=%04x\n", hlen, ip->ip_sum));
2134 }
2135 }
2136
2137 if ((txdw0 & CP_TX_LGSEN) && ip_protocol == IP_PROTO_TCP)
2138 {
2139 #if defined (DEBUG_RTL8139)
2140 int large_send_mss = (txdw0 >> 16) & CP_TC_LGSEN_MSS_MASK;
2141 #endif
2142 DEBUG_PRINT(("RTL8139: +++ C+ mode offloaded task TSO MTU=%d IP data %d frame data %d specified MSS=%d\n",
2143 ETH_MTU, ip_data_len, saved_size - ETH_HLEN, large_send_mss));
2144
2145 int tcp_send_offset = 0;
2146 int send_count = 0;
2147
2148 /* maximum IP header length is 60 bytes */
2149 uint8_t saved_ip_header[60];
2150
2151 /* save IP header template; data area is used in tcp checksum calculation */
2152 memcpy(saved_ip_header, eth_payload_data, hlen);
2153
2154 /* a placeholder for checksum calculation routine in tcp case */
2155 uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2156 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
2157
2158 /* pointer to TCP header */
2159 tcp_header *p_tcp_hdr = (tcp_header*)(eth_payload_data + hlen);
2160
2161 int tcp_hlen = TCP_HEADER_DATA_OFFSET(p_tcp_hdr);
2162
2163 /* ETH_MTU = ip header len + tcp header len + payload */
2164 int tcp_data_len = ip_data_len - tcp_hlen;
2165 int tcp_chunk_size = ETH_MTU - hlen - tcp_hlen;
2166
2167 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO IP data len %d TCP hlen %d TCP data len %d TCP chunk size %d\n",
2168 ip_data_len, tcp_hlen, tcp_data_len, tcp_chunk_size));
2169
2170 /* note the cycle below overwrites IP header data,
2171 but restores it from saved_ip_header before sending packet */
2172
2173 int is_last_frame = 0;
2174
2175 for (tcp_send_offset = 0; tcp_send_offset < tcp_data_len; tcp_send_offset += tcp_chunk_size)
2176 {
2177 uint16_t chunk_size = tcp_chunk_size;
2178
2179 /* check if this is the last frame */
2180 if (tcp_send_offset + tcp_chunk_size >= tcp_data_len)
2181 {
2182 is_last_frame = 1;
2183 chunk_size = tcp_data_len - tcp_send_offset;
2184 }
2185
2186 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO TCP seqno %08x\n", be32_to_cpu(p_tcp_hdr->th_seq)));
2187
2188 /* add 4 TCP pseudoheader fields */
2189 /* copy IP source and destination fields */
2190 memcpy(data_to_checksum, saved_ip_header + 12, 8);
2191
2192 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO calculating TCP checksum for packet with %d bytes data\n", tcp_hlen + chunk_size));
2193
2194 if (tcp_send_offset)
2195 {
2196 memcpy((uint8_t*)p_tcp_hdr + tcp_hlen, (uint8_t*)p_tcp_hdr + tcp_hlen + tcp_send_offset, chunk_size);
2197 }
2198
2199 /* keep PUSH and FIN flags only for the last frame */
2200 if (!is_last_frame)
2201 {
2202 TCP_HEADER_CLEAR_FLAGS(p_tcp_hdr, TCP_FLAG_PUSH|TCP_FLAG_FIN);
2203 }
2204
2205 /* recalculate TCP checksum */
2206 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2207 p_tcpip_hdr->zeros = 0;
2208 p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2209 p_tcpip_hdr->ip_payload = cpu_to_be16(tcp_hlen + chunk_size);
2210
2211 p_tcp_hdr->th_sum = 0;
2212
2213 int tcp_checksum = ip_checksum(data_to_checksum, tcp_hlen + chunk_size + 12);
2214 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO TCP checksum %04x\n", tcp_checksum));
2215
2216 p_tcp_hdr->th_sum = tcp_checksum;
2217
2218 /* restore IP header */
2219 memcpy(eth_payload_data, saved_ip_header, hlen);
2220
2221 /* set IP data length and recalculate IP checksum */
2222 ip->ip_len = cpu_to_be16(hlen + tcp_hlen + chunk_size);
2223
2224 /* increment IP id for subsequent frames */
2225 ip->ip_id = cpu_to_be16(tcp_send_offset/tcp_chunk_size + be16_to_cpu(ip->ip_id));
2226
2227 ip->ip_sum = 0;
2228 ip->ip_sum = ip_checksum(eth_payload_data, hlen);
2229 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO IP header len=%d checksum=%04x\n", hlen, ip->ip_sum));
2230
2231 int tso_send_size = ETH_HLEN + hlen + tcp_hlen + chunk_size;
2232 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO transferring packet size %d\n", tso_send_size));
2233 rtl8139_transfer_frame(s, saved_buffer, tso_send_size, 0);
2234
2235 /* add transferred count to TCP sequence number */
2236 p_tcp_hdr->th_seq = cpu_to_be32(chunk_size + be32_to_cpu(p_tcp_hdr->th_seq));
2237 ++send_count;
2238 }
2239
2240 /* Stop sending this frame */
2241 saved_size = 0;
2242 }
2243 else if (txdw0 & (CP_TX_TCPCS|CP_TX_UDPCS))
2244 {
2245 DEBUG_PRINT(("RTL8139: +++ C+ mode need TCP or UDP checksum\n"));
2246
2247 /* maximum IP header length is 60 bytes */
2248 uint8_t saved_ip_header[60];
2249 memcpy(saved_ip_header, eth_payload_data, hlen);
2250
2251 uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2252 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
2253
2254 /* add 4 TCP pseudoheader fields */
2255 /* copy IP source and destination fields */
2256 memcpy(data_to_checksum, saved_ip_header + 12, 8);
2257
2258 if ((txdw0 & CP_TX_TCPCS) && ip_protocol == IP_PROTO_TCP)
2259 {
2260 DEBUG_PRINT(("RTL8139: +++ C+ mode calculating TCP checksum for packet with %d bytes data\n", ip_data_len));
2261
2262 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2263 p_tcpip_hdr->zeros = 0;
2264 p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2265 p_tcpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
2266
2267 tcp_header* p_tcp_hdr = (tcp_header *) (data_to_checksum+12);
2268
2269 p_tcp_hdr->th_sum = 0;
2270
2271 int tcp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
2272 DEBUG_PRINT(("RTL8139: +++ C+ mode TCP checksum %04x\n", tcp_checksum));
2273
2274 p_tcp_hdr->th_sum = tcp_checksum;
2275 }
2276 else if ((txdw0 & CP_TX_UDPCS) && ip_protocol == IP_PROTO_UDP)
2277 {
2278 DEBUG_PRINT(("RTL8139: +++ C+ mode calculating UDP checksum for packet with %d bytes data\n", ip_data_len));
2279
2280 ip_pseudo_header *p_udpip_hdr = (ip_pseudo_header *)data_to_checksum;
2281 p_udpip_hdr->zeros = 0;
2282 p_udpip_hdr->ip_proto = IP_PROTO_UDP;
2283 p_udpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
2284
2285 udp_header *p_udp_hdr = (udp_header *) (data_to_checksum+12);
2286
2287 p_udp_hdr->uh_sum = 0;
2288
2289 int udp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
2290 DEBUG_PRINT(("RTL8139: +++ C+ mode UDP checksum %04x\n", udp_checksum));
2291
2292 p_udp_hdr->uh_sum = udp_checksum;
2293 }
2294
2295 /* restore IP header */
2296 memcpy(eth_payload_data, saved_ip_header, hlen);
2297 }
2298 }
2299 }
2300
2301 /* update tally counter */
2302 ++s->tally_counters.TxOk;
2303
2304 DEBUG_PRINT(("RTL8139: +++ C+ mode transmitting %d bytes packet\n", saved_size));
2305
2306 rtl8139_transfer_frame(s, saved_buffer, saved_size, 1);
2307
2308 /* restore card space if there was no recursion and reset offset */
2309 if (!s->cplus_txbuffer)
2310 {
2311 s->cplus_txbuffer = saved_buffer;
2312 s->cplus_txbuffer_len = saved_buffer_len;
2313 s->cplus_txbuffer_offset = 0;
2314 }
2315 else
2316 {
2317 free(saved_buffer);
2318 }
2319 }
2320 else
2321 {
2322 DEBUG_PRINT(("RTL8139: +++ C+ mode transmission continue to next descriptor\n"));
2323 }
2324
2325 return 1;
2326 }
2327
2328 static void rtl8139_cplus_transmit(RTL8139State *s)
2329 {
2330 int txcount = 0;
2331
2332 while (rtl8139_cplus_transmit_one(s))
2333 {
2334 ++txcount;
2335 }
2336
2337 /* Mark transfer completed */
2338 if (!txcount)
2339 {
2340 DEBUG_PRINT(("RTL8139: C+ mode : transmitter queue stalled, current TxDesc = %d\n",
2341 s->currCPlusTxDesc));
2342 }
2343 else
2344 {
2345 /* update interrupt status */
2346 s->IntrStatus |= TxOK;
2347 rtl8139_update_irq(s);
2348 }
2349 }
2350
2351 static void rtl8139_transmit(RTL8139State *s)
2352 {
2353 int descriptor = s->currTxDesc, txcount = 0;
2354
2355 /*while*/
2356 if (rtl8139_transmit_one(s, descriptor))
2357 {
2358 ++s->currTxDesc;
2359 s->currTxDesc %= 4;
2360 ++txcount;
2361 }
2362
2363 /* Mark transfer completed */
2364 if (!txcount)
2365 {
2366 DEBUG_PRINT(("RTL8139: transmitter queue stalled, current TxDesc = %d\n", s->currTxDesc));
2367 }
2368 }
2369
2370 static void rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32_t val)
2371 {
2372
2373 int descriptor = txRegOffset/4;
2374
2375 /* handle C+ transmit mode register configuration */
2376
2377 if (s->cplus_enabled)
2378 {
2379 DEBUG_PRINT(("RTL8139C+ DTCCR write offset=0x%x val=0x%08x descriptor=%d\n", txRegOffset, val, descriptor));
2380
2381 /* handle Dump Tally Counters command */
2382 s->TxStatus[descriptor] = val;
2383
2384 if (descriptor == 0 && (val & 0x8))
2385 {
2386 target_phys_addr_t tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f, s->TxStatus[1]);
2387
2388 /* dump tally counters to specified memory location */
2389 RTL8139TallyCounters_physical_memory_write( tc_addr, &s->tally_counters);
2390
2391 /* mark dump completed */
2392 s->TxStatus[0] &= ~0x8;
2393 }
2394
2395 return;
2396 }
2397
2398 DEBUG_PRINT(("RTL8139: TxStatus write offset=0x%x val=0x%08x descriptor=%d\n", txRegOffset, val, descriptor));
2399
2400 /* mask only reserved bits */
2401 val &= ~0xff00c000; /* these bits are reset on write */
2402 val = SET_MASKED(val, 0x00c00000, s->TxStatus[descriptor]);
2403
2404 s->TxStatus[descriptor] = val;
2405
2406 /* attempt to start transmission */
2407 rtl8139_transmit(s);
2408 }
2409
2410 static uint32_t rtl8139_TxStatus_read(RTL8139State *s, uint32_t txRegOffset)
2411 {
2412 uint32_t ret = s->TxStatus[txRegOffset/4];
2413
2414 DEBUG_PRINT(("RTL8139: TxStatus read offset=0x%x val=0x%08x\n", txRegOffset, ret));
2415
2416 return ret;
2417 }
2418
2419 static uint16_t rtl8139_TSAD_read(RTL8139State *s)
2420 {
2421 uint16_t ret = 0;
2422
2423 /* Simulate TSAD, it is read only anyway */
2424
2425 ret = ((s->TxStatus[3] & TxStatOK )?TSAD_TOK3:0)
2426 |((s->TxStatus[2] & TxStatOK )?TSAD_TOK2:0)
2427 |((s->TxStatus[1] & TxStatOK )?TSAD_TOK1:0)
2428 |((s->TxStatus[0] & TxStatOK )?TSAD_TOK0:0)
2429
2430 |((s->TxStatus[3] & TxUnderrun)?TSAD_TUN3:0)
2431 |((s->TxStatus[2] & TxUnderrun)?TSAD_TUN2:0)
2432 |((s->TxStatus[1] & TxUnderrun)?TSAD_TUN1:0)
2433 |((s->TxStatus[0] & TxUnderrun)?TSAD_TUN0:0)
2434
2435 |((s->TxStatus[3] & TxAborted )?TSAD_TABT3:0)
2436 |((s->TxStatus[2] & TxAborted )?TSAD_TABT2:0)
2437 |((s->TxStatus[1] & TxAborted )?TSAD_TABT1:0)
2438 |((s->TxStatus[0] & TxAborted )?TSAD_TABT0:0)
2439
2440 |((s->TxStatus[3] & TxHostOwns )?TSAD_OWN3:0)
2441 |((s->TxStatus[2] & TxHostOwns )?TSAD_OWN2:0)
2442 |((s->TxStatus[1] & TxHostOwns )?TSAD_OWN1:0)
2443 |((s->TxStatus[0] & TxHostOwns )?TSAD_OWN0:0) ;
2444
2445
2446 DEBUG_PRINT(("RTL8139: TSAD read val=0x%04x\n", ret));
2447
2448 return ret;
2449 }
2450
2451 static uint16_t rtl8139_CSCR_read(RTL8139State *s)
2452 {
2453 uint16_t ret = s->CSCR;
2454
2455 DEBUG_PRINT(("RTL8139: CSCR read val=0x%04x\n", ret));
2456
2457 return ret;
2458 }
2459
2460 static void rtl8139_TxAddr_write(RTL8139State *s, uint32_t txAddrOffset, uint32_t val)
2461 {
2462 DEBUG_PRINT(("RTL8139: TxAddr write offset=0x%x val=0x%08x\n", txAddrOffset, val));
2463
2464 s->TxAddr[txAddrOffset/4] = val;
2465 }
2466
2467 static uint32_t rtl8139_TxAddr_read(RTL8139State *s, uint32_t txAddrOffset)
2468 {
2469 uint32_t ret = s->TxAddr[txAddrOffset/4];
2470
2471 DEBUG_PRINT(("RTL8139: TxAddr read offset=0x%x val=0x%08x\n", txAddrOffset, ret));
2472
2473 return ret;
2474 }
2475
2476 static void rtl8139_RxBufPtr_write(RTL8139State *s, uint32_t val)
2477 {
2478 DEBUG_PRINT(("RTL8139: RxBufPtr write val=0x%04x\n", val));
2479
2480 /* this value is off by 16 */
2481 s->RxBufPtr = MOD2(val + 0x10, s->RxBufferSize);
2482
2483 DEBUG_PRINT((" CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n",
2484 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr));
2485 }
2486
2487 static uint32_t rtl8139_RxBufPtr_read(RTL8139State *s)
2488 {
2489 /* this value is off by 16 */
2490 uint32_t ret = s->RxBufPtr - 0x10;
2491
2492 DEBUG_PRINT(("RTL8139: RxBufPtr read val=0x%04x\n", ret));
2493
2494 return ret;
2495 }
2496
2497 static uint32_t rtl8139_RxBufAddr_read(RTL8139State *s)
2498 {
2499 /* this value is NOT off by 16 */
2500 uint32_t ret = s->RxBufAddr;
2501
2502 DEBUG_PRINT(("RTL8139: RxBufAddr read val=0x%04x\n", ret));
2503
2504 return ret;
2505 }
2506
2507 static void rtl8139_RxBuf_write(RTL8139State *s, uint32_t val)
2508 {
2509 DEBUG_PRINT(("RTL8139: RxBuf write val=0x%08x\n", val));
2510
2511 s->RxBuf = val;
2512
2513 /* may need to reset rxring here */
2514 }
2515
2516 static uint32_t rtl8139_RxBuf_read(RTL8139State *s)
2517 {
2518 uint32_t ret = s->RxBuf;
2519
2520 DEBUG_PRINT(("RTL8139: RxBuf read val=0x%08x\n", ret));
2521
2522 return ret;
2523 }
2524
2525 static void rtl8139_IntrMask_write(RTL8139State *s, uint32_t val)
2526 {
2527 DEBUG_PRINT(("RTL8139: IntrMask write(w) val=0x%04x\n", val));
2528
2529 /* mask unwriteable bits */
2530 val = SET_MASKED(val, 0x1e00, s->IntrMask);
2531
2532 s->IntrMask = val;
2533
2534 rtl8139_update_irq(s);
2535 }
2536
2537 static uint32_t rtl8139_IntrMask_read(RTL8139State *s)
2538 {
2539 uint32_t ret = s->IntrMask;
2540
2541 DEBUG_PRINT(("RTL8139: IntrMask read(w) val=0x%04x\n", ret));
2542
2543 return ret;
2544 }
2545
2546 static void rtl8139_IntrStatus_write(RTL8139State *s, uint32_t val)
2547 {
2548 DEBUG_PRINT(("RTL8139: IntrStatus write(w) val=0x%04x\n", val));
2549
2550 #if 0
2551
2552 /* writing to ISR has no effect */
2553
2554 return;
2555
2556 #else
2557 uint16_t newStatus = s->IntrStatus & ~val;
2558
2559 /* mask unwriteable bits */
2560 newStatus = SET_MASKED(newStatus, 0x1e00, s->IntrStatus);
2561
2562 /* writing 1 to interrupt status register bit clears it */
2563 s->IntrStatus = 0;
2564 rtl8139_update_irq(s);
2565
2566 s->IntrStatus = newStatus;
2567 rtl8139_update_irq(s);
2568 #endif
2569 }
2570
2571 static uint32_t rtl8139_IntrStatus_read(RTL8139State *s)
2572 {
2573 uint32_t ret = s->IntrStatus;
2574
2575 DEBUG_PRINT(("RTL8139: IntrStatus read(w) val=0x%04x\n", ret));
2576
2577 #if 0
2578
2579 /* reading ISR clears all interrupts */
2580 s->IntrStatus = 0;
2581
2582 rtl8139_update_irq(s);
2583
2584 #endif
2585
2586 return ret;
2587 }
2588
2589 static void rtl8139_MultiIntr_write(RTL8139State *s, uint32_t val)
2590 {
2591 DEBUG_PRINT(("RTL8139: MultiIntr write(w) val=0x%04x\n", val));
2592
2593 /* mask unwriteable bits */
2594 val = SET_MASKED(val, 0xf000, s->MultiIntr);
2595
2596 s->MultiIntr = val;
2597 }
2598
2599 static uint32_t rtl8139_MultiIntr_read(RTL8139State *s)
2600 {
2601 uint32_t ret = s->MultiIntr;
2602
2603 DEBUG_PRINT(("RTL8139: MultiIntr read(w) val=0x%04x\n", ret));
2604
2605 return ret;
2606 }
2607
2608 static void rtl8139_io_writeb(void *opaque, uint8_t addr, uint32_t val)
2609 {
2610 RTL8139State *s = opaque;
2611
2612 addr &= 0xff;
2613
2614 switch (addr)
2615 {
2616 case MAC0 ... MAC0+5:
2617 s->phys[addr - MAC0] = val;
2618 break;
2619 case MAC0+6 ... MAC0+7:
2620 /* reserved */
2621 break;
2622 case MAR0 ... MAR0+7:
2623 s->mult[addr - MAR0] = val;
2624 break;
2625 case ChipCmd:
2626 rtl8139_ChipCmd_write(s, val);
2627 break;
2628 case Cfg9346:
2629 rtl8139_Cfg9346_write(s, val);
2630 break;
2631 case TxConfig: /* windows driver sometimes writes using byte-lenth call */
2632 rtl8139_TxConfig_writeb(s, val);
2633 break;
2634 case Config0:
2635 rtl8139_Config0_write(s, val);
2636 break;
2637 case Config1:
2638 rtl8139_Config1_write(s, val);
2639 break;
2640 case Config3:
2641 rtl8139_Config3_write(s, val);
2642 break;
2643 case Config4:
2644 rtl8139_Config4_write(s, val);
2645 break;
2646 case Config5:
2647 rtl8139_Config5_write(s, val);
2648 break;
2649 case MediaStatus:
2650 /* ignore */
2651 DEBUG_PRINT(("RTL8139: not implemented write(b) to MediaStatus val=0x%02x\n", val));
2652 break;
2653
2654 case HltClk:
2655 DEBUG_PRINT(("RTL8139: HltClk write val=0x%08x\n", val));
2656 if (val == 'R')
2657 {
2658 s->clock_enabled = 1;
2659 }
2660 else if (val == 'H')
2661 {
2662 s->clock_enabled = 0;
2663 }
2664 break;
2665
2666 case TxThresh:
2667 DEBUG_PRINT(("RTL8139C+ TxThresh write(b) val=0x%02x\n", val));
2668 s->TxThresh = val;
2669 break;
2670
2671 case TxPoll:
2672 DEBUG_PRINT(("RTL8139C+ TxPoll write(b) val=0x%02x\n", val));
2673 if (val & (1 << 7))
2674 {
2675 DEBUG_PRINT(("RTL8139C+ TxPoll high priority transmission (not implemented)\n"));
2676 //rtl8139_cplus_transmit(s);
2677 }
2678 if (val & (1 << 6))
2679 {
2680 DEBUG_PRINT(("RTL8139C+ TxPoll normal priority transmission\n"));
2681 rtl8139_cplus_transmit(s);
2682 }
2683
2684 break;
2685
2686 default:
2687 DEBUG_PRINT(("RTL8139: not implemented write(b) addr=0x%x val=0x%02x\n", addr, val));
2688 break;
2689 }
2690 }
2691
2692 static void rtl8139_io_writew(void *opaque, uint8_t addr, uint32_t val)
2693 {
2694 RTL8139State *s = opaque;
2695
2696 addr &= 0xfe;
2697
2698 switch (addr)
2699 {
2700 case IntrMask:
2701 rtl8139_IntrMask_write(s, val);
2702 break;
2703
2704 case IntrStatus:
2705 rtl8139_IntrStatus_write(s, val);
2706 break;
2707
2708 case MultiIntr:
2709 rtl8139_MultiIntr_write(s, val);
2710 break;
2711
2712 case RxBufPtr:
2713 rtl8139_RxBufPtr_write(s, val);
2714 break;
2715
2716 case BasicModeCtrl:
2717 rtl8139_BasicModeCtrl_write(s, val);
2718 break;
2719 case BasicModeStatus:
2720 rtl8139_BasicModeStatus_write(s, val);
2721 break;
2722 case NWayAdvert:
2723 DEBUG_PRINT(("RTL8139: NWayAdvert write(w) val=0x%04x\n", val));
2724 s->NWayAdvert = val;
2725 break;
2726 case NWayLPAR:
2727 DEBUG_PRINT(("RTL8139: forbidden NWayLPAR write(w) val=0x%04x\n", val));
2728 break;
2729 case NWayExpansion:
2730 DEBUG_PRINT(("RTL8139: NWayExpansion write(w) val=0x%04x\n", val));
2731 s->NWayExpansion = val;
2732 break;
2733
2734 case CpCmd:
2735 rtl8139_CpCmd_write(s, val);
2736 break;
2737
2738 case IntrMitigate:
2739 rtl8139_IntrMitigate_write(s, val);
2740 break;
2741
2742 default:
2743 DEBUG_PRINT(("RTL8139: ioport write(w) addr=0x%x val=0x%04x via write(b)\n", addr, val));
2744
2745 rtl8139_io_writeb(opaque, addr, val & 0xff);
2746 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2747 break;
2748 }
2749 }
2750
2751 static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val)
2752 {
2753 RTL8139State *s = opaque;
2754
2755 addr &= 0xfc;
2756
2757 switch (addr)
2758 {
2759 case RxMissed:
2760 DEBUG_PRINT(("RTL8139: RxMissed clearing on write\n"));
2761 s->RxMissed = 0;
2762 break;
2763
2764 case TxConfig:
2765 rtl8139_TxConfig_write(s, val);
2766 break;
2767
2768 case RxConfig:
2769 rtl8139_RxConfig_write(s, val);
2770 break;
2771
2772 case TxStatus0 ... TxStatus0+4*4-1:
2773 rtl8139_TxStatus_write(s, addr-TxStatus0, val);
2774 break;
2775
2776 case TxAddr0 ... TxAddr0+4*4-1:
2777 rtl8139_TxAddr_write(s, addr-TxAddr0, val);
2778 break;
2779
2780 case RxBuf:
2781 rtl8139_RxBuf_write(s, val);
2782 break;
2783
2784 case RxRingAddrLO:
2785 DEBUG_PRINT(("RTL8139: C+ RxRing low bits write val=0x%08x\n", val));
2786 s->RxRingAddrLO = val;
2787 break;
2788
2789 case RxRingAddrHI:
2790 DEBUG_PRINT(("RTL8139: C+ RxRing high bits write val=0x%08x\n", val));
2791 s->RxRingAddrHI = val;
2792 break;
2793
2794 case Timer:
2795 DEBUG_PRINT(("RTL8139: TCTR Timer reset on write\n"));
2796 s->TCTR = 0;
2797 s->TCTR_base = qemu_get_clock(vm_clock);
2798 break;
2799
2800 case FlashReg:
2801 DEBUG_PRINT(("RTL8139: FlashReg TimerInt write val=0x%08x\n", val));
2802 s->TimerInt = val;
2803 break;
2804
2805 default:
2806 DEBUG_PRINT(("RTL8139: ioport write(l) addr=0x%x val=0x%08x via write(b)\n", addr, val));
2807 rtl8139_io_writeb(opaque, addr, val & 0xff);
2808 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2809 rtl8139_io_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2810 rtl8139_io_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2811 break;
2812 }
2813 }
2814
2815 static uint32_t rtl8139_io_readb(void *opaque, uint8_t addr)
2816 {
2817 RTL8139State *s = opaque;
2818 int ret;
2819
2820 addr &= 0xff;
2821
2822 switch (addr)
2823 {
2824 case MAC0 ... MAC0+5:
2825 ret = s->phys[addr - MAC0];
2826 break;
2827 case MAC0+6 ... MAC0+7:
2828 ret = 0;
2829 break;
2830 case MAR0 ... MAR0+7:
2831 ret = s->mult[addr - MAR0];
2832 break;
2833 case ChipCmd:
2834 ret = rtl8139_ChipCmd_read(s);
2835 break;
2836 case Cfg9346:
2837 ret = rtl8139_Cfg9346_read(s);
2838 break;
2839 case Config0:
2840 ret = rtl8139_Config0_read(s);
2841 break;
2842 case Config1:
2843 ret = rtl8139_Config1_read(s);
2844 break;
2845 case Config3:
2846 ret = rtl8139_Config3_read(s);
2847 break;
2848 case Config4:
2849 ret = rtl8139_Config4_read(s);
2850 break;
2851 case Config5:
2852 ret = rtl8139_Config5_read(s);
2853 break;
2854
2855 case MediaStatus:
2856 ret = 0xd0;
2857 DEBUG_PRINT(("RTL8139: MediaStatus read 0x%x\n", ret));
2858 break;
2859
2860 case HltClk:
2861 ret = s->clock_enabled;
2862 DEBUG_PRINT(("RTL8139: HltClk read 0x%x\n", ret));
2863 break;
2864
2865 case PCIRevisionID:
2866 ret = RTL8139_PCI_REVID;
2867 DEBUG_PRINT(("RTL8139: PCI Revision ID read 0x%x\n", ret));
2868 break;
2869
2870 case TxThresh:
2871 ret = s->TxThresh;
2872 DEBUG_PRINT(("RTL8139C+ TxThresh read(b) val=0x%02x\n", ret));
2873 break;
2874
2875 case 0x43: /* Part of TxConfig register. Windows driver tries to read it */
2876 ret = s->TxConfig >> 24;
2877 DEBUG_PRINT(("RTL8139C TxConfig at 0x43 read(b) val=0x%02x\n", ret));
2878 break;
2879
2880 default:
2881 DEBUG_PRINT(("RTL8139: not implemented read(b) addr=0x%x\n", addr));
2882 ret = 0;
2883 break;
2884 }
2885
2886 return ret;
2887 }
2888
2889 static uint32_t rtl8139_io_readw(void *opaque, uint8_t addr)
2890 {
2891 RTL8139State *s = opaque;
2892 uint32_t ret;
2893
2894 addr &= 0xfe; /* mask lower bit */
2895
2896 switch (addr)
2897 {
2898 case IntrMask:
2899 ret = rtl8139_IntrMask_read(s);
2900 break;
2901
2902 case IntrStatus:
2903 ret = rtl8139_IntrStatus_read(s);
2904 break;
2905
2906 case MultiIntr:
2907 ret = rtl8139_MultiIntr_read(s);
2908 break;
2909
2910 case RxBufPtr:
2911 ret = rtl8139_RxBufPtr_read(s);
2912 break;
2913
2914 case RxBufAddr:
2915 ret = rtl8139_RxBufAddr_read(s);
2916 break;
2917
2918 case BasicModeCtrl:
2919 ret = rtl8139_BasicModeCtrl_read(s);
2920 break;
2921 case BasicModeStatus:
2922 ret = rtl8139_BasicModeStatus_read(s);
2923 break;
2924 case NWayAdvert:
2925 ret = s->NWayAdvert;
2926 DEBUG_PRINT(("RTL8139: NWayAdvert read(w) val=0x%04x\n", ret));
2927 break;
2928 case NWayLPAR:
2929 ret = s->NWayLPAR;
2930 DEBUG_PRINT(("RTL8139: NWayLPAR read(w) val=0x%04x\n", ret));
2931 break;
2932 case NWayExpansion:
2933 ret = s->NWayExpansion;
2934 DEBUG_PRINT(("RTL8139: NWayExpansion read(w) val=0x%04x\n", ret));
2935 break;
2936
2937 case CpCmd:
2938 ret = rtl8139_CpCmd_read(s);
2939 break;
2940
2941 case IntrMitigate:
2942 ret = rtl8139_IntrMitigate_read(s);
2943 break;
2944
2945 case TxSummary:
2946 ret = rtl8139_TSAD_read(s);
2947 break;
2948
2949 case CSCR:
2950 ret = rtl8139_CSCR_read(s);
2951 break;
2952
2953 default:
2954 DEBUG_PRINT(("RTL8139: ioport read(w) addr=0x%x via read(b)\n", addr));
2955
2956 ret = rtl8139_io_readb(opaque, addr);
2957 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
2958
2959 DEBUG_PRINT(("RTL8139: ioport read(w) addr=0x%x val=0x%04x\n", addr, ret));
2960 break;
2961 }
2962
2963 return ret;
2964 }
2965
2966 static uint32_t rtl8139_io_readl(void *opaque, uint8_t addr)
2967 {
2968 RTL8139State *s = opaque;
2969 uint32_t ret;
2970
2971 addr &= 0xfc; /* also mask low 2 bits */
2972
2973 switch (addr)
2974 {
2975 case RxMissed:
2976 ret = s->RxMissed;
2977
2978 DEBUG_PRINT(("RTL8139: RxMissed read val=0x%08x\n", ret));
2979 break;
2980
2981 case TxConfig:
2982 ret = rtl8139_TxConfig_read(s);
2983 break;
2984
2985 case RxConfig:
2986 ret = rtl8139_RxConfig_read(s);
2987 break;
2988
2989 case TxStatus0 ... TxStatus0+4*4-1:
2990 ret = rtl8139_TxStatus_read(s, addr-TxStatus0);
2991 break;
2992
2993 case TxAddr0 ... TxAddr0+4*4-1:
2994 ret = rtl8139_TxAddr_read(s, addr-TxAddr0);
2995 break;
2996
2997 case RxBuf:
2998 ret = rtl8139_RxBuf_read(s);
2999 break;
3000
3001 case RxRingAddrLO:
3002 ret = s->RxRingAddrLO;
3003 DEBUG_PRINT(("RTL8139: C+ RxRing low bits read val=0x%08x\n", ret));
3004 break;
3005
3006 case RxRingAddrHI:
3007 ret = s->RxRingAddrHI;
3008 DEBUG_PRINT(("RTL8139: C+ RxRing high bits read val=0x%08x\n", ret));
3009 break;
3010
3011 case Timer:
3012 ret = s->TCTR;
3013 DEBUG_PRINT(("RTL8139: TCTR Timer read val=0x%08x\n", ret));
3014 break;
3015
3016 case FlashReg:
3017 ret = s->TimerInt;
3018 DEBUG_PRINT(("RTL8139: FlashReg TimerInt read val=0x%08x\n", ret));
3019 break;
3020
3021 default:
3022 DEBUG_PRINT(("RTL8139: ioport read(l) addr=0x%x via read(b)\n", addr));
3023
3024 ret = rtl8139_io_readb(opaque, addr);
3025 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
3026 ret |= rtl8139_io_readb(opaque, addr + 2) << 16;
3027 ret |= rtl8139_io_readb(opaque, addr + 3) << 24;
3028
3029 DEBUG_PRINT(("RTL8139: read(l) addr=0x%x val=%08x\n", addr, ret));
3030 break;
3031 }
3032
3033 return ret;
3034 }
3035
3036 /* */
3037
3038 static void rtl8139_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
3039 {
3040 rtl8139_io_writeb(opaque, addr & 0xFF, val);
3041 }
3042
3043 static void rtl8139_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
3044 {
3045 rtl8139_io_writew(opaque, addr & 0xFF, val);
3046 }
3047
3048 static void rtl8139_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
3049 {
3050 rtl8139_io_writel(opaque, addr & 0xFF, val);
3051 }
3052
3053 static uint32_t rtl8139_ioport_readb(void *opaque, uint32_t addr)
3054 {
3055 return rtl8139_io_readb(opaque, addr & 0xFF);
3056 }
3057
3058 static uint32_t rtl8139_ioport_readw(void *opaque, uint32_t addr)
3059 {
3060 return rtl8139_io_readw(opaque, addr & 0xFF);
3061 }
3062
3063 static uint32_t rtl8139_ioport_readl(void *opaque, uint32_t addr)
3064 {
3065 return rtl8139_io_readl(opaque, addr & 0xFF);
3066 }
3067
3068 /* */
3069
3070 static void rtl8139_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
3071 {
3072 rtl8139_io_writeb(opaque, addr & 0xFF, val);
3073 }
3074
3075 static void rtl8139_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
3076 {
3077 #ifdef TARGET_WORDS_BIGENDIAN
3078 val = bswap16(val);
3079 #endif
3080 rtl8139_io_writew(opaque, addr & 0xFF, val);
3081 }
3082
3083 static void rtl8139_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
3084 {
3085 #ifdef TARGET_WORDS_BIGENDIAN
3086 val = bswap32(val);
3087 #endif
3088 rtl8139_io_writel(opaque, addr & 0xFF, val);
3089 }
3090
3091 static uint32_t rtl8139_mmio_readb(void *opaque, target_phys_addr_t addr)
3092 {
3093 return rtl8139_io_readb(opaque, addr & 0xFF);
3094 }
3095
3096 static uint32_t rtl8139_mmio_readw(void *opaque, target_phys_addr_t addr)
3097 {
3098 uint32_t val = rtl8139_io_readw(opaque, addr & 0xFF);
3099 #ifdef TARGET_WORDS_BIGENDIAN
3100 val = bswap16(val);
3101 #endif
3102 return val;
3103 }
3104
3105 static uint32_t rtl8139_mmio_readl(void *opaque, target_phys_addr_t addr)
3106 {
3107 uint32_t val = rtl8139_io_readl(opaque, addr & 0xFF);
3108 #ifdef TARGET_WORDS_BIGENDIAN
3109 val = bswap32(val);
3110 #endif
3111 return val;
3112 }
3113
3114 /* */
3115
3116 static void rtl8139_save(QEMUFile* f,void* opaque)
3117 {
3118 RTL8139State* s=(RTL8139State*)opaque;
3119 unsigned int i;
3120
3121 pci_device_save(s->pci_dev, f);
3122
3123 qemu_put_buffer(f, s->phys, 6);
3124 qemu_put_buffer(f, s->mult, 8);
3125
3126 for (i=0; i<4; ++i)
3127 {
3128 qemu_put_be32s(f, &s->TxStatus[i]); /* TxStatus0 */
3129 }
3130 for (i=0; i<4; ++i)
3131 {
3132 qemu_put_be32s(f, &s->TxAddr[i]); /* TxAddr0 */
3133 }
3134
3135 qemu_put_be32s(f, &s->RxBuf); /* Receive buffer */
3136 qemu_put_be32s(f, &s->RxBufferSize);/* internal variable, receive ring buffer size in C mode */
3137 qemu_put_be32s(f, &s->RxBufPtr);
3138 qemu_put_be32s(f, &s->RxBufAddr);
3139
3140 qemu_put_be16s(f, &s->IntrStatus);
3141 qemu_put_be16s(f, &s->IntrMask);
3142
3143 qemu_put_be32s(f, &s->TxConfig);
3144 qemu_put_be32s(f, &s->RxConfig);
3145 qemu_put_be32s(f, &s->RxMissed);
3146 qemu_put_be16s(f, &s->CSCR);
3147
3148 qemu_put_8s(f, &s->Cfg9346);
3149 qemu_put_8s(f, &s->Config0);
3150 qemu_put_8s(f, &s->Config1);
3151 qemu_put_8s(f, &s->Config3);
3152 qemu_put_8s(f, &s->Config4);
3153 qemu_put_8s(f, &s->Config5);
3154
3155 qemu_put_8s(f, &s->clock_enabled);
3156 qemu_put_8s(f, &s->bChipCmdState);
3157
3158 qemu_put_be16s(f, &s->MultiIntr);
3159
3160 qemu_put_be16s(f, &s->BasicModeCtrl);
3161 qemu_put_be16s(f, &s->BasicModeStatus);
3162 qemu_put_be16s(f, &s->NWayAdvert);
3163 qemu_put_be16s(f, &s->NWayLPAR);
3164 qemu_put_be16s(f, &s->NWayExpansion);
3165
3166 qemu_put_be16s(f, &s->CpCmd);
3167 qemu_put_8s(f, &s->TxThresh);
3168
3169 i = 0;
3170 qemu_put_be32s(f, &i); /* unused. */
3171 qemu_put_buffer(f, s->macaddr, 6);
3172 qemu_put_be32(f, s->rtl8139_mmio_io_addr);
3173
3174 qemu_put_be32s(f, &s->currTxDesc);
3175 qemu_put_be32s(f, &s->currCPlusRxDesc);
3176 qemu_put_be32s(f, &s->currCPlusTxDesc);
3177 qemu_put_be32s(f, &s->RxRingAddrLO);
3178 qemu_put_be32s(f, &s->RxRingAddrHI);
3179
3180 for (i=0; i<EEPROM_9346_SIZE; ++i)
3181 {
3182 qemu_put_be16s(f, &s->eeprom.contents[i]);
3183 }
3184 qemu_put_be32(f, s->eeprom.mode);
3185 qemu_put_be32s(f, &s->eeprom.tick);
3186 qemu_put_8s(f, &s->eeprom.address);
3187 qemu_put_be16s(f, &s->eeprom.input);
3188 qemu_put_be16s(f, &s->eeprom.output);
3189
3190 qemu_put_8s(f, &s->eeprom.eecs);
3191 qemu_put_8s(f, &s->eeprom.eesk);
3192 qemu_put_8s(f, &s->eeprom.eedi);
3193 qemu_put_8s(f, &s->eeprom.eedo);
3194
3195 qemu_put_be32s(f, &s->TCTR);
3196 qemu_put_be32s(f, &s->TimerInt);
3197 qemu_put_be64(f, s->TCTR_base);
3198
3199 RTL8139TallyCounters_save(f, &s->tally_counters);
3200
3201 qemu_put_be32s(f, &s->cplus_enabled);
3202 }
3203
3204 static int rtl8139_load(QEMUFile* f,void* opaque,int version_id)
3205 {
3206 RTL8139State* s=(RTL8139State*)opaque;
3207 unsigned int i;
3208 int ret;
3209
3210 /* just 2 versions for now */
3211 if (version_id > 4)
3212 return -EINVAL;
3213
3214 if (version_id >= 3) {
3215 ret = pci_device_load(s->pci_dev, f);
3216 if (ret < 0)
3217 return ret;
3218 }
3219
3220 /* saved since version 1 */
3221 qemu_get_buffer(f, s->phys, 6);
3222 qemu_get_buffer(f, s->mult, 8);
3223
3224 for (i=0; i<4; ++i)
3225 {
3226 qemu_get_be32s(f, &s->TxStatus[i]); /* TxStatus0 */
3227 }
3228 for (i=0; i<4; ++i)
3229 {
3230 qemu_get_be32s(f, &s->TxAddr[i]); /* TxAddr0 */
3231 }
3232
3233 qemu_get_be32s(f, &s->RxBuf); /* Receive buffer */
3234 qemu_get_be32s(f, &s->RxBufferSize);/* internal variable, receive ring buffer size in C mode */
3235 qemu_get_be32s(f, &s->RxBufPtr);
3236 qemu_get_be32s(f, &s->RxBufAddr);
3237
3238 qemu_get_be16s(f, &s->IntrStatus);
3239 qemu_get_be16s(f, &s->IntrMask);
3240
3241 qemu_get_be32s(f, &s->TxConfig);
3242 qemu_get_be32s(f, &s->RxConfig);
3243 qemu_get_be32s(f, &s->RxMissed);
3244 qemu_get_be16s(f, &s->CSCR);
3245
3246 qemu_get_8s(f, &s->Cfg9346);
3247 qemu_get_8s(f, &s->Config0);
3248 qemu_get_8s(f, &s->Config1);
3249 qemu_get_8s(f, &s->Config3);
3250 qemu_get_8s(f, &s->Config4);
3251 qemu_get_8s(f, &s->Config5);
3252
3253 qemu_get_8s(f, &s->clock_enabled);
3254 qemu_get_8s(f, &s->bChipCmdState);
3255
3256 qemu_get_be16s(f, &s->MultiIntr);
3257
3258 qemu_get_be16s(f, &s->BasicModeCtrl);
3259 qemu_get_be16s(f, &s->BasicModeStatus);
3260 qemu_get_be16s(f, &s->NWayAdvert);
3261 qemu_get_be16s(f, &s->NWayLPAR);
3262 qemu_get_be16s(f, &s->NWayExpansion);
3263
3264 qemu_get_be16s(f, &s->CpCmd);
3265 qemu_get_8s(f, &s->TxThresh);
3266
3267 qemu_get_be32s(f, &i); /* unused. */
3268 qemu_get_buffer(f, s->macaddr, 6);
3269 s->rtl8139_mmio_io_addr=qemu_get_be32(f);
3270
3271 qemu_get_be32s(f, &s->currTxDesc);
3272 qemu_get_be32s(f, &s->currCPlusRxDesc);
3273 qemu_get_be32s(f, &s->currCPlusTxDesc);
3274 qemu_get_be32s(f, &s->RxRingAddrLO);
3275 qemu_get_be32s(f, &s->RxRingAddrHI);
3276
3277 for (i=0; i<EEPROM_9346_SIZE; ++i)
3278 {
3279 qemu_get_be16s(f, &s->eeprom.contents[i]);
3280 }
3281 s->eeprom.mode=qemu_get_be32(f);
3282 qemu_get_be32s(f, &s->eeprom.tick);
3283 qemu_get_8s(f, &s->eeprom.address);
3284 qemu_get_be16s(f, &s->eeprom.input);
3285 qemu_get_be16s(f, &s->eeprom.output);
3286
3287 qemu_get_8s(f, &s->eeprom.eecs);
3288 qemu_get_8s(f, &s->eeprom.eesk);
3289 qemu_get_8s(f, &s->eeprom.eedi);
3290 qemu_get_8s(f, &s->eeprom.eedo);
3291
3292 /* saved since version 2 */
3293 if (version_id >= 2)
3294 {
3295 qemu_get_be32s(f, &s->TCTR);
3296 qemu_get_be32s(f, &s->TimerInt);
3297 s->TCTR_base=qemu_get_be64(f);
3298
3299 RTL8139TallyCounters_load(f, &s->tally_counters);
3300 }
3301 else
3302 {
3303 /* not saved, use default */
3304 s->TCTR = 0;
3305 s->TimerInt = 0;
3306 s->TCTR_base = 0;
3307
3308 RTL8139TallyCounters_clear(&s->tally_counters);
3309 }
3310
3311 if (version_id >= 4) {
3312 qemu_get_be32s(f, &s->cplus_enabled);
3313 } else {
3314 s->cplus_enabled = s->CpCmd != 0;
3315 }
3316
3317 return 0;
3318 }
3319
3320 /***********************************************************/
3321 /* PCI RTL8139 definitions */
3322
3323 typedef struct PCIRTL8139State {
3324 PCIDevice dev;
3325 RTL8139State rtl8139;
3326 } PCIRTL8139State;
3327
3328 static void rtl8139_mmio_map(PCIDevice *pci_dev, int region_num,
3329 uint32_t addr, uint32_t size, int type)
3330 {
3331 PCIRTL8139State *d = (PCIRTL8139State *)pci_dev;
3332 RTL8139State *s = &d->rtl8139;
3333
3334 cpu_register_physical_memory(addr + 0, 0x100, s->rtl8139_mmio_io_addr);
3335 }
3336
3337 static void rtl8139_ioport_map(PCIDevice *pci_dev, int region_num,
3338 uint32_t addr, uint32_t size, int type)
3339 {
3340 PCIRTL8139State *d = (PCIRTL8139State *)pci_dev;
3341 RTL8139State *s = &d->rtl8139;
3342
3343 register_ioport_write(addr, 0x100, 1, rtl8139_ioport_writeb, s);
3344 register_ioport_read( addr, 0x100, 1, rtl8139_ioport_readb, s);
3345
3346 register_ioport_write(addr, 0x100, 2, rtl8139_ioport_writew, s);
3347 register_ioport_read( addr, 0x100, 2, rtl8139_ioport_readw, s);
3348
3349 register_ioport_write(addr, 0x100, 4, rtl8139_ioport_writel, s);
3350 register_ioport_read( addr, 0x100, 4, rtl8139_ioport_readl, s);
3351 }
3352
3353 static CPUReadMemoryFunc *rtl8139_mmio_read[3] = {
3354 rtl8139_mmio_readb,
3355 rtl8139_mmio_readw,
3356 rtl8139_mmio_readl,
3357 };
3358
3359 static CPUWriteMemoryFunc *rtl8139_mmio_write[3] = {
3360 rtl8139_mmio_writeb,
3361 rtl8139_mmio_writew,
3362 rtl8139_mmio_writel,
3363 };
3364
3365 static inline int64_t rtl8139_get_next_tctr_time(RTL8139State *s, int64_t current_time)
3366 {
3367 int64_t next_time = current_time +
3368 muldiv64(1, ticks_per_sec, PCI_FREQUENCY);
3369 if (next_time <= current_time)
3370 next_time = current_time + 1;
3371 return next_time;
3372 }
3373
3374 #ifdef RTL8139_ONBOARD_TIMER
3375 static void rtl8139_timer(void *opaque)
3376 {
3377 RTL8139State *s = opaque;
3378
3379 int is_timeout = 0;
3380
3381 int64_t curr_time;
3382 uint32_t curr_tick;
3383
3384 if (!s->clock_enabled)
3385 {
3386 DEBUG_PRINT(("RTL8139: >>> timer: clock is not running\n"));
3387 return;
3388 }
3389
3390 curr_time = qemu_get_clock(vm_clock);
3391
3392 curr_tick = muldiv64(curr_time - s->TCTR_base, PCI_FREQUENCY, ticks_per_sec);
3393
3394 if (s->TimerInt && curr_tick >= s->TimerInt)
3395 {
3396 if (s->TCTR < s->TimerInt || curr_tick < s->TCTR)
3397 {
3398 is_timeout = 1;
3399 }
3400 }
3401
3402 s->TCTR = curr_tick;
3403
3404 // DEBUG_PRINT(("RTL8139: >>> timer: tick=%08u\n", s->TCTR));
3405
3406 if (is_timeout)
3407 {
3408 DEBUG_PRINT(("RTL8139: >>> timer: timeout tick=%08u\n", s->TCTR));
3409 s->IntrStatus |= PCSTimeout;
3410 rtl8139_update_irq(s);
3411 }
3412
3413 qemu_mod_timer(s->timer,
3414 rtl8139_get_next_tctr_time(s,curr_time));
3415 }
3416 #endif /* RTL8139_ONBOARD_TIMER */
3417
3418 static void rtl8139_cleanup(VLANClientState *vc)
3419 {
3420 RTL8139State *s = vc->opaque;
3421
3422 if (s->cplus_txbuffer) {
3423 qemu_free(s->cplus_txbuffer);
3424 s->cplus_txbuffer = NULL;
3425 }
3426
3427 #ifdef RTL8139_ONBOARD_TIMER
3428 qemu_del_timer(s->timer);
3429 qemu_free_timer(s->timer);
3430 #endif
3431
3432 unregister_savevm("rtl8139", s);
3433 }
3434
3435 static int pci_rtl8139_uninit(PCIDevice *dev)
3436 {
3437 PCIRTL8139State *d = (PCIRTL8139State *)dev;
3438 RTL8139State *s = &d->rtl8139;
3439
3440 cpu_unregister_io_memory(s->rtl8139_mmio_io_addr);
3441
3442 return 0;
3443 }
3444
3445 static void pci_rtl8139_init(PCIDevice *dev)
3446 {
3447 PCIRTL8139State *d = (PCIRTL8139State *)dev;
3448 RTL8139State *s;
3449 uint8_t *pci_conf;
3450
3451 d->dev.unregister = pci_rtl8139_uninit;
3452
3453 pci_conf = d->dev.config;
3454 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_REALTEK);
3455 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_REALTEK_8139);
3456 pci_conf[0x04] = 0x05; /* command = I/O space, Bus Master */
3457 pci_conf[0x08] = RTL8139_PCI_REVID; /* PCI revision ID; >=0x20 is for 8139C+ */
3458 pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
3459 pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; /* header_type */
3460 pci_conf[0x3d] = 1; /* interrupt pin 0 */
3461 pci_conf[0x34] = 0xdc;
3462
3463 s = &d->rtl8139;
3464
3465 /* I/O handler for memory-mapped I/O */
3466 s->rtl8139_mmio_io_addr =
3467 cpu_register_io_memory(0, rtl8139_mmio_read, rtl8139_mmio_write, s);
3468
3469 pci_register_io_region(&d->dev, 0, 0x100,
3470 PCI_ADDRESS_SPACE_IO, rtl8139_ioport_map);
3471
3472 pci_register_io_region(&d->dev, 1, 0x100,
3473 PCI_ADDRESS_SPACE_MEM, rtl8139_mmio_map);
3474
3475 s->pci_dev = (PCIDevice *)d;
3476 qdev_get_macaddr(&dev->qdev, s->macaddr);
3477 qemu_register_reset(rtl8139_reset, 0, s);
3478 rtl8139_reset(s);
3479 s->vc = qdev_get_vlan_client(&dev->qdev,
3480 rtl8139_receive, rtl8139_can_receive,
3481 rtl8139_cleanup, s);
3482
3483 qemu_format_nic_info_str(s->vc, s->macaddr);
3484
3485 s->cplus_txbuffer = NULL;
3486 s->cplus_txbuffer_len = 0;
3487 s->cplus_txbuffer_offset = 0;
3488
3489 register_savevm("rtl8139", -1, 4, rtl8139_save, rtl8139_load, s);
3490
3491 #ifdef RTL8139_ONBOARD_TIMER
3492 s->timer = qemu_new_timer(vm_clock, rtl8139_timer, s);
3493
3494 qemu_mod_timer(s->timer,
3495 rtl8139_get_next_tctr_time(s,qemu_get_clock(vm_clock)));
3496 #endif /* RTL8139_ONBOARD_TIMER */
3497 }
3498
3499 static void rtl8139_register_devices(void)
3500 {
3501 pci_qdev_register("rtl8139", sizeof(PCIRTL8139State), pci_rtl8139_init);
3502 }
3503
3504 device_init(rtl8139_register_devices)
QEmu