target-arm: Handle UNDEF and UNPREDICTABLE cases for VLDM, VSTM
[qemu.git] / tests / lm32 / macros.inc
blob367c7c50d83963ef9e51d212881e1b11c8d8f651
2 .macro test_name name
3         .data
4 tn_\name:
5         .asciz "\name"
6         .text
7         mvhi r13, hi(tn_\name)
8         ori r13, r13, lo(tn_\name)
9         sw (r12+8), r13
10 .endm
12 .macro load reg val
13         mvhi \reg, hi(\val)
14         ori \reg, \reg, lo(\val)
15 .endm
17 .macro tc_pass
18         mvi r13, 0
19         sw (r12+4), r13
20 .endm
22 .macro tc_fail
23         mvi r13, 1
24         sw (r12+4), r13
25 .endm
27 .macro check_r3 val
28         mvhi r13, hi(\val)
29         ori r13, r13, lo(\val)
30         be r3, r13, 1f
31         tc_fail
32         bi 2f
34         tc_pass
36 .endm
38 .macro check_mem adr val
39         mvhi r13, hi(\adr)
40         ori r13, r13, lo(\adr)
41         mvhi r14, hi(\val)
42         ori r14, r14, lo(\val)
43         lw r13, (r13+0)
44         be r13, r14, 1f
45         tc_fail
46         bi 2f
48         tc_pass
50 .endm
52 .macro check_excp excp
53         andi r13, r25, \excp
54         bne r13, r0, 1f
55         tc_fail
56         bi 2f
58         tc_pass
60 .endm
62 .macro start
63         .global _main
64         .text
65 _main:
66         mvhi r12, hi(0xffff0000)      # base address of test block
67         ori r12, r12, lo(0xffff0000)
68 .endm
70 .macro end
71         sw (r12+0), r0
73         bi 1b
74 .endm
76 # base +
77 #  0  ctrl
78 #  4  pass/fail
79 #  8  ptr to test name