target-arm: Handle UNDEF and UNPREDICTABLE cases for VLDM, VSTM
[qemu.git] / tests / cris / check_ret.s
blobb44fb25933ae7eb31248c9a4a9c9ed8338889ef1
1 # mach: crisv3 crisv8 crisv10
2 # output: 3\n
4 # Test that ret works.
6 .include "testutils.inc"
7 start
8 x:
9 moveq 0,r3
10 jsr z
12 quit
14 addq 1,r3
15 checkr3 3
16 quit
19 addq 1,r3
20 move srp,r2
21 add.d y-w,r2
22 move r2,srp
23 ret
24 addq 1,r3
25 quit