target-arm: Handle UNDEF and UNPREDICTABLE cases for VLDM, VSTM
[qemu.git] / tests / cris / check_cmpm.s
blobe4dde15b32e9fee5c120a609ee8912251772fead
1 # mach: crisv0 crisv3 crisv8 crisv10 crisv32
2 # output: ffffffff\n2\nffff\nffffffff\n78134452\nffffffff\n2\nffff\nfedaffff\n78134452\nffffffff\n2\nff\nfeda49ff\n78134452\n85649222\n
4 .include "testutils.inc"
5 .data
6 x:
7 .dword -2,1,-0xffff,1,-0x5432f789
8 .word -2,1,1,0x877
9 .byte -2,1,0x77
10 .byte 0x22
12 start
13 moveq -1,r3
14 move.d x,r5
15 cmp.d [r5+],r3
16 test_cc 0 0 0 0
17 checkr3 ffffffff
19 moveq 2,r3
20 cmp.d [r5],r3
21 test_cc 0 0 0 0
22 addq 4,r5
23 checkr3 2
25 move.d 0xffff,r3
26 cmp.d [r5+],r3
27 test_cc 0 0 0 1
28 checkr3 ffff
30 moveq -1,r3
31 cmp.d [r5+],r3
32 test_cc 1 0 0 0
33 checkr3 ffffffff
35 move.d 0x78134452,r3
36 cmp.d [r5+],r3
37 test_cc 1 0 1 1
38 checkr3 78134452
40 moveq -1,r3
41 cmp.w [r5+],r3
42 test_cc 0 0 0 0
43 checkr3 ffffffff
45 moveq 2,r3
46 cmp.w [r5+],r3
47 test_cc 0 0 0 0
48 checkr3 2
50 move.d 0xffff,r3
51 cmp.w [r5],r3
52 test_cc 1 0 0 0
53 checkr3 ffff
55 move.d 0xfedaffff,r3
56 cmp.w [r5+],r3
57 test_cc 1 0 0 0
58 checkr3 fedaffff
60 move.d 0x78134452,r3
61 cmp.w [r5+],r3
62 test_cc 0 0 0 0
63 checkr3 78134452
65 moveq -1,r3
66 cmp.b [r5],r3
67 test_cc 0 0 0 0
68 addq 1,r5
69 checkr3 ffffffff
71 moveq 2,r3
72 cmp.b [r5],r3
73 test_cc 0 0 0 0
74 checkr3 2
76 move.d 0xff,r3
77 cmp.b [r5],r3
78 test_cc 1 0 0 0
79 checkr3 ff
81 move.d 0xfeda49ff,r3
82 cmp.b [r5+],r3
83 test_cc 1 0 0 0
84 checkr3 feda49ff
86 move.d 0x78134452,r3
87 cmp.b [r5+],r3
88 test_cc 1 0 0 1
89 checkr3 78134452
91 move.d 0x85649222,r3
92 cmp.b [r5],r3
93 test_cc 0 1 0 0
94 checkr3 85649222
96 quit