target-arm/kvm32.c

   1 /*
   2  * ARM implementation of KVM hooks, 32 bit specific code.
   3  *
   4  * Copyright Christoffer Dall 2009-2010
   5  *
   6  * This work is licensed under the terms of the GNU GPL, version 2 or later.
   7  * See the COPYING file in the top-level directory.
   8  *
   9  */
  10
  11 #include <stdio.h>
  12 #include <sys/types.h>
  13 #include <sys/ioctl.h>
  14 #include <sys/mman.h>
  15
  16 #include <linux/kvm.h>
  17
  18 #include "qemu-common.h"
  19 #include "qemu/timer.h"
  20 #include "sysemu/sysemu.h"
  21 #include "sysemu/kvm.h"
  22 #include "kvm_arm.h"
  23 #include "cpu.h"
  24 #include "internals.h"
  25 #include "hw/arm/arm.h"
  26
  27 static inline void set_feature(uint64_t *features, int feature)
  28 {
  29     *features |= 1ULL << feature;
  30 }
  31
  32 bool kvm_arm_get_host_cpu_features(ARMHostCPUClass *ahcc)
  33 {
  34     /* Identify the feature bits corresponding to the host CPU, and
  35      * fill out the ARMHostCPUClass fields accordingly. To do this
  36      * we have to create a scratch VM, create a single CPU inside it,
  37      * and then query that CPU for the relevant ID registers.
  38      */
  39     int i, ret, fdarray[3];
  40     uint32_t midr, id_pfr0, id_isar0, mvfr1;
  41     uint64_t features = 0;
  42     /* Old kernels may not know about the PREFERRED_TARGET ioctl: however
  43      * we know these will only support creating one kind of guest CPU,
  44      * which is its preferred CPU type.
  45      */
  46     static const uint32_t cpus_to_try[] = {
  47         QEMU_KVM_ARM_TARGET_CORTEX_A15,
  48         QEMU_KVM_ARM_TARGET_NONE
  49     };
  50     struct kvm_vcpu_init init;
  51     struct kvm_one_reg idregs[] = {
  52         {
  53             .id = KVM_REG_ARM | KVM_REG_SIZE_U32
  54             | ENCODE_CP_REG(15, 0, 0, 0, 0, 0),
  55             .addr = (uintptr_t)&midr,
  56         },
  57         {
  58             .id = KVM_REG_ARM | KVM_REG_SIZE_U32
  59             | ENCODE_CP_REG(15, 0, 0, 1, 0, 0),
  60             .addr = (uintptr_t)&id_pfr0,
  61         },
  62         {
  63             .id = KVM_REG_ARM | KVM_REG_SIZE_U32
  64             | ENCODE_CP_REG(15, 0, 0, 2, 0, 0),
  65             .addr = (uintptr_t)&id_isar0,
  66         },
  67         {
  68             .id = KVM_REG_ARM | KVM_REG_SIZE_U32
  69             | KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR1,
  70             .addr = (uintptr_t)&mvfr1,
  71         },
  72     };
  73
  74     if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) {
  75         return false;
  76     }
  77
  78     ahcc->target = init.target;
  79
  80     /* This is not strictly blessed by the device tree binding docs yet,
  81      * but in practice the kernel does not care about this string so
  82      * there is no point maintaining an KVM_ARM_TARGET_* -> string table.
  83      */
  84     ahcc->dtb_compatible = "arm,arm-v7";
  85
  86     for (i = 0; i < ARRAY_SIZE(idregs); i++) {
  87         ret = ioctl(fdarray[2], KVM_GET_ONE_REG, &idregs[i]);
  88         if (ret) {
  89             break;
  90         }
  91     }
  92
  93     kvm_arm_destroy_scratch_host_vcpu(fdarray);
  94
  95     if (ret) {
  96         return false;
  97     }
  98
  99     /* Now we've retrieved all the register information we can
 100      * set the feature bits based on the ID register fields.
 101      * We can assume any KVM supporting CPU is at least a v7
 102      * with VFPv3, LPAE and the generic timers; this in turn implies
 103      * most of the other feature bits, but a few must be tested.
 104      */
 105     set_feature(&features, ARM_FEATURE_V7);
 106     set_feature(&features, ARM_FEATURE_VFP3);
 107     set_feature(&features, ARM_FEATURE_LPAE);
 108     set_feature(&features, ARM_FEATURE_GENERIC_TIMER);
 109
 110     switch (extract32(id_isar0, 24, 4)) {
 111     case 1:
 112         set_feature(&features, ARM_FEATURE_THUMB_DIV);
 113         break;
 114     case 2:
 115         set_feature(&features, ARM_FEATURE_ARM_DIV);
 116         set_feature(&features, ARM_FEATURE_THUMB_DIV);
 117         break;
 118     default:
 119         break;
 120     }
 121
 122     if (extract32(id_pfr0, 12, 4) == 1) {
 123         set_feature(&features, ARM_FEATURE_THUMB2EE);
 124     }
 125     if (extract32(mvfr1, 20, 4) == 1) {
 126         set_feature(&features, ARM_FEATURE_VFP_FP16);
 127     }
 128     if (extract32(mvfr1, 12, 4) == 1) {
 129         set_feature(&features, ARM_FEATURE_NEON);
 130     }
 131     if (extract32(mvfr1, 28, 4) == 1) {
 132         /* FMAC support implies VFPv4 */
 133         set_feature(&features, ARM_FEATURE_VFP4);
 134     }
 135
 136     ahcc->features = features;
 137
 138     return true;
 139 }
 140
 141 static bool reg_syncs_via_tuple_list(uint64_t regidx)
 142 {
 143     /* Return true if the regidx is a register we should synchronize
 144      * via the cpreg_tuples array (ie is not a core reg we sync by
 145      * hand in kvm_arch_get/put_registers())
 146      */
 147     switch (regidx & KVM_REG_ARM_COPROC_MASK) {
 148     case KVM_REG_ARM_CORE:
 149     case KVM_REG_ARM_VFP:
 150         return false;
 151     default:
 152         return true;
 153     }
 154 }
 155
 156 static int compare_u64(const void *a, const void *b)
 157 {
 158     if (*(uint64_t *)a > *(uint64_t *)b) {
 159         return 1;
 160     }
 161     if (*(uint64_t *)a < *(uint64_t *)b) {
 162         return -1;
 163     }
 164     return 0;
 165 }
 166
 167 int kvm_arch_init_vcpu(CPUState *cs)
 168 {
 169     int i, ret, arraylen;
 170     uint64_t v;
 171     struct kvm_one_reg r;
 172     struct kvm_reg_list rl;
 173     struct kvm_reg_list *rlp;
 174     ARMCPU *cpu = ARM_CPU(cs);
 175
 176     if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE) {
 177         fprintf(stderr, "KVM is not supported for this guest CPU type\n");
 178         return -EINVAL;
 179     }
 180
 181     /* Determine init features for this CPU */
 182     memset(cpu->kvm_init_features, 0, sizeof(cpu->kvm_init_features));
 183     if (cpu->start_powered_off) {
 184         cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_POWER_OFF;
 185     }
 186
 187     /* Do KVM_ARM_VCPU_INIT ioctl */
 188     ret = kvm_arm_vcpu_init(cs);
 189     if (ret) {
 190         return ret;
 191     }
 192
 193     /* Query the kernel to make sure it supports 32 VFP
 194      * registers: QEMU's "cortex-a15" CPU is always a
 195      * VFP-D32 core. The simplest way to do this is just
 196      * to attempt to read register d31.
 197      */
 198     r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP | 31;
 199     r.addr = (uintptr_t)(&v);
 200     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
 201     if (ret == -ENOENT) {
 202         return -EINVAL;
 203     }
 204
 205     /* Populate the cpreg list based on the kernel's idea
 206      * of what registers exist (and throw away the TCG-created list).
 207      */
 208     rl.n = 0;
 209     ret = kvm_vcpu_ioctl(cs, KVM_GET_REG_LIST, &rl);
 210     if (ret != -E2BIG) {
 211         return ret;
 212     }
 213     rlp = g_malloc(sizeof(struct kvm_reg_list) + rl.n * sizeof(uint64_t));
 214     rlp->n = rl.n;
 215     ret = kvm_vcpu_ioctl(cs, KVM_GET_REG_LIST, rlp);
 216     if (ret) {
 217         goto out;
 218     }
 219     /* Sort the list we get back from the kernel, since cpreg_tuples
 220      * must be in strictly ascending order.
 221      */
 222     qsort(&rlp->reg, rlp->n, sizeof(rlp->reg[0]), compare_u64);
 223
 224     for (i = 0, arraylen = 0; i < rlp->n; i++) {
 225         if (!reg_syncs_via_tuple_list(rlp->reg[i])) {
 226             continue;
 227         }
 228         switch (rlp->reg[i] & KVM_REG_SIZE_MASK) {
 229         case KVM_REG_SIZE_U32:
 230         case KVM_REG_SIZE_U64:
 231             break;
 232         default:
 233             fprintf(stderr, "Can't handle size of register in kernel list\n");
 234             ret = -EINVAL;
 235             goto out;
 236         }
 237
 238         arraylen++;
 239     }
 240
 241     cpu->cpreg_indexes = g_renew(uint64_t, cpu->cpreg_indexes, arraylen);
 242     cpu->cpreg_values = g_renew(uint64_t, cpu->cpreg_values, arraylen);
 243     cpu->cpreg_vmstate_indexes = g_renew(uint64_t, cpu->cpreg_vmstate_indexes,
 244                                          arraylen);
 245     cpu->cpreg_vmstate_values = g_renew(uint64_t, cpu->cpreg_vmstate_values,
 246                                         arraylen);
 247     cpu->cpreg_array_len = arraylen;
 248     cpu->cpreg_vmstate_array_len = arraylen;
 249
 250     for (i = 0, arraylen = 0; i < rlp->n; i++) {
 251         uint64_t regidx = rlp->reg[i];
 252         if (!reg_syncs_via_tuple_list(regidx)) {
 253             continue;
 254         }
 255         cpu->cpreg_indexes[arraylen] = regidx;
 256         arraylen++;
 257     }
 258     assert(cpu->cpreg_array_len == arraylen);
 259
 260     if (!write_kvmstate_to_list(cpu)) {
 261         /* Shouldn't happen unless kernel is inconsistent about
 262          * what registers exist.
 263          */
 264         fprintf(stderr, "Initial read of kernel register state failed\n");
 265         ret = -EINVAL;
 266         goto out;
 267     }
 268
 269     /* Save a copy of the initial register values so that we can
 270      * feed it back to the kernel on VCPU reset.
 271      */
 272     cpu->cpreg_reset_values = g_memdup(cpu->cpreg_values,
 273                                        cpu->cpreg_array_len *
 274                                        sizeof(cpu->cpreg_values[0]));
 275
 276 out:
 277     g_free(rlp);
 278     return ret;
 279 }
 280
 281 typedef struct Reg {
 282     uint64_t id;
 283     int offset;
 284 } Reg;
 285
 286 #define COREREG(KERNELNAME, QEMUFIELD)                       \
 287     {                                                        \
 288         KVM_REG_ARM | KVM_REG_SIZE_U32 |                     \
 289         KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(KERNELNAME), \
 290         offsetof(CPUARMState, QEMUFIELD)                     \
 291     }
 292
 293 #define VFPSYSREG(R)                                       \
 294     {                                                      \
 295         KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP | \
 296         KVM_REG_ARM_VFP_##R,                               \
 297         offsetof(CPUARMState, vfp.xregs[ARM_VFP_##R])      \
 298     }
 299
 300 /* Like COREREG, but handle fields which are in a uint64_t in CPUARMState. */
 301 #define COREREG64(KERNELNAME, QEMUFIELD)                     \
 302     {                                                        \
 303         KVM_REG_ARM | KVM_REG_SIZE_U32 |                     \
 304         KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(KERNELNAME), \
 305         offsetoflow32(CPUARMState, QEMUFIELD)                \
 306     }
 307
 308 static const Reg regs[] = {
 309     /* R0_usr .. R14_usr */
 310     COREREG(usr_regs.uregs[0], regs[0]),
 311     COREREG(usr_regs.uregs[1], regs[1]),
 312     COREREG(usr_regs.uregs[2], regs[2]),
 313     COREREG(usr_regs.uregs[3], regs[3]),
 314     COREREG(usr_regs.uregs[4], regs[4]),
 315     COREREG(usr_regs.uregs[5], regs[5]),
 316     COREREG(usr_regs.uregs[6], regs[6]),
 317     COREREG(usr_regs.uregs[7], regs[7]),
 318     COREREG(usr_regs.uregs[8], usr_regs[0]),
 319     COREREG(usr_regs.uregs[9], usr_regs[1]),
 320     COREREG(usr_regs.uregs[10], usr_regs[2]),
 321     COREREG(usr_regs.uregs[11], usr_regs[3]),
 322     COREREG(usr_regs.uregs[12], usr_regs[4]),
 323     COREREG(usr_regs.uregs[13], banked_r13[0]),
 324     COREREG(usr_regs.uregs[14], banked_r14[0]),
 325     /* R13, R14, SPSR for SVC, ABT, UND, IRQ banks */
 326     COREREG(svc_regs[0], banked_r13[1]),
 327     COREREG(svc_regs[1], banked_r14[1]),
 328     COREREG64(svc_regs[2], banked_spsr[1]),
 329     COREREG(abt_regs[0], banked_r13[2]),
 330     COREREG(abt_regs[1], banked_r14[2]),
 331     COREREG64(abt_regs[2], banked_spsr[2]),
 332     COREREG(und_regs[0], banked_r13[3]),
 333     COREREG(und_regs[1], banked_r14[3]),
 334     COREREG64(und_regs[2], banked_spsr[3]),
 335     COREREG(irq_regs[0], banked_r13[4]),
 336     COREREG(irq_regs[1], banked_r14[4]),
 337     COREREG64(irq_regs[2], banked_spsr[4]),
 338     /* R8_fiq .. R14_fiq and SPSR_fiq */
 339     COREREG(fiq_regs[0], fiq_regs[0]),
 340     COREREG(fiq_regs[1], fiq_regs[1]),
 341     COREREG(fiq_regs[2], fiq_regs[2]),
 342     COREREG(fiq_regs[3], fiq_regs[3]),
 343     COREREG(fiq_regs[4], fiq_regs[4]),
 344     COREREG(fiq_regs[5], banked_r13[5]),
 345     COREREG(fiq_regs[6], banked_r14[5]),
 346     COREREG64(fiq_regs[7], banked_spsr[5]),
 347     /* R15 */
 348     COREREG(usr_regs.uregs[15], regs[15]),
 349     /* VFP system registers */
 350     VFPSYSREG(FPSID),
 351     VFPSYSREG(MVFR1),
 352     VFPSYSREG(MVFR0),
 353     VFPSYSREG(FPEXC),
 354     VFPSYSREG(FPINST),
 355     VFPSYSREG(FPINST2),
 356 };
 357
 358 int kvm_arch_put_registers(CPUState *cs, int level)
 359 {
 360     ARMCPU *cpu = ARM_CPU(cs);
 361     CPUARMState *env = &cpu->env;
 362     struct kvm_one_reg r;
 363     int mode, bn;
 364     int ret, i;
 365     uint32_t cpsr, fpscr;
 366
 367     /* Make sure the banked regs are properly set */
 368     mode = env->uncached_cpsr & CPSR_M;
 369     bn = bank_number(mode);
 370     if (mode == ARM_CPU_MODE_FIQ) {
 371         memcpy(env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
 372     } else {
 373         memcpy(env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
 374     }
 375     env->banked_r13[bn] = env->regs[13];
 376     env->banked_r14[bn] = env->regs[14];
 377     env->banked_spsr[bn] = env->spsr;
 378
 379     /* Now we can safely copy stuff down to the kernel */
 380     for (i = 0; i < ARRAY_SIZE(regs); i++) {
 381         r.id = regs[i].id;
 382         r.addr = (uintptr_t)(env) + regs[i].offset;
 383         ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
 384         if (ret) {
 385             return ret;
 386         }
 387     }
 388
 389     /* Special cases which aren't a single CPUARMState field */
 390     cpsr = cpsr_read(env);
 391     r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 |
 392         KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(usr_regs.ARM_cpsr);
 393     r.addr = (uintptr_t)(&cpsr);
 394     ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
 395     if (ret) {
 396         return ret;
 397     }
 398
 399     /* VFP registers */
 400     r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP;
 401     for (i = 0; i < 32; i++) {
 402         r.addr = (uintptr_t)(&env->vfp.regs[i]);
 403         ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
 404         if (ret) {
 405             return ret;
 406         }
 407         r.id++;
 408     }
 409
 410     r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP |
 411         KVM_REG_ARM_VFP_FPSCR;
 412     fpscr = vfp_get_fpscr(env);
 413     r.addr = (uintptr_t)&fpscr;
 414     ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
 415     if (ret) {
 416         return ret;
 417     }
 418
 419     /* Note that we do not call write_cpustate_to_list()
 420      * here, so we are only writing the tuple list back to
 421      * KVM. This is safe because nothing can change the
 422      * CPUARMState cp15 fields (in particular gdb accesses cannot)
 423      * and so there are no changes to sync. In fact syncing would
 424      * be wrong at this point: for a constant register where TCG and
 425      * KVM disagree about its value, the preceding write_list_to_cpustate()
 426      * would not have had any effect on the CPUARMState value (since the
 427      * register is read-only), and a write_cpustate_to_list() here would
 428      * then try to write the TCG value back into KVM -- this would either
 429      * fail or incorrectly change the value the guest sees.
 430      *
 431      * If we ever want to allow the user to modify cp15 registers via
 432      * the gdb stub, we would need to be more clever here (for instance
 433      * tracking the set of registers kvm_arch_get_registers() successfully
 434      * managed to update the CPUARMState with, and only allowing those
 435      * to be written back up into the kernel).
 436      */
 437     if (!write_list_to_kvmstate(cpu)) {
 438         return EINVAL;
 439     }
 440
 441     return ret;
 442 }
 443
 444 int kvm_arch_get_registers(CPUState *cs)
 445 {
 446     ARMCPU *cpu = ARM_CPU(cs);
 447     CPUARMState *env = &cpu->env;
 448     struct kvm_one_reg r;
 449     int mode, bn;
 450     int ret, i;
 451     uint32_t cpsr, fpscr;
 452
 453     for (i = 0; i < ARRAY_SIZE(regs); i++) {
 454         r.id = regs[i].id;
 455         r.addr = (uintptr_t)(env) + regs[i].offset;
 456         ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
 457         if (ret) {
 458             return ret;
 459         }
 460     }
 461
 462     /* Special cases which aren't a single CPUARMState field */
 463     r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 |
 464         KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(usr_regs.ARM_cpsr);
 465     r.addr = (uintptr_t)(&cpsr);
 466     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
 467     if (ret) {
 468         return ret;
 469     }
 470     cpsr_write(env, cpsr, 0xffffffff);
 471
 472     /* Make sure the current mode regs are properly set */
 473     mode = env->uncached_cpsr & CPSR_M;
 474     bn = bank_number(mode);
 475     if (mode == ARM_CPU_MODE_FIQ) {
 476         memcpy(env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
 477     } else {
 478         memcpy(env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
 479     }
 480     env->regs[13] = env->banked_r13[bn];
 481     env->regs[14] = env->banked_r14[bn];
 482     env->spsr = env->banked_spsr[bn];
 483
 484     /* VFP registers */
 485     r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP;
 486     for (i = 0; i < 32; i++) {
 487         r.addr = (uintptr_t)(&env->vfp.regs[i]);
 488         ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
 489         if (ret) {
 490             return ret;
 491         }
 492         r.id++;
 493     }
 494
 495     r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP |
 496         KVM_REG_ARM_VFP_FPSCR;
 497     r.addr = (uintptr_t)&fpscr;
 498     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
 499     if (ret) {
 500         return ret;
 501     }
 502     vfp_set_fpscr(env, fpscr);
 503
 504     if (!write_kvmstate_to_list(cpu)) {
 505         return EINVAL;
 506     }
 507     /* Note that it's OK to have registers which aren't in CPUState,
 508      * so we can ignore a failure return here.
 509      */
 510     write_list_to_cpustate(cpu);
 511
 512     return 0;
 513 }
 514
 515 void kvm_arm_reset_vcpu(ARMCPU *cpu)
 516 {
 517     /* Feed the kernel back its initial register state */
 518     memmove(cpu->cpreg_values, cpu->cpreg_reset_values,
 519             cpu->cpreg_array_len * sizeof(cpu->cpreg_values[0]));
 520
 521     if (!write_list_to_kvmstate(cpu)) {
 522         abort();
 523     }
 524 }