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m25p80: add support for two bytes WRSR for Macronix chips
[qemu.git] / hw / block / m25p80.c
blobb0ed8fa41887040de848c8d3cb7de2ecdd5459fe
1 /*
2 * ST M25P80 emulator. Emulate all SPI flash devices based on the m25p80 command
3 * set. Known devices table current as of Jun/2012 and taken from linux.
4 * See drivers/mtd/devices/m25p80.c.
5 *
6 * Copyright (C) 2011 Edgar E. Iglesias <edgar.iglesias@gmail.com>
7 * Copyright (C) 2012 Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
8 * Copyright (C) 2012 PetaLogix
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 or
13 * (at your option) a later version of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, see <http://www.gnu.org/licenses/>.
22 */
23
24 #include "qemu/osdep.h"
25 #include "hw/hw.h"
26 #include "sysemu/block-backend.h"
27 #include "hw/ssi/ssi.h"
28 #include "qemu/bitops.h"
29 #include "qemu/log.h"
30 #include "qemu/error-report.h"
31 #include "qapi/error.h"
32
33 #ifndef M25P80_ERR_DEBUG
34 #define M25P80_ERR_DEBUG 0
35 #endif
36
37 #define DB_PRINT_L(level, ...) do { \
38 if (M25P80_ERR_DEBUG > (level)) { \
39 fprintf(stderr, ": %s: ", __func__); \
40 fprintf(stderr, ## __VA_ARGS__); \
41 } \
42 } while (0)
43
44 /* Fields for FlashPartInfo->flags */
45
46 /* erase capabilities */
47 #define ER_4K 1
48 #define ER_32K 2
49 /* set to allow the page program command to write 0s back to 1. Useful for
50 * modelling EEPROM with SPI flash command set
51 */
52 #define EEPROM 0x100
53
54 /* 16 MiB max in 3 byte address mode */
55 #define MAX_3BYTES_SIZE 0x1000000
56
57 #define SPI_NOR_MAX_ID_LEN 6
58
59 typedef struct FlashPartInfo {
60 const char *part_name;
61 /*
62 * This array stores the ID bytes.
63 * The first three bytes are the JEDIC ID.
64 * JEDEC ID zero means "no ID" (mostly older chips).
65 */
66 uint8_t id[SPI_NOR_MAX_ID_LEN];
67 uint8_t id_len;
68 /* there is confusion between manufacturers as to what a sector is. In this
69 * device model, a "sector" is the size that is erased by the ERASE_SECTOR
70 * command (opcode 0xd8).
71 */
72 uint32_t sector_size;
73 uint32_t n_sectors;
74 uint32_t page_size;
75 uint16_t flags;
76 /*
77 * Big sized spi nor are often stacked devices, thus sometime
78 * replace chip erase with die erase.
79 * This field inform how many die is in the chip.
80 */
81 uint8_t die_cnt;
82 } FlashPartInfo;
83
84 /* adapted from linux */
85 /* Used when the "_ext_id" is two bytes at most */
86 #define INFO(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\
87 .part_name = _part_name,\
88 .id = {\
89 ((_jedec_id) >> 16) & 0xff,\
90 ((_jedec_id) >> 8) & 0xff,\
91 (_jedec_id) & 0xff,\
92 ((_ext_id) >> 8) & 0xff,\
93 (_ext_id) & 0xff,\
94 },\
95 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),\
96 .sector_size = (_sector_size),\
97 .n_sectors = (_n_sectors),\
98 .page_size = 256,\
99 .flags = (_flags),\
100 .die_cnt = 0
101
102 #define INFO6(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\
103 .part_name = _part_name,\
104 .id = {\
105 ((_jedec_id) >> 16) & 0xff,\
106 ((_jedec_id) >> 8) & 0xff,\
107 (_jedec_id) & 0xff,\
108 ((_ext_id) >> 16) & 0xff,\
109 ((_ext_id) >> 8) & 0xff,\
110 (_ext_id) & 0xff,\
111 },\
112 .id_len = 6,\
113 .sector_size = (_sector_size),\
114 .n_sectors = (_n_sectors),\
115 .page_size = 256,\
116 .flags = (_flags),\
117 .die_cnt = 0
118
119 #define INFO_STACKED(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors,\
120 _flags, _die_cnt)\
121 .part_name = _part_name,\
122 .id = {\
123 ((_jedec_id) >> 16) & 0xff,\
124 ((_jedec_id) >> 8) & 0xff,\
125 (_jedec_id) & 0xff,\
126 ((_ext_id) >> 8) & 0xff,\
127 (_ext_id) & 0xff,\
128 },\
129 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),\
130 .sector_size = (_sector_size),\
131 .n_sectors = (_n_sectors),\
132 .page_size = 256,\
133 .flags = (_flags),\
134 .die_cnt = _die_cnt
135
136 #define JEDEC_NUMONYX 0x20
137 #define JEDEC_WINBOND 0xEF
138 #define JEDEC_SPANSION 0x01
139
140 /* Numonyx (Micron) Configuration register macros */
141 #define VCFG_DUMMY 0x1
142 #define VCFG_WRAP_SEQUENTIAL 0x2
143 #define NVCFG_XIP_MODE_DISABLED (7 << 9)
144 #define NVCFG_XIP_MODE_MASK (7 << 9)
145 #define VCFG_XIP_MODE_ENABLED (1 << 3)
146 #define CFG_DUMMY_CLK_LEN 4
147 #define NVCFG_DUMMY_CLK_POS 12
148 #define VCFG_DUMMY_CLK_POS 4
149 #define EVCFG_OUT_DRIVER_STRENGTH_DEF 7
150 #define EVCFG_VPP_ACCELERATOR (1 << 3)
151 #define EVCFG_RESET_HOLD_ENABLED (1 << 4)
152 #define NVCFG_DUAL_IO_MASK (1 << 2)
153 #define EVCFG_DUAL_IO_ENABLED (1 << 6)
154 #define NVCFG_QUAD_IO_MASK (1 << 3)
155 #define EVCFG_QUAD_IO_ENABLED (1 << 7)
156 #define NVCFG_4BYTE_ADDR_MASK (1 << 0)
157 #define NVCFG_LOWER_SEGMENT_MASK (1 << 1)
158
159 /* Numonyx (Micron) Flag Status Register macros */
160 #define FSR_4BYTE_ADDR_MODE_ENABLED 0x1
161 #define FSR_FLASH_READY (1 << 7)
162
163 /* Spansion configuration registers macros. */
164 #define SPANSION_QUAD_CFG_POS 0
165 #define SPANSION_QUAD_CFG_LEN 1
166 #define SPANSION_DUMMY_CLK_POS 0
167 #define SPANSION_DUMMY_CLK_LEN 4
168 #define SPANSION_ADDR_LEN_POS 7
169 #define SPANSION_ADDR_LEN_LEN 1
170
171 /*
172 * Spansion read mode command length in bytes,
173 * the mode is currently not supported.
174 */
175
176 #define SPANSION_CONTINUOUS_READ_MODE_CMD_LEN 1
177 #define WINBOND_CONTINUOUS_READ_MODE_CMD_LEN 1
178
179 static const FlashPartInfo known_devices[] = {
180 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
181 { INFO("at25fs010", 0x1f6601, 0, 32 << 10, 4, ER_4K) },
182 { INFO("at25fs040", 0x1f6604, 0, 64 << 10, 8, ER_4K) },
183
184 { INFO("at25df041a", 0x1f4401, 0, 64 << 10, 8, ER_4K) },
185 { INFO("at25df321a", 0x1f4701, 0, 64 << 10, 64, ER_4K) },
186 { INFO("at25df641", 0x1f4800, 0, 64 << 10, 128, ER_4K) },
187
188 { INFO("at26f004", 0x1f0400, 0, 64 << 10, 8, ER_4K) },
189 { INFO("at26df081a", 0x1f4501, 0, 64 << 10, 16, ER_4K) },
190 { INFO("at26df161a", 0x1f4601, 0, 64 << 10, 32, ER_4K) },
191 { INFO("at26df321", 0x1f4700, 0, 64 << 10, 64, ER_4K) },
192
193 { INFO("at45db081d", 0x1f2500, 0, 64 << 10, 16, ER_4K) },
194
195 /* Atmel EEPROMS - it is assumed, that don't care bit in command
196 * is set to 0. Block protection is not supported.
197 */
198 { INFO("at25128a-nonjedec", 0x0, 0, 1, 131072, EEPROM) },
199 { INFO("at25256a-nonjedec", 0x0, 0, 1, 262144, EEPROM) },
200
201 /* EON -- en25xxx */
202 { INFO("en25f32", 0x1c3116, 0, 64 << 10, 64, ER_4K) },
203 { INFO("en25p32", 0x1c2016, 0, 64 << 10, 64, 0) },
204 { INFO("en25q32b", 0x1c3016, 0, 64 << 10, 64, 0) },
205 { INFO("en25p64", 0x1c2017, 0, 64 << 10, 128, 0) },
206 { INFO("en25q64", 0x1c3017, 0, 64 << 10, 128, ER_4K) },
207
208 /* GigaDevice */
209 { INFO("gd25q32", 0xc84016, 0, 64 << 10, 64, ER_4K) },
210 { INFO("gd25q64", 0xc84017, 0, 64 << 10, 128, ER_4K) },
211
212 /* Intel/Numonyx -- xxxs33b */
213 { INFO("160s33b", 0x898911, 0, 64 << 10, 32, 0) },
214 { INFO("320s33b", 0x898912, 0, 64 << 10, 64, 0) },
215 { INFO("640s33b", 0x898913, 0, 64 << 10, 128, 0) },
216 { INFO("n25q064", 0x20ba17, 0, 64 << 10, 128, 0) },
217
218 /* Macronix */
219 { INFO("mx25l2005a", 0xc22012, 0, 64 << 10, 4, ER_4K) },
220 { INFO("mx25l4005a", 0xc22013, 0, 64 << 10, 8, ER_4K) },
221 { INFO("mx25l8005", 0xc22014, 0, 64 << 10, 16, 0) },
222 { INFO("mx25l1606e", 0xc22015, 0, 64 << 10, 32, ER_4K) },
223 { INFO("mx25l3205d", 0xc22016, 0, 64 << 10, 64, 0) },
224 { INFO("mx25l6405d", 0xc22017, 0, 64 << 10, 128, 0) },
225 { INFO("mx25l12805d", 0xc22018, 0, 64 << 10, 256, 0) },
226 { INFO("mx25l12855e", 0xc22618, 0, 64 << 10, 256, 0) },
227 { INFO("mx25l25635e", 0xc22019, 0, 64 << 10, 512, 0) },
228 { INFO("mx25l25655e", 0xc22619, 0, 64 << 10, 512, 0) },
229 { INFO("mx66u51235f", 0xc2253a, 0, 64 << 10, 1024, ER_4K | ER_32K) },
230 { INFO("mx66u1g45g", 0xc2253b, 0, 64 << 10, 2048, ER_4K | ER_32K) },
231 { INFO("mx66l1g45g", 0xc2201b, 0, 64 << 10, 2048, ER_4K | ER_32K) },
232
233 /* Micron */
234 { INFO("n25q032a11", 0x20bb16, 0, 64 << 10, 64, ER_4K) },
235 { INFO("n25q032a13", 0x20ba16, 0, 64 << 10, 64, ER_4K) },
236 { INFO("n25q064a11", 0x20bb17, 0, 64 << 10, 128, ER_4K) },
237 { INFO("n25q064a13", 0x20ba17, 0, 64 << 10, 128, ER_4K) },
238 { INFO("n25q128a11", 0x20bb18, 0, 64 << 10, 256, ER_4K) },
239 { INFO("n25q128a13", 0x20ba18, 0, 64 << 10, 256, ER_4K) },
240 { INFO("n25q256a11", 0x20bb19, 0, 64 << 10, 512, ER_4K) },
241 { INFO("n25q256a13", 0x20ba19, 0, 64 << 10, 512, ER_4K) },
242 { INFO("n25q512a11", 0x20bb20, 0, 64 << 10, 1024, ER_4K) },
243 { INFO("n25q512a13", 0x20ba20, 0, 64 << 10, 1024, ER_4K) },
244 { INFO("n25q128", 0x20ba18, 0, 64 << 10, 256, 0) },
245 { INFO("n25q256a", 0x20ba19, 0, 64 << 10, 512, ER_4K) },
246 { INFO("n25q512a", 0x20ba20, 0, 64 << 10, 1024, ER_4K) },
247 { INFO_STACKED("n25q00", 0x20ba21, 0x1000, 64 << 10, 2048, ER_4K, 4) },
248 { INFO_STACKED("n25q00a", 0x20bb21, 0x1000, 64 << 10, 2048, ER_4K, 4) },
249 { INFO_STACKED("mt25ql01g", 0x20ba21, 0x1040, 64 << 10, 2048, ER_4K, 2) },
250 { INFO_STACKED("mt25qu01g", 0x20bb21, 0x1040, 64 << 10, 2048, ER_4K, 2) },
251
252 /* Spansion -- single (large) sector size only, at least
253 * for the chips listed here (without boot sectors).
254 */
255 { INFO("s25sl032p", 0x010215, 0x4d00, 64 << 10, 64, ER_4K) },
256 { INFO("s25sl064p", 0x010216, 0x4d00, 64 << 10, 128, ER_4K) },
257 { INFO("s25fl256s0", 0x010219, 0x4d00, 256 << 10, 128, 0) },
258 { INFO("s25fl256s1", 0x010219, 0x4d01, 64 << 10, 512, 0) },
259 { INFO6("s25fl512s", 0x010220, 0x4d0080, 256 << 10, 256, 0) },
260 { INFO6("s70fl01gs", 0x010221, 0x4d0080, 256 << 10, 512, 0) },
261 { INFO("s25sl12800", 0x012018, 0x0300, 256 << 10, 64, 0) },
262 { INFO("s25sl12801", 0x012018, 0x0301, 64 << 10, 256, 0) },
263 { INFO("s25fl129p0", 0x012018, 0x4d00, 256 << 10, 64, 0) },
264 { INFO("s25fl129p1", 0x012018, 0x4d01, 64 << 10, 256, 0) },
265 { INFO("s25sl004a", 0x010212, 0, 64 << 10, 8, 0) },
266 { INFO("s25sl008a", 0x010213, 0, 64 << 10, 16, 0) },
267 { INFO("s25sl016a", 0x010214, 0, 64 << 10, 32, 0) },
268 { INFO("s25sl032a", 0x010215, 0, 64 << 10, 64, 0) },
269 { INFO("s25sl064a", 0x010216, 0, 64 << 10, 128, 0) },
270 { INFO("s25fl016k", 0xef4015, 0, 64 << 10, 32, ER_4K | ER_32K) },
271 { INFO("s25fl064k", 0xef4017, 0, 64 << 10, 128, ER_4K | ER_32K) },
272
273 /* Spansion -- boot sectors support */
274 { INFO6("s25fs512s", 0x010220, 0x4d0081, 256 << 10, 256, 0) },
275 { INFO6("s70fs01gs", 0x010221, 0x4d0081, 256 << 10, 512, 0) },
276
277 /* SST -- large erase sizes are "overlays", "sectors" are 4<< 10 */
278 { INFO("sst25vf040b", 0xbf258d, 0, 64 << 10, 8, ER_4K) },
279 { INFO("sst25vf080b", 0xbf258e, 0, 64 << 10, 16, ER_4K) },
280 { INFO("sst25vf016b", 0xbf2541, 0, 64 << 10, 32, ER_4K) },
281 { INFO("sst25vf032b", 0xbf254a, 0, 64 << 10, 64, ER_4K) },
282 { INFO("sst25wf512", 0xbf2501, 0, 64 << 10, 1, ER_4K) },
283 { INFO("sst25wf010", 0xbf2502, 0, 64 << 10, 2, ER_4K) },
284 { INFO("sst25wf020", 0xbf2503, 0, 64 << 10, 4, ER_4K) },
285 { INFO("sst25wf040", 0xbf2504, 0, 64 << 10, 8, ER_4K) },
286 { INFO("sst25wf080", 0xbf2505, 0, 64 << 10, 16, ER_4K) },
287
288 /* ST Microelectronics -- newer production may have feature updates */
289 { INFO("m25p05", 0x202010, 0, 32 << 10, 2, 0) },
290 { INFO("m25p10", 0x202011, 0, 32 << 10, 4, 0) },
291 { INFO("m25p20", 0x202012, 0, 64 << 10, 4, 0) },
292 { INFO("m25p40", 0x202013, 0, 64 << 10, 8, 0) },
293 { INFO("m25p80", 0x202014, 0, 64 << 10, 16, 0) },
294 { INFO("m25p16", 0x202015, 0, 64 << 10, 32, 0) },
295 { INFO("m25p32", 0x202016, 0, 64 << 10, 64, 0) },
296 { INFO("m25p64", 0x202017, 0, 64 << 10, 128, 0) },
297 { INFO("m25p128", 0x202018, 0, 256 << 10, 64, 0) },
298 { INFO("n25q032", 0x20ba16, 0, 64 << 10, 64, 0) },
299
300 { INFO("m45pe10", 0x204011, 0, 64 << 10, 2, 0) },
301 { INFO("m45pe80", 0x204014, 0, 64 << 10, 16, 0) },
302 { INFO("m45pe16", 0x204015, 0, 64 << 10, 32, 0) },
303
304 { INFO("m25pe20", 0x208012, 0, 64 << 10, 4, 0) },
305 { INFO("m25pe80", 0x208014, 0, 64 << 10, 16, 0) },
306 { INFO("m25pe16", 0x208015, 0, 64 << 10, 32, ER_4K) },
307
308 { INFO("m25px32", 0x207116, 0, 64 << 10, 64, ER_4K) },
309 { INFO("m25px32-s0", 0x207316, 0, 64 << 10, 64, ER_4K) },
310 { INFO("m25px32-s1", 0x206316, 0, 64 << 10, 64, ER_4K) },
311 { INFO("m25px64", 0x207117, 0, 64 << 10, 128, 0) },
312
313 /* Winbond -- w25x "blocks" are 64k, "sectors" are 4KiB */
314 { INFO("w25x10", 0xef3011, 0, 64 << 10, 2, ER_4K) },
315 { INFO("w25x20", 0xef3012, 0, 64 << 10, 4, ER_4K) },
316 { INFO("w25x40", 0xef3013, 0, 64 << 10, 8, ER_4K) },
317 { INFO("w25x80", 0xef3014, 0, 64 << 10, 16, ER_4K) },
318 { INFO("w25x16", 0xef3015, 0, 64 << 10, 32, ER_4K) },
319 { INFO("w25x32", 0xef3016, 0, 64 << 10, 64, ER_4K) },
320 { INFO("w25q32", 0xef4016, 0, 64 << 10, 64, ER_4K) },
321 { INFO("w25q32dw", 0xef6016, 0, 64 << 10, 64, ER_4K) },
322 { INFO("w25x64", 0xef3017, 0, 64 << 10, 128, ER_4K) },
323 { INFO("w25q64", 0xef4017, 0, 64 << 10, 128, ER_4K) },
324 { INFO("w25q80", 0xef5014, 0, 64 << 10, 16, ER_4K) },
325 { INFO("w25q80bl", 0xef4014, 0, 64 << 10, 16, ER_4K) },
326 { INFO("w25q256", 0xef4019, 0, 64 << 10, 512, ER_4K) },
327 };
328
329 typedef enum {
330 NOP = 0,
331 WRSR = 0x1,
332 WRDI = 0x4,
333 RDSR = 0x5,
334 WREN = 0x6,
335 BRRD = 0x16,
336 BRWR = 0x17,
337 JEDEC_READ = 0x9f,
338 BULK_ERASE_60 = 0x60,
339 BULK_ERASE = 0xc7,
340 READ_FSR = 0x70,
341 RDCR = 0x15,
342
343 READ = 0x03,
344 READ4 = 0x13,
345 FAST_READ = 0x0b,
346 FAST_READ4 = 0x0c,
347 DOR = 0x3b,
348 DOR4 = 0x3c,
349 QOR = 0x6b,
350 QOR4 = 0x6c,
351 DIOR = 0xbb,
352 DIOR4 = 0xbc,
353 QIOR = 0xeb,
354 QIOR4 = 0xec,
355
356 PP = 0x02,
357 PP4 = 0x12,
358 PP4_4 = 0x3e,
359 DPP = 0xa2,
360 QPP = 0x32,
361 QPP_4 = 0x34,
362 RDID_90 = 0x90,
363 RDID_AB = 0xab,
364
365 ERASE_4K = 0x20,
366 ERASE4_4K = 0x21,
367 ERASE_32K = 0x52,
368 ERASE4_32K = 0x5c,
369 ERASE_SECTOR = 0xd8,
370 ERASE4_SECTOR = 0xdc,
371
372 EN_4BYTE_ADDR = 0xB7,
373 EX_4BYTE_ADDR = 0xE9,
374
375 EXTEND_ADDR_READ = 0xC8,
376 EXTEND_ADDR_WRITE = 0xC5,
377
378 RESET_ENABLE = 0x66,
379 RESET_MEMORY = 0x99,
380
381 /*
382 * Micron: 0x35 - enable QPI
383 * Spansion: 0x35 - read control register
384 */
385 RDCR_EQIO = 0x35,
386 RSTQIO = 0xf5,
387
388 RNVCR = 0xB5,
389 WNVCR = 0xB1,
390
391 RVCR = 0x85,
392 WVCR = 0x81,
393
394 REVCR = 0x65,
395 WEVCR = 0x61,
396
397 DIE_ERASE = 0xC4,
398 } FlashCMD;
399
400 typedef enum {
401 STATE_IDLE,
402 STATE_PAGE_PROGRAM,
403 STATE_READ,
404 STATE_COLLECTING_DATA,
405 STATE_COLLECTING_VAR_LEN_DATA,
406 STATE_READING_DATA,
407 } CMDState;
408
409 typedef enum {
410 MAN_SPANSION,
411 MAN_MACRONIX,
412 MAN_NUMONYX,
413 MAN_WINBOND,
414 MAN_SST,
415 MAN_GENERIC,
416 } Manufacturer;
417
418 #define M25P80_INTERNAL_DATA_BUFFER_SZ 16
419
420 typedef struct Flash {
421 SSISlave parent_obj;
422
423 BlockBackend *blk;
424
425 uint8_t *storage;
426 uint32_t size;
427 int page_size;
428
429 uint8_t state;
430 uint8_t data[M25P80_INTERNAL_DATA_BUFFER_SZ];
431 uint32_t len;
432 uint32_t pos;
433 bool data_read_loop;
434 uint8_t needed_bytes;
435 uint8_t cmd_in_progress;
436 uint32_t cur_addr;
437 uint32_t nonvolatile_cfg;
438 /* Configuration register for Macronix */
439 uint32_t volatile_cfg;
440 uint32_t enh_volatile_cfg;
441 /* Spansion cfg registers. */
442 uint8_t spansion_cr1nv;
443 uint8_t spansion_cr2nv;
444 uint8_t spansion_cr3nv;
445 uint8_t spansion_cr4nv;
446 uint8_t spansion_cr1v;
447 uint8_t spansion_cr2v;
448 uint8_t spansion_cr3v;
449 uint8_t spansion_cr4v;
450 bool write_enable;
451 bool four_bytes_address_mode;
452 bool reset_enable;
453 bool quad_enable;
454 uint8_t ear;
455
456 int64_t dirty_page;
457
458 const FlashPartInfo *pi;
459
460 } Flash;
461
462 typedef struct M25P80Class {
463 SSISlaveClass parent_class;
464 FlashPartInfo *pi;
465 } M25P80Class;
466
467 #define TYPE_M25P80 "m25p80-generic"
468 #define M25P80(obj) \
469 OBJECT_CHECK(Flash, (obj), TYPE_M25P80)
470 #define M25P80_CLASS(klass) \
471 OBJECT_CLASS_CHECK(M25P80Class, (klass), TYPE_M25P80)
472 #define M25P80_GET_CLASS(obj) \
473 OBJECT_GET_CLASS(M25P80Class, (obj), TYPE_M25P80)
474
475 static inline Manufacturer get_man(Flash *s)
476 {
477 switch (s->pi->id[0]) {
478 case 0x20:
479 return MAN_NUMONYX;
480 case 0xEF:
481 return MAN_WINBOND;
482 case 0x01:
483 return MAN_SPANSION;
484 case 0xC2:
485 return MAN_MACRONIX;
486 case 0xBF:
487 return MAN_SST;
488 default:
489 return MAN_GENERIC;
490 }
491 }
492
493 static void blk_sync_complete(void *opaque, int ret)
494 {
495 QEMUIOVector *iov = opaque;
496
497 qemu_iovec_destroy(iov);
498 g_free(iov);
499
500 /* do nothing. Masters do not directly interact with the backing store,
501 * only the working copy so no mutexing required.
502 */
503 }
504
505 static void flash_sync_page(Flash *s, int page)
506 {
507 QEMUIOVector *iov;
508
509 if (!s->blk || blk_is_read_only(s->blk)) {
510 return;
511 }
512
513 iov = g_new(QEMUIOVector, 1);
514 qemu_iovec_init(iov, 1);
515 qemu_iovec_add(iov, s->storage + page * s->pi->page_size,
516 s->pi->page_size);
517 blk_aio_pwritev(s->blk, page * s->pi->page_size, iov, 0,
518 blk_sync_complete, iov);
519 }
520
521 static inline void flash_sync_area(Flash *s, int64_t off, int64_t len)
522 {
523 QEMUIOVector *iov;
524
525 if (!s->blk || blk_is_read_only(s->blk)) {
526 return;
527 }
528
529 assert(!(len % BDRV_SECTOR_SIZE));
530 iov = g_new(QEMUIOVector, 1);
531 qemu_iovec_init(iov, 1);
532 qemu_iovec_add(iov, s->storage + off, len);
533 blk_aio_pwritev(s->blk, off, iov, 0, blk_sync_complete, iov);
534 }
535
536 static void flash_erase(Flash *s, int offset, FlashCMD cmd)
537 {
538 uint32_t len;
539 uint8_t capa_to_assert = 0;
540
541 switch (cmd) {
542 case ERASE_4K:
543 case ERASE4_4K:
544 len = 4 << 10;
545 capa_to_assert = ER_4K;
546 break;
547 case ERASE_32K:
548 case ERASE4_32K:
549 len = 32 << 10;
550 capa_to_assert = ER_32K;
551 break;
552 case ERASE_SECTOR:
553 case ERASE4_SECTOR:
554 len = s->pi->sector_size;
555 break;
556 case BULK_ERASE:
557 len = s->size;
558 break;
559 case DIE_ERASE:
560 if (s->pi->die_cnt) {
561 len = s->size / s->pi->die_cnt;
562 offset = offset & (~(len - 1));
563 } else {
564 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: die erase is not supported"
565 " by device\n");
566 return;
567 }
568 break;
569 default:
570 abort();
571 }
572
573 DB_PRINT_L(0, "offset = %#x, len = %d\n", offset, len);
574 if ((s->pi->flags & capa_to_assert) != capa_to_assert) {
575 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: %d erase size not supported by"
576 " device\n", len);
577 }
578
579 if (!s->write_enable) {
580 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: erase with write protect!\n");
581 return;
582 }
583 memset(s->storage + offset, 0xff, len);
584 flash_sync_area(s, offset, len);
585 }
586
587 static inline void flash_sync_dirty(Flash *s, int64_t newpage)
588 {
589 if (s->dirty_page >= 0 && s->dirty_page != newpage) {
590 flash_sync_page(s, s->dirty_page);
591 s->dirty_page = newpage;
592 }
593 }
594
595 static inline
596 void flash_write8(Flash *s, uint32_t addr, uint8_t data)
597 {
598 uint32_t page = addr / s->pi->page_size;
599 uint8_t prev = s->storage[s->cur_addr];
600
601 if (!s->write_enable) {
602 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: write with write protect!\n");
603 }
604
605 if ((prev ^ data) & data) {
606 DB_PRINT_L(1, "programming zero to one! addr=%" PRIx32 " %" PRIx8
607 " -> %" PRIx8 "\n", addr, prev, data);
608 }
609
610 if (s->pi->flags & EEPROM) {
611 s->storage[s->cur_addr] = data;
612 } else {
613 s->storage[s->cur_addr] &= data;
614 }
615
616 flash_sync_dirty(s, page);
617 s->dirty_page = page;
618 }
619
620 static inline int get_addr_length(Flash *s)
621 {
622 /* check if eeprom is in use */
623 if (s->pi->flags == EEPROM) {
624 return 2;
625 }
626
627 switch (s->cmd_in_progress) {
628 case PP4:
629 case PP4_4:
630 case QPP_4:
631 case READ4:
632 case QIOR4:
633 case ERASE4_4K:
634 case ERASE4_32K:
635 case ERASE4_SECTOR:
636 case FAST_READ4:
637 case DOR4:
638 case QOR4:
639 case DIOR4:
640 return 4;
641 default:
642 return s->four_bytes_address_mode ? 4 : 3;
643 }
644 }
645
646 static void complete_collecting_data(Flash *s)
647 {
648 int i, n;
649
650 n = get_addr_length(s);
651 s->cur_addr = (n == 3 ? s->ear : 0);
652 for (i = 0; i < n; ++i) {
653 s->cur_addr <<= 8;
654 s->cur_addr |= s->data[i];
655 }
656
657 s->cur_addr &= s->size - 1;
658
659 s->state = STATE_IDLE;
660
661 switch (s->cmd_in_progress) {
662 case DPP:
663 case QPP:
664 case QPP_4:
665 case PP:
666 case PP4:
667 case PP4_4:
668 s->state = STATE_PAGE_PROGRAM;
669 break;
670 case READ:
671 case READ4:
672 case FAST_READ:
673 case FAST_READ4:
674 case DOR:
675 case DOR4:
676 case QOR:
677 case QOR4:
678 case DIOR:
679 case DIOR4:
680 case QIOR:
681 case QIOR4:
682 s->state = STATE_READ;
683 break;
684 case ERASE_4K:
685 case ERASE4_4K:
686 case ERASE_32K:
687 case ERASE4_32K:
688 case ERASE_SECTOR:
689 case ERASE4_SECTOR:
690 case DIE_ERASE:
691 flash_erase(s, s->cur_addr, s->cmd_in_progress);
692 break;
693 case WRSR:
694 switch (get_man(s)) {
695 case MAN_SPANSION:
696 s->quad_enable = !!(s->data[1] & 0x02);
697 break;
698 case MAN_MACRONIX:
699 s->quad_enable = extract32(s->data[0], 6, 1);
700 if (s->len > 1) {
701 s->volatile_cfg = s->data[1];
702 s->four_bytes_address_mode = extract32(s->data[1], 5, 1);
703 }
704 break;
705 default:
706 break;
707 }
708 if (s->write_enable) {
709 s->write_enable = false;
710 }
711 break;
712 case BRWR:
713 case EXTEND_ADDR_WRITE:
714 s->ear = s->data[0];
715 break;
716 case WNVCR:
717 s->nonvolatile_cfg = s->data[0] | (s->data[1] << 8);
718 break;
719 case WVCR:
720 s->volatile_cfg = s->data[0];
721 break;
722 case WEVCR:
723 s->enh_volatile_cfg = s->data[0];
724 break;
725 case RDID_90:
726 case RDID_AB:
727 if (get_man(s) == MAN_SST) {
728 if (s->cur_addr <= 1) {
729 if (s->cur_addr) {
730 s->data[0] = s->pi->id[2];
731 s->data[1] = s->pi->id[0];
732 } else {
733 s->data[0] = s->pi->id[0];
734 s->data[1] = s->pi->id[2];
735 }
736 s->pos = 0;
737 s->len = 2;
738 s->data_read_loop = true;
739 s->state = STATE_READING_DATA;
740 } else {
741 qemu_log_mask(LOG_GUEST_ERROR,
742 "M25P80: Invalid read id address\n");
743 }
744 } else {
745 qemu_log_mask(LOG_GUEST_ERROR,
746 "M25P80: Read id (command 0x90/0xAB) is not supported"
747 " by device\n");
748 }
749 break;
750 default:
751 break;
752 }
753 }
754
755 static void reset_memory(Flash *s)
756 {
757 s->cmd_in_progress = NOP;
758 s->cur_addr = 0;
759 s->ear = 0;
760 s->four_bytes_address_mode = false;
761 s->len = 0;
762 s->needed_bytes = 0;
763 s->pos = 0;
764 s->state = STATE_IDLE;
765 s->write_enable = false;
766 s->reset_enable = false;
767 s->quad_enable = false;
768
769 switch (get_man(s)) {
770 case MAN_NUMONYX:
771 s->volatile_cfg = 0;
772 s->volatile_cfg |= VCFG_DUMMY;
773 s->volatile_cfg |= VCFG_WRAP_SEQUENTIAL;
774 if ((s->nonvolatile_cfg & NVCFG_XIP_MODE_MASK)
775 != NVCFG_XIP_MODE_DISABLED) {
776 s->volatile_cfg |= VCFG_XIP_MODE_ENABLED;
777 }
778 s->volatile_cfg |= deposit32(s->volatile_cfg,
779 VCFG_DUMMY_CLK_POS,
780 CFG_DUMMY_CLK_LEN,
781 extract32(s->nonvolatile_cfg,
782 NVCFG_DUMMY_CLK_POS,
783 CFG_DUMMY_CLK_LEN)
784 );
785
786 s->enh_volatile_cfg = 0;
787 s->enh_volatile_cfg |= EVCFG_OUT_DRIVER_STRENGTH_DEF;
788 s->enh_volatile_cfg |= EVCFG_VPP_ACCELERATOR;
789 s->enh_volatile_cfg |= EVCFG_RESET_HOLD_ENABLED;
790 if (s->nonvolatile_cfg & NVCFG_DUAL_IO_MASK) {
791 s->enh_volatile_cfg |= EVCFG_DUAL_IO_ENABLED;
792 }
793 if (s->nonvolatile_cfg & NVCFG_QUAD_IO_MASK) {
794 s->enh_volatile_cfg |= EVCFG_QUAD_IO_ENABLED;
795 }
796 if (!(s->nonvolatile_cfg & NVCFG_4BYTE_ADDR_MASK)) {
797 s->four_bytes_address_mode = true;
798 }
799 if (!(s->nonvolatile_cfg & NVCFG_LOWER_SEGMENT_MASK)) {
800 s->ear = s->size / MAX_3BYTES_SIZE - 1;
801 }
802 break;
803 case MAN_MACRONIX:
804 s->volatile_cfg = 0x7;
805 break;
806 case MAN_SPANSION:
807 s->spansion_cr1v = s->spansion_cr1nv;
808 s->spansion_cr2v = s->spansion_cr2nv;
809 s->spansion_cr3v = s->spansion_cr3nv;
810 s->spansion_cr4v = s->spansion_cr4nv;
811 s->quad_enable = extract32(s->spansion_cr1v,
812 SPANSION_QUAD_CFG_POS,
813 SPANSION_QUAD_CFG_LEN
814 );
815 s->four_bytes_address_mode = extract32(s->spansion_cr2v,
816 SPANSION_ADDR_LEN_POS,
817 SPANSION_ADDR_LEN_LEN
818 );
819 break;
820 default:
821 break;
822 }
823
824 DB_PRINT_L(0, "Reset done.\n");
825 }
826
827 static void decode_fast_read_cmd(Flash *s)
828 {
829 s->needed_bytes = get_addr_length(s);
830 switch (get_man(s)) {
831 /* Dummy cycles - modeled with bytes writes instead of bits */
832 case MAN_WINBOND:
833 s->needed_bytes += 8;
834 break;
835 case MAN_NUMONYX:
836 s->needed_bytes += extract32(s->volatile_cfg, 4, 4);
837 break;
838 case MAN_MACRONIX:
839 if (extract32(s->volatile_cfg, 6, 2) == 1) {
840 s->needed_bytes += 6;
841 } else {
842 s->needed_bytes += 8;
843 }
844 break;
845 case MAN_SPANSION:
846 s->needed_bytes += extract32(s->spansion_cr2v,
847 SPANSION_DUMMY_CLK_POS,
848 SPANSION_DUMMY_CLK_LEN
849 );
850 break;
851 default:
852 break;
853 }
854 s->pos = 0;
855 s->len = 0;
856 s->state = STATE_COLLECTING_DATA;
857 }
858
859 static void decode_dio_read_cmd(Flash *s)
860 {
861 s->needed_bytes = get_addr_length(s);
862 /* Dummy cycles modeled with bytes writes instead of bits */
863 switch (get_man(s)) {
864 case MAN_WINBOND:
865 s->needed_bytes += WINBOND_CONTINUOUS_READ_MODE_CMD_LEN;
866 break;
867 case MAN_SPANSION:
868 s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN;
869 s->needed_bytes += extract32(s->spansion_cr2v,
870 SPANSION_DUMMY_CLK_POS,
871 SPANSION_DUMMY_CLK_LEN
872 );
873 break;
874 case MAN_NUMONYX:
875 s->needed_bytes += extract32(s->volatile_cfg, 4, 4);
876 break;
877 case MAN_MACRONIX:
878 switch (extract32(s->volatile_cfg, 6, 2)) {
879 case 1:
880 s->needed_bytes += 6;
881 break;
882 case 2:
883 s->needed_bytes += 8;
884 break;
885 default:
886 s->needed_bytes += 4;
887 break;
888 }
889 break;
890 default:
891 break;
892 }
893 s->pos = 0;
894 s->len = 0;
895 s->state = STATE_COLLECTING_DATA;
896 }
897
898 static void decode_qio_read_cmd(Flash *s)
899 {
900 s->needed_bytes = get_addr_length(s);
901 /* Dummy cycles modeled with bytes writes instead of bits */
902 switch (get_man(s)) {
903 case MAN_WINBOND:
904 s->needed_bytes += WINBOND_CONTINUOUS_READ_MODE_CMD_LEN;
905 s->needed_bytes += 4;
906 break;
907 case MAN_SPANSION:
908 s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN;
909 s->needed_bytes += extract32(s->spansion_cr2v,
910 SPANSION_DUMMY_CLK_POS,
911 SPANSION_DUMMY_CLK_LEN
912 );
913 break;
914 case MAN_NUMONYX:
915 s->needed_bytes += extract32(s->volatile_cfg, 4, 4);
916 break;
917 case MAN_MACRONIX:
918 switch (extract32(s->volatile_cfg, 6, 2)) {
919 case 1:
920 s->needed_bytes += 4;
921 break;
922 case 2:
923 s->needed_bytes += 8;
924 break;
925 default:
926 s->needed_bytes += 6;
927 break;
928 }
929 break;
930 default:
931 break;
932 }
933 s->pos = 0;
934 s->len = 0;
935 s->state = STATE_COLLECTING_DATA;
936 }
937
938 static void decode_new_cmd(Flash *s, uint32_t value)
939 {
940 s->cmd_in_progress = value;
941 int i;
942 DB_PRINT_L(0, "decoded new command:%x\n", value);
943
944 if (value != RESET_MEMORY) {
945 s->reset_enable = false;
946 }
947
948 switch (value) {
949
950 case ERASE_4K:
951 case ERASE4_4K:
952 case ERASE_32K:
953 case ERASE4_32K:
954 case ERASE_SECTOR:
955 case ERASE4_SECTOR:
956 case READ:
957 case READ4:
958 case DPP:
959 case QPP:
960 case QPP_4:
961 case PP:
962 case PP4:
963 case PP4_4:
964 case DIE_ERASE:
965 case RDID_90:
966 case RDID_AB:
967 s->needed_bytes = get_addr_length(s);
968 s->pos = 0;
969 s->len = 0;
970 s->state = STATE_COLLECTING_DATA;
971 break;
972
973 case FAST_READ:
974 case FAST_READ4:
975 case DOR:
976 case DOR4:
977 case QOR:
978 case QOR4:
979 decode_fast_read_cmd(s);
980 break;
981
982 case DIOR:
983 case DIOR4:
984 decode_dio_read_cmd(s);
985 break;
986
987 case QIOR:
988 case QIOR4:
989 decode_qio_read_cmd(s);
990 break;
991
992 case WRSR:
993 if (s->write_enable) {
994 switch (get_man(s)) {
995 case MAN_SPANSION:
996 s->needed_bytes = 2;
997 s->state = STATE_COLLECTING_DATA;
998 break;
999 case MAN_MACRONIX:
1000 s->needed_bytes = 2;
1001 s->state = STATE_COLLECTING_VAR_LEN_DATA;
1002 break;
1003 default:
1004 s->needed_bytes = 1;
1005 s->state = STATE_COLLECTING_DATA;
1006 }
1007 s->pos = 0;
1008 }
1009 break;
1010
1011 case WRDI:
1012 s->write_enable = false;
1013 break;
1014 case WREN:
1015 s->write_enable = true;
1016 break;
1017
1018 case RDSR:
1019 s->data[0] = (!!s->write_enable) << 1;
1020 if (get_man(s) == MAN_MACRONIX) {
1021 s->data[0] |= (!!s->quad_enable) << 6;
1022 }
1023 s->pos = 0;
1024 s->len = 1;
1025 s->data_read_loop = true;
1026 s->state = STATE_READING_DATA;
1027 break;
1028
1029 case READ_FSR:
1030 s->data[0] = FSR_FLASH_READY;
1031 if (s->four_bytes_address_mode) {
1032 s->data[0] |= FSR_4BYTE_ADDR_MODE_ENABLED;
1033 }
1034 s->pos = 0;
1035 s->len = 1;
1036 s->data_read_loop = true;
1037 s->state = STATE_READING_DATA;
1038 break;
1039
1040 case JEDEC_READ:
1041 DB_PRINT_L(0, "populated jedec code\n");
1042 for (i = 0; i < s->pi->id_len; i++) {
1043 s->data[i] = s->pi->id[i];
1044 }
1045
1046 s->len = s->pi->id_len;
1047 s->pos = 0;
1048 s->state = STATE_READING_DATA;
1049 break;
1050
1051 case RDCR:
1052 s->data[0] = s->volatile_cfg & 0xFF;
1053 s->data[0] |= (!!s->four_bytes_address_mode) << 5;
1054 s->pos = 0;
1055 s->len = 1;
1056 s->state = STATE_READING_DATA;
1057 break;
1058
1059 case BULK_ERASE_60:
1060 case BULK_ERASE:
1061 if (s->write_enable) {
1062 DB_PRINT_L(0, "chip erase\n");
1063 flash_erase(s, 0, BULK_ERASE);
1064 } else {
1065 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: chip erase with write "
1066 "protect!\n");
1067 }
1068 break;
1069 case NOP:
1070 break;
1071 case EN_4BYTE_ADDR:
1072 s->four_bytes_address_mode = true;
1073 break;
1074 case EX_4BYTE_ADDR:
1075 s->four_bytes_address_mode = false;
1076 break;
1077 case BRRD:
1078 case EXTEND_ADDR_READ:
1079 s->data[0] = s->ear;
1080 s->pos = 0;
1081 s->len = 1;
1082 s->state = STATE_READING_DATA;
1083 break;
1084 case BRWR:
1085 case EXTEND_ADDR_WRITE:
1086 if (s->write_enable) {
1087 s->needed_bytes = 1;
1088 s->pos = 0;
1089 s->len = 0;
1090 s->state = STATE_COLLECTING_DATA;
1091 }
1092 break;
1093 case RNVCR:
1094 s->data[0] = s->nonvolatile_cfg & 0xFF;
1095 s->data[1] = (s->nonvolatile_cfg >> 8) & 0xFF;
1096 s->pos = 0;
1097 s->len = 2;
1098 s->state = STATE_READING_DATA;
1099 break;
1100 case WNVCR:
1101 if (s->write_enable && get_man(s) == MAN_NUMONYX) {
1102 s->needed_bytes = 2;
1103 s->pos = 0;
1104 s->len = 0;
1105 s->state = STATE_COLLECTING_DATA;
1106 }
1107 break;
1108 case RVCR:
1109 s->data[0] = s->volatile_cfg & 0xFF;
1110 s->pos = 0;
1111 s->len = 1;
1112 s->state = STATE_READING_DATA;
1113 break;
1114 case WVCR:
1115 if (s->write_enable) {
1116 s->needed_bytes = 1;
1117 s->pos = 0;
1118 s->len = 0;
1119 s->state = STATE_COLLECTING_DATA;
1120 }
1121 break;
1122 case REVCR:
1123 s->data[0] = s->enh_volatile_cfg & 0xFF;
1124 s->pos = 0;
1125 s->len = 1;
1126 s->state = STATE_READING_DATA;
1127 break;
1128 case WEVCR:
1129 if (s->write_enable) {
1130 s->needed_bytes = 1;
1131 s->pos = 0;
1132 s->len = 0;
1133 s->state = STATE_COLLECTING_DATA;
1134 }
1135 break;
1136 case RESET_ENABLE:
1137 s->reset_enable = true;
1138 break;
1139 case RESET_MEMORY:
1140 if (s->reset_enable) {
1141 reset_memory(s);
1142 }
1143 break;
1144 case RDCR_EQIO:
1145 switch (get_man(s)) {
1146 case MAN_SPANSION:
1147 s->data[0] = (!!s->quad_enable) << 1;
1148 s->pos = 0;
1149 s->len = 1;
1150 s->state = STATE_READING_DATA;
1151 break;
1152 case MAN_MACRONIX:
1153 s->quad_enable = true;
1154 break;
1155 default:
1156 break;
1157 }
1158 break;
1159 case RSTQIO:
1160 s->quad_enable = false;
1161 break;
1162 default:
1163 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value);
1164 break;
1165 }
1166 }
1167
1168 static int m25p80_cs(SSISlave *ss, bool select)
1169 {
1170 Flash *s = M25P80(ss);
1171
1172 if (select) {
1173 if (s->state == STATE_COLLECTING_VAR_LEN_DATA) {
1174 complete_collecting_data(s);
1175 }
1176 s->len = 0;
1177 s->pos = 0;
1178 s->state = STATE_IDLE;
1179 flash_sync_dirty(s, -1);
1180 s->data_read_loop = false;
1181 }
1182
1183 DB_PRINT_L(0, "%sselect\n", select ? "de" : "");
1184
1185 return 0;
1186 }
1187
1188 static uint32_t m25p80_transfer8(SSISlave *ss, uint32_t tx)
1189 {
1190 Flash *s = M25P80(ss);
1191 uint32_t r = 0;
1192
1193 switch (s->state) {
1194
1195 case STATE_PAGE_PROGRAM:
1196 DB_PRINT_L(1, "page program cur_addr=%#" PRIx32 " data=%" PRIx8 "\n",
1197 s->cur_addr, (uint8_t)tx);
1198 flash_write8(s, s->cur_addr, (uint8_t)tx);
1199 s->cur_addr = (s->cur_addr + 1) & (s->size - 1);
1200 break;
1201
1202 case STATE_READ:
1203 r = s->storage[s->cur_addr];
1204 DB_PRINT_L(1, "READ 0x%" PRIx32 "=%" PRIx8 "\n", s->cur_addr,
1205 (uint8_t)r);
1206 s->cur_addr = (s->cur_addr + 1) & (s->size - 1);
1207 break;
1208
1209 case STATE_COLLECTING_DATA:
1210 case STATE_COLLECTING_VAR_LEN_DATA:
1211
1212 if (s->len >= M25P80_INTERNAL_DATA_BUFFER_SZ) {
1213 qemu_log_mask(LOG_GUEST_ERROR,
1214 "M25P80: Write overrun internal data buffer. "
1215 "SPI controller (QEMU emulator or guest driver) "
1216 "is misbehaving\n");
1217 s->len = s->pos = 0;
1218 s->state = STATE_IDLE;
1219 break;
1220 }
1221
1222 s->data[s->len] = (uint8_t)tx;
1223 s->len++;
1224
1225 if (s->len == s->needed_bytes) {
1226 complete_collecting_data(s);
1227 }
1228 break;
1229
1230 case STATE_READING_DATA:
1231
1232 if (s->pos >= M25P80_INTERNAL_DATA_BUFFER_SZ) {
1233 qemu_log_mask(LOG_GUEST_ERROR,
1234 "M25P80: Read overrun internal data buffer. "
1235 "SPI controller (QEMU emulator or guest driver) "
1236 "is misbehaving\n");
1237 s->len = s->pos = 0;
1238 s->state = STATE_IDLE;
1239 break;
1240 }
1241
1242 r = s->data[s->pos];
1243 s->pos++;
1244 if (s->pos == s->len) {
1245 s->pos = 0;
1246 if (!s->data_read_loop) {
1247 s->state = STATE_IDLE;
1248 }
1249 }
1250 break;
1251
1252 default:
1253 case STATE_IDLE:
1254 decode_new_cmd(s, (uint8_t)tx);
1255 break;
1256 }
1257
1258 return r;
1259 }
1260
1261 static void m25p80_realize(SSISlave *ss, Error **errp)
1262 {
1263 Flash *s = M25P80(ss);
1264 M25P80Class *mc = M25P80_GET_CLASS(s);
1265 int ret;
1266
1267 s->pi = mc->pi;
1268
1269 s->size = s->pi->sector_size * s->pi->n_sectors;
1270 s->dirty_page = -1;
1271
1272 if (s->blk) {
1273 uint64_t perm = BLK_PERM_CONSISTENT_READ |
1274 (blk_is_read_only(s->blk) ? 0 : BLK_PERM_WRITE);
1275 ret = blk_set_perm(s->blk, perm, BLK_PERM_ALL, errp);
1276 if (ret < 0) {
1277 return;
1278 }
1279
1280 DB_PRINT_L(0, "Binding to IF_MTD drive\n");
1281 s->storage = blk_blockalign(s->blk, s->size);
1282
1283 if (blk_pread(s->blk, 0, s->storage, s->size) != s->size) {
1284 error_setg(errp, "failed to read the initial flash content");
1285 return;
1286 }
1287 } else {
1288 DB_PRINT_L(0, "No BDRV - binding to RAM\n");
1289 s->storage = blk_blockalign(NULL, s->size);
1290 memset(s->storage, 0xFF, s->size);
1291 }
1292 }
1293
1294 static void m25p80_reset(DeviceState *d)
1295 {
1296 Flash *s = M25P80(d);
1297
1298 reset_memory(s);
1299 }
1300
1301 static int m25p80_pre_save(void *opaque)
1302 {
1303 flash_sync_dirty((Flash *)opaque, -1);
1304
1305 return 0;
1306 }
1307
1308 static Property m25p80_properties[] = {
1309 /* This is default value for Micron flash */
1310 DEFINE_PROP_UINT32("nonvolatile-cfg", Flash, nonvolatile_cfg, 0x8FFF),
1311 DEFINE_PROP_UINT8("spansion-cr1nv", Flash, spansion_cr1nv, 0x0),
1312 DEFINE_PROP_UINT8("spansion-cr2nv", Flash, spansion_cr2nv, 0x8),
1313 DEFINE_PROP_UINT8("spansion-cr3nv", Flash, spansion_cr3nv, 0x2),
1314 DEFINE_PROP_UINT8("spansion-cr4nv", Flash, spansion_cr4nv, 0x10),
1315 DEFINE_PROP_DRIVE("drive", Flash, blk),
1316 DEFINE_PROP_END_OF_LIST(),
1317 };
1318
1319 static int m25p80_pre_load(void *opaque)
1320 {
1321 Flash *s = (Flash *)opaque;
1322
1323 s->data_read_loop = false;
1324 return 0;
1325 }
1326
1327 static bool m25p80_data_read_loop_needed(void *opaque)
1328 {
1329 Flash *s = (Flash *)opaque;
1330
1331 return s->data_read_loop;
1332 }
1333
1334 static const VMStateDescription vmstate_m25p80_data_read_loop = {
1335 .name = "m25p80/data_read_loop",
1336 .version_id = 1,
1337 .minimum_version_id = 1,
1338 .needed = m25p80_data_read_loop_needed,
1339 .fields = (VMStateField[]) {
1340 VMSTATE_BOOL(data_read_loop, Flash),
1341 VMSTATE_END_OF_LIST()
1342 }
1343 };
1344
1345 static const VMStateDescription vmstate_m25p80 = {
1346 .name = "m25p80",
1347 .version_id = 0,
1348 .minimum_version_id = 0,
1349 .pre_save = m25p80_pre_save,
1350 .pre_load = m25p80_pre_load,
1351 .fields = (VMStateField[]) {
1352 VMSTATE_UINT8(state, Flash),
1353 VMSTATE_UINT8_ARRAY(data, Flash, M25P80_INTERNAL_DATA_BUFFER_SZ),
1354 VMSTATE_UINT32(len, Flash),
1355 VMSTATE_UINT32(pos, Flash),
1356 VMSTATE_UINT8(needed_bytes, Flash),
1357 VMSTATE_UINT8(cmd_in_progress, Flash),
1358 VMSTATE_UINT32(cur_addr, Flash),
1359 VMSTATE_BOOL(write_enable, Flash),
1360 VMSTATE_BOOL(reset_enable, Flash),
1361 VMSTATE_UINT8(ear, Flash),
1362 VMSTATE_BOOL(four_bytes_address_mode, Flash),
1363 VMSTATE_UINT32(nonvolatile_cfg, Flash),
1364 VMSTATE_UINT32(volatile_cfg, Flash),
1365 VMSTATE_UINT32(enh_volatile_cfg, Flash),
1366 VMSTATE_BOOL(quad_enable, Flash),
1367 VMSTATE_UINT8(spansion_cr1nv, Flash),
1368 VMSTATE_UINT8(spansion_cr2nv, Flash),
1369 VMSTATE_UINT8(spansion_cr3nv, Flash),
1370 VMSTATE_UINT8(spansion_cr4nv, Flash),
1371 VMSTATE_END_OF_LIST()
1372 },
1373 .subsections = (const VMStateDescription * []) {
1374 &vmstate_m25p80_data_read_loop,
1375 NULL
1376 }
1377 };
1378
1379 static void m25p80_class_init(ObjectClass *klass, void *data)
1380 {
1381 DeviceClass *dc = DEVICE_CLASS(klass);
1382 SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
1383 M25P80Class *mc = M25P80_CLASS(klass);
1384
1385 k->realize = m25p80_realize;
1386 k->transfer = m25p80_transfer8;
1387 k->set_cs = m25p80_cs;
1388 k->cs_polarity = SSI_CS_LOW;
1389 dc->vmsd = &vmstate_m25p80;
1390 dc->props = m25p80_properties;
1391 dc->reset = m25p80_reset;
1392 mc->pi = data;
1393 }
1394
1395 static const TypeInfo m25p80_info = {
1396 .name = TYPE_M25P80,
1397 .parent = TYPE_SSI_SLAVE,
1398 .instance_size = sizeof(Flash),
1399 .class_size = sizeof(M25P80Class),
1400 .abstract = true,
1401 };
1402
1403 static void m25p80_register_types(void)
1404 {
1405 int i;
1406
1407 type_register_static(&m25p80_info);
1408 for (i = 0; i < ARRAY_SIZE(known_devices); ++i) {
1409 TypeInfo ti = {
1410 .name = known_devices[i].part_name,
1411 .parent = TYPE_M25P80,
1412 .class_init = m25p80_class_init,
1413 .class_data = (void *)&known_devices[i],
1414 };
1415 type_register(&ti);
1416 }
1417 }
1418
1419 type_init(m25p80_register_types)
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