tcg/tci/tcg-target.c

   1 /*
   2  * Tiny Code Generator for QEMU
   3  *
   4  * Copyright (c) 2009, 2011 Stefan Weil
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "tcg-be-null.h"
  27
  28 /* TODO list:
  29  * - See TODO comments in code.
  30  */
  31
  32 /* Marker for missing code. */
  33 #define TODO() \
  34     do { \
  35         fprintf(stderr, "TODO %s:%u: %s()\n", \
  36                 __FILE__, __LINE__, __func__); \
  37         tcg_abort(); \
  38     } while (0)
  39
  40 /* Bitfield n...m (in 32 bit value). */
  41 #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
  42
  43 /* Macros used in tcg_target_op_defs. */
  44 #define R       "r"
  45 #define RI      "ri"
  46 #if TCG_TARGET_REG_BITS == 32
  47 # define R64    "r", "r"
  48 #else
  49 # define R64    "r"
  50 #endif
  51 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
  52 # define L      "L", "L"
  53 # define S      "S", "S"
  54 #else
  55 # define L      "L"
  56 # define S      "S"
  57 #endif
  58
  59 /* TODO: documentation. */
  60 static const TCGTargetOpDef tcg_target_op_defs[] = {
  61     { INDEX_op_exit_tb, { NULL } },
  62     { INDEX_op_goto_tb, { NULL } },
  63     { INDEX_op_br, { NULL } },
  64
  65     { INDEX_op_ld8u_i32, { R, R } },
  66     { INDEX_op_ld8s_i32, { R, R } },
  67     { INDEX_op_ld16u_i32, { R, R } },
  68     { INDEX_op_ld16s_i32, { R, R } },
  69     { INDEX_op_ld_i32, { R, R } },
  70     { INDEX_op_st8_i32, { R, R } },
  71     { INDEX_op_st16_i32, { R, R } },
  72     { INDEX_op_st_i32, { R, R } },
  73
  74     { INDEX_op_add_i32, { R, RI, RI } },
  75     { INDEX_op_sub_i32, { R, RI, RI } },
  76     { INDEX_op_mul_i32, { R, RI, RI } },
  77 #if TCG_TARGET_HAS_div_i32
  78     { INDEX_op_div_i32, { R, R, R } },
  79     { INDEX_op_divu_i32, { R, R, R } },
  80     { INDEX_op_rem_i32, { R, R, R } },
  81     { INDEX_op_remu_i32, { R, R, R } },
  82 #elif TCG_TARGET_HAS_div2_i32
  83     { INDEX_op_div2_i32, { R, R, "0", "1", R } },
  84     { INDEX_op_divu2_i32, { R, R, "0", "1", R } },
  85 #endif
  86     /* TODO: Does R, RI, RI result in faster code than R, R, RI?
  87        If both operands are constants, we can optimize. */
  88     { INDEX_op_and_i32, { R, RI, RI } },
  89 #if TCG_TARGET_HAS_andc_i32
  90     { INDEX_op_andc_i32, { R, RI, RI } },
  91 #endif
  92 #if TCG_TARGET_HAS_eqv_i32
  93     { INDEX_op_eqv_i32, { R, RI, RI } },
  94 #endif
  95 #if TCG_TARGET_HAS_nand_i32
  96     { INDEX_op_nand_i32, { R, RI, RI } },
  97 #endif
  98 #if TCG_TARGET_HAS_nor_i32
  99     { INDEX_op_nor_i32, { R, RI, RI } },
 100 #endif
 101     { INDEX_op_or_i32, { R, RI, RI } },
 102 #if TCG_TARGET_HAS_orc_i32
 103     { INDEX_op_orc_i32, { R, RI, RI } },
 104 #endif
 105     { INDEX_op_xor_i32, { R, RI, RI } },
 106     { INDEX_op_shl_i32, { R, RI, RI } },
 107     { INDEX_op_shr_i32, { R, RI, RI } },
 108     { INDEX_op_sar_i32, { R, RI, RI } },
 109 #if TCG_TARGET_HAS_rot_i32
 110     { INDEX_op_rotl_i32, { R, RI, RI } },
 111     { INDEX_op_rotr_i32, { R, RI, RI } },
 112 #endif
 113 #if TCG_TARGET_HAS_deposit_i32
 114     { INDEX_op_deposit_i32, { R, "0", R } },
 115 #endif
 116
 117     { INDEX_op_brcond_i32, { R, RI } },
 118
 119     { INDEX_op_setcond_i32, { R, R, RI } },
 120 #if TCG_TARGET_REG_BITS == 64
 121     { INDEX_op_setcond_i64, { R, R, RI } },
 122 #endif /* TCG_TARGET_REG_BITS == 64 */
 123
 124 #if TCG_TARGET_REG_BITS == 32
 125     /* TODO: Support R, R, R, R, RI, RI? Will it be faster? */
 126     { INDEX_op_add2_i32, { R, R, R, R, R, R } },
 127     { INDEX_op_sub2_i32, { R, R, R, R, R, R } },
 128     { INDEX_op_brcond2_i32, { R, R, RI, RI } },
 129     { INDEX_op_mulu2_i32, { R, R, R, R } },
 130     { INDEX_op_setcond2_i32, { R, R, R, RI, RI } },
 131 #endif
 132
 133 #if TCG_TARGET_HAS_not_i32
 134     { INDEX_op_not_i32, { R, R } },
 135 #endif
 136 #if TCG_TARGET_HAS_neg_i32
 137     { INDEX_op_neg_i32, { R, R } },
 138 #endif
 139
 140 #if TCG_TARGET_REG_BITS == 64
 141     { INDEX_op_ld8u_i64, { R, R } },
 142     { INDEX_op_ld8s_i64, { R, R } },
 143     { INDEX_op_ld16u_i64, { R, R } },
 144     { INDEX_op_ld16s_i64, { R, R } },
 145     { INDEX_op_ld32u_i64, { R, R } },
 146     { INDEX_op_ld32s_i64, { R, R } },
 147     { INDEX_op_ld_i64, { R, R } },
 148
 149     { INDEX_op_st8_i64, { R, R } },
 150     { INDEX_op_st16_i64, { R, R } },
 151     { INDEX_op_st32_i64, { R, R } },
 152     { INDEX_op_st_i64, { R, R } },
 153
 154     { INDEX_op_add_i64, { R, RI, RI } },
 155     { INDEX_op_sub_i64, { R, RI, RI } },
 156     { INDEX_op_mul_i64, { R, RI, RI } },
 157 #if TCG_TARGET_HAS_div_i64
 158     { INDEX_op_div_i64, { R, R, R } },
 159     { INDEX_op_divu_i64, { R, R, R } },
 160     { INDEX_op_rem_i64, { R, R, R } },
 161     { INDEX_op_remu_i64, { R, R, R } },
 162 #elif TCG_TARGET_HAS_div2_i64
 163     { INDEX_op_div2_i64, { R, R, "0", "1", R } },
 164     { INDEX_op_divu2_i64, { R, R, "0", "1", R } },
 165 #endif
 166     { INDEX_op_and_i64, { R, RI, RI } },
 167 #if TCG_TARGET_HAS_andc_i64
 168     { INDEX_op_andc_i64, { R, RI, RI } },
 169 #endif
 170 #if TCG_TARGET_HAS_eqv_i64
 171     { INDEX_op_eqv_i64, { R, RI, RI } },
 172 #endif
 173 #if TCG_TARGET_HAS_nand_i64
 174     { INDEX_op_nand_i64, { R, RI, RI } },
 175 #endif
 176 #if TCG_TARGET_HAS_nor_i64
 177     { INDEX_op_nor_i64, { R, RI, RI } },
 178 #endif
 179     { INDEX_op_or_i64, { R, RI, RI } },
 180 #if TCG_TARGET_HAS_orc_i64
 181     { INDEX_op_orc_i64, { R, RI, RI } },
 182 #endif
 183     { INDEX_op_xor_i64, { R, RI, RI } },
 184     { INDEX_op_shl_i64, { R, RI, RI } },
 185     { INDEX_op_shr_i64, { R, RI, RI } },
 186     { INDEX_op_sar_i64, { R, RI, RI } },
 187 #if TCG_TARGET_HAS_rot_i64
 188     { INDEX_op_rotl_i64, { R, RI, RI } },
 189     { INDEX_op_rotr_i64, { R, RI, RI } },
 190 #endif
 191 #if TCG_TARGET_HAS_deposit_i64
 192     { INDEX_op_deposit_i64, { R, "0", R } },
 193 #endif
 194     { INDEX_op_brcond_i64, { R, RI } },
 195
 196 #if TCG_TARGET_HAS_ext8s_i64
 197     { INDEX_op_ext8s_i64, { R, R } },
 198 #endif
 199 #if TCG_TARGET_HAS_ext16s_i64
 200     { INDEX_op_ext16s_i64, { R, R } },
 201 #endif
 202 #if TCG_TARGET_HAS_ext32s_i64
 203     { INDEX_op_ext32s_i64, { R, R } },
 204 #endif
 205 #if TCG_TARGET_HAS_ext8u_i64
 206     { INDEX_op_ext8u_i64, { R, R } },
 207 #endif
 208 #if TCG_TARGET_HAS_ext16u_i64
 209     { INDEX_op_ext16u_i64, { R, R } },
 210 #endif
 211 #if TCG_TARGET_HAS_ext32u_i64
 212     { INDEX_op_ext32u_i64, { R, R } },
 213 #endif
 214     { INDEX_op_ext_i32_i64, { R, R } },
 215     { INDEX_op_extu_i32_i64, { R, R } },
 216 #if TCG_TARGET_HAS_bswap16_i64
 217     { INDEX_op_bswap16_i64, { R, R } },
 218 #endif
 219 #if TCG_TARGET_HAS_bswap32_i64
 220     { INDEX_op_bswap32_i64, { R, R } },
 221 #endif
 222 #if TCG_TARGET_HAS_bswap64_i64
 223     { INDEX_op_bswap64_i64, { R, R } },
 224 #endif
 225 #if TCG_TARGET_HAS_not_i64
 226     { INDEX_op_not_i64, { R, R } },
 227 #endif
 228 #if TCG_TARGET_HAS_neg_i64
 229     { INDEX_op_neg_i64, { R, R } },
 230 #endif
 231 #endif /* TCG_TARGET_REG_BITS == 64 */
 232
 233     { INDEX_op_qemu_ld_i32, { R, L } },
 234     { INDEX_op_qemu_ld_i64, { R64, L } },
 235
 236     { INDEX_op_qemu_st_i32, { R, S } },
 237     { INDEX_op_qemu_st_i64, { R64, S } },
 238
 239 #if TCG_TARGET_HAS_ext8s_i32
 240     { INDEX_op_ext8s_i32, { R, R } },
 241 #endif
 242 #if TCG_TARGET_HAS_ext16s_i32
 243     { INDEX_op_ext16s_i32, { R, R } },
 244 #endif
 245 #if TCG_TARGET_HAS_ext8u_i32
 246     { INDEX_op_ext8u_i32, { R, R } },
 247 #endif
 248 #if TCG_TARGET_HAS_ext16u_i32
 249     { INDEX_op_ext16u_i32, { R, R } },
 250 #endif
 251
 252 #if TCG_TARGET_HAS_bswap16_i32
 253     { INDEX_op_bswap16_i32, { R, R } },
 254 #endif
 255 #if TCG_TARGET_HAS_bswap32_i32
 256     { INDEX_op_bswap32_i32, { R, R } },
 257 #endif
 258
 259     { -1 },
 260 };
 261
 262 static const int tcg_target_reg_alloc_order[] = {
 263     TCG_REG_R0,
 264     TCG_REG_R1,
 265     TCG_REG_R2,
 266     TCG_REG_R3,
 267 #if 0 /* used for TCG_REG_CALL_STACK */
 268     TCG_REG_R4,
 269 #endif
 270     TCG_REG_R5,
 271     TCG_REG_R6,
 272     TCG_REG_R7,
 273 #if TCG_TARGET_NB_REGS >= 16
 274     TCG_REG_R8,
 275     TCG_REG_R9,
 276     TCG_REG_R10,
 277     TCG_REG_R11,
 278     TCG_REG_R12,
 279     TCG_REG_R13,
 280     TCG_REG_R14,
 281     TCG_REG_R15,
 282 #endif
 283 };
 284
 285 #if MAX_OPC_PARAM_IARGS != 5
 286 # error Fix needed, number of supported input arguments changed!
 287 #endif
 288
 289 static const int tcg_target_call_iarg_regs[] = {
 290     TCG_REG_R0,
 291     TCG_REG_R1,
 292     TCG_REG_R2,
 293     TCG_REG_R3,
 294 #if 0 /* used for TCG_REG_CALL_STACK */
 295     TCG_REG_R4,
 296 #endif
 297     TCG_REG_R5,
 298 #if TCG_TARGET_REG_BITS == 32
 299     /* 32 bit hosts need 2 * MAX_OPC_PARAM_IARGS registers. */
 300     TCG_REG_R6,
 301     TCG_REG_R7,
 302 #if TCG_TARGET_NB_REGS >= 16
 303     TCG_REG_R8,
 304     TCG_REG_R9,
 305     TCG_REG_R10,
 306 #else
 307 # error Too few input registers available
 308 #endif
 309 #endif
 310 };
 311
 312 static const int tcg_target_call_oarg_regs[] = {
 313     TCG_REG_R0,
 314 #if TCG_TARGET_REG_BITS == 32
 315     TCG_REG_R1
 316 #endif
 317 };
 318
 319 #ifndef NDEBUG
 320 static const char *const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
 321     "r00",
 322     "r01",
 323     "r02",
 324     "r03",
 325     "r04",
 326     "r05",
 327     "r06",
 328     "r07",
 329 #if TCG_TARGET_NB_REGS >= 16
 330     "r08",
 331     "r09",
 332     "r10",
 333     "r11",
 334     "r12",
 335     "r13",
 336     "r14",
 337     "r15",
 338 #if TCG_TARGET_NB_REGS >= 32
 339     "r16",
 340     "r17",
 341     "r18",
 342     "r19",
 343     "r20",
 344     "r21",
 345     "r22",
 346     "r23",
 347     "r24",
 348     "r25",
 349     "r26",
 350     "r27",
 351     "r28",
 352     "r29",
 353     "r30",
 354     "r31"
 355 #endif
 356 #endif
 357 };
 358 #endif
 359
 360 static void patch_reloc(tcg_insn_unit *code_ptr, int type,
 361                         intptr_t value, intptr_t addend)
 362 {
 363     /* tcg_out_reloc always uses the same type, addend. */
 364     assert(type == sizeof(tcg_target_long));
 365     assert(addend == 0);
 366     assert(value != 0);
 367     if (TCG_TARGET_REG_BITS == 32) {
 368         tcg_patch32(code_ptr, value);
 369     } else {
 370         tcg_patch64(code_ptr, value);
 371     }
 372 }
 373
 374 /* Parse target specific constraints. */
 375 static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
 376 {
 377     const char *ct_str = *pct_str;
 378     switch (ct_str[0]) {
 379     case 'r':
 380     case 'L':                   /* qemu_ld constraint */
 381     case 'S':                   /* qemu_st constraint */
 382         ct->ct |= TCG_CT_REG;
 383         tcg_regset_set32(ct->u.regs, 0, BIT(TCG_TARGET_NB_REGS) - 1);
 384         break;
 385     default:
 386         return -1;
 387     }
 388     ct_str++;
 389     *pct_str = ct_str;
 390     return 0;
 391 }
 392
 393 #if defined(CONFIG_DEBUG_TCG_INTERPRETER)
 394 /* Show current bytecode. Used by tcg interpreter. */
 395 void tci_disas(uint8_t opc)
 396 {
 397     const TCGOpDef *def = &tcg_op_defs[opc];
 398     fprintf(stderr, "TCG %s %u, %u, %u\n",
 399             def->name, def->nb_oargs, def->nb_iargs, def->nb_cargs);
 400 }
 401 #endif
 402
 403 /* Write value (native size). */
 404 static void tcg_out_i(TCGContext *s, tcg_target_ulong v)
 405 {
 406     if (TCG_TARGET_REG_BITS == 32) {
 407         tcg_out32(s, v);
 408     } else {
 409         tcg_out64(s, v);
 410     }
 411 }
 412
 413 /* Write opcode. */
 414 static void tcg_out_op_t(TCGContext *s, TCGOpcode op)
 415 {
 416     tcg_out8(s, op);
 417     tcg_out8(s, 0);
 418 }
 419
 420 /* Write register. */
 421 static void tcg_out_r(TCGContext *s, TCGArg t0)
 422 {
 423     assert(t0 < TCG_TARGET_NB_REGS);
 424     tcg_out8(s, t0);
 425 }
 426
 427 /* Write register or constant (native size). */
 428 static void tcg_out_ri(TCGContext *s, int const_arg, TCGArg arg)
 429 {
 430     if (const_arg) {
 431         assert(const_arg == 1);
 432         tcg_out8(s, TCG_CONST);
 433         tcg_out_i(s, arg);
 434     } else {
 435         tcg_out_r(s, arg);
 436     }
 437 }
 438
 439 /* Write register or constant (32 bit). */
 440 static void tcg_out_ri32(TCGContext *s, int const_arg, TCGArg arg)
 441 {
 442     if (const_arg) {
 443         assert(const_arg == 1);
 444         tcg_out8(s, TCG_CONST);
 445         tcg_out32(s, arg);
 446     } else {
 447         tcg_out_r(s, arg);
 448     }
 449 }
 450
 451 #if TCG_TARGET_REG_BITS == 64
 452 /* Write register or constant (64 bit). */
 453 static void tcg_out_ri64(TCGContext *s, int const_arg, TCGArg arg)
 454 {
 455     if (const_arg) {
 456         assert(const_arg == 1);
 457         tcg_out8(s, TCG_CONST);
 458         tcg_out64(s, arg);
 459     } else {
 460         tcg_out_r(s, arg);
 461     }
 462 }
 463 #endif
 464
 465 /* Write label. */
 466 static void tci_out_label(TCGContext *s, TCGLabel *label)
 467 {
 468     if (label->has_value) {
 469         tcg_out_i(s, label->u.value);
 470         assert(label->u.value);
 471     } else {
 472         tcg_out_reloc(s, s->code_ptr, sizeof(tcg_target_ulong), label, 0);
 473         s->code_ptr += sizeof(tcg_target_ulong);
 474     }
 475 }
 476
 477 static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1,
 478                        intptr_t arg2)
 479 {
 480     uint8_t *old_code_ptr = s->code_ptr;
 481     if (type == TCG_TYPE_I32) {
 482         tcg_out_op_t(s, INDEX_op_ld_i32);
 483         tcg_out_r(s, ret);
 484         tcg_out_r(s, arg1);
 485         tcg_out32(s, arg2);
 486     } else {
 487         assert(type == TCG_TYPE_I64);
 488 #if TCG_TARGET_REG_BITS == 64
 489         tcg_out_op_t(s, INDEX_op_ld_i64);
 490         tcg_out_r(s, ret);
 491         tcg_out_r(s, arg1);
 492         assert(arg2 == (int32_t)arg2);
 493         tcg_out32(s, arg2);
 494 #else
 495         TODO();
 496 #endif
 497     }
 498     old_code_ptr[1] = s->code_ptr - old_code_ptr;
 499 }
 500
 501 static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
 502 {
 503     uint8_t *old_code_ptr = s->code_ptr;
 504     assert(ret != arg);
 505 #if TCG_TARGET_REG_BITS == 32
 506     tcg_out_op_t(s, INDEX_op_mov_i32);
 507 #else
 508     tcg_out_op_t(s, INDEX_op_mov_i64);
 509 #endif
 510     tcg_out_r(s, ret);
 511     tcg_out_r(s, arg);
 512     old_code_ptr[1] = s->code_ptr - old_code_ptr;
 513 }
 514
 515 static void tcg_out_movi(TCGContext *s, TCGType type,
 516                          TCGReg t0, tcg_target_long arg)
 517 {
 518     uint8_t *old_code_ptr = s->code_ptr;
 519     uint32_t arg32 = arg;
 520     if (type == TCG_TYPE_I32 || arg == arg32) {
 521         tcg_out_op_t(s, INDEX_op_movi_i32);
 522         tcg_out_r(s, t0);
 523         tcg_out32(s, arg32);
 524     } else {
 525         assert(type == TCG_TYPE_I64);
 526 #if TCG_TARGET_REG_BITS == 64
 527         tcg_out_op_t(s, INDEX_op_movi_i64);
 528         tcg_out_r(s, t0);
 529         tcg_out64(s, arg);
 530 #else
 531         TODO();
 532 #endif
 533     }
 534     old_code_ptr[1] = s->code_ptr - old_code_ptr;
 535 }
 536
 537 static inline void tcg_out_call(TCGContext *s, tcg_insn_unit *arg)
 538 {
 539     uint8_t *old_code_ptr = s->code_ptr;
 540     tcg_out_op_t(s, INDEX_op_call);
 541     tcg_out_ri(s, 1, (uintptr_t)arg);
 542     old_code_ptr[1] = s->code_ptr - old_code_ptr;
 543 }
 544
 545 static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
 546                        const int *const_args)
 547 {
 548     uint8_t *old_code_ptr = s->code_ptr;
 549
 550     tcg_out_op_t(s, opc);
 551
 552     switch (opc) {
 553     case INDEX_op_exit_tb:
 554         tcg_out64(s, args[0]);
 555         break;
 556     case INDEX_op_goto_tb:
 557         if (s->tb_jmp_offset) {
 558             /* Direct jump method. */
 559             assert(args[0] < ARRAY_SIZE(s->tb_jmp_offset));
 560             s->tb_jmp_offset[args[0]] = tcg_current_code_size(s);
 561             tcg_out32(s, 0);
 562         } else {
 563             /* Indirect jump method. */
 564             TODO();
 565         }
 566         assert(args[0] < ARRAY_SIZE(s->tb_next_offset));
 567         s->tb_next_offset[args[0]] = tcg_current_code_size(s);
 568         break;
 569     case INDEX_op_br:
 570         tci_out_label(s, arg_label(args[0]));
 571         break;
 572     case INDEX_op_setcond_i32:
 573         tcg_out_r(s, args[0]);
 574         tcg_out_r(s, args[1]);
 575         tcg_out_ri32(s, const_args[2], args[2]);
 576         tcg_out8(s, args[3]);   /* condition */
 577         break;
 578 #if TCG_TARGET_REG_BITS == 32
 579     case INDEX_op_setcond2_i32:
 580         /* setcond2_i32 cond, t0, t1_low, t1_high, t2_low, t2_high */
 581         tcg_out_r(s, args[0]);
 582         tcg_out_r(s, args[1]);
 583         tcg_out_r(s, args[2]);
 584         tcg_out_ri32(s, const_args[3], args[3]);
 585         tcg_out_ri32(s, const_args[4], args[4]);
 586         tcg_out8(s, args[5]);   /* condition */
 587         break;
 588 #elif TCG_TARGET_REG_BITS == 64
 589     case INDEX_op_setcond_i64:
 590         tcg_out_r(s, args[0]);
 591         tcg_out_r(s, args[1]);
 592         tcg_out_ri64(s, const_args[2], args[2]);
 593         tcg_out8(s, args[3]);   /* condition */
 594         break;
 595 #endif
 596     case INDEX_op_ld8u_i32:
 597     case INDEX_op_ld8s_i32:
 598     case INDEX_op_ld16u_i32:
 599     case INDEX_op_ld16s_i32:
 600     case INDEX_op_ld_i32:
 601     case INDEX_op_st8_i32:
 602     case INDEX_op_st16_i32:
 603     case INDEX_op_st_i32:
 604     case INDEX_op_ld8u_i64:
 605     case INDEX_op_ld8s_i64:
 606     case INDEX_op_ld16u_i64:
 607     case INDEX_op_ld16s_i64:
 608     case INDEX_op_ld32u_i64:
 609     case INDEX_op_ld32s_i64:
 610     case INDEX_op_ld_i64:
 611     case INDEX_op_st8_i64:
 612     case INDEX_op_st16_i64:
 613     case INDEX_op_st32_i64:
 614     case INDEX_op_st_i64:
 615         tcg_out_r(s, args[0]);
 616         tcg_out_r(s, args[1]);
 617         assert(args[2] == (int32_t)args[2]);
 618         tcg_out32(s, args[2]);
 619         break;
 620     case INDEX_op_add_i32:
 621     case INDEX_op_sub_i32:
 622     case INDEX_op_mul_i32:
 623     case INDEX_op_and_i32:
 624     case INDEX_op_andc_i32:     /* Optional (TCG_TARGET_HAS_andc_i32). */
 625     case INDEX_op_eqv_i32:      /* Optional (TCG_TARGET_HAS_eqv_i32). */
 626     case INDEX_op_nand_i32:     /* Optional (TCG_TARGET_HAS_nand_i32). */
 627     case INDEX_op_nor_i32:      /* Optional (TCG_TARGET_HAS_nor_i32). */
 628     case INDEX_op_or_i32:
 629     case INDEX_op_orc_i32:      /* Optional (TCG_TARGET_HAS_orc_i32). */
 630     case INDEX_op_xor_i32:
 631     case INDEX_op_shl_i32:
 632     case INDEX_op_shr_i32:
 633     case INDEX_op_sar_i32:
 634     case INDEX_op_rotl_i32:     /* Optional (TCG_TARGET_HAS_rot_i32). */
 635     case INDEX_op_rotr_i32:     /* Optional (TCG_TARGET_HAS_rot_i32). */
 636         tcg_out_r(s, args[0]);
 637         tcg_out_ri32(s, const_args[1], args[1]);
 638         tcg_out_ri32(s, const_args[2], args[2]);
 639         break;
 640     case INDEX_op_deposit_i32:  /* Optional (TCG_TARGET_HAS_deposit_i32). */
 641         tcg_out_r(s, args[0]);
 642         tcg_out_r(s, args[1]);
 643         tcg_out_r(s, args[2]);
 644         assert(args[3] <= UINT8_MAX);
 645         tcg_out8(s, args[3]);
 646         assert(args[4] <= UINT8_MAX);
 647         tcg_out8(s, args[4]);
 648         break;
 649
 650 #if TCG_TARGET_REG_BITS == 64
 651     case INDEX_op_add_i64:
 652     case INDEX_op_sub_i64:
 653     case INDEX_op_mul_i64:
 654     case INDEX_op_and_i64:
 655     case INDEX_op_andc_i64:     /* Optional (TCG_TARGET_HAS_andc_i64). */
 656     case INDEX_op_eqv_i64:      /* Optional (TCG_TARGET_HAS_eqv_i64). */
 657     case INDEX_op_nand_i64:     /* Optional (TCG_TARGET_HAS_nand_i64). */
 658     case INDEX_op_nor_i64:      /* Optional (TCG_TARGET_HAS_nor_i64). */
 659     case INDEX_op_or_i64:
 660     case INDEX_op_orc_i64:      /* Optional (TCG_TARGET_HAS_orc_i64). */
 661     case INDEX_op_xor_i64:
 662     case INDEX_op_shl_i64:
 663     case INDEX_op_shr_i64:
 664     case INDEX_op_sar_i64:
 665     case INDEX_op_rotl_i64:     /* Optional (TCG_TARGET_HAS_rot_i64). */
 666     case INDEX_op_rotr_i64:     /* Optional (TCG_TARGET_HAS_rot_i64). */
 667         tcg_out_r(s, args[0]);
 668         tcg_out_ri64(s, const_args[1], args[1]);
 669         tcg_out_ri64(s, const_args[2], args[2]);
 670         break;
 671     case INDEX_op_deposit_i64:  /* Optional (TCG_TARGET_HAS_deposit_i64). */
 672         tcg_out_r(s, args[0]);
 673         tcg_out_r(s, args[1]);
 674         tcg_out_r(s, args[2]);
 675         assert(args[3] <= UINT8_MAX);
 676         tcg_out8(s, args[3]);
 677         assert(args[4] <= UINT8_MAX);
 678         tcg_out8(s, args[4]);
 679         break;
 680     case INDEX_op_div_i64:      /* Optional (TCG_TARGET_HAS_div_i64). */
 681     case INDEX_op_divu_i64:     /* Optional (TCG_TARGET_HAS_div_i64). */
 682     case INDEX_op_rem_i64:      /* Optional (TCG_TARGET_HAS_div_i64). */
 683     case INDEX_op_remu_i64:     /* Optional (TCG_TARGET_HAS_div_i64). */
 684         TODO();
 685         break;
 686     case INDEX_op_div2_i64:     /* Optional (TCG_TARGET_HAS_div2_i64). */
 687     case INDEX_op_divu2_i64:    /* Optional (TCG_TARGET_HAS_div2_i64). */
 688         TODO();
 689         break;
 690     case INDEX_op_brcond_i64:
 691         tcg_out_r(s, args[0]);
 692         tcg_out_ri64(s, const_args[1], args[1]);
 693         tcg_out8(s, args[2]);           /* condition */
 694         tci_out_label(s, arg_label(args[3]));
 695         break;
 696     case INDEX_op_bswap16_i64:  /* Optional (TCG_TARGET_HAS_bswap16_i64). */
 697     case INDEX_op_bswap32_i64:  /* Optional (TCG_TARGET_HAS_bswap32_i64). */
 698     case INDEX_op_bswap64_i64:  /* Optional (TCG_TARGET_HAS_bswap64_i64). */
 699     case INDEX_op_not_i64:      /* Optional (TCG_TARGET_HAS_not_i64). */
 700     case INDEX_op_neg_i64:      /* Optional (TCG_TARGET_HAS_neg_i64). */
 701     case INDEX_op_ext8s_i64:    /* Optional (TCG_TARGET_HAS_ext8s_i64). */
 702     case INDEX_op_ext8u_i64:    /* Optional (TCG_TARGET_HAS_ext8u_i64). */
 703     case INDEX_op_ext16s_i64:   /* Optional (TCG_TARGET_HAS_ext16s_i64). */
 704     case INDEX_op_ext16u_i64:   /* Optional (TCG_TARGET_HAS_ext16u_i64). */
 705     case INDEX_op_ext32s_i64:   /* Optional (TCG_TARGET_HAS_ext32s_i64). */
 706     case INDEX_op_ext32u_i64:   /* Optional (TCG_TARGET_HAS_ext32u_i64). */
 707     case INDEX_op_ext_i32_i64:
 708     case INDEX_op_extu_i32_i64:
 709 #endif /* TCG_TARGET_REG_BITS == 64 */
 710     case INDEX_op_neg_i32:      /* Optional (TCG_TARGET_HAS_neg_i32). */
 711     case INDEX_op_not_i32:      /* Optional (TCG_TARGET_HAS_not_i32). */
 712     case INDEX_op_ext8s_i32:    /* Optional (TCG_TARGET_HAS_ext8s_i32). */
 713     case INDEX_op_ext16s_i32:   /* Optional (TCG_TARGET_HAS_ext16s_i32). */
 714     case INDEX_op_ext8u_i32:    /* Optional (TCG_TARGET_HAS_ext8u_i32). */
 715     case INDEX_op_ext16u_i32:   /* Optional (TCG_TARGET_HAS_ext16u_i32). */
 716     case INDEX_op_bswap16_i32:  /* Optional (TCG_TARGET_HAS_bswap16_i32). */
 717     case INDEX_op_bswap32_i32:  /* Optional (TCG_TARGET_HAS_bswap32_i32). */
 718         tcg_out_r(s, args[0]);
 719         tcg_out_r(s, args[1]);
 720         break;
 721     case INDEX_op_div_i32:      /* Optional (TCG_TARGET_HAS_div_i32). */
 722     case INDEX_op_divu_i32:     /* Optional (TCG_TARGET_HAS_div_i32). */
 723     case INDEX_op_rem_i32:      /* Optional (TCG_TARGET_HAS_div_i32). */
 724     case INDEX_op_remu_i32:     /* Optional (TCG_TARGET_HAS_div_i32). */
 725         tcg_out_r(s, args[0]);
 726         tcg_out_ri32(s, const_args[1], args[1]);
 727         tcg_out_ri32(s, const_args[2], args[2]);
 728         break;
 729     case INDEX_op_div2_i32:     /* Optional (TCG_TARGET_HAS_div2_i32). */
 730     case INDEX_op_divu2_i32:    /* Optional (TCG_TARGET_HAS_div2_i32). */
 731         TODO();
 732         break;
 733 #if TCG_TARGET_REG_BITS == 32
 734     case INDEX_op_add2_i32:
 735     case INDEX_op_sub2_i32:
 736         tcg_out_r(s, args[0]);
 737         tcg_out_r(s, args[1]);
 738         tcg_out_r(s, args[2]);
 739         tcg_out_r(s, args[3]);
 740         tcg_out_r(s, args[4]);
 741         tcg_out_r(s, args[5]);
 742         break;
 743     case INDEX_op_brcond2_i32:
 744         tcg_out_r(s, args[0]);
 745         tcg_out_r(s, args[1]);
 746         tcg_out_ri32(s, const_args[2], args[2]);
 747         tcg_out_ri32(s, const_args[3], args[3]);
 748         tcg_out8(s, args[4]);           /* condition */
 749         tci_out_label(s, arg_label(args[5]));
 750         break;
 751     case INDEX_op_mulu2_i32:
 752         tcg_out_r(s, args[0]);
 753         tcg_out_r(s, args[1]);
 754         tcg_out_r(s, args[2]);
 755         tcg_out_r(s, args[3]);
 756         break;
 757 #endif
 758     case INDEX_op_brcond_i32:
 759         tcg_out_r(s, args[0]);
 760         tcg_out_ri32(s, const_args[1], args[1]);
 761         tcg_out8(s, args[2]);           /* condition */
 762         tci_out_label(s, arg_label(args[3]));
 763         break;
 764     case INDEX_op_qemu_ld_i32:
 765         tcg_out_r(s, *args++);
 766         tcg_out_r(s, *args++);
 767         if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
 768             tcg_out_r(s, *args++);
 769         }
 770         tcg_out_i(s, *args++);
 771         break;
 772     case INDEX_op_qemu_ld_i64:
 773         tcg_out_r(s, *args++);
 774         if (TCG_TARGET_REG_BITS == 32) {
 775             tcg_out_r(s, *args++);
 776         }
 777         tcg_out_r(s, *args++);
 778         if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
 779             tcg_out_r(s, *args++);
 780         }
 781         tcg_out_i(s, *args++);
 782         break;
 783     case INDEX_op_qemu_st_i32:
 784         tcg_out_r(s, *args++);
 785         tcg_out_r(s, *args++);
 786         if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
 787             tcg_out_r(s, *args++);
 788         }
 789         tcg_out_i(s, *args++);
 790         break;
 791     case INDEX_op_qemu_st_i64:
 792         tcg_out_r(s, *args++);
 793         if (TCG_TARGET_REG_BITS == 32) {
 794             tcg_out_r(s, *args++);
 795         }
 796         tcg_out_r(s, *args++);
 797         if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
 798             tcg_out_r(s, *args++);
 799         }
 800         tcg_out_i(s, *args++);
 801         break;
 802     case INDEX_op_mov_i32:  /* Always emitted via tcg_out_mov.  */
 803     case INDEX_op_mov_i64:
 804     case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi.  */
 805     case INDEX_op_movi_i64:
 806     case INDEX_op_call:     /* Always emitted via tcg_out_call.  */
 807     default:
 808         tcg_abort();
 809     }
 810     old_code_ptr[1] = s->code_ptr - old_code_ptr;
 811 }
 812
 813 static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1,
 814                        intptr_t arg2)
 815 {
 816     uint8_t *old_code_ptr = s->code_ptr;
 817     if (type == TCG_TYPE_I32) {
 818         tcg_out_op_t(s, INDEX_op_st_i32);
 819         tcg_out_r(s, arg);
 820         tcg_out_r(s, arg1);
 821         tcg_out32(s, arg2);
 822     } else {
 823         assert(type == TCG_TYPE_I64);
 824 #if TCG_TARGET_REG_BITS == 64
 825         tcg_out_op_t(s, INDEX_op_st_i64);
 826         tcg_out_r(s, arg);
 827         tcg_out_r(s, arg1);
 828         tcg_out32(s, arg2);
 829 #else
 830         TODO();
 831 #endif
 832     }
 833     old_code_ptr[1] = s->code_ptr - old_code_ptr;
 834 }
 835
 836 /* Test if a constant matches the constraint. */
 837 static int tcg_target_const_match(tcg_target_long val, TCGType type,
 838                                   const TCGArgConstraint *arg_ct)
 839 {
 840     /* No need to return 0 or 1, 0 or != 0 is good enough. */
 841     return arg_ct->ct & TCG_CT_CONST;
 842 }
 843
 844 static void tcg_target_init(TCGContext *s)
 845 {
 846 #if defined(CONFIG_DEBUG_TCG_INTERPRETER)
 847     const char *envval = getenv("DEBUG_TCG");
 848     if (envval) {
 849         qemu_set_log(strtol(envval, NULL, 0));
 850     }
 851 #endif
 852
 853     /* The current code uses uint8_t for tcg operations. */
 854     assert(tcg_op_defs_max <= UINT8_MAX);
 855
 856     /* Registers available for 32 bit operations. */
 857     tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0,
 858                      BIT(TCG_TARGET_NB_REGS) - 1);
 859     /* Registers available for 64 bit operations. */
 860     tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0,
 861                      BIT(TCG_TARGET_NB_REGS) - 1);
 862     /* TODO: Which registers should be set here? */
 863     tcg_regset_set32(tcg_target_call_clobber_regs, 0,
 864                      BIT(TCG_TARGET_NB_REGS) - 1);
 865
 866     tcg_regset_clear(s->reserved_regs);
 867     tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
 868     tcg_add_target_add_op_defs(tcg_target_op_defs);
 869
 870     /* We use negative offsets from "sp" so that we can distinguish
 871        stores that might pretend to be call arguments.  */
 872     tcg_set_frame(s, TCG_REG_CALL_STACK,
 873                   -CPU_TEMP_BUF_NLONGS * sizeof(long),
 874                   CPU_TEMP_BUF_NLONGS * sizeof(long));
 875 }
 876
 877 /* Generate global QEMU prologue and epilogue code. */
 878 static inline void tcg_target_qemu_prologue(TCGContext *s)
 879 {
 880 }