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Update version for v1.0-rc1
[qemu.git] / hw / usb-ehci.c
blobcdd5aae1e946229a7417461a890db3f923d2fedc
1 /*
2 * QEMU USB EHCI Emulation
3 *
4 * Copyright(c) 2008 Emutex Ltd. (address@hidden)
5 *
6 * EHCI project was started by Mark Burkley, with contributions by
7 * Niels de Vos. David S. Ahern continued working on it. Kevin Wolf,
8 * Jan Kiszka and Vincent Palatin contributed bugfixes.
9 *
10 *
11 * This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU Lesser General Public
13 * License as published by the Free Software Foundation; either
14 * version 2 of the License, or(at your option) any later version.
15 *
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * Lesser General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <http://www.gnu.org/licenses/>.
23 */
24
25 #include "hw.h"
26 #include "qemu-timer.h"
27 #include "usb.h"
28 #include "pci.h"
29 #include "monitor.h"
30 #include "trace.h"
31 #include "dma.h"
32
33 #define EHCI_DEBUG 0
34
35 #if EHCI_DEBUG
36 #define DPRINTF printf
37 #else
38 #define DPRINTF(...)
39 #endif
40
41 /* internal processing - reset HC to try and recover */
42 #define USB_RET_PROCERR (-99)
43
44 #define MMIO_SIZE 0x1000
45
46 /* Capability Registers Base Address - section 2.2 */
47 #define CAPREGBASE 0x0000
48 #define CAPLENGTH CAPREGBASE + 0x0000 // 1-byte, 0x0001 reserved
49 #define HCIVERSION CAPREGBASE + 0x0002 // 2-bytes, i/f version #
50 #define HCSPARAMS CAPREGBASE + 0x0004 // 4-bytes, structural params
51 #define HCCPARAMS CAPREGBASE + 0x0008 // 4-bytes, capability params
52 #define EECP HCCPARAMS + 1
53 #define HCSPPORTROUTE1 CAPREGBASE + 0x000c
54 #define HCSPPORTROUTE2 CAPREGBASE + 0x0010
55
56 #define OPREGBASE 0x0020 // Operational Registers Base Address
57
58 #define USBCMD OPREGBASE + 0x0000
59 #define USBCMD_RUNSTOP (1 << 0) // run / Stop
60 #define USBCMD_HCRESET (1 << 1) // HC Reset
61 #define USBCMD_FLS (3 << 2) // Frame List Size
62 #define USBCMD_FLS_SH 2 // Frame List Size Shift
63 #define USBCMD_PSE (1 << 4) // Periodic Schedule Enable
64 #define USBCMD_ASE (1 << 5) // Asynch Schedule Enable
65 #define USBCMD_IAAD (1 << 6) // Int Asynch Advance Doorbell
66 #define USBCMD_LHCR (1 << 7) // Light Host Controller Reset
67 #define USBCMD_ASPMC (3 << 8) // Async Sched Park Mode Count
68 #define USBCMD_ASPME (1 << 11) // Async Sched Park Mode Enable
69 #define USBCMD_ITC (0x7f << 16) // Int Threshold Control
70 #define USBCMD_ITC_SH 16 // Int Threshold Control Shift
71
72 #define USBSTS OPREGBASE + 0x0004
73 #define USBSTS_RO_MASK 0x0000003f
74 #define USBSTS_INT (1 << 0) // USB Interrupt
75 #define USBSTS_ERRINT (1 << 1) // Error Interrupt
76 #define USBSTS_PCD (1 << 2) // Port Change Detect
77 #define USBSTS_FLR (1 << 3) // Frame List Rollover
78 #define USBSTS_HSE (1 << 4) // Host System Error
79 #define USBSTS_IAA (1 << 5) // Interrupt on Async Advance
80 #define USBSTS_HALT (1 << 12) // HC Halted
81 #define USBSTS_REC (1 << 13) // Reclamation
82 #define USBSTS_PSS (1 << 14) // Periodic Schedule Status
83 #define USBSTS_ASS (1 << 15) // Asynchronous Schedule Status
84
85 /*
86 * Interrupt enable bits correspond to the interrupt active bits in USBSTS
87 * so no need to redefine here.
88 */
89 #define USBINTR OPREGBASE + 0x0008
90 #define USBINTR_MASK 0x0000003f
91
92 #define FRINDEX OPREGBASE + 0x000c
93 #define CTRLDSSEGMENT OPREGBASE + 0x0010
94 #define PERIODICLISTBASE OPREGBASE + 0x0014
95 #define ASYNCLISTADDR OPREGBASE + 0x0018
96 #define ASYNCLISTADDR_MASK 0xffffffe0
97
98 #define CONFIGFLAG OPREGBASE + 0x0040
99
100 #define PORTSC (OPREGBASE + 0x0044)
101 #define PORTSC_BEGIN PORTSC
102 #define PORTSC_END (PORTSC + 4 * NB_PORTS)
103 /*
104 * Bits that are reserved or are read-only are masked out of values
105 * written to us by software
106 */
107 #define PORTSC_RO_MASK 0x007001c0
108 #define PORTSC_RWC_MASK 0x0000002a
109 #define PORTSC_WKOC_E (1 << 22) // Wake on Over Current Enable
110 #define PORTSC_WKDS_E (1 << 21) // Wake on Disconnect Enable
111 #define PORTSC_WKCN_E (1 << 20) // Wake on Connect Enable
112 #define PORTSC_PTC (15 << 16) // Port Test Control
113 #define PORTSC_PTC_SH 16 // Port Test Control shift
114 #define PORTSC_PIC (3 << 14) // Port Indicator Control
115 #define PORTSC_PIC_SH 14 // Port Indicator Control Shift
116 #define PORTSC_POWNER (1 << 13) // Port Owner
117 #define PORTSC_PPOWER (1 << 12) // Port Power
118 #define PORTSC_LINESTAT (3 << 10) // Port Line Status
119 #define PORTSC_LINESTAT_SH 10 // Port Line Status Shift
120 #define PORTSC_PRESET (1 << 8) // Port Reset
121 #define PORTSC_SUSPEND (1 << 7) // Port Suspend
122 #define PORTSC_FPRES (1 << 6) // Force Port Resume
123 #define PORTSC_OCC (1 << 5) // Over Current Change
124 #define PORTSC_OCA (1 << 4) // Over Current Active
125 #define PORTSC_PEDC (1 << 3) // Port Enable/Disable Change
126 #define PORTSC_PED (1 << 2) // Port Enable/Disable
127 #define PORTSC_CSC (1 << 1) // Connect Status Change
128 #define PORTSC_CONNECT (1 << 0) // Current Connect Status
129
130 #define FRAME_TIMER_FREQ 1000
131 #define FRAME_TIMER_NS (1000000000 / FRAME_TIMER_FREQ)
132
133 #define NB_MAXINTRATE 8 // Max rate at which controller issues ints
134 #define NB_PORTS 6 // Number of downstream ports
135 #define BUFF_SIZE 5*4096 // Max bytes to transfer per transaction
136 #define MAX_ITERATIONS 20 // Max number of QH before we break the loop
137 #define MAX_QH 100 // Max allowable queue heads in a chain
138
139 /* Internal periodic / asynchronous schedule state machine states
140 */
141 typedef enum {
142 EST_INACTIVE = 1000,
143 EST_ACTIVE,
144 EST_EXECUTING,
145 EST_SLEEPING,
146 /* The following states are internal to the state machine function
147 */
148 EST_WAITLISTHEAD,
149 EST_FETCHENTRY,
150 EST_FETCHQH,
151 EST_FETCHITD,
152 EST_FETCHSITD,
153 EST_ADVANCEQUEUE,
154 EST_FETCHQTD,
155 EST_EXECUTE,
156 EST_WRITEBACK,
157 EST_HORIZONTALQH
158 } EHCI_STATES;
159
160 /* macros for accessing fields within next link pointer entry */
161 #define NLPTR_GET(x) ((x) & 0xffffffe0)
162 #define NLPTR_TYPE_GET(x) (((x) >> 1) & 3)
163 #define NLPTR_TBIT(x) ((x) & 1) // 1=invalid, 0=valid
164
165 /* link pointer types */
166 #define NLPTR_TYPE_ITD 0 // isoc xfer descriptor
167 #define NLPTR_TYPE_QH 1 // queue head
168 #define NLPTR_TYPE_STITD 2 // split xaction, isoc xfer descriptor
169 #define NLPTR_TYPE_FSTN 3 // frame span traversal node
170
171
172 /* EHCI spec version 1.0 Section 3.3
173 */
174 typedef struct EHCIitd {
175 uint32_t next;
176
177 uint32_t transact[8];
178 #define ITD_XACT_ACTIVE (1 << 31)
179 #define ITD_XACT_DBERROR (1 << 30)
180 #define ITD_XACT_BABBLE (1 << 29)
181 #define ITD_XACT_XACTERR (1 << 28)
182 #define ITD_XACT_LENGTH_MASK 0x0fff0000
183 #define ITD_XACT_LENGTH_SH 16
184 #define ITD_XACT_IOC (1 << 15)
185 #define ITD_XACT_PGSEL_MASK 0x00007000
186 #define ITD_XACT_PGSEL_SH 12
187 #define ITD_XACT_OFFSET_MASK 0x00000fff
188
189 uint32_t bufptr[7];
190 #define ITD_BUFPTR_MASK 0xfffff000
191 #define ITD_BUFPTR_SH 12
192 #define ITD_BUFPTR_EP_MASK 0x00000f00
193 #define ITD_BUFPTR_EP_SH 8
194 #define ITD_BUFPTR_DEVADDR_MASK 0x0000007f
195 #define ITD_BUFPTR_DEVADDR_SH 0
196 #define ITD_BUFPTR_DIRECTION (1 << 11)
197 #define ITD_BUFPTR_MAXPKT_MASK 0x000007ff
198 #define ITD_BUFPTR_MAXPKT_SH 0
199 #define ITD_BUFPTR_MULT_MASK 0x00000003
200 #define ITD_BUFPTR_MULT_SH 0
201 } EHCIitd;
202
203 /* EHCI spec version 1.0 Section 3.4
204 */
205 typedef struct EHCIsitd {
206 uint32_t next; // Standard next link pointer
207 uint32_t epchar;
208 #define SITD_EPCHAR_IO (1 << 31)
209 #define SITD_EPCHAR_PORTNUM_MASK 0x7f000000
210 #define SITD_EPCHAR_PORTNUM_SH 24
211 #define SITD_EPCHAR_HUBADD_MASK 0x007f0000
212 #define SITD_EPCHAR_HUBADDR_SH 16
213 #define SITD_EPCHAR_EPNUM_MASK 0x00000f00
214 #define SITD_EPCHAR_EPNUM_SH 8
215 #define SITD_EPCHAR_DEVADDR_MASK 0x0000007f
216
217 uint32_t uframe;
218 #define SITD_UFRAME_CMASK_MASK 0x0000ff00
219 #define SITD_UFRAME_CMASK_SH 8
220 #define SITD_UFRAME_SMASK_MASK 0x000000ff
221
222 uint32_t results;
223 #define SITD_RESULTS_IOC (1 << 31)
224 #define SITD_RESULTS_PGSEL (1 << 30)
225 #define SITD_RESULTS_TBYTES_MASK 0x03ff0000
226 #define SITD_RESULTS_TYBYTES_SH 16
227 #define SITD_RESULTS_CPROGMASK_MASK 0x0000ff00
228 #define SITD_RESULTS_CPROGMASK_SH 8
229 #define SITD_RESULTS_ACTIVE (1 << 7)
230 #define SITD_RESULTS_ERR (1 << 6)
231 #define SITD_RESULTS_DBERR (1 << 5)
232 #define SITD_RESULTS_BABBLE (1 << 4)
233 #define SITD_RESULTS_XACTERR (1 << 3)
234 #define SITD_RESULTS_MISSEDUF (1 << 2)
235 #define SITD_RESULTS_SPLITXSTATE (1 << 1)
236
237 uint32_t bufptr[2];
238 #define SITD_BUFPTR_MASK 0xfffff000
239 #define SITD_BUFPTR_CURROFF_MASK 0x00000fff
240 #define SITD_BUFPTR_TPOS_MASK 0x00000018
241 #define SITD_BUFPTR_TPOS_SH 3
242 #define SITD_BUFPTR_TCNT_MASK 0x00000007
243
244 uint32_t backptr; // Standard next link pointer
245 } EHCIsitd;
246
247 /* EHCI spec version 1.0 Section 3.5
248 */
249 typedef struct EHCIqtd {
250 uint32_t next; // Standard next link pointer
251 uint32_t altnext; // Standard next link pointer
252 uint32_t token;
253 #define QTD_TOKEN_DTOGGLE (1 << 31)
254 #define QTD_TOKEN_TBYTES_MASK 0x7fff0000
255 #define QTD_TOKEN_TBYTES_SH 16
256 #define QTD_TOKEN_IOC (1 << 15)
257 #define QTD_TOKEN_CPAGE_MASK 0x00007000
258 #define QTD_TOKEN_CPAGE_SH 12
259 #define QTD_TOKEN_CERR_MASK 0x00000c00
260 #define QTD_TOKEN_CERR_SH 10
261 #define QTD_TOKEN_PID_MASK 0x00000300
262 #define QTD_TOKEN_PID_SH 8
263 #define QTD_TOKEN_ACTIVE (1 << 7)
264 #define QTD_TOKEN_HALT (1 << 6)
265 #define QTD_TOKEN_DBERR (1 << 5)
266 #define QTD_TOKEN_BABBLE (1 << 4)
267 #define QTD_TOKEN_XACTERR (1 << 3)
268 #define QTD_TOKEN_MISSEDUF (1 << 2)
269 #define QTD_TOKEN_SPLITXSTATE (1 << 1)
270 #define QTD_TOKEN_PING (1 << 0)
271
272 uint32_t bufptr[5]; // Standard buffer pointer
273 #define QTD_BUFPTR_MASK 0xfffff000
274 #define QTD_BUFPTR_SH 12
275 } EHCIqtd;
276
277 /* EHCI spec version 1.0 Section 3.6
278 */
279 typedef struct EHCIqh {
280 uint32_t next; // Standard next link pointer
281
282 /* endpoint characteristics */
283 uint32_t epchar;
284 #define QH_EPCHAR_RL_MASK 0xf0000000
285 #define QH_EPCHAR_RL_SH 28
286 #define QH_EPCHAR_C (1 << 27)
287 #define QH_EPCHAR_MPLEN_MASK 0x07FF0000
288 #define QH_EPCHAR_MPLEN_SH 16
289 #define QH_EPCHAR_H (1 << 15)
290 #define QH_EPCHAR_DTC (1 << 14)
291 #define QH_EPCHAR_EPS_MASK 0x00003000
292 #define QH_EPCHAR_EPS_SH 12
293 #define EHCI_QH_EPS_FULL 0
294 #define EHCI_QH_EPS_LOW 1
295 #define EHCI_QH_EPS_HIGH 2
296 #define EHCI_QH_EPS_RESERVED 3
297
298 #define QH_EPCHAR_EP_MASK 0x00000f00
299 #define QH_EPCHAR_EP_SH 8
300 #define QH_EPCHAR_I (1 << 7)
301 #define QH_EPCHAR_DEVADDR_MASK 0x0000007f
302 #define QH_EPCHAR_DEVADDR_SH 0
303
304 /* endpoint capabilities */
305 uint32_t epcap;
306 #define QH_EPCAP_MULT_MASK 0xc0000000
307 #define QH_EPCAP_MULT_SH 30
308 #define QH_EPCAP_PORTNUM_MASK 0x3f800000
309 #define QH_EPCAP_PORTNUM_SH 23
310 #define QH_EPCAP_HUBADDR_MASK 0x007f0000
311 #define QH_EPCAP_HUBADDR_SH 16
312 #define QH_EPCAP_CMASK_MASK 0x0000ff00
313 #define QH_EPCAP_CMASK_SH 8
314 #define QH_EPCAP_SMASK_MASK 0x000000ff
315 #define QH_EPCAP_SMASK_SH 0
316
317 uint32_t current_qtd; // Standard next link pointer
318 uint32_t next_qtd; // Standard next link pointer
319 uint32_t altnext_qtd;
320 #define QH_ALTNEXT_NAKCNT_MASK 0x0000001e
321 #define QH_ALTNEXT_NAKCNT_SH 1
322
323 uint32_t token; // Same as QTD token
324 uint32_t bufptr[5]; // Standard buffer pointer
325 #define BUFPTR_CPROGMASK_MASK 0x000000ff
326 #define BUFPTR_FRAMETAG_MASK 0x0000001f
327 #define BUFPTR_SBYTES_MASK 0x00000fe0
328 #define BUFPTR_SBYTES_SH 5
329 } EHCIqh;
330
331 /* EHCI spec version 1.0 Section 3.7
332 */
333 typedef struct EHCIfstn {
334 uint32_t next; // Standard next link pointer
335 uint32_t backptr; // Standard next link pointer
336 } EHCIfstn;
337
338 typedef struct EHCIQueue EHCIQueue;
339 typedef struct EHCIState EHCIState;
340
341 enum async_state {
342 EHCI_ASYNC_NONE = 0,
343 EHCI_ASYNC_INFLIGHT,
344 EHCI_ASYNC_FINISHED,
345 };
346
347 struct EHCIQueue {
348 EHCIState *ehci;
349 QTAILQ_ENTRY(EHCIQueue) next;
350 bool async_schedule;
351 uint32_t seen;
352 uint64_t ts;
353
354 /* cached data from guest - needs to be flushed
355 * when guest removes an entry (doorbell, handshake sequence)
356 */
357 EHCIqh qh; // copy of current QH (being worked on)
358 uint32_t qhaddr; // address QH read from
359 EHCIqtd qtd; // copy of current QTD (being worked on)
360 uint32_t qtdaddr; // address QTD read from
361
362 USBPacket packet;
363 QEMUSGList sgl;
364 int pid;
365 uint32_t tbytes;
366 enum async_state async;
367 int usb_status;
368 };
369
370 struct EHCIState {
371 PCIDevice dev;
372 USBBus bus;
373 qemu_irq irq;
374 MemoryRegion mem;
375 int companion_count;
376
377 /* properties */
378 uint32_t freq;
379 uint32_t maxframes;
380
381 /*
382 * EHCI spec version 1.0 Section 2.3
383 * Host Controller Operational Registers
384 */
385 union {
386 uint8_t mmio[MMIO_SIZE];
387 struct {
388 uint8_t cap[OPREGBASE];
389 uint32_t usbcmd;
390 uint32_t usbsts;
391 uint32_t usbintr;
392 uint32_t frindex;
393 uint32_t ctrldssegment;
394 uint32_t periodiclistbase;
395 uint32_t asynclistaddr;
396 uint32_t notused[9];
397 uint32_t configflag;
398 uint32_t portsc[NB_PORTS];
399 };
400 };
401
402 /*
403 * Internal states, shadow registers, etc
404 */
405 uint32_t sofv;
406 QEMUTimer *frame_timer;
407 int attach_poll_counter;
408 int astate; // Current state in asynchronous schedule
409 int pstate; // Current state in periodic schedule
410 USBPort ports[NB_PORTS];
411 USBPort *companion_ports[NB_PORTS];
412 uint32_t usbsts_pending;
413 QTAILQ_HEAD(, EHCIQueue) queues;
414
415 uint32_t a_fetch_addr; // which address to look at next
416 uint32_t p_fetch_addr; // which address to look at next
417
418 USBPacket ipacket;
419 QEMUSGList isgl;
420 int isoch_pause;
421
422 uint64_t last_run_ns;
423 };
424
425 #define SET_LAST_RUN_CLOCK(s) \
426 (s)->last_run_ns = qemu_get_clock_ns(vm_clock);
427
428 /* nifty macros from Arnon's EHCI version */
429 #define get_field(data, field) \
430 (((data) & field##_MASK) >> field##_SH)
431
432 #define set_field(data, newval, field) do { \
433 uint32_t val = *data; \
434 val &= ~ field##_MASK; \
435 val |= ((newval) << field##_SH) & field##_MASK; \
436 *data = val; \
437 } while(0)
438
439 static const char *ehci_state_names[] = {
440 [ EST_INACTIVE ] = "INACTIVE",
441 [ EST_ACTIVE ] = "ACTIVE",
442 [ EST_EXECUTING ] = "EXECUTING",
443 [ EST_SLEEPING ] = "SLEEPING",
444 [ EST_WAITLISTHEAD ] = "WAITLISTHEAD",
445 [ EST_FETCHENTRY ] = "FETCH ENTRY",
446 [ EST_FETCHQH ] = "FETCH QH",
447 [ EST_FETCHITD ] = "FETCH ITD",
448 [ EST_ADVANCEQUEUE ] = "ADVANCEQUEUE",
449 [ EST_FETCHQTD ] = "FETCH QTD",
450 [ EST_EXECUTE ] = "EXECUTE",
451 [ EST_WRITEBACK ] = "WRITEBACK",
452 [ EST_HORIZONTALQH ] = "HORIZONTALQH",
453 };
454
455 static const char *ehci_mmio_names[] = {
456 [ CAPLENGTH ] = "CAPLENGTH",
457 [ HCIVERSION ] = "HCIVERSION",
458 [ HCSPARAMS ] = "HCSPARAMS",
459 [ HCCPARAMS ] = "HCCPARAMS",
460 [ USBCMD ] = "USBCMD",
461 [ USBSTS ] = "USBSTS",
462 [ USBINTR ] = "USBINTR",
463 [ FRINDEX ] = "FRINDEX",
464 [ PERIODICLISTBASE ] = "P-LIST BASE",
465 [ ASYNCLISTADDR ] = "A-LIST ADDR",
466 [ PORTSC_BEGIN ] = "PORTSC #0",
467 [ PORTSC_BEGIN + 4] = "PORTSC #1",
468 [ PORTSC_BEGIN + 8] = "PORTSC #2",
469 [ PORTSC_BEGIN + 12] = "PORTSC #3",
470 [ CONFIGFLAG ] = "CONFIGFLAG",
471 };
472
473 static const char *nr2str(const char **n, size_t len, uint32_t nr)
474 {
475 if (nr < len && n[nr] != NULL) {
476 return n[nr];
477 } else {
478 return "unknown";
479 }
480 }
481
482 static const char *state2str(uint32_t state)
483 {
484 return nr2str(ehci_state_names, ARRAY_SIZE(ehci_state_names), state);
485 }
486
487 static const char *addr2str(target_phys_addr_t addr)
488 {
489 return nr2str(ehci_mmio_names, ARRAY_SIZE(ehci_mmio_names), addr);
490 }
491
492 static void ehci_trace_usbsts(uint32_t mask, int state)
493 {
494 /* interrupts */
495 if (mask & USBSTS_INT) {
496 trace_usb_ehci_usbsts("INT", state);
497 }
498 if (mask & USBSTS_ERRINT) {
499 trace_usb_ehci_usbsts("ERRINT", state);
500 }
501 if (mask & USBSTS_PCD) {
502 trace_usb_ehci_usbsts("PCD", state);
503 }
504 if (mask & USBSTS_FLR) {
505 trace_usb_ehci_usbsts("FLR", state);
506 }
507 if (mask & USBSTS_HSE) {
508 trace_usb_ehci_usbsts("HSE", state);
509 }
510 if (mask & USBSTS_IAA) {
511 trace_usb_ehci_usbsts("IAA", state);
512 }
513
514 /* status */
515 if (mask & USBSTS_HALT) {
516 trace_usb_ehci_usbsts("HALT", state);
517 }
518 if (mask & USBSTS_REC) {
519 trace_usb_ehci_usbsts("REC", state);
520 }
521 if (mask & USBSTS_PSS) {
522 trace_usb_ehci_usbsts("PSS", state);
523 }
524 if (mask & USBSTS_ASS) {
525 trace_usb_ehci_usbsts("ASS", state);
526 }
527 }
528
529 static inline void ehci_set_usbsts(EHCIState *s, int mask)
530 {
531 if ((s->usbsts & mask) == mask) {
532 return;
533 }
534 ehci_trace_usbsts(mask, 1);
535 s->usbsts |= mask;
536 }
537
538 static inline void ehci_clear_usbsts(EHCIState *s, int mask)
539 {
540 if ((s->usbsts & mask) == 0) {
541 return;
542 }
543 ehci_trace_usbsts(mask, 0);
544 s->usbsts &= ~mask;
545 }
546
547 static inline void ehci_set_interrupt(EHCIState *s, int intr)
548 {
549 int level = 0;
550
551 // TODO honour interrupt threshold requests
552
553 ehci_set_usbsts(s, intr);
554
555 if ((s->usbsts & USBINTR_MASK) & s->usbintr) {
556 level = 1;
557 }
558
559 qemu_set_irq(s->irq, level);
560 }
561
562 static inline void ehci_record_interrupt(EHCIState *s, int intr)
563 {
564 s->usbsts_pending |= intr;
565 }
566
567 static inline void ehci_commit_interrupt(EHCIState *s)
568 {
569 if (!s->usbsts_pending) {
570 return;
571 }
572 ehci_set_interrupt(s, s->usbsts_pending);
573 s->usbsts_pending = 0;
574 }
575
576 static void ehci_set_state(EHCIState *s, int async, int state)
577 {
578 if (async) {
579 trace_usb_ehci_state("async", state2str(state));
580 s->astate = state;
581 } else {
582 trace_usb_ehci_state("periodic", state2str(state));
583 s->pstate = state;
584 }
585 }
586
587 static int ehci_get_state(EHCIState *s, int async)
588 {
589 return async ? s->astate : s->pstate;
590 }
591
592 static void ehci_set_fetch_addr(EHCIState *s, int async, uint32_t addr)
593 {
594 if (async) {
595 s->a_fetch_addr = addr;
596 } else {
597 s->p_fetch_addr = addr;
598 }
599 }
600
601 static int ehci_get_fetch_addr(EHCIState *s, int async)
602 {
603 return async ? s->a_fetch_addr : s->p_fetch_addr;
604 }
605
606 static void ehci_trace_qh(EHCIQueue *q, target_phys_addr_t addr, EHCIqh *qh)
607 {
608 /* need three here due to argument count limits */
609 trace_usb_ehci_qh_ptrs(q, addr, qh->next,
610 qh->current_qtd, qh->next_qtd, qh->altnext_qtd);
611 trace_usb_ehci_qh_fields(addr,
612 get_field(qh->epchar, QH_EPCHAR_RL),
613 get_field(qh->epchar, QH_EPCHAR_MPLEN),
614 get_field(qh->epchar, QH_EPCHAR_EPS),
615 get_field(qh->epchar, QH_EPCHAR_EP),
616 get_field(qh->epchar, QH_EPCHAR_DEVADDR));
617 trace_usb_ehci_qh_bits(addr,
618 (bool)(qh->epchar & QH_EPCHAR_C),
619 (bool)(qh->epchar & QH_EPCHAR_H),
620 (bool)(qh->epchar & QH_EPCHAR_DTC),
621 (bool)(qh->epchar & QH_EPCHAR_I));
622 }
623
624 static void ehci_trace_qtd(EHCIQueue *q, target_phys_addr_t addr, EHCIqtd *qtd)
625 {
626 /* need three here due to argument count limits */
627 trace_usb_ehci_qtd_ptrs(q, addr, qtd->next, qtd->altnext);
628 trace_usb_ehci_qtd_fields(addr,
629 get_field(qtd->token, QTD_TOKEN_TBYTES),
630 get_field(qtd->token, QTD_TOKEN_CPAGE),
631 get_field(qtd->token, QTD_TOKEN_CERR),
632 get_field(qtd->token, QTD_TOKEN_PID));
633 trace_usb_ehci_qtd_bits(addr,
634 (bool)(qtd->token & QTD_TOKEN_IOC),
635 (bool)(qtd->token & QTD_TOKEN_ACTIVE),
636 (bool)(qtd->token & QTD_TOKEN_HALT),
637 (bool)(qtd->token & QTD_TOKEN_BABBLE),
638 (bool)(qtd->token & QTD_TOKEN_XACTERR));
639 }
640
641 static void ehci_trace_itd(EHCIState *s, target_phys_addr_t addr, EHCIitd *itd)
642 {
643 trace_usb_ehci_itd(addr, itd->next,
644 get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT),
645 get_field(itd->bufptr[2], ITD_BUFPTR_MULT),
646 get_field(itd->bufptr[0], ITD_BUFPTR_EP),
647 get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR));
648 }
649
650 static void ehci_trace_sitd(EHCIState *s, target_phys_addr_t addr,
651 EHCIsitd *sitd)
652 {
653 trace_usb_ehci_sitd(addr, sitd->next,
654 (bool)(sitd->results & SITD_RESULTS_ACTIVE));
655 }
656
657 /* queue management */
658
659 static EHCIQueue *ehci_alloc_queue(EHCIState *ehci, int async)
660 {
661 EHCIQueue *q;
662
663 q = g_malloc0(sizeof(*q));
664 q->ehci = ehci;
665 q->async_schedule = async;
666 QTAILQ_INSERT_HEAD(&ehci->queues, q, next);
667 trace_usb_ehci_queue_action(q, "alloc");
668 return q;
669 }
670
671 static void ehci_free_queue(EHCIQueue *q)
672 {
673 trace_usb_ehci_queue_action(q, "free");
674 if (q->async == EHCI_ASYNC_INFLIGHT) {
675 usb_cancel_packet(&q->packet);
676 }
677 QTAILQ_REMOVE(&q->ehci->queues, q, next);
678 g_free(q);
679 }
680
681 static EHCIQueue *ehci_find_queue_by_qh(EHCIState *ehci, uint32_t addr)
682 {
683 EHCIQueue *q;
684
685 QTAILQ_FOREACH(q, &ehci->queues, next) {
686 if (addr == q->qhaddr) {
687 return q;
688 }
689 }
690 return NULL;
691 }
692
693 static void ehci_queues_rip_unused(EHCIState *ehci)
694 {
695 EHCIQueue *q, *tmp;
696
697 QTAILQ_FOREACH_SAFE(q, &ehci->queues, next, tmp) {
698 if (q->seen) {
699 q->seen = 0;
700 q->ts = ehci->last_run_ns;
701 continue;
702 }
703 if (ehci->last_run_ns < q->ts + 250000000) {
704 /* allow 0.25 sec idle */
705 continue;
706 }
707 ehci_free_queue(q);
708 }
709 }
710
711 static void ehci_queues_rip_device(EHCIState *ehci, USBDevice *dev)
712 {
713 EHCIQueue *q, *tmp;
714
715 QTAILQ_FOREACH_SAFE(q, &ehci->queues, next, tmp) {
716 if (q->packet.owner != dev) {
717 continue;
718 }
719 ehci_free_queue(q);
720 }
721 }
722
723 static void ehci_queues_rip_all(EHCIState *ehci)
724 {
725 EHCIQueue *q, *tmp;
726
727 QTAILQ_FOREACH_SAFE(q, &ehci->queues, next, tmp) {
728 ehci_free_queue(q);
729 }
730 }
731
732 /* Attach or detach a device on root hub */
733
734 static void ehci_attach(USBPort *port)
735 {
736 EHCIState *s = port->opaque;
737 uint32_t *portsc = &s->portsc[port->index];
738
739 trace_usb_ehci_port_attach(port->index, port->dev->product_desc);
740
741 if (*portsc & PORTSC_POWNER) {
742 USBPort *companion = s->companion_ports[port->index];
743 companion->dev = port->dev;
744 companion->ops->attach(companion);
745 return;
746 }
747
748 *portsc |= PORTSC_CONNECT;
749 *portsc |= PORTSC_CSC;
750
751 ehci_set_interrupt(s, USBSTS_PCD);
752 }
753
754 static void ehci_detach(USBPort *port)
755 {
756 EHCIState *s = port->opaque;
757 uint32_t *portsc = &s->portsc[port->index];
758
759 trace_usb_ehci_port_detach(port->index);
760
761 if (*portsc & PORTSC_POWNER) {
762 USBPort *companion = s->companion_ports[port->index];
763 companion->ops->detach(companion);
764 companion->dev = NULL;
765 return;
766 }
767
768 ehci_queues_rip_device(s, port->dev);
769
770 *portsc &= ~(PORTSC_CONNECT|PORTSC_PED);
771 *portsc |= PORTSC_CSC;
772
773 ehci_set_interrupt(s, USBSTS_PCD);
774 }
775
776 static void ehci_child_detach(USBPort *port, USBDevice *child)
777 {
778 EHCIState *s = port->opaque;
779 uint32_t portsc = s->portsc[port->index];
780
781 if (portsc & PORTSC_POWNER) {
782 USBPort *companion = s->companion_ports[port->index];
783 companion->ops->child_detach(companion, child);
784 companion->dev = NULL;
785 return;
786 }
787
788 ehci_queues_rip_device(s, child);
789 }
790
791 static void ehci_wakeup(USBPort *port)
792 {
793 EHCIState *s = port->opaque;
794 uint32_t portsc = s->portsc[port->index];
795
796 if (portsc & PORTSC_POWNER) {
797 USBPort *companion = s->companion_ports[port->index];
798 if (companion->ops->wakeup) {
799 companion->ops->wakeup(companion);
800 }
801 }
802 }
803
804 static int ehci_register_companion(USBBus *bus, USBPort *ports[],
805 uint32_t portcount, uint32_t firstport)
806 {
807 EHCIState *s = container_of(bus, EHCIState, bus);
808 uint32_t i;
809
810 if (firstport + portcount > NB_PORTS) {
811 qerror_report(QERR_INVALID_PARAMETER_VALUE, "firstport",
812 "firstport on masterbus");
813 error_printf_unless_qmp(
814 "firstport value of %u makes companion take ports %u - %u, which "
815 "is outside of the valid range of 0 - %u\n", firstport, firstport,
816 firstport + portcount - 1, NB_PORTS - 1);
817 return -1;
818 }
819
820 for (i = 0; i < portcount; i++) {
821 if (s->companion_ports[firstport + i]) {
822 qerror_report(QERR_INVALID_PARAMETER_VALUE, "masterbus",
823 "an USB masterbus");
824 error_printf_unless_qmp(
825 "port %u on masterbus %s already has a companion assigned\n",
826 firstport + i, bus->qbus.name);
827 return -1;
828 }
829 }
830
831 for (i = 0; i < portcount; i++) {
832 s->companion_ports[firstport + i] = ports[i];
833 s->ports[firstport + i].speedmask |=
834 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL;
835 /* Ensure devs attached before the initial reset go to the companion */
836 s->portsc[firstport + i] = PORTSC_POWNER;
837 }
838
839 s->companion_count++;
840 s->mmio[0x05] = (s->companion_count << 4) | portcount;
841
842 return 0;
843 }
844
845 /* 4.1 host controller initialization */
846 static void ehci_reset(void *opaque)
847 {
848 EHCIState *s = opaque;
849 int i;
850 USBDevice *devs[NB_PORTS];
851
852 trace_usb_ehci_reset();
853
854 /*
855 * Do the detach before touching portsc, so that it correctly gets send to
856 * us or to our companion based on PORTSC_POWNER before the reset.
857 */
858 for(i = 0; i < NB_PORTS; i++) {
859 devs[i] = s->ports[i].dev;
860 if (devs[i] && devs[i]->attached) {
861 usb_detach(&s->ports[i]);
862 }
863 }
864
865 memset(&s->mmio[OPREGBASE], 0x00, MMIO_SIZE - OPREGBASE);
866
867 s->usbcmd = NB_MAXINTRATE << USBCMD_ITC_SH;
868 s->usbsts = USBSTS_HALT;
869
870 s->astate = EST_INACTIVE;
871 s->pstate = EST_INACTIVE;
872 s->isoch_pause = -1;
873 s->attach_poll_counter = 0;
874
875 for(i = 0; i < NB_PORTS; i++) {
876 if (s->companion_ports[i]) {
877 s->portsc[i] = PORTSC_POWNER | PORTSC_PPOWER;
878 } else {
879 s->portsc[i] = PORTSC_PPOWER;
880 }
881 if (devs[i] && devs[i]->attached) {
882 usb_attach(&s->ports[i]);
883 usb_send_msg(devs[i], USB_MSG_RESET);
884 }
885 }
886 ehci_queues_rip_all(s);
887 }
888
889 static uint32_t ehci_mem_readb(void *ptr, target_phys_addr_t addr)
890 {
891 EHCIState *s = ptr;
892 uint32_t val;
893
894 val = s->mmio[addr];
895
896 return val;
897 }
898
899 static uint32_t ehci_mem_readw(void *ptr, target_phys_addr_t addr)
900 {
901 EHCIState *s = ptr;
902 uint32_t val;
903
904 val = s->mmio[addr] | (s->mmio[addr+1] << 8);
905
906 return val;
907 }
908
909 static uint32_t ehci_mem_readl(void *ptr, target_phys_addr_t addr)
910 {
911 EHCIState *s = ptr;
912 uint32_t val;
913
914 val = s->mmio[addr] | (s->mmio[addr+1] << 8) |
915 (s->mmio[addr+2] << 16) | (s->mmio[addr+3] << 24);
916
917 trace_usb_ehci_mmio_readl(addr, addr2str(addr), val);
918 return val;
919 }
920
921 static void ehci_mem_writeb(void *ptr, target_phys_addr_t addr, uint32_t val)
922 {
923 fprintf(stderr, "EHCI doesn't handle byte writes to MMIO\n");
924 exit(1);
925 }
926
927 static void ehci_mem_writew(void *ptr, target_phys_addr_t addr, uint32_t val)
928 {
929 fprintf(stderr, "EHCI doesn't handle 16-bit writes to MMIO\n");
930 exit(1);
931 }
932
933 static void handle_port_owner_write(EHCIState *s, int port, uint32_t owner)
934 {
935 USBDevice *dev = s->ports[port].dev;
936 uint32_t *portsc = &s->portsc[port];
937 uint32_t orig;
938
939 if (s->companion_ports[port] == NULL)
940 return;
941
942 owner = owner & PORTSC_POWNER;
943 orig = *portsc & PORTSC_POWNER;
944
945 if (!(owner ^ orig)) {
946 return;
947 }
948
949 if (dev && dev->attached) {
950 usb_detach(&s->ports[port]);
951 }
952
953 *portsc &= ~PORTSC_POWNER;
954 *portsc |= owner;
955
956 if (dev && dev->attached) {
957 usb_attach(&s->ports[port]);
958 }
959 }
960
961 static void handle_port_status_write(EHCIState *s, int port, uint32_t val)
962 {
963 uint32_t *portsc = &s->portsc[port];
964 USBDevice *dev = s->ports[port].dev;
965
966 /* Clear rwc bits */
967 *portsc &= ~(val & PORTSC_RWC_MASK);
968 /* The guest may clear, but not set the PED bit */
969 *portsc &= val | ~PORTSC_PED;
970 /* POWNER is masked out by RO_MASK as it is RO when we've no companion */
971 handle_port_owner_write(s, port, val);
972 /* And finally apply RO_MASK */
973 val &= PORTSC_RO_MASK;
974
975 if ((val & PORTSC_PRESET) && !(*portsc & PORTSC_PRESET)) {
976 trace_usb_ehci_port_reset(port, 1);
977 }
978
979 if (!(val & PORTSC_PRESET) &&(*portsc & PORTSC_PRESET)) {
980 trace_usb_ehci_port_reset(port, 0);
981 if (dev && dev->attached) {
982 usb_reset(&s->ports[port]);
983 *portsc &= ~PORTSC_CSC;
984 }
985
986 /*
987 * Table 2.16 Set the enable bit(and enable bit change) to indicate
988 * to SW that this port has a high speed device attached
989 */
990 if (dev && dev->attached && (dev->speedmask & USB_SPEED_MASK_HIGH)) {
991 val |= PORTSC_PED;
992 }
993 }
994
995 *portsc &= ~PORTSC_RO_MASK;
996 *portsc |= val;
997 }
998
999 static void ehci_mem_writel(void *ptr, target_phys_addr_t addr, uint32_t val)
1000 {
1001 EHCIState *s = ptr;
1002 uint32_t *mmio = (uint32_t *)(&s->mmio[addr]);
1003 uint32_t old = *mmio;
1004 int i;
1005
1006 trace_usb_ehci_mmio_writel(addr, addr2str(addr), val);
1007
1008 /* Only aligned reads are allowed on OHCI */
1009 if (addr & 3) {
1010 fprintf(stderr, "usb-ehci: Mis-aligned write to addr 0x"
1011 TARGET_FMT_plx "\n", addr);
1012 return;
1013 }
1014
1015 if (addr >= PORTSC && addr < PORTSC + 4 * NB_PORTS) {
1016 handle_port_status_write(s, (addr-PORTSC)/4, val);
1017 trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old);
1018 return;
1019 }
1020
1021 if (addr < OPREGBASE) {
1022 fprintf(stderr, "usb-ehci: write attempt to read-only register"
1023 TARGET_FMT_plx "\n", addr);
1024 return;
1025 }
1026
1027
1028 /* Do any register specific pre-write processing here. */
1029 switch(addr) {
1030 case USBCMD:
1031 if ((val & USBCMD_RUNSTOP) && !(s->usbcmd & USBCMD_RUNSTOP)) {
1032 qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock));
1033 SET_LAST_RUN_CLOCK(s);
1034 ehci_clear_usbsts(s, USBSTS_HALT);
1035 }
1036
1037 if (!(val & USBCMD_RUNSTOP) && (s->usbcmd & USBCMD_RUNSTOP)) {
1038 qemu_del_timer(s->frame_timer);
1039 // TODO - should finish out some stuff before setting halt
1040 ehci_set_usbsts(s, USBSTS_HALT);
1041 }
1042
1043 if (val & USBCMD_HCRESET) {
1044 ehci_reset(s);
1045 val &= ~USBCMD_HCRESET;
1046 }
1047
1048 /* not supporting dynamic frame list size at the moment */
1049 if ((val & USBCMD_FLS) && !(s->usbcmd & USBCMD_FLS)) {
1050 fprintf(stderr, "attempt to set frame list size -- value %d\n",
1051 val & USBCMD_FLS);
1052 val &= ~USBCMD_FLS;
1053 }
1054 break;
1055
1056 case USBSTS:
1057 val &= USBSTS_RO_MASK; // bits 6 thru 31 are RO
1058 ehci_clear_usbsts(s, val); // bits 0 thru 5 are R/WC
1059 val = s->usbsts;
1060 ehci_set_interrupt(s, 0);
1061 break;
1062
1063 case USBINTR:
1064 val &= USBINTR_MASK;
1065 break;
1066
1067 case FRINDEX:
1068 s->sofv = val >> 3;
1069 break;
1070
1071 case CONFIGFLAG:
1072 val &= 0x1;
1073 if (val) {
1074 for(i = 0; i < NB_PORTS; i++)
1075 handle_port_owner_write(s, i, 0);
1076 }
1077 break;
1078
1079 case PERIODICLISTBASE:
1080 if ((s->usbcmd & USBCMD_PSE) && (s->usbcmd & USBCMD_RUNSTOP)) {
1081 fprintf(stderr,
1082 "ehci: PERIODIC list base register set while periodic schedule\n"
1083 " is enabled and HC is enabled\n");
1084 }
1085 break;
1086
1087 case ASYNCLISTADDR:
1088 if ((s->usbcmd & USBCMD_ASE) && (s->usbcmd & USBCMD_RUNSTOP)) {
1089 fprintf(stderr,
1090 "ehci: ASYNC list address register set while async schedule\n"
1091 " is enabled and HC is enabled\n");
1092 }
1093 break;
1094 }
1095
1096 *mmio = val;
1097 trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old);
1098 }
1099
1100
1101 // TODO : Put in common header file, duplication from usb-ohci.c
1102
1103 /* Get an array of dwords from main memory */
1104 static inline int get_dwords(EHCIState *ehci, uint32_t addr,
1105 uint32_t *buf, int num)
1106 {
1107 int i;
1108
1109 for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
1110 pci_dma_read(&ehci->dev, addr, (uint8_t *)buf, sizeof(*buf));
1111 *buf = le32_to_cpu(*buf);
1112 }
1113
1114 return 1;
1115 }
1116
1117 /* Put an array of dwords in to main memory */
1118 static inline int put_dwords(EHCIState *ehci, uint32_t addr,
1119 uint32_t *buf, int num)
1120 {
1121 int i;
1122
1123 for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
1124 uint32_t tmp = cpu_to_le32(*buf);
1125 pci_dma_write(&ehci->dev, addr, (uint8_t *)&tmp, sizeof(tmp));
1126 }
1127
1128 return 1;
1129 }
1130
1131 // 4.10.2
1132
1133 static int ehci_qh_do_overlay(EHCIQueue *q)
1134 {
1135 int i;
1136 int dtoggle;
1137 int ping;
1138 int eps;
1139 int reload;
1140
1141 // remember values in fields to preserve in qh after overlay
1142
1143 dtoggle = q->qh.token & QTD_TOKEN_DTOGGLE;
1144 ping = q->qh.token & QTD_TOKEN_PING;
1145
1146 q->qh.current_qtd = q->qtdaddr;
1147 q->qh.next_qtd = q->qtd.next;
1148 q->qh.altnext_qtd = q->qtd.altnext;
1149 q->qh.token = q->qtd.token;
1150
1151
1152 eps = get_field(q->qh.epchar, QH_EPCHAR_EPS);
1153 if (eps == EHCI_QH_EPS_HIGH) {
1154 q->qh.token &= ~QTD_TOKEN_PING;
1155 q->qh.token |= ping;
1156 }
1157
1158 reload = get_field(q->qh.epchar, QH_EPCHAR_RL);
1159 set_field(&q->qh.altnext_qtd, reload, QH_ALTNEXT_NAKCNT);
1160
1161 for (i = 0; i < 5; i++) {
1162 q->qh.bufptr[i] = q->qtd.bufptr[i];
1163 }
1164
1165 if (!(q->qh.epchar & QH_EPCHAR_DTC)) {
1166 // preserve QH DT bit
1167 q->qh.token &= ~QTD_TOKEN_DTOGGLE;
1168 q->qh.token |= dtoggle;
1169 }
1170
1171 q->qh.bufptr[1] &= ~BUFPTR_CPROGMASK_MASK;
1172 q->qh.bufptr[2] &= ~BUFPTR_FRAMETAG_MASK;
1173
1174 put_dwords(q->ehci, NLPTR_GET(q->qhaddr), (uint32_t *) &q->qh,
1175 sizeof(EHCIqh) >> 2);
1176
1177 return 0;
1178 }
1179
1180 static int ehci_init_transfer(EHCIQueue *q)
1181 {
1182 uint32_t cpage, offset, bytes, plen;
1183 dma_addr_t page;
1184
1185 cpage = get_field(q->qh.token, QTD_TOKEN_CPAGE);
1186 bytes = get_field(q->qh.token, QTD_TOKEN_TBYTES);
1187 offset = q->qh.bufptr[0] & ~QTD_BUFPTR_MASK;
1188 pci_dma_sglist_init(&q->sgl, &q->ehci->dev, 5);
1189
1190 while (bytes > 0) {
1191 if (cpage > 4) {
1192 fprintf(stderr, "cpage out of range (%d)\n", cpage);
1193 return USB_RET_PROCERR;
1194 }
1195
1196 page = q->qh.bufptr[cpage] & QTD_BUFPTR_MASK;
1197 page += offset;
1198 plen = bytes;
1199 if (plen > 4096 - offset) {
1200 plen = 4096 - offset;
1201 offset = 0;
1202 cpage++;
1203 }
1204
1205 qemu_sglist_add(&q->sgl, page, plen);
1206 bytes -= plen;
1207 }
1208 return 0;
1209 }
1210
1211 static void ehci_finish_transfer(EHCIQueue *q, int status)
1212 {
1213 uint32_t cpage, offset;
1214
1215 qemu_sglist_destroy(&q->sgl);
1216
1217 if (status > 0) {
1218 /* update cpage & offset */
1219 cpage = get_field(q->qh.token, QTD_TOKEN_CPAGE);
1220 offset = q->qh.bufptr[0] & ~QTD_BUFPTR_MASK;
1221
1222 offset += status;
1223 cpage += offset >> QTD_BUFPTR_SH;
1224 offset &= ~QTD_BUFPTR_MASK;
1225
1226 set_field(&q->qh.token, cpage, QTD_TOKEN_CPAGE);
1227 q->qh.bufptr[0] &= QTD_BUFPTR_MASK;
1228 q->qh.bufptr[0] |= offset;
1229 }
1230 }
1231
1232 static void ehci_async_complete_packet(USBPort *port, USBPacket *packet)
1233 {
1234 EHCIQueue *q;
1235 EHCIState *s = port->opaque;
1236 uint32_t portsc = s->portsc[port->index];
1237
1238 if (portsc & PORTSC_POWNER) {
1239 USBPort *companion = s->companion_ports[port->index];
1240 companion->ops->complete(companion, packet);
1241 return;
1242 }
1243
1244 q = container_of(packet, EHCIQueue, packet);
1245 trace_usb_ehci_queue_action(q, "wakeup");
1246 assert(q->async == EHCI_ASYNC_INFLIGHT);
1247 q->async = EHCI_ASYNC_FINISHED;
1248 q->usb_status = packet->result;
1249 }
1250
1251 static void ehci_execute_complete(EHCIQueue *q)
1252 {
1253 int c_err, reload;
1254
1255 assert(q->async != EHCI_ASYNC_INFLIGHT);
1256 q->async = EHCI_ASYNC_NONE;
1257
1258 DPRINTF("execute_complete: qhaddr 0x%x, next %x, qtdaddr 0x%x, status %d\n",
1259 q->qhaddr, q->qh.next, q->qtdaddr, q->usb_status);
1260
1261 if (q->usb_status < 0) {
1262 err:
1263 /* TO-DO: put this is in a function that can be invoked below as well */
1264 c_err = get_field(q->qh.token, QTD_TOKEN_CERR);
1265 c_err--;
1266 set_field(&q->qh.token, c_err, QTD_TOKEN_CERR);
1267
1268 switch(q->usb_status) {
1269 case USB_RET_NODEV:
1270 q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_XACTERR);
1271 ehci_record_interrupt(q->ehci, USBSTS_ERRINT);
1272 break;
1273 case USB_RET_STALL:
1274 q->qh.token |= QTD_TOKEN_HALT;
1275 ehci_record_interrupt(q->ehci, USBSTS_ERRINT);
1276 break;
1277 case USB_RET_NAK:
1278 /* 4.10.3 */
1279 reload = get_field(q->qh.epchar, QH_EPCHAR_RL);
1280 if ((q->pid == USB_TOKEN_IN) && reload) {
1281 int nakcnt = get_field(q->qh.altnext_qtd, QH_ALTNEXT_NAKCNT);
1282 nakcnt--;
1283 set_field(&q->qh.altnext_qtd, nakcnt, QH_ALTNEXT_NAKCNT);
1284 } else if (!reload) {
1285 return;
1286 }
1287 break;
1288 case USB_RET_BABBLE:
1289 q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_BABBLE);
1290 ehci_record_interrupt(q->ehci, USBSTS_ERRINT);
1291 break;
1292 default:
1293 /* should not be triggerable */
1294 fprintf(stderr, "USB invalid response %d to handle\n", q->usb_status);
1295 assert(0);
1296 break;
1297 }
1298 } else {
1299 // DPRINTF("Short packet condition\n");
1300 // TODO check 4.12 for splits
1301
1302 if ((q->usb_status > q->tbytes) && (q->pid == USB_TOKEN_IN)) {
1303 q->usb_status = USB_RET_BABBLE;
1304 goto err;
1305 }
1306
1307 if (q->tbytes && q->pid == USB_TOKEN_IN) {
1308 q->tbytes -= q->usb_status;
1309 } else {
1310 q->tbytes = 0;
1311 }
1312
1313 DPRINTF("updating tbytes to %d\n", q->tbytes);
1314 set_field(&q->qh.token, q->tbytes, QTD_TOKEN_TBYTES);
1315 }
1316 ehci_finish_transfer(q, q->usb_status);
1317 usb_packet_unmap(&q->packet);
1318
1319 q->qh.token ^= QTD_TOKEN_DTOGGLE;
1320 q->qh.token &= ~QTD_TOKEN_ACTIVE;
1321
1322 if ((q->usb_status >= 0) && (q->qh.token & QTD_TOKEN_IOC)) {
1323 ehci_record_interrupt(q->ehci, USBSTS_INT);
1324 }
1325 }
1326
1327 // 4.10.3
1328
1329 static int ehci_execute(EHCIQueue *q)
1330 {
1331 USBPort *port;
1332 USBDevice *dev;
1333 int ret;
1334 int i;
1335 int endp;
1336 int devadr;
1337
1338 if ( !(q->qh.token & QTD_TOKEN_ACTIVE)) {
1339 fprintf(stderr, "Attempting to execute inactive QH\n");
1340 return USB_RET_PROCERR;
1341 }
1342
1343 q->tbytes = (q->qh.token & QTD_TOKEN_TBYTES_MASK) >> QTD_TOKEN_TBYTES_SH;
1344 if (q->tbytes > BUFF_SIZE) {
1345 fprintf(stderr, "Request for more bytes than allowed\n");
1346 return USB_RET_PROCERR;
1347 }
1348
1349 q->pid = (q->qh.token & QTD_TOKEN_PID_MASK) >> QTD_TOKEN_PID_SH;
1350 switch(q->pid) {
1351 case 0: q->pid = USB_TOKEN_OUT; break;
1352 case 1: q->pid = USB_TOKEN_IN; break;
1353 case 2: q->pid = USB_TOKEN_SETUP; break;
1354 default: fprintf(stderr, "bad token\n"); break;
1355 }
1356
1357 if (ehci_init_transfer(q) != 0) {
1358 return USB_RET_PROCERR;
1359 }
1360
1361 endp = get_field(q->qh.epchar, QH_EPCHAR_EP);
1362 devadr = get_field(q->qh.epchar, QH_EPCHAR_DEVADDR);
1363
1364 ret = USB_RET_NODEV;
1365
1366 usb_packet_setup(&q->packet, q->pid, devadr, endp);
1367 usb_packet_map(&q->packet, &q->sgl);
1368
1369 // TO-DO: associating device with ehci port
1370 for(i = 0; i < NB_PORTS; i++) {
1371 port = &q->ehci->ports[i];
1372 dev = port->dev;
1373
1374 if (!(q->ehci->portsc[i] &(PORTSC_CONNECT))) {
1375 DPRINTF("Port %d, no exec, not connected(%08X)\n",
1376 i, q->ehci->portsc[i]);
1377 continue;
1378 }
1379
1380 ret = usb_handle_packet(dev, &q->packet);
1381
1382 DPRINTF("submit: qh %x next %x qtd %x pid %x len %zd "
1383 "(total %d) endp %x ret %d\n",
1384 q->qhaddr, q->qh.next, q->qtdaddr, q->pid,
1385 q->packet.iov.size, q->tbytes, endp, ret);
1386
1387 if (ret != USB_RET_NODEV) {
1388 break;
1389 }
1390 }
1391
1392 if (ret > BUFF_SIZE) {
1393 fprintf(stderr, "ret from usb_handle_packet > BUFF_SIZE\n");
1394 return USB_RET_PROCERR;
1395 }
1396
1397 return ret;
1398 }
1399
1400 /* 4.7.2
1401 */
1402
1403 static int ehci_process_itd(EHCIState *ehci,
1404 EHCIitd *itd)
1405 {
1406 USBPort *port;
1407 USBDevice *dev;
1408 int ret;
1409 uint32_t i, j, len, pid, dir, devaddr, endp;
1410 uint32_t pg, off, ptr1, ptr2, max, mult;
1411
1412 dir =(itd->bufptr[1] & ITD_BUFPTR_DIRECTION);
1413 devaddr = get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR);
1414 endp = get_field(itd->bufptr[0], ITD_BUFPTR_EP);
1415 max = get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT);
1416 mult = get_field(itd->bufptr[2], ITD_BUFPTR_MULT);
1417
1418 for(i = 0; i < 8; i++) {
1419 if (itd->transact[i] & ITD_XACT_ACTIVE) {
1420 pg = get_field(itd->transact[i], ITD_XACT_PGSEL);
1421 off = itd->transact[i] & ITD_XACT_OFFSET_MASK;
1422 ptr1 = (itd->bufptr[pg] & ITD_BUFPTR_MASK);
1423 ptr2 = (itd->bufptr[pg+1] & ITD_BUFPTR_MASK);
1424 len = get_field(itd->transact[i], ITD_XACT_LENGTH);
1425
1426 if (len > max * mult) {
1427 len = max * mult;
1428 }
1429
1430 if (len > BUFF_SIZE) {
1431 return USB_RET_PROCERR;
1432 }
1433
1434 pci_dma_sglist_init(&ehci->isgl, &ehci->dev, 2);
1435 if (off + len > 4096) {
1436 /* transfer crosses page border */
1437 uint32_t len2 = off + len - 4096;
1438 uint32_t len1 = len - len2;
1439 qemu_sglist_add(&ehci->isgl, ptr1 + off, len1);
1440 qemu_sglist_add(&ehci->isgl, ptr2, len2);
1441 } else {
1442 qemu_sglist_add(&ehci->isgl, ptr1 + off, len);
1443 }
1444
1445 pid = dir ? USB_TOKEN_IN : USB_TOKEN_OUT;
1446
1447 usb_packet_setup(&ehci->ipacket, pid, devaddr, endp);
1448 usb_packet_map(&ehci->ipacket, &ehci->isgl);
1449
1450 ret = USB_RET_NODEV;
1451 for (j = 0; j < NB_PORTS; j++) {
1452 port = &ehci->ports[j];
1453 dev = port->dev;
1454
1455 if (!(ehci->portsc[j] &(PORTSC_CONNECT))) {
1456 continue;
1457 }
1458
1459 ret = usb_handle_packet(dev, &ehci->ipacket);
1460
1461 if (ret != USB_RET_NODEV) {
1462 break;
1463 }
1464 }
1465
1466 usb_packet_unmap(&ehci->ipacket);
1467 qemu_sglist_destroy(&ehci->isgl);
1468
1469 #if 0
1470 /* In isoch, there is no facility to indicate a NAK so let's
1471 * instead just complete a zero-byte transaction. Setting
1472 * DBERR seems too draconian.
1473 */
1474
1475 if (ret == USB_RET_NAK) {
1476 if (ehci->isoch_pause > 0) {
1477 DPRINTF("ISOCH: received a NAK but paused so returning\n");
1478 ehci->isoch_pause--;
1479 return 0;
1480 } else if (ehci->isoch_pause == -1) {
1481 DPRINTF("ISOCH: recv NAK & isoch pause inactive, setting\n");
1482 // Pause frindex for up to 50 msec waiting for data from
1483 // remote
1484 ehci->isoch_pause = 50;
1485 return 0;
1486 } else {
1487 DPRINTF("ISOCH: isoch pause timeout! return 0\n");
1488 ret = 0;
1489 }
1490 } else {
1491 DPRINTF("ISOCH: received ACK, clearing pause\n");
1492 ehci->isoch_pause = -1;
1493 }
1494 #else
1495 if (ret == USB_RET_NAK) {
1496 ret = 0;
1497 }
1498 #endif
1499
1500 if (ret >= 0) {
1501 if (!dir) {
1502 /* OUT */
1503 set_field(&itd->transact[i], len - ret, ITD_XACT_LENGTH);
1504 } else {
1505 /* IN */
1506 set_field(&itd->transact[i], ret, ITD_XACT_LENGTH);
1507 }
1508
1509 if (itd->transact[i] & ITD_XACT_IOC) {
1510 ehci_record_interrupt(ehci, USBSTS_INT);
1511 }
1512 }
1513 itd->transact[i] &= ~ITD_XACT_ACTIVE;
1514 }
1515 }
1516 return 0;
1517 }
1518
1519 /* This state is the entry point for asynchronous schedule
1520 * processing. Entry here consitutes a EHCI start event state (4.8.5)
1521 */
1522 static int ehci_state_waitlisthead(EHCIState *ehci, int async)
1523 {
1524 EHCIqh qh;
1525 int i = 0;
1526 int again = 0;
1527 uint32_t entry = ehci->asynclistaddr;
1528
1529 /* set reclamation flag at start event (4.8.6) */
1530 if (async) {
1531 ehci_set_usbsts(ehci, USBSTS_REC);
1532 }
1533
1534 ehci_queues_rip_unused(ehci);
1535
1536 /* Find the head of the list (4.9.1.1) */
1537 for(i = 0; i < MAX_QH; i++) {
1538 get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &qh,
1539 sizeof(EHCIqh) >> 2);
1540 ehci_trace_qh(NULL, NLPTR_GET(entry), &qh);
1541
1542 if (qh.epchar & QH_EPCHAR_H) {
1543 if (async) {
1544 entry |= (NLPTR_TYPE_QH << 1);
1545 }
1546
1547 ehci_set_fetch_addr(ehci, async, entry);
1548 ehci_set_state(ehci, async, EST_FETCHENTRY);
1549 again = 1;
1550 goto out;
1551 }
1552
1553 entry = qh.next;
1554 if (entry == ehci->asynclistaddr) {
1555 break;
1556 }
1557 }
1558
1559 /* no head found for list. */
1560
1561 ehci_set_state(ehci, async, EST_ACTIVE);
1562
1563 out:
1564 return again;
1565 }
1566
1567
1568 /* This state is the entry point for periodic schedule processing as
1569 * well as being a continuation state for async processing.
1570 */
1571 static int ehci_state_fetchentry(EHCIState *ehci, int async)
1572 {
1573 int again = 0;
1574 uint32_t entry = ehci_get_fetch_addr(ehci, async);
1575
1576 if (entry < 0x1000) {
1577 DPRINTF("fetchentry: entry invalid (0x%08x)\n", entry);
1578 ehci_set_state(ehci, async, EST_ACTIVE);
1579 goto out;
1580 }
1581
1582 /* section 4.8, only QH in async schedule */
1583 if (async && (NLPTR_TYPE_GET(entry) != NLPTR_TYPE_QH)) {
1584 fprintf(stderr, "non queue head request in async schedule\n");
1585 return -1;
1586 }
1587
1588 switch (NLPTR_TYPE_GET(entry)) {
1589 case NLPTR_TYPE_QH:
1590 ehci_set_state(ehci, async, EST_FETCHQH);
1591 again = 1;
1592 break;
1593
1594 case NLPTR_TYPE_ITD:
1595 ehci_set_state(ehci, async, EST_FETCHITD);
1596 again = 1;
1597 break;
1598
1599 case NLPTR_TYPE_STITD:
1600 ehci_set_state(ehci, async, EST_FETCHSITD);
1601 again = 1;
1602 break;
1603
1604 default:
1605 /* TODO: handle FSTN type */
1606 fprintf(stderr, "FETCHENTRY: entry at %X is of type %d "
1607 "which is not supported yet\n", entry, NLPTR_TYPE_GET(entry));
1608 return -1;
1609 }
1610
1611 out:
1612 return again;
1613 }
1614
1615 static EHCIQueue *ehci_state_fetchqh(EHCIState *ehci, int async)
1616 {
1617 uint32_t entry;
1618 EHCIQueue *q;
1619 int reload;
1620
1621 entry = ehci_get_fetch_addr(ehci, async);
1622 q = ehci_find_queue_by_qh(ehci, entry);
1623 if (NULL == q) {
1624 q = ehci_alloc_queue(ehci, async);
1625 }
1626 q->qhaddr = entry;
1627 q->seen++;
1628
1629 if (q->seen > 1) {
1630 /* we are going in circles -- stop processing */
1631 ehci_set_state(ehci, async, EST_ACTIVE);
1632 q = NULL;
1633 goto out;
1634 }
1635
1636 get_dwords(ehci, NLPTR_GET(q->qhaddr),
1637 (uint32_t *) &q->qh, sizeof(EHCIqh) >> 2);
1638 ehci_trace_qh(q, NLPTR_GET(q->qhaddr), &q->qh);
1639
1640 if (q->async == EHCI_ASYNC_INFLIGHT) {
1641 /* I/O still in progress -- skip queue */
1642 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1643 goto out;
1644 }
1645 if (q->async == EHCI_ASYNC_FINISHED) {
1646 /* I/O finished -- continue processing queue */
1647 trace_usb_ehci_queue_action(q, "resume");
1648 ehci_set_state(ehci, async, EST_EXECUTING);
1649 goto out;
1650 }
1651
1652 if (async && (q->qh.epchar & QH_EPCHAR_H)) {
1653
1654 /* EHCI spec version 1.0 Section 4.8.3 & 4.10.1 */
1655 if (ehci->usbsts & USBSTS_REC) {
1656 ehci_clear_usbsts(ehci, USBSTS_REC);
1657 } else {
1658 DPRINTF("FETCHQH: QH 0x%08x. H-bit set, reclamation status reset"
1659 " - done processing\n", q->qhaddr);
1660 ehci_set_state(ehci, async, EST_ACTIVE);
1661 q = NULL;
1662 goto out;
1663 }
1664 }
1665
1666 #if EHCI_DEBUG
1667 if (q->qhaddr != q->qh.next) {
1668 DPRINTF("FETCHQH: QH 0x%08x (h %x halt %x active %x) next 0x%08x\n",
1669 q->qhaddr,
1670 q->qh.epchar & QH_EPCHAR_H,
1671 q->qh.token & QTD_TOKEN_HALT,
1672 q->qh.token & QTD_TOKEN_ACTIVE,
1673 q->qh.next);
1674 }
1675 #endif
1676
1677 reload = get_field(q->qh.epchar, QH_EPCHAR_RL);
1678 if (reload) {
1679 set_field(&q->qh.altnext_qtd, reload, QH_ALTNEXT_NAKCNT);
1680 }
1681
1682 if (q->qh.token & QTD_TOKEN_HALT) {
1683 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1684
1685 } else if ((q->qh.token & QTD_TOKEN_ACTIVE) && (q->qh.current_qtd > 0x1000)) {
1686 q->qtdaddr = q->qh.current_qtd;
1687 ehci_set_state(ehci, async, EST_FETCHQTD);
1688
1689 } else {
1690 /* EHCI spec version 1.0 Section 4.10.2 */
1691 ehci_set_state(ehci, async, EST_ADVANCEQUEUE);
1692 }
1693
1694 out:
1695 return q;
1696 }
1697
1698 static int ehci_state_fetchitd(EHCIState *ehci, int async)
1699 {
1700 uint32_t entry;
1701 EHCIitd itd;
1702
1703 assert(!async);
1704 entry = ehci_get_fetch_addr(ehci, async);
1705
1706 get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd,
1707 sizeof(EHCIitd) >> 2);
1708 ehci_trace_itd(ehci, entry, &itd);
1709
1710 if (ehci_process_itd(ehci, &itd) != 0) {
1711 return -1;
1712 }
1713
1714 put_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd,
1715 sizeof(EHCIitd) >> 2);
1716 ehci_set_fetch_addr(ehci, async, itd.next);
1717 ehci_set_state(ehci, async, EST_FETCHENTRY);
1718
1719 return 1;
1720 }
1721
1722 static int ehci_state_fetchsitd(EHCIState *ehci, int async)
1723 {
1724 uint32_t entry;
1725 EHCIsitd sitd;
1726
1727 assert(!async);
1728 entry = ehci_get_fetch_addr(ehci, async);
1729
1730 get_dwords(ehci, NLPTR_GET(entry), (uint32_t *)&sitd,
1731 sizeof(EHCIsitd) >> 2);
1732 ehci_trace_sitd(ehci, entry, &sitd);
1733
1734 if (!(sitd.results & SITD_RESULTS_ACTIVE)) {
1735 /* siTD is not active, nothing to do */;
1736 } else {
1737 /* TODO: split transfers are not implemented */
1738 fprintf(stderr, "WARNING: Skipping active siTD\n");
1739 }
1740
1741 ehci_set_fetch_addr(ehci, async, sitd.next);
1742 ehci_set_state(ehci, async, EST_FETCHENTRY);
1743 return 1;
1744 }
1745
1746 /* Section 4.10.2 - paragraph 3 */
1747 static int ehci_state_advqueue(EHCIQueue *q, int async)
1748 {
1749 #if 0
1750 /* TO-DO: 4.10.2 - paragraph 2
1751 * if I-bit is set to 1 and QH is not active
1752 * go to horizontal QH
1753 */
1754 if (I-bit set) {
1755 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1756 goto out;
1757 }
1758 #endif
1759
1760 /*
1761 * want data and alt-next qTD is valid
1762 */
1763 if (((q->qh.token & QTD_TOKEN_TBYTES_MASK) != 0) &&
1764 (q->qh.altnext_qtd > 0x1000) &&
1765 (NLPTR_TBIT(q->qh.altnext_qtd) == 0)) {
1766 q->qtdaddr = q->qh.altnext_qtd;
1767 ehci_set_state(q->ehci, async, EST_FETCHQTD);
1768
1769 /*
1770 * next qTD is valid
1771 */
1772 } else if ((q->qh.next_qtd > 0x1000) &&
1773 (NLPTR_TBIT(q->qh.next_qtd) == 0)) {
1774 q->qtdaddr = q->qh.next_qtd;
1775 ehci_set_state(q->ehci, async, EST_FETCHQTD);
1776
1777 /*
1778 * no valid qTD, try next QH
1779 */
1780 } else {
1781 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1782 }
1783
1784 return 1;
1785 }
1786
1787 /* Section 4.10.2 - paragraph 4 */
1788 static int ehci_state_fetchqtd(EHCIQueue *q, int async)
1789 {
1790 int again = 0;
1791
1792 get_dwords(q->ehci, NLPTR_GET(q->qtdaddr), (uint32_t *) &q->qtd,
1793 sizeof(EHCIqtd) >> 2);
1794 ehci_trace_qtd(q, NLPTR_GET(q->qtdaddr), &q->qtd);
1795
1796 if (q->qtd.token & QTD_TOKEN_ACTIVE) {
1797 ehci_set_state(q->ehci, async, EST_EXECUTE);
1798 again = 1;
1799 } else {
1800 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1801 again = 1;
1802 }
1803
1804 return again;
1805 }
1806
1807 static int ehci_state_horizqh(EHCIQueue *q, int async)
1808 {
1809 int again = 0;
1810
1811 if (ehci_get_fetch_addr(q->ehci, async) != q->qh.next) {
1812 ehci_set_fetch_addr(q->ehci, async, q->qh.next);
1813 ehci_set_state(q->ehci, async, EST_FETCHENTRY);
1814 again = 1;
1815 } else {
1816 ehci_set_state(q->ehci, async, EST_ACTIVE);
1817 }
1818
1819 return again;
1820 }
1821
1822 /*
1823 * Write the qh back to guest physical memory. This step isn't
1824 * in the EHCI spec but we need to do it since we don't share
1825 * physical memory with our guest VM.
1826 *
1827 * The first three dwords are read-only for the EHCI, so skip them
1828 * when writing back the qh.
1829 */
1830 static void ehci_flush_qh(EHCIQueue *q)
1831 {
1832 uint32_t *qh = (uint32_t *) &q->qh;
1833 uint32_t dwords = sizeof(EHCIqh) >> 2;
1834 uint32_t addr = NLPTR_GET(q->qhaddr);
1835
1836 put_dwords(q->ehci, addr + 3 * sizeof(uint32_t), qh + 3, dwords - 3);
1837 }
1838
1839 static int ehci_state_execute(EHCIQueue *q, int async)
1840 {
1841 int again = 0;
1842 int reload, nakcnt;
1843 int smask;
1844
1845 if (ehci_qh_do_overlay(q) != 0) {
1846 return -1;
1847 }
1848
1849 smask = get_field(q->qh.epcap, QH_EPCAP_SMASK);
1850
1851 if (!smask) {
1852 reload = get_field(q->qh.epchar, QH_EPCHAR_RL);
1853 nakcnt = get_field(q->qh.altnext_qtd, QH_ALTNEXT_NAKCNT);
1854 if (reload && !nakcnt) {
1855 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1856 again = 1;
1857 goto out;
1858 }
1859 }
1860
1861 // TODO verify enough time remains in the uframe as in 4.4.1.1
1862 // TODO write back ptr to async list when done or out of time
1863 // TODO Windows does not seem to ever set the MULT field
1864
1865 if (!async) {
1866 int transactCtr = get_field(q->qh.epcap, QH_EPCAP_MULT);
1867 if (!transactCtr) {
1868 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1869 again = 1;
1870 goto out;
1871 }
1872 }
1873
1874 if (async) {
1875 ehci_set_usbsts(q->ehci, USBSTS_REC);
1876 }
1877
1878 q->usb_status = ehci_execute(q);
1879 if (q->usb_status == USB_RET_PROCERR) {
1880 again = -1;
1881 goto out;
1882 }
1883 if (q->usb_status == USB_RET_ASYNC) {
1884 ehci_flush_qh(q);
1885 trace_usb_ehci_queue_action(q, "suspend");
1886 q->async = EHCI_ASYNC_INFLIGHT;
1887 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1888 again = 1;
1889 goto out;
1890 }
1891
1892 ehci_set_state(q->ehci, async, EST_EXECUTING);
1893 again = 1;
1894
1895 out:
1896 return again;
1897 }
1898
1899 static int ehci_state_executing(EHCIQueue *q, int async)
1900 {
1901 int again = 0;
1902 int reload, nakcnt;
1903
1904 ehci_execute_complete(q);
1905 if (q->usb_status == USB_RET_ASYNC) {
1906 goto out;
1907 }
1908 if (q->usb_status == USB_RET_PROCERR) {
1909 again = -1;
1910 goto out;
1911 }
1912
1913 // 4.10.3
1914 if (!async) {
1915 int transactCtr = get_field(q->qh.epcap, QH_EPCAP_MULT);
1916 transactCtr--;
1917 set_field(&q->qh.epcap, transactCtr, QH_EPCAP_MULT);
1918 // 4.10.3, bottom of page 82, should exit this state when transaction
1919 // counter decrements to 0
1920 }
1921
1922 reload = get_field(q->qh.epchar, QH_EPCHAR_RL);
1923 if (reload) {
1924 nakcnt = get_field(q->qh.altnext_qtd, QH_ALTNEXT_NAKCNT);
1925 if (q->usb_status == USB_RET_NAK) {
1926 if (nakcnt) {
1927 nakcnt--;
1928 }
1929 } else {
1930 nakcnt = reload;
1931 }
1932 set_field(&q->qh.altnext_qtd, nakcnt, QH_ALTNEXT_NAKCNT);
1933 }
1934
1935 /* 4.10.5 */
1936 if ((q->usb_status == USB_RET_NAK) || (q->qh.token & QTD_TOKEN_ACTIVE)) {
1937 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1938 } else {
1939 ehci_set_state(q->ehci, async, EST_WRITEBACK);
1940 }
1941
1942 again = 1;
1943
1944 out:
1945 ehci_flush_qh(q);
1946 return again;
1947 }
1948
1949
1950 static int ehci_state_writeback(EHCIQueue *q, int async)
1951 {
1952 int again = 0;
1953
1954 /* Write back the QTD from the QH area */
1955 ehci_trace_qtd(q, NLPTR_GET(q->qtdaddr), (EHCIqtd*) &q->qh.next_qtd);
1956 put_dwords(q->ehci, NLPTR_GET(q->qtdaddr), (uint32_t *) &q->qh.next_qtd,
1957 sizeof(EHCIqtd) >> 2);
1958
1959 /*
1960 * EHCI specs say go horizontal here.
1961 *
1962 * We can also advance the queue here for performance reasons. We
1963 * need to take care to only take that shortcut in case we've
1964 * processed the qtd just written back without errors, i.e. halt
1965 * bit is clear.
1966 */
1967 if (q->qh.token & QTD_TOKEN_HALT) {
1968 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1969 again = 1;
1970 } else {
1971 ehci_set_state(q->ehci, async, EST_ADVANCEQUEUE);
1972 again = 1;
1973 }
1974 return again;
1975 }
1976
1977 /*
1978 * This is the state machine that is common to both async and periodic
1979 */
1980
1981 static void ehci_advance_state(EHCIState *ehci,
1982 int async)
1983 {
1984 EHCIQueue *q = NULL;
1985 int again;
1986 int iter = 0;
1987
1988 do {
1989 if (ehci_get_state(ehci, async) == EST_FETCHQH) {
1990 iter++;
1991 /* if we are roaming a lot of QH without executing a qTD
1992 * something is wrong with the linked list. TO-DO: why is
1993 * this hack needed?
1994 */
1995 assert(iter < MAX_ITERATIONS);
1996 #if 0
1997 if (iter > MAX_ITERATIONS) {
1998 DPRINTF("\n*** advance_state: bailing on MAX ITERATIONS***\n");
1999 ehci_set_state(ehci, async, EST_ACTIVE);
2000 break;
2001 }
2002 #endif
2003 }
2004 switch(ehci_get_state(ehci, async)) {
2005 case EST_WAITLISTHEAD:
2006 again = ehci_state_waitlisthead(ehci, async);
2007 break;
2008
2009 case EST_FETCHENTRY:
2010 again = ehci_state_fetchentry(ehci, async);
2011 break;
2012
2013 case EST_FETCHQH:
2014 q = ehci_state_fetchqh(ehci, async);
2015 again = q ? 1 : 0;
2016 break;
2017
2018 case EST_FETCHITD:
2019 again = ehci_state_fetchitd(ehci, async);
2020 break;
2021
2022 case EST_FETCHSITD:
2023 again = ehci_state_fetchsitd(ehci, async);
2024 break;
2025
2026 case EST_ADVANCEQUEUE:
2027 again = ehci_state_advqueue(q, async);
2028 break;
2029
2030 case EST_FETCHQTD:
2031 again = ehci_state_fetchqtd(q, async);
2032 break;
2033
2034 case EST_HORIZONTALQH:
2035 again = ehci_state_horizqh(q, async);
2036 break;
2037
2038 case EST_EXECUTE:
2039 iter = 0;
2040 again = ehci_state_execute(q, async);
2041 break;
2042
2043 case EST_EXECUTING:
2044 assert(q != NULL);
2045 again = ehci_state_executing(q, async);
2046 break;
2047
2048 case EST_WRITEBACK:
2049 again = ehci_state_writeback(q, async);
2050 break;
2051
2052 default:
2053 fprintf(stderr, "Bad state!\n");
2054 again = -1;
2055 assert(0);
2056 break;
2057 }
2058
2059 if (again < 0) {
2060 fprintf(stderr, "processing error - resetting ehci HC\n");
2061 ehci_reset(ehci);
2062 again = 0;
2063 assert(0);
2064 }
2065 }
2066 while (again);
2067
2068 ehci_commit_interrupt(ehci);
2069 }
2070
2071 static void ehci_advance_async_state(EHCIState *ehci)
2072 {
2073 int async = 1;
2074
2075 switch(ehci_get_state(ehci, async)) {
2076 case EST_INACTIVE:
2077 if (!(ehci->usbcmd & USBCMD_ASE)) {
2078 break;
2079 }
2080 ehci_set_usbsts(ehci, USBSTS_ASS);
2081 ehci_set_state(ehci, async, EST_ACTIVE);
2082 // No break, fall through to ACTIVE
2083
2084 case EST_ACTIVE:
2085 if ( !(ehci->usbcmd & USBCMD_ASE)) {
2086 ehci_clear_usbsts(ehci, USBSTS_ASS);
2087 ehci_set_state(ehci, async, EST_INACTIVE);
2088 break;
2089 }
2090
2091 /* If the doorbell is set, the guest wants to make a change to the
2092 * schedule. The host controller needs to release cached data.
2093 * (section 4.8.2)
2094 */
2095 if (ehci->usbcmd & USBCMD_IAAD) {
2096 DPRINTF("ASYNC: doorbell request acknowledged\n");
2097 ehci->usbcmd &= ~USBCMD_IAAD;
2098 ehci_set_interrupt(ehci, USBSTS_IAA);
2099 break;
2100 }
2101
2102 /* make sure guest has acknowledged */
2103 /* TO-DO: is this really needed? */
2104 if (ehci->usbsts & USBSTS_IAA) {
2105 DPRINTF("IAA status bit still set.\n");
2106 break;
2107 }
2108
2109 /* check that address register has been set */
2110 if (ehci->asynclistaddr == 0) {
2111 break;
2112 }
2113
2114 ehci_set_state(ehci, async, EST_WAITLISTHEAD);
2115 ehci_advance_state(ehci, async);
2116 break;
2117
2118 default:
2119 /* this should only be due to a developer mistake */
2120 fprintf(stderr, "ehci: Bad asynchronous state %d. "
2121 "Resetting to active\n", ehci->astate);
2122 assert(0);
2123 }
2124 }
2125
2126 static void ehci_advance_periodic_state(EHCIState *ehci)
2127 {
2128 uint32_t entry;
2129 uint32_t list;
2130 int async = 0;
2131
2132 // 4.6
2133
2134 switch(ehci_get_state(ehci, async)) {
2135 case EST_INACTIVE:
2136 if ( !(ehci->frindex & 7) && (ehci->usbcmd & USBCMD_PSE)) {
2137 ehci_set_usbsts(ehci, USBSTS_PSS);
2138 ehci_set_state(ehci, async, EST_ACTIVE);
2139 // No break, fall through to ACTIVE
2140 } else
2141 break;
2142
2143 case EST_ACTIVE:
2144 if ( !(ehci->frindex & 7) && !(ehci->usbcmd & USBCMD_PSE)) {
2145 ehci_clear_usbsts(ehci, USBSTS_PSS);
2146 ehci_set_state(ehci, async, EST_INACTIVE);
2147 break;
2148 }
2149
2150 list = ehci->periodiclistbase & 0xfffff000;
2151 /* check that register has been set */
2152 if (list == 0) {
2153 break;
2154 }
2155 list |= ((ehci->frindex & 0x1ff8) >> 1);
2156
2157 pci_dma_read(&ehci->dev, list, (uint8_t *) &entry, sizeof entry);
2158 entry = le32_to_cpu(entry);
2159
2160 DPRINTF("PERIODIC state adv fr=%d. [%08X] -> %08X\n",
2161 ehci->frindex / 8, list, entry);
2162 ehci_set_fetch_addr(ehci, async,entry);
2163 ehci_set_state(ehci, async, EST_FETCHENTRY);
2164 ehci_advance_state(ehci, async);
2165 break;
2166
2167 default:
2168 /* this should only be due to a developer mistake */
2169 fprintf(stderr, "ehci: Bad periodic state %d. "
2170 "Resetting to active\n", ehci->pstate);
2171 assert(0);
2172 }
2173 }
2174
2175 static void ehci_frame_timer(void *opaque)
2176 {
2177 EHCIState *ehci = opaque;
2178 int64_t expire_time, t_now;
2179 uint64_t ns_elapsed;
2180 int frames;
2181 int i;
2182 int skipped_frames = 0;
2183
2184 t_now = qemu_get_clock_ns(vm_clock);
2185 expire_time = t_now + (get_ticks_per_sec() / ehci->freq);
2186
2187 ns_elapsed = t_now - ehci->last_run_ns;
2188 frames = ns_elapsed / FRAME_TIMER_NS;
2189
2190 for (i = 0; i < frames; i++) {
2191 if ( !(ehci->usbsts & USBSTS_HALT)) {
2192 if (ehci->isoch_pause <= 0) {
2193 ehci->frindex += 8;
2194 }
2195
2196 if (ehci->frindex > 0x00001fff) {
2197 ehci->frindex = 0;
2198 ehci_set_interrupt(ehci, USBSTS_FLR);
2199 }
2200
2201 ehci->sofv = (ehci->frindex - 1) >> 3;
2202 ehci->sofv &= 0x000003ff;
2203 }
2204
2205 if (frames - i > ehci->maxframes) {
2206 skipped_frames++;
2207 } else {
2208 ehci_advance_periodic_state(ehci);
2209 }
2210
2211 ehci->last_run_ns += FRAME_TIMER_NS;
2212 }
2213
2214 #if 0
2215 if (skipped_frames) {
2216 DPRINTF("WARNING - EHCI skipped %d frames\n", skipped_frames);
2217 }
2218 #endif
2219
2220 /* Async is not inside loop since it executes everything it can once
2221 * called
2222 */
2223 ehci_advance_async_state(ehci);
2224
2225 qemu_mod_timer(ehci->frame_timer, expire_time);
2226 }
2227
2228
2229 static const MemoryRegionOps ehci_mem_ops = {
2230 .old_mmio = {
2231 .read = { ehci_mem_readb, ehci_mem_readw, ehci_mem_readl },
2232 .write = { ehci_mem_writeb, ehci_mem_writew, ehci_mem_writel },
2233 },
2234 .endianness = DEVICE_LITTLE_ENDIAN,
2235 };
2236
2237 static int usb_ehci_initfn(PCIDevice *dev);
2238
2239 static USBPortOps ehci_port_ops = {
2240 .attach = ehci_attach,
2241 .detach = ehci_detach,
2242 .child_detach = ehci_child_detach,
2243 .wakeup = ehci_wakeup,
2244 .complete = ehci_async_complete_packet,
2245 };
2246
2247 static USBBusOps ehci_bus_ops = {
2248 .register_companion = ehci_register_companion,
2249 };
2250
2251 static const VMStateDescription vmstate_ehci = {
2252 .name = "ehci",
2253 .unmigratable = 1,
2254 };
2255
2256 static Property ehci_properties[] = {
2257 DEFINE_PROP_UINT32("freq", EHCIState, freq, FRAME_TIMER_FREQ),
2258 DEFINE_PROP_UINT32("maxframes", EHCIState, maxframes, 128),
2259 DEFINE_PROP_END_OF_LIST(),
2260 };
2261
2262 static PCIDeviceInfo ehci_info[] = {
2263 {
2264 .qdev.name = "usb-ehci",
2265 .qdev.size = sizeof(EHCIState),
2266 .qdev.vmsd = &vmstate_ehci,
2267 .init = usb_ehci_initfn,
2268 .vendor_id = PCI_VENDOR_ID_INTEL,
2269 .device_id = PCI_DEVICE_ID_INTEL_82801D, /* ich4 */
2270 .revision = 0x10,
2271 .class_id = PCI_CLASS_SERIAL_USB,
2272 .qdev.props = ehci_properties,
2273 },{
2274 .qdev.name = "ich9-usb-ehci1",
2275 .qdev.size = sizeof(EHCIState),
2276 .qdev.vmsd = &vmstate_ehci,
2277 .init = usb_ehci_initfn,
2278 .vendor_id = PCI_VENDOR_ID_INTEL,
2279 .device_id = PCI_DEVICE_ID_INTEL_82801I_EHCI1,
2280 .revision = 0x03,
2281 .class_id = PCI_CLASS_SERIAL_USB,
2282 .qdev.props = ehci_properties,
2283 },{
2284 /* end of list */
2285 }
2286 };
2287
2288 static int usb_ehci_initfn(PCIDevice *dev)
2289 {
2290 EHCIState *s = DO_UPCAST(EHCIState, dev, dev);
2291 uint8_t *pci_conf = s->dev.config;
2292 int i;
2293
2294 pci_set_byte(&pci_conf[PCI_CLASS_PROG], 0x20);
2295
2296 /* capabilities pointer */
2297 pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x00);
2298 //pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x50);
2299
2300 pci_set_byte(&pci_conf[PCI_INTERRUPT_PIN], 4); /* interrupt pin D */
2301 pci_set_byte(&pci_conf[PCI_MIN_GNT], 0);
2302 pci_set_byte(&pci_conf[PCI_MAX_LAT], 0);
2303
2304 // pci_conf[0x50] = 0x01; // power management caps
2305
2306 pci_set_byte(&pci_conf[USB_SBRN], USB_RELEASE_2); // release number (2.1.4)
2307 pci_set_byte(&pci_conf[0x61], 0x20); // frame length adjustment (2.1.5)
2308 pci_set_word(&pci_conf[0x62], 0x00); // port wake up capability (2.1.6)
2309
2310 pci_conf[0x64] = 0x00;
2311 pci_conf[0x65] = 0x00;
2312 pci_conf[0x66] = 0x00;
2313 pci_conf[0x67] = 0x00;
2314 pci_conf[0x68] = 0x01;
2315 pci_conf[0x69] = 0x00;
2316 pci_conf[0x6a] = 0x00;
2317 pci_conf[0x6b] = 0x00; // USBLEGSUP
2318 pci_conf[0x6c] = 0x00;
2319 pci_conf[0x6d] = 0x00;
2320 pci_conf[0x6e] = 0x00;
2321 pci_conf[0x6f] = 0xc0; // USBLEFCTLSTS
2322
2323 // 2.2 host controller interface version
2324 s->mmio[0x00] = (uint8_t) OPREGBASE;
2325 s->mmio[0x01] = 0x00;
2326 s->mmio[0x02] = 0x00;
2327 s->mmio[0x03] = 0x01; // HC version
2328 s->mmio[0x04] = NB_PORTS; // Number of downstream ports
2329 s->mmio[0x05] = 0x00; // No companion ports at present
2330 s->mmio[0x06] = 0x00;
2331 s->mmio[0x07] = 0x00;
2332 s->mmio[0x08] = 0x80; // We can cache whole frame, not 64-bit capable
2333 s->mmio[0x09] = 0x68; // EECP
2334 s->mmio[0x0a] = 0x00;
2335 s->mmio[0x0b] = 0x00;
2336
2337 s->irq = s->dev.irq[3];
2338
2339 usb_bus_new(&s->bus, &ehci_bus_ops, &s->dev.qdev);
2340 for(i = 0; i < NB_PORTS; i++) {
2341 usb_register_port(&s->bus, &s->ports[i], s, i, &ehci_port_ops,
2342 USB_SPEED_MASK_HIGH);
2343 s->ports[i].dev = 0;
2344 }
2345
2346 s->frame_timer = qemu_new_timer_ns(vm_clock, ehci_frame_timer, s);
2347 QTAILQ_INIT(&s->queues);
2348
2349 qemu_register_reset(ehci_reset, s);
2350
2351 memory_region_init_io(&s->mem, &ehci_mem_ops, s, "ehci", MMIO_SIZE);
2352 pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mem);
2353
2354 fprintf(stderr, "*** EHCI support is under development ***\n");
2355
2356 return 0;
2357 }
2358
2359 static void ehci_register(void)
2360 {
2361 pci_qdev_register_many(ehci_info);
2362 }
2363 device_init(ehci_register);
2364
2365 /*
2366 * vim: expandtab ts=4
2367 */
QEmu