hw/pci.h

   1 #ifndef QEMU_PCI_H
   2 #define QEMU_PCI_H
   3
   4 #include "qemu-common.h"
   5
   6 #include "qdev.h"
   7 #include "memory.h"
   8 #include "dma.h"
   9
  10 /* PCI includes legacy ISA access.  */
  11 #include "isa.h"
  12
  13 #include "pcie.h"
  14
  15 /* PCI bus */
  16
  17 #define PCI_DEVFN(slot, func)   ((((slot) & 0x1f) << 3) | ((func) & 0x07))
  18 #define PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
  19 #define PCI_FUNC(devfn)         ((devfn) & 0x07)
  20 #define PCI_SLOT_MAX            32
  21 #define PCI_FUNC_MAX            8
  22
  23 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
  24 #include "pci_ids.h"
  25
  26 /* QEMU-specific Vendor and Device ID definitions */
  27
  28 /* IBM (0x1014) */
  29 #define PCI_DEVICE_ID_IBM_440GX          0x027f
  30 #define PCI_DEVICE_ID_IBM_OPENPIC2       0xffff
  31
  32 /* Hitachi (0x1054) */
  33 #define PCI_VENDOR_ID_HITACHI            0x1054
  34 #define PCI_DEVICE_ID_HITACHI_SH7751R    0x350e
  35
  36 /* Apple (0x106b) */
  37 #define PCI_DEVICE_ID_APPLE_343S1201     0x0010
  38 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI  0x001e
  39 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI    0x001f
  40 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL   0x0022
  41 #define PCI_DEVICE_ID_APPLE_IPID_USB     0x003f
  42
  43 /* Realtek (0x10ec) */
  44 #define PCI_DEVICE_ID_REALTEK_8029       0x8029
  45
  46 /* Xilinx (0x10ee) */
  47 #define PCI_DEVICE_ID_XILINX_XC2VP30     0x0300
  48
  49 /* Marvell (0x11ab) */
  50 #define PCI_DEVICE_ID_MARVELL_GT6412X    0x4620
  51
  52 /* QEMU/Bochs VGA (0x1234) */
  53 #define PCI_VENDOR_ID_QEMU               0x1234
  54 #define PCI_DEVICE_ID_QEMU_VGA           0x1111
  55
  56 /* VMWare (0x15ad) */
  57 #define PCI_VENDOR_ID_VMWARE             0x15ad
  58 #define PCI_DEVICE_ID_VMWARE_SVGA2       0x0405
  59 #define PCI_DEVICE_ID_VMWARE_SVGA        0x0710
  60 #define PCI_DEVICE_ID_VMWARE_NET         0x0720
  61 #define PCI_DEVICE_ID_VMWARE_SCSI        0x0730
  62 #define PCI_DEVICE_ID_VMWARE_IDE         0x1729
  63
  64 /* Intel (0x8086) */
  65 #define PCI_DEVICE_ID_INTEL_82551IT      0x1209
  66 #define PCI_DEVICE_ID_INTEL_82557        0x1229
  67 #define PCI_DEVICE_ID_INTEL_82801IR      0x2922
  68
  69 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
  70 #define PCI_VENDOR_ID_REDHAT_QUMRANET    0x1af4
  71 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
  72 #define PCI_SUBDEVICE_ID_QEMU            0x1100
  73
  74 #define PCI_DEVICE_ID_VIRTIO_NET         0x1000
  75 #define PCI_DEVICE_ID_VIRTIO_BLOCK       0x1001
  76 #define PCI_DEVICE_ID_VIRTIO_BALLOON     0x1002
  77 #define PCI_DEVICE_ID_VIRTIO_CONSOLE     0x1003
  78
  79 #define FMT_PCIBUS                      PRIx64
  80
  81 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
  82                                 uint32_t address, uint32_t data, int len);
  83 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
  84                                    uint32_t address, int len);
  85 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
  86                                 pcibus_t addr, pcibus_t size, int type);
  87 typedef int PCIUnregisterFunc(PCIDevice *pci_dev);
  88
  89 typedef struct PCIIORegion {
  90     pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
  91 #define PCI_BAR_UNMAPPED (~(pcibus_t)0)
  92     pcibus_t size;
  93     uint8_t type;
  94     MemoryRegion *memory;
  95     MemoryRegion *address_space;
  96 } PCIIORegion;
  97
  98 #define PCI_ROM_SLOT 6
  99 #define PCI_NUM_REGIONS 7
 100
 101 #include "pci_regs.h"
 102
 103 /* PCI HEADER_TYPE */
 104 #define  PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
 105
 106 /* Size of the standard PCI config header */
 107 #define PCI_CONFIG_HEADER_SIZE 0x40
 108 /* Size of the standard PCI config space */
 109 #define PCI_CONFIG_SPACE_SIZE 0x100
 110 /* Size of the standart PCIe config space: 4KB */
 111 #define PCIE_CONFIG_SPACE_SIZE  0x1000
 112
 113 #define PCI_NUM_PINS 4 /* A-D */
 114
 115 /* Bits in cap_present field. */
 116 enum {
 117     QEMU_PCI_CAP_MSI = 0x1,
 118     QEMU_PCI_CAP_MSIX = 0x2,
 119     QEMU_PCI_CAP_EXPRESS = 0x4,
 120
 121     /* multifunction capable device */
 122 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR        3
 123     QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
 124
 125     /* command register SERR bit enabled */
 126 #define QEMU_PCI_CAP_SERR_BITNR 4
 127     QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
 128 };
 129
 130 struct PCIDevice {
 131     DeviceState qdev;
 132     /* PCI config space */
 133     uint8_t *config;
 134
 135     /* Used to enable config checks on load. Note that writable bits are
 136      * never checked even if set in cmask. */
 137     uint8_t *cmask;
 138
 139     /* Used to implement R/W bytes */
 140     uint8_t *wmask;
 141
 142     /* Used to implement RW1C(Write 1 to Clear) bytes */
 143     uint8_t *w1cmask;
 144
 145     /* Used to allocate config space for capabilities. */
 146     uint8_t *used;
 147
 148     /* the following fields are read only */
 149     PCIBus *bus;
 150     uint32_t devfn;
 151     char name[64];
 152     PCIIORegion io_regions[PCI_NUM_REGIONS];
 153
 154     /* do not access the following fields */
 155     PCIConfigReadFunc *config_read;
 156     PCIConfigWriteFunc *config_write;
 157
 158     /* IRQ objects for the INTA-INTD pins.  */
 159     qemu_irq *irq;
 160
 161     /* Current IRQ levels.  Used internally by the generic PCI code.  */
 162     uint8_t irq_state;
 163
 164     /* Capability bits */
 165     uint32_t cap_present;
 166
 167     /* Offset of MSI-X capability in config space */
 168     uint8_t msix_cap;
 169
 170     /* MSI-X entries */
 171     int msix_entries_nr;
 172
 173     /* Space to store MSIX table */
 174     uint8_t *msix_table_page;
 175     /* MMIO index used to map MSIX table and pending bit entries. */
 176     MemoryRegion msix_mmio;
 177     /* Reference-count for entries actually in use by driver. */
 178     unsigned *msix_entry_used;
 179     /* Region including the MSI-X table */
 180     uint32_t msix_bar_size;
 181     /* Version id needed for VMState */
 182     int32_t version_id;
 183
 184     /* Offset of MSI capability in config space */
 185     uint8_t msi_cap;
 186
 187     /* PCI Express */
 188     PCIExpressDevice exp;
 189
 190     /* Location of option rom */
 191     char *romfile;
 192     bool has_rom;
 193     MemoryRegion rom;
 194     uint32_t rom_bar;
 195 };
 196
 197 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 198                                int instance_size, int devfn,
 199                                PCIConfigReadFunc *config_read,
 200                                PCIConfigWriteFunc *config_write);
 201
 202 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 203                       uint8_t attr, MemoryRegion *memory);
 204 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num);
 205
 206 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
 207                        uint8_t offset, uint8_t size);
 208
 209 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
 210
 211 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
 212
 213
 214 uint32_t pci_default_read_config(PCIDevice *d,
 215                                  uint32_t address, int len);
 216 void pci_default_write_config(PCIDevice *d,
 217                               uint32_t address, uint32_t val, int len);
 218 void pci_device_save(PCIDevice *s, QEMUFile *f);
 219 int pci_device_load(PCIDevice *s, QEMUFile *f);
 220 MemoryRegion *pci_address_space(PCIDevice *dev);
 221 MemoryRegion *pci_address_space_io(PCIDevice *dev);
 222
 223 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
 224 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
 225
 226 typedef enum {
 227     PCI_HOTPLUG_DISABLED,
 228     PCI_HOTPLUG_ENABLED,
 229     PCI_COLDPLUG_ENABLED,
 230 } PCIHotplugState;
 231
 232 typedef int (*pci_hotplug_fn)(DeviceState *qdev, PCIDevice *pci_dev,
 233                               PCIHotplugState state);
 234 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
 235                          const char *name,
 236                          MemoryRegion *address_space_mem,
 237                          MemoryRegion *address_space_io,
 238                          uint8_t devfn_min);
 239 PCIBus *pci_bus_new(DeviceState *parent, const char *name,
 240                     MemoryRegion *address_space_mem,
 241                     MemoryRegion *address_space_io,
 242                     uint8_t devfn_min);
 243 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 244                   void *irq_opaque, int nirq);
 245 int pci_bus_get_irq_level(PCIBus *bus, int irq_num);
 246 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev);
 247 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 248                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 249                          void *irq_opaque,
 250                          MemoryRegion *address_space_mem,
 251                          MemoryRegion *address_space_io,
 252                          uint8_t devfn_min, int nirq);
 253 void pci_device_reset(PCIDevice *dev);
 254 void pci_bus_reset(PCIBus *bus);
 255
 256 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
 257                         const char *default_devaddr);
 258 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
 259                                const char *default_devaddr);
 260 int pci_bus_num(PCIBus *s);
 261 void pci_for_each_device(PCIBus *bus, int bus_num, void (*fn)(PCIBus *bus, PCIDevice *d));
 262 PCIBus *pci_find_root_bus(int domain);
 263 int pci_find_domain(const PCIBus *bus);
 264 PCIBus *pci_find_bus(PCIBus *bus, int bus_num);
 265 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn);
 266 int pci_qdev_find_device(const char *id, PCIDevice **pdev);
 267 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr);
 268
 269 int pci_parse_devaddr(const char *addr, int *domp, int *busp,
 270                       unsigned int *slotp, unsigned int *funcp);
 271 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
 272                      unsigned *slotp);
 273
 274 void pci_device_deassert_intx(PCIDevice *dev);
 275
 276 static inline void
 277 pci_set_byte(uint8_t *config, uint8_t val)
 278 {
 279     *config = val;
 280 }
 281
 282 static inline uint8_t
 283 pci_get_byte(const uint8_t *config)
 284 {
 285     return *config;
 286 }
 287
 288 static inline void
 289 pci_set_word(uint8_t *config, uint16_t val)
 290 {
 291     cpu_to_le16wu((uint16_t *)config, val);
 292 }
 293
 294 static inline uint16_t
 295 pci_get_word(const uint8_t *config)
 296 {
 297     return le16_to_cpupu((const uint16_t *)config);
 298 }
 299
 300 static inline void
 301 pci_set_long(uint8_t *config, uint32_t val)
 302 {
 303     cpu_to_le32wu((uint32_t *)config, val);
 304 }
 305
 306 static inline uint32_t
 307 pci_get_long(const uint8_t *config)
 308 {
 309     return le32_to_cpupu((const uint32_t *)config);
 310 }
 311
 312 static inline void
 313 pci_set_quad(uint8_t *config, uint64_t val)
 314 {
 315     cpu_to_le64w((uint64_t *)config, val);
 316 }
 317
 318 static inline uint64_t
 319 pci_get_quad(const uint8_t *config)
 320 {
 321     return le64_to_cpup((const uint64_t *)config);
 322 }
 323
 324 static inline void
 325 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
 326 {
 327     pci_set_word(&pci_config[PCI_VENDOR_ID], val);
 328 }
 329
 330 static inline void
 331 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
 332 {
 333     pci_set_word(&pci_config[PCI_DEVICE_ID], val);
 334 }
 335
 336 static inline void
 337 pci_config_set_revision(uint8_t *pci_config, uint8_t val)
 338 {
 339     pci_set_byte(&pci_config[PCI_REVISION_ID], val);
 340 }
 341
 342 static inline void
 343 pci_config_set_class(uint8_t *pci_config, uint16_t val)
 344 {
 345     pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
 346 }
 347
 348 static inline void
 349 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val)
 350 {
 351     pci_set_byte(&pci_config[PCI_CLASS_PROG], val);
 352 }
 353
 354 static inline void
 355 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val)
 356 {
 357     pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val);
 358 }
 359
 360 /*
 361  * helper functions to do bit mask operation on configuration space.
 362  * Just to set bit, use test-and-set and discard returned value.
 363  * Just to clear bit, use test-and-clear and discard returned value.
 364  * NOTE: They aren't atomic.
 365  */
 366 static inline uint8_t
 367 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask)
 368 {
 369     uint8_t val = pci_get_byte(config);
 370     pci_set_byte(config, val & ~mask);
 371     return val & mask;
 372 }
 373
 374 static inline uint8_t
 375 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask)
 376 {
 377     uint8_t val = pci_get_byte(config);
 378     pci_set_byte(config, val | mask);
 379     return val & mask;
 380 }
 381
 382 static inline uint16_t
 383 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask)
 384 {
 385     uint16_t val = pci_get_word(config);
 386     pci_set_word(config, val & ~mask);
 387     return val & mask;
 388 }
 389
 390 static inline uint16_t
 391 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask)
 392 {
 393     uint16_t val = pci_get_word(config);
 394     pci_set_word(config, val | mask);
 395     return val & mask;
 396 }
 397
 398 static inline uint32_t
 399 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask)
 400 {
 401     uint32_t val = pci_get_long(config);
 402     pci_set_long(config, val & ~mask);
 403     return val & mask;
 404 }
 405
 406 static inline uint32_t
 407 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask)
 408 {
 409     uint32_t val = pci_get_long(config);
 410     pci_set_long(config, val | mask);
 411     return val & mask;
 412 }
 413
 414 static inline uint64_t
 415 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask)
 416 {
 417     uint64_t val = pci_get_quad(config);
 418     pci_set_quad(config, val & ~mask);
 419     return val & mask;
 420 }
 421
 422 static inline uint64_t
 423 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask)
 424 {
 425     uint64_t val = pci_get_quad(config);
 426     pci_set_quad(config, val | mask);
 427     return val & mask;
 428 }
 429
 430 typedef int (*pci_qdev_initfn)(PCIDevice *dev);
 431 typedef struct {
 432     DeviceInfo qdev;
 433     pci_qdev_initfn init;
 434     PCIUnregisterFunc *exit;
 435     PCIConfigReadFunc *config_read;
 436     PCIConfigWriteFunc *config_write;
 437
 438     uint16_t vendor_id;
 439     uint16_t device_id;
 440     uint8_t revision;
 441     uint16_t class_id;
 442     uint16_t subsystem_vendor_id;       /* only for header type = 0 */
 443     uint16_t subsystem_id;              /* only for header type = 0 */
 444
 445     /*
 446      * pci-to-pci bridge or normal device.
 447      * This doesn't mean pci host switch.
 448      * When card bus bridge is supported, this would be enhanced.
 449      */
 450     int is_bridge;
 451
 452     /* pcie stuff */
 453     int is_express;   /* is this device pci express? */
 454
 455     /* device isn't hot-pluggable */
 456     int no_hotplug;
 457
 458     /* rom bar */
 459     const char *romfile;
 460 } PCIDeviceInfo;
 461
 462 void pci_qdev_register(PCIDeviceInfo *info);
 463 void pci_qdev_register_many(PCIDeviceInfo *info);
 464
 465 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
 466                                     const char *name);
 467 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
 468                                            bool multifunction,
 469                                            const char *name);
 470 PCIDevice *pci_try_create_multifunction(PCIBus *bus, int devfn,
 471                                         bool multifunction,
 472                                         const char *name);
 473 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name);
 474 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
 475 PCIDevice *pci_try_create(PCIBus *bus, int devfn, const char *name);
 476
 477 static inline int pci_is_express(const PCIDevice *d)
 478 {
 479     return d->cap_present & QEMU_PCI_CAP_EXPRESS;
 480 }
 481
 482 static inline uint32_t pci_config_size(const PCIDevice *d)
 483 {
 484     return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
 485 }
 486
 487 /* DMA access functions */
 488 static inline int pci_dma_rw(PCIDevice *dev, dma_addr_t addr,
 489                              void *buf, dma_addr_t len, DMADirection dir)
 490 {
 491     cpu_physical_memory_rw(addr, buf, len, dir == DMA_DIRECTION_FROM_DEVICE);
 492     return 0;
 493 }
 494
 495 static inline int pci_dma_read(PCIDevice *dev, dma_addr_t addr,
 496                                void *buf, dma_addr_t len)
 497 {
 498     return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE);
 499 }
 500
 501 static inline int pci_dma_write(PCIDevice *dev, dma_addr_t addr,
 502                                 const void *buf, dma_addr_t len)
 503 {
 504     return pci_dma_rw(dev, addr, (void *) buf, len, DMA_DIRECTION_FROM_DEVICE);
 505 }
 506
 507 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits)                              \
 508     static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev,      \
 509                                                    dma_addr_t addr)     \
 510     {                                                                   \
 511         return ld##_l##_phys(addr);                                     \
 512     }                                                                   \
 513     static inline void st##_s##_pci_dma(PCIDevice *dev,                 \
 514                           dma_addr_t addr, uint##_bits##_t val)         \
 515     {                                                                   \
 516         st##_s##_phys(addr, val);                                       \
 517     }
 518
 519 PCI_DMA_DEFINE_LDST(ub, b, 8);
 520 PCI_DMA_DEFINE_LDST(uw_le, w_le, 16)
 521 PCI_DMA_DEFINE_LDST(l_le, l_le, 32);
 522 PCI_DMA_DEFINE_LDST(q_le, q_le, 64);
 523 PCI_DMA_DEFINE_LDST(uw_be, w_be, 16)
 524 PCI_DMA_DEFINE_LDST(l_be, l_be, 32);
 525 PCI_DMA_DEFINE_LDST(q_be, q_be, 64);
 526
 527 #undef PCI_DMA_DEFINE_LDST
 528
 529 static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr,
 530                                 dma_addr_t *plen, DMADirection dir)
 531 {
 532     target_phys_addr_t len = *plen;
 533     void *buf;
 534
 535     buf = cpu_physical_memory_map(addr, &len, dir == DMA_DIRECTION_FROM_DEVICE);
 536     *plen = len;
 537     return buf;
 538 }
 539
 540 static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len,
 541                                  DMADirection dir, dma_addr_t access_len)
 542 {
 543     cpu_physical_memory_unmap(buffer, len, dir == DMA_DIRECTION_FROM_DEVICE,
 544                               access_len);
 545 }
 546
 547 static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev,
 548                                        int alloc_hint)
 549 {
 550     qemu_sglist_init(qsg, alloc_hint);
 551 }
 552
 553 #endif