hw/omap_uart.c

   1 /*
   2  * TI OMAP processors UART emulation.
   3  *
   4  * Copyright (C) 2006-2008 Andrzej Zaborowski  <balrog@zabor.org>
   5  * Copyright (C) 2007-2009 Nokia Corporation
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 or
  10  * (at your option) version 3 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along
  18  * with this program; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20 #include "qemu-char.h"
  21 #include "hw.h"
  22 #include "omap.h"
  23 /* We use pc-style serial ports.  */
  24 #include "pc.h"
  25 #include "exec-memory.h"
  26
  27 /* UARTs */
  28 struct omap_uart_s {
  29     target_phys_addr_t base;
  30     SerialState *serial; /* TODO */
  31     struct omap_target_agent_s *ta;
  32     omap_clk fclk;
  33     qemu_irq irq;
  34
  35     uint8_t eblr;
  36     uint8_t syscontrol;
  37     uint8_t wkup;
  38     uint8_t cfps;
  39     uint8_t mdr[2];
  40     uint8_t scr;
  41     uint8_t clksel;
  42 };
  43
  44 void omap_uart_reset(struct omap_uart_s *s)
  45 {
  46     s->eblr = 0x00;
  47     s->syscontrol = 0;
  48     s->wkup = 0x3f;
  49     s->cfps = 0x69;
  50     s->clksel = 0;
  51 }
  52
  53 struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
  54                 qemu_irq irq, omap_clk fclk, omap_clk iclk,
  55                 qemu_irq txdma, qemu_irq rxdma,
  56                 const char *label, CharDriverState *chr)
  57 {
  58     struct omap_uart_s *s = (struct omap_uart_s *)
  59             g_malloc0(sizeof(struct omap_uart_s));
  60
  61     s->base = base;
  62     s->fclk = fclk;
  63     s->irq = irq;
  64     s->serial = serial_mm_init(get_system_memory(), base, 2, irq,
  65                                omap_clk_getrate(fclk)/16,
  66                                chr ?: qemu_chr_new(label, "null", NULL),
  67                                DEVICE_NATIVE_ENDIAN);
  68     return s;
  69 }
  70
  71 static uint32_t omap_uart_read(void *opaque, target_phys_addr_t addr)
  72 {
  73     struct omap_uart_s *s = (struct omap_uart_s *) opaque;
  74
  75     addr &= 0xff;
  76     switch (addr) {
  77     case 0x20:  /* MDR1 */
  78         return s->mdr[0];
  79     case 0x24:  /* MDR2 */
  80         return s->mdr[1];
  81     case 0x40:  /* SCR */
  82         return s->scr;
  83     case 0x44:  /* SSR */
  84         return 0x0;
  85     case 0x48:  /* EBLR (OMAP2) */
  86         return s->eblr;
  87     case 0x4C:  /* OSC_12M_SEL (OMAP1) */
  88         return s->clksel;
  89     case 0x50:  /* MVR */
  90         return 0x30;
  91     case 0x54:  /* SYSC (OMAP2) */
  92         return s->syscontrol;
  93     case 0x58:  /* SYSS (OMAP2) */
  94         return 1;
  95     case 0x5c:  /* WER (OMAP2) */
  96         return s->wkup;
  97     case 0x60:  /* CFPS (OMAP2) */
  98         return s->cfps;
  99     }
 100
 101     OMAP_BAD_REG(addr);
 102     return 0;
 103 }
 104
 105 static void omap_uart_write(void *opaque, target_phys_addr_t addr,
 106                 uint32_t value)
 107 {
 108     struct omap_uart_s *s = (struct omap_uart_s *) opaque;
 109
 110     addr &= 0xff;
 111     switch (addr) {
 112     case 0x20:  /* MDR1 */
 113         s->mdr[0] = value & 0x7f;
 114         break;
 115     case 0x24:  /* MDR2 */
 116         s->mdr[1] = value & 0xff;
 117         break;
 118     case 0x40:  /* SCR */
 119         s->scr = value & 0xff;
 120         break;
 121     case 0x48:  /* EBLR (OMAP2) */
 122         s->eblr = value & 0xff;
 123         break;
 124     case 0x4C:  /* OSC_12M_SEL (OMAP1) */
 125         s->clksel = value & 1;
 126         break;
 127     case 0x44:  /* SSR */
 128     case 0x50:  /* MVR */
 129     case 0x58:  /* SYSS (OMAP2) */
 130         OMAP_RO_REG(addr);
 131         break;
 132     case 0x54:  /* SYSC (OMAP2) */
 133         s->syscontrol = value & 0x1d;
 134         if (value & 2)
 135             omap_uart_reset(s);
 136         break;
 137     case 0x5c:  /* WER (OMAP2) */
 138         s->wkup = value & 0x7f;
 139         break;
 140     case 0x60:  /* CFPS (OMAP2) */
 141         s->cfps = value & 0xff;
 142         break;
 143     default:
 144         OMAP_BAD_REG(addr);
 145     }
 146 }
 147
 148 static CPUReadMemoryFunc * const omap_uart_readfn[] = {
 149     omap_uart_read,
 150     omap_uart_read,
 151     omap_badwidth_read8,
 152 };
 153
 154 static CPUWriteMemoryFunc * const omap_uart_writefn[] = {
 155     omap_uart_write,
 156     omap_uart_write,
 157     omap_badwidth_write8,
 158 };
 159
 160 struct omap_uart_s *omap2_uart_init(struct omap_target_agent_s *ta,
 161                 qemu_irq irq, omap_clk fclk, omap_clk iclk,
 162                 qemu_irq txdma, qemu_irq rxdma,
 163                 const char *label, CharDriverState *chr)
 164 {
 165     target_phys_addr_t base = omap_l4_attach(ta, 0, 0);
 166     struct omap_uart_s *s = omap_uart_init(base, irq,
 167                     fclk, iclk, txdma, rxdma, label, chr);
 168     int iomemtype = cpu_register_io_memory(omap_uart_readfn,
 169                     omap_uart_writefn, s, DEVICE_NATIVE_ENDIAN);
 170
 171     s->ta = ta;
 172
 173     cpu_register_physical_memory(base + 0x20, 0x100, iomemtype);
 174
 175     return s;
 176 }
 177
 178 void omap_uart_attach(struct omap_uart_s *s, CharDriverState *chr)
 179 {
 180     /* TODO: Should reuse or destroy current s->serial */
 181     s->serial = serial_mm_init(get_system_memory(), s->base, 2, s->irq,
 182                                omap_clk_getrate(s->fclk) / 16,
 183                                chr ?: qemu_chr_new("null", "null", NULL),
 184                                DEVICE_NATIVE_ENDIAN);
 185 }