aspeed/smc: handle dummies only in fast read mode
[qemu.git] / qtest.c
blob1446719e8ddcc320c90719aaa1c76e983041495d
1 /*
2 * Test Server
4 * Copyright IBM, Corp. 2011
6 * Authors:
7 * Anthony Liguori <aliguori@us.ibm.com>
9 * This work is licensed under the terms of the GNU GPL, version 2 or later.
10 * See the COPYING file in the top-level directory.
14 #include "qemu/osdep.h"
15 #include "qapi/error.h"
16 #include "qemu-common.h"
17 #include "cpu.h"
18 #include "sysemu/qtest.h"
19 #include "hw/qdev.h"
20 #include "sysemu/char.h"
21 #include "exec/ioport.h"
22 #include "exec/memory.h"
23 #include "hw/irq.h"
24 #include "sysemu/accel.h"
25 #include "sysemu/sysemu.h"
26 #include "sysemu/cpus.h"
27 #include "qemu/config-file.h"
28 #include "qemu/option.h"
29 #include "qemu/error-report.h"
30 #include "qemu/cutils.h"
31 #ifdef TARGET_PPC64
32 #include "hw/ppc/spapr_rtas.h"
33 #endif
35 #define MAX_IRQ 256
37 bool qtest_allowed;
39 static DeviceState *irq_intercept_dev;
40 static FILE *qtest_log_fp;
41 static CharBackend qtest_chr;
42 static GString *inbuf;
43 static int irq_levels[MAX_IRQ];
44 static qemu_timeval start_time;
45 static bool qtest_opened;
47 #define FMT_timeval "%ld.%06ld"
49 /**
50 * QTest Protocol
52 * Line based protocol, request/response based. Server can send async messages
53 * so clients should always handle many async messages before the response
54 * comes in.
56 * Valid requests
58 * Clock management:
60 * The qtest client is completely in charge of the QEMU_CLOCK_VIRTUAL. qtest commands
61 * let you adjust the value of the clock (monotonically). All the commands
62 * return the current value of the clock in nanoseconds.
64 * > clock_step
65 * < OK VALUE
67 * Advance the clock to the next deadline. Useful when waiting for
68 * asynchronous events.
70 * > clock_step NS
71 * < OK VALUE
73 * Advance the clock by NS nanoseconds.
75 * > clock_set NS
76 * < OK VALUE
78 * Advance the clock to NS nanoseconds (do nothing if it's already past).
80 * PIO and memory access:
82 * > outb ADDR VALUE
83 * < OK
85 * > outw ADDR VALUE
86 * < OK
88 * > outl ADDR VALUE
89 * < OK
91 * > inb ADDR
92 * < OK VALUE
94 * > inw ADDR
95 * < OK VALUE
97 * > inl ADDR
98 * < OK VALUE
100 * > writeb ADDR VALUE
101 * < OK
103 * > writew ADDR VALUE
104 * < OK
106 * > writel ADDR VALUE
107 * < OK
109 * > writeq ADDR VALUE
110 * < OK
112 * > readb ADDR
113 * < OK VALUE
115 * > readw ADDR
116 * < OK VALUE
118 * > readl ADDR
119 * < OK VALUE
121 * > readq ADDR
122 * < OK VALUE
124 * > read ADDR SIZE
125 * < OK DATA
127 * > write ADDR SIZE DATA
128 * < OK
130 * > b64read ADDR SIZE
131 * < OK B64_DATA
133 * > b64write ADDR SIZE B64_DATA
134 * < OK
136 * > memset ADDR SIZE VALUE
137 * < OK
139 * ADDR, SIZE, VALUE are all integers parsed with strtoul() with a base of 0.
140 * For 'memset' a zero size is permitted and does nothing.
142 * DATA is an arbitrarily long hex number prefixed with '0x'. If it's smaller
143 * than the expected size, the value will be zero filled at the end of the data
144 * sequence.
146 * B64_DATA is an arbitrarily long base64 encoded string.
147 * If the sizes do not match, the data will be truncated.
149 * IRQ management:
151 * > irq_intercept_in QOM-PATH
152 * < OK
154 * > irq_intercept_out QOM-PATH
155 * < OK
157 * Attach to the gpio-in (resp. gpio-out) pins exported by the device at
158 * QOM-PATH. When the pin is triggered, one of the following async messages
159 * will be printed to the qtest stream:
161 * IRQ raise NUM
162 * IRQ lower NUM
164 * where NUM is an IRQ number. For the PC, interrupts can be intercepted
165 * simply with "irq_intercept_in ioapic" (note that IRQ0 comes out with
166 * NUM=0 even though it is remapped to GSI 2).
169 static int hex2nib(char ch)
171 if (ch >= '0' && ch <= '9') {
172 return ch - '0';
173 } else if (ch >= 'a' && ch <= 'f') {
174 return 10 + (ch - 'a');
175 } else if (ch >= 'A' && ch <= 'F') {
176 return 10 + (ch - 'A');
177 } else {
178 return -1;
182 static void qtest_get_time(qemu_timeval *tv)
184 qemu_gettimeofday(tv);
185 tv->tv_sec -= start_time.tv_sec;
186 tv->tv_usec -= start_time.tv_usec;
187 if (tv->tv_usec < 0) {
188 tv->tv_usec += 1000000;
189 tv->tv_sec -= 1;
193 static void qtest_send_prefix(CharBackend *chr)
195 qemu_timeval tv;
197 if (!qtest_log_fp || !qtest_opened) {
198 return;
201 qtest_get_time(&tv);
202 fprintf(qtest_log_fp, "[S +" FMT_timeval "] ",
203 (long) tv.tv_sec, (long) tv.tv_usec);
206 static void GCC_FMT_ATTR(1, 2) qtest_log_send(const char *fmt, ...)
208 va_list ap;
210 if (!qtest_log_fp || !qtest_opened) {
211 return;
214 qtest_send_prefix(NULL);
216 va_start(ap, fmt);
217 vfprintf(qtest_log_fp, fmt, ap);
218 va_end(ap);
221 static void do_qtest_send(CharBackend *chr, const char *str, size_t len)
223 qemu_chr_fe_write_all(chr, (uint8_t *)str, len);
224 if (qtest_log_fp && qtest_opened) {
225 fprintf(qtest_log_fp, "%s", str);
229 static void qtest_send(CharBackend *chr, const char *str)
231 do_qtest_send(chr, str, strlen(str));
234 static void GCC_FMT_ATTR(2, 3) qtest_sendf(CharBackend *chr,
235 const char *fmt, ...)
237 va_list ap;
238 gchar *buffer;
240 va_start(ap, fmt);
241 buffer = g_strdup_vprintf(fmt, ap);
242 qtest_send(chr, buffer);
243 va_end(ap);
246 static void qtest_irq_handler(void *opaque, int n, int level)
248 qemu_irq old_irq = *(qemu_irq *)opaque;
249 qemu_set_irq(old_irq, level);
251 if (irq_levels[n] != level) {
252 CharBackend *chr = &qtest_chr;
253 irq_levels[n] = level;
254 qtest_send_prefix(chr);
255 qtest_sendf(chr, "IRQ %s %d\n",
256 level ? "raise" : "lower", n);
260 static void qtest_process_command(CharBackend *chr, gchar **words)
262 const gchar *command;
264 g_assert(words);
266 command = words[0];
268 if (qtest_log_fp) {
269 qemu_timeval tv;
270 int i;
272 qtest_get_time(&tv);
273 fprintf(qtest_log_fp, "[R +" FMT_timeval "]",
274 (long) tv.tv_sec, (long) tv.tv_usec);
275 for (i = 0; words[i]; i++) {
276 fprintf(qtest_log_fp, " %s", words[i]);
278 fprintf(qtest_log_fp, "\n");
281 g_assert(command);
282 if (strcmp(words[0], "irq_intercept_out") == 0
283 || strcmp(words[0], "irq_intercept_in") == 0) {
284 DeviceState *dev;
285 NamedGPIOList *ngl;
287 g_assert(words[1]);
288 dev = DEVICE(object_resolve_path(words[1], NULL));
289 if (!dev) {
290 qtest_send_prefix(chr);
291 qtest_send(chr, "FAIL Unknown device\n");
292 return;
295 if (irq_intercept_dev) {
296 qtest_send_prefix(chr);
297 if (irq_intercept_dev != dev) {
298 qtest_send(chr, "FAIL IRQ intercept already enabled\n");
299 } else {
300 qtest_send(chr, "OK\n");
302 return;
305 QLIST_FOREACH(ngl, &dev->gpios, node) {
306 /* We don't support intercept of named GPIOs yet */
307 if (ngl->name) {
308 continue;
310 if (words[0][14] == 'o') {
311 int i;
312 for (i = 0; i < ngl->num_out; ++i) {
313 qemu_irq *disconnected = g_new0(qemu_irq, 1);
314 qemu_irq icpt = qemu_allocate_irq(qtest_irq_handler,
315 disconnected, i);
317 *disconnected = qdev_intercept_gpio_out(dev, icpt,
318 ngl->name, i);
320 } else {
321 qemu_irq_intercept_in(ngl->in, qtest_irq_handler,
322 ngl->num_in);
325 irq_intercept_dev = dev;
326 qtest_send_prefix(chr);
327 qtest_send(chr, "OK\n");
329 } else if (strcmp(words[0], "outb") == 0 ||
330 strcmp(words[0], "outw") == 0 ||
331 strcmp(words[0], "outl") == 0) {
332 unsigned long addr;
333 unsigned long value;
335 g_assert(words[1] && words[2]);
336 g_assert(qemu_strtoul(words[1], NULL, 0, &addr) == 0);
337 g_assert(qemu_strtoul(words[2], NULL, 0, &value) == 0);
338 g_assert(addr <= 0xffff);
340 if (words[0][3] == 'b') {
341 cpu_outb(addr, value);
342 } else if (words[0][3] == 'w') {
343 cpu_outw(addr, value);
344 } else if (words[0][3] == 'l') {
345 cpu_outl(addr, value);
347 qtest_send_prefix(chr);
348 qtest_send(chr, "OK\n");
349 } else if (strcmp(words[0], "inb") == 0 ||
350 strcmp(words[0], "inw") == 0 ||
351 strcmp(words[0], "inl") == 0) {
352 unsigned long addr;
353 uint32_t value = -1U;
355 g_assert(words[1]);
356 g_assert(qemu_strtoul(words[1], NULL, 0, &addr) == 0);
357 g_assert(addr <= 0xffff);
359 if (words[0][2] == 'b') {
360 value = cpu_inb(addr);
361 } else if (words[0][2] == 'w') {
362 value = cpu_inw(addr);
363 } else if (words[0][2] == 'l') {
364 value = cpu_inl(addr);
366 qtest_send_prefix(chr);
367 qtest_sendf(chr, "OK 0x%04x\n", value);
368 } else if (strcmp(words[0], "writeb") == 0 ||
369 strcmp(words[0], "writew") == 0 ||
370 strcmp(words[0], "writel") == 0 ||
371 strcmp(words[0], "writeq") == 0) {
372 uint64_t addr;
373 uint64_t value;
375 g_assert(words[1] && words[2]);
376 g_assert(qemu_strtoull(words[1], NULL, 0, &addr) == 0);
377 g_assert(qemu_strtoull(words[2], NULL, 0, &value) == 0);
379 if (words[0][5] == 'b') {
380 uint8_t data = value;
381 cpu_physical_memory_write(addr, &data, 1);
382 } else if (words[0][5] == 'w') {
383 uint16_t data = value;
384 tswap16s(&data);
385 cpu_physical_memory_write(addr, &data, 2);
386 } else if (words[0][5] == 'l') {
387 uint32_t data = value;
388 tswap32s(&data);
389 cpu_physical_memory_write(addr, &data, 4);
390 } else if (words[0][5] == 'q') {
391 uint64_t data = value;
392 tswap64s(&data);
393 cpu_physical_memory_write(addr, &data, 8);
395 qtest_send_prefix(chr);
396 qtest_send(chr, "OK\n");
397 } else if (strcmp(words[0], "readb") == 0 ||
398 strcmp(words[0], "readw") == 0 ||
399 strcmp(words[0], "readl") == 0 ||
400 strcmp(words[0], "readq") == 0) {
401 uint64_t addr;
402 uint64_t value = UINT64_C(-1);
404 g_assert(words[1]);
405 g_assert(qemu_strtoull(words[1], NULL, 0, &addr) == 0);
407 if (words[0][4] == 'b') {
408 uint8_t data;
409 cpu_physical_memory_read(addr, &data, 1);
410 value = data;
411 } else if (words[0][4] == 'w') {
412 uint16_t data;
413 cpu_physical_memory_read(addr, &data, 2);
414 value = tswap16(data);
415 } else if (words[0][4] == 'l') {
416 uint32_t data;
417 cpu_physical_memory_read(addr, &data, 4);
418 value = tswap32(data);
419 } else if (words[0][4] == 'q') {
420 cpu_physical_memory_read(addr, &value, 8);
421 tswap64s(&value);
423 qtest_send_prefix(chr);
424 qtest_sendf(chr, "OK 0x%016" PRIx64 "\n", value);
425 } else if (strcmp(words[0], "read") == 0) {
426 uint64_t addr, len, i;
427 uint8_t *data;
428 char *enc;
430 g_assert(words[1] && words[2]);
431 g_assert(qemu_strtoull(words[1], NULL, 0, &addr) == 0);
432 g_assert(qemu_strtoull(words[2], NULL, 0, &len) == 0);
433 /* We'd send garbage to libqtest if len is 0 */
434 g_assert(len);
436 data = g_malloc(len);
437 cpu_physical_memory_read(addr, data, len);
439 enc = g_malloc(2 * len + 1);
440 for (i = 0; i < len; i++) {
441 sprintf(&enc[i * 2], "%02x", data[i]);
444 qtest_send_prefix(chr);
445 qtest_sendf(chr, "OK 0x%s\n", enc);
447 g_free(data);
448 g_free(enc);
449 } else if (strcmp(words[0], "b64read") == 0) {
450 uint64_t addr, len;
451 uint8_t *data;
452 gchar *b64_data;
454 g_assert(words[1] && words[2]);
455 g_assert(qemu_strtoull(words[1], NULL, 0, &addr) == 0);
456 g_assert(qemu_strtoull(words[2], NULL, 0, &len) == 0);
458 data = g_malloc(len);
459 cpu_physical_memory_read(addr, data, len);
460 b64_data = g_base64_encode(data, len);
461 qtest_send_prefix(chr);
462 qtest_sendf(chr, "OK %s\n", b64_data);
464 g_free(data);
465 g_free(b64_data);
466 } else if (strcmp(words[0], "write") == 0) {
467 uint64_t addr, len, i;
468 uint8_t *data;
469 size_t data_len;
471 g_assert(words[1] && words[2] && words[3]);
472 g_assert(qemu_strtoull(words[1], NULL, 0, &addr) == 0);
473 g_assert(qemu_strtoull(words[2], NULL, 0, &len) == 0);
475 data_len = strlen(words[3]);
476 if (data_len < 3) {
477 qtest_send(chr, "ERR invalid argument size\n");
478 return;
481 data = g_malloc(len);
482 for (i = 0; i < len; i++) {
483 if ((i * 2 + 4) <= data_len) {
484 data[i] = hex2nib(words[3][i * 2 + 2]) << 4;
485 data[i] |= hex2nib(words[3][i * 2 + 3]);
486 } else {
487 data[i] = 0;
490 cpu_physical_memory_write(addr, data, len);
491 g_free(data);
493 qtest_send_prefix(chr);
494 qtest_send(chr, "OK\n");
495 } else if (strcmp(words[0], "memset") == 0) {
496 uint64_t addr, len;
497 uint8_t *data;
498 unsigned long pattern;
500 g_assert(words[1] && words[2] && words[3]);
501 g_assert(qemu_strtoull(words[1], NULL, 0, &addr) == 0);
502 g_assert(qemu_strtoull(words[2], NULL, 0, &len) == 0);
503 g_assert(qemu_strtoul(words[3], NULL, 0, &pattern) == 0);
505 if (len) {
506 data = g_malloc(len);
507 memset(data, pattern, len);
508 cpu_physical_memory_write(addr, data, len);
509 g_free(data);
512 qtest_send_prefix(chr);
513 qtest_send(chr, "OK\n");
514 } else if (strcmp(words[0], "b64write") == 0) {
515 uint64_t addr, len;
516 uint8_t *data;
517 size_t data_len;
518 gsize out_len;
520 g_assert(words[1] && words[2] && words[3]);
521 g_assert(qemu_strtoull(words[1], NULL, 0, &addr) == 0);
522 g_assert(qemu_strtoull(words[2], NULL, 0, &len) == 0);
524 data_len = strlen(words[3]);
525 if (data_len < 3) {
526 qtest_send(chr, "ERR invalid argument size\n");
527 return;
530 data = g_base64_decode_inplace(words[3], &out_len);
531 if (out_len != len) {
532 qtest_log_send("b64write: data length mismatch (told %"PRIu64", "
533 "found %zu)\n",
534 len, out_len);
535 out_len = MIN(out_len, len);
538 cpu_physical_memory_write(addr, data, out_len);
540 qtest_send_prefix(chr);
541 qtest_send(chr, "OK\n");
542 } else if (strcmp(words[0], "endianness") == 0) {
543 qtest_send_prefix(chr);
544 #if defined(TARGET_WORDS_BIGENDIAN)
545 qtest_sendf(chr, "OK big\n");
546 #else
547 qtest_sendf(chr, "OK little\n");
548 #endif
549 #ifdef TARGET_PPC64
550 } else if (strcmp(words[0], "rtas") == 0) {
551 uint64_t res, args, ret;
552 unsigned long nargs, nret;
554 g_assert(qemu_strtoul(words[2], NULL, 0, &nargs) == 0);
555 g_assert(qemu_strtoull(words[3], NULL, 0, &args) == 0);
556 g_assert(qemu_strtoul(words[4], NULL, 0, &nret) == 0);
557 g_assert(qemu_strtoull(words[5], NULL, 0, &ret) == 0);
558 res = qtest_rtas_call(words[1], nargs, args, nret, ret);
560 qtest_send_prefix(chr);
561 qtest_sendf(chr, "OK %"PRIu64"\n", res);
562 #endif
563 } else if (qtest_enabled() && strcmp(words[0], "clock_step") == 0) {
564 int64_t ns;
566 if (words[1]) {
567 g_assert(qemu_strtoll(words[1], NULL, 0, &ns) == 0);
568 } else {
569 ns = qemu_clock_deadline_ns_all(QEMU_CLOCK_VIRTUAL);
571 qtest_clock_warp(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + ns);
572 qtest_send_prefix(chr);
573 qtest_sendf(chr, "OK %"PRIi64"\n",
574 (int64_t)qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
575 } else if (qtest_enabled() && strcmp(words[0], "clock_set") == 0) {
576 int64_t ns;
578 g_assert(words[1]);
579 g_assert(qemu_strtoll(words[1], NULL, 0, &ns) == 0);
580 qtest_clock_warp(ns);
581 qtest_send_prefix(chr);
582 qtest_sendf(chr, "OK %"PRIi64"\n",
583 (int64_t)qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
584 } else {
585 qtest_send_prefix(chr);
586 qtest_sendf(chr, "FAIL Unknown command '%s'\n", words[0]);
590 static void qtest_process_inbuf(CharBackend *chr, GString *inbuf)
592 char *end;
594 while ((end = strchr(inbuf->str, '\n')) != NULL) {
595 size_t offset;
596 GString *cmd;
597 gchar **words;
599 offset = end - inbuf->str;
601 cmd = g_string_new_len(inbuf->str, offset);
602 g_string_erase(inbuf, 0, offset + 1);
604 words = g_strsplit(cmd->str, " ", 0);
605 qtest_process_command(chr, words);
606 g_strfreev(words);
608 g_string_free(cmd, TRUE);
612 static void qtest_read(void *opaque, const uint8_t *buf, int size)
614 CharBackend *chr = opaque;
616 g_string_append_len(inbuf, (const gchar *)buf, size);
617 qtest_process_inbuf(chr, inbuf);
620 static int qtest_can_read(void *opaque)
622 return 1024;
625 static void qtest_event(void *opaque, int event)
627 int i;
629 switch (event) {
630 case CHR_EVENT_OPENED:
632 * We used to call qemu_system_reset() here, hoping we could
633 * use the same process for multiple tests that way. Never
634 * used. Injects an extra reset even when it's not used, and
635 * that can mess up tests, e.g. -boot once.
637 for (i = 0; i < ARRAY_SIZE(irq_levels); i++) {
638 irq_levels[i] = 0;
640 qemu_gettimeofday(&start_time);
641 qtest_opened = true;
642 if (qtest_log_fp) {
643 fprintf(qtest_log_fp, "[I " FMT_timeval "] OPENED\n",
644 (long) start_time.tv_sec, (long) start_time.tv_usec);
646 break;
647 case CHR_EVENT_CLOSED:
648 qtest_opened = false;
649 if (qtest_log_fp) {
650 qemu_timeval tv;
651 qtest_get_time(&tv);
652 fprintf(qtest_log_fp, "[I +" FMT_timeval "] CLOSED\n",
653 (long) tv.tv_sec, (long) tv.tv_usec);
655 break;
656 default:
657 break;
661 static int qtest_init_accel(MachineState *ms)
663 QemuOpts *opts = qemu_opts_create(qemu_find_opts("icount"), NULL, 0,
664 &error_abort);
665 qemu_opt_set(opts, "shift", "0", &error_abort);
666 configure_icount(opts, &error_abort);
667 qemu_opts_del(opts);
668 return 0;
671 void qtest_init(const char *qtest_chrdev, const char *qtest_log, Error **errp)
673 Chardev *chr;
675 chr = qemu_chr_new("qtest", qtest_chrdev);
677 if (chr == NULL) {
678 error_setg(errp, "Failed to initialize device for qtest: \"%s\"",
679 qtest_chrdev);
680 return;
683 if (qtest_log) {
684 if (strcmp(qtest_log, "none") != 0) {
685 qtest_log_fp = fopen(qtest_log, "w+");
687 } else {
688 qtest_log_fp = stderr;
691 qemu_chr_fe_init(&qtest_chr, chr, errp);
692 qemu_chr_fe_set_handlers(&qtest_chr, qtest_can_read, qtest_read,
693 qtest_event, &qtest_chr, NULL, true);
694 qemu_chr_fe_set_echo(&qtest_chr, true);
696 inbuf = g_string_new("");
699 bool qtest_driver(void)
701 return qtest_chr.chr != NULL;
704 static void qtest_accel_class_init(ObjectClass *oc, void *data)
706 AccelClass *ac = ACCEL_CLASS(oc);
707 ac->name = "QTest";
708 ac->available = qtest_available;
709 ac->init_machine = qtest_init_accel;
710 ac->allowed = &qtest_allowed;
713 #define TYPE_QTEST_ACCEL ACCEL_CLASS_NAME("qtest")
715 static const TypeInfo qtest_accel_type = {
716 .name = TYPE_QTEST_ACCEL,
717 .parent = TYPE_ACCEL,
718 .class_init = qtest_accel_class_init,
721 static void qtest_type_init(void)
723 type_register_static(&qtest_accel_type);
726 type_init(qtest_type_init);