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[qemu.git] / exec-all.h
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1 /*
2 * internal execution defines for qemu
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #ifndef _EXEC_ALL_H_
21 #define _EXEC_ALL_H_
23 #include "qemu-common.h"
25 /* allow to see translation results - the slowdown should be negligible, so we leave it */
26 #define DEBUG_DISAS
28 /* Page tracking code uses ram addresses in system mode, and virtual
29 addresses in userspace mode. Define tb_page_addr_t to be an appropriate
30 type. */
31 #if defined(CONFIG_USER_ONLY)
32 typedef abi_ulong tb_page_addr_t;
33 #else
34 typedef ram_addr_t tb_page_addr_t;
35 #endif
37 /* is_jmp field values */
38 #define DISAS_NEXT 0 /* next instruction can be analyzed */
39 #define DISAS_JUMP 1 /* only pc was modified dynamically */
40 #define DISAS_UPDATE 2 /* cpu state was modified dynamically */
41 #define DISAS_TB_JUMP 3 /* only pc was modified statically */
43 typedef struct TranslationBlock TranslationBlock;
45 /* XXX: make safe guess about sizes */
46 #define MAX_OP_PER_INSTR 96
48 #if HOST_LONG_BITS == 32
49 #define MAX_OPC_PARAM_PER_ARG 2
50 #else
51 #define MAX_OPC_PARAM_PER_ARG 1
52 #endif
53 #define MAX_OPC_PARAM_IARGS 4
54 #define MAX_OPC_PARAM_OARGS 1
55 #define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS)
57 /* A Call op needs up to 4 + 2N parameters on 32-bit archs,
58 * and up to 4 + N parameters on 64-bit archs
59 * (N = number of input arguments + output arguments). */
60 #define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS))
61 #define OPC_BUF_SIZE 640
62 #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
64 /* Maximum size a TCG op can expand to. This is complicated because a
65 single op may require several host instructions and register reloads.
66 For now take a wild guess at 192 bytes, which should allow at least
67 a couple of fixup instructions per argument. */
68 #define TCG_MAX_OP_SIZE 192
70 #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
72 extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
73 extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
74 extern uint16_t gen_opc_icount[OPC_BUF_SIZE];
76 #include "qemu-log.h"
78 void gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
79 void gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb);
80 void gen_pc_load(CPUState *env, struct TranslationBlock *tb,
81 unsigned long searched_pc, int pc_pos, void *puc);
83 unsigned long code_gen_max_block_size(void);
84 void cpu_gen_init(void);
85 int cpu_gen_code(CPUState *env, struct TranslationBlock *tb,
86 int *gen_code_size_ptr);
87 int cpu_restore_state(struct TranslationBlock *tb,
88 CPUState *env, unsigned long searched_pc,
89 void *puc);
90 int cpu_restore_state_copy(struct TranslationBlock *tb,
91 CPUState *env, unsigned long searched_pc,
92 void *puc);
93 void cpu_resume_from_signal(CPUState *env1, void *puc);
94 void cpu_io_recompile(CPUState *env, void *retaddr);
95 TranslationBlock *tb_gen_code(CPUState *env,
96 target_ulong pc, target_ulong cs_base, int flags,
97 int cflags);
98 void cpu_exec_init(CPUState *env);
99 void QEMU_NORETURN cpu_loop_exit(void);
100 int page_unprotect(target_ulong address, unsigned long pc, void *puc);
101 void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
102 int is_cpu_write_access);
103 void tb_invalidate_page_range(target_ulong start, target_ulong end);
104 void tlb_flush_page(CPUState *env, target_ulong addr);
105 void tlb_flush(CPUState *env, int flush_global);
106 #if !defined(CONFIG_USER_ONLY)
107 void tlb_set_page(CPUState *env, target_ulong vaddr,
108 target_phys_addr_t paddr, int prot,
109 int mmu_idx, target_ulong size);
110 #endif
112 #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
114 #define CODE_GEN_PHYS_HASH_BITS 15
115 #define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS)
117 #define MIN_CODE_GEN_BUFFER_SIZE (1024 * 1024)
119 /* estimated block size for TB allocation */
120 /* XXX: use a per code average code fragment size and modulate it
121 according to the host CPU */
122 #if defined(CONFIG_SOFTMMU)
123 #define CODE_GEN_AVG_BLOCK_SIZE 128
124 #else
125 #define CODE_GEN_AVG_BLOCK_SIZE 64
126 #endif
128 #if defined(_ARCH_PPC) || defined(__x86_64__) || defined(__arm__) || defined(__i386__)
129 #define USE_DIRECT_JUMP
130 #endif
132 struct TranslationBlock {
133 target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
134 target_ulong cs_base; /* CS base for this block */
135 uint64_t flags; /* flags defining in which context the code was generated */
136 uint16_t size; /* size of target code for this block (1 <=
137 size <= TARGET_PAGE_SIZE) */
138 uint16_t cflags; /* compile flags */
139 #define CF_COUNT_MASK 0x7fff
140 #define CF_LAST_IO 0x8000 /* Last insn may be an IO access. */
142 uint8_t *tc_ptr; /* pointer to the translated code */
143 /* next matching tb for physical address. */
144 struct TranslationBlock *phys_hash_next;
145 /* first and second physical page containing code. The lower bit
146 of the pointer tells the index in page_next[] */
147 struct TranslationBlock *page_next[2];
148 tb_page_addr_t page_addr[2];
150 /* the following data are used to directly call another TB from
151 the code of this one. */
152 uint16_t tb_next_offset[2]; /* offset of original jump target */
153 #ifdef USE_DIRECT_JUMP
154 uint16_t tb_jmp_offset[2]; /* offset of jump instruction */
155 #else
156 unsigned long tb_next[2]; /* address of jump generated code */
157 #endif
158 /* list of TBs jumping to this one. This is a circular list using
159 the two least significant bits of the pointers to tell what is
160 the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
161 jmp_first */
162 struct TranslationBlock *jmp_next[2];
163 struct TranslationBlock *jmp_first;
164 uint32_t icount;
167 static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc)
169 target_ulong tmp;
170 tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
171 return (tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK;
174 static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
176 target_ulong tmp;
177 tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
178 return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK)
179 | (tmp & TB_JMP_ADDR_MASK));
182 static inline unsigned int tb_phys_hash_func(tb_page_addr_t pc)
184 return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
187 TranslationBlock *tb_alloc(target_ulong pc);
188 void tb_free(TranslationBlock *tb);
189 void tb_flush(CPUState *env);
190 void tb_link_page(TranslationBlock *tb,
191 tb_page_addr_t phys_pc, tb_page_addr_t phys_page2);
192 void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);
194 extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
195 extern uint8_t *code_gen_ptr;
196 extern int code_gen_max_blocks;
198 #if defined(USE_DIRECT_JUMP)
200 #if defined(_ARCH_PPC)
201 extern void ppc_tb_set_jmp_target(unsigned long jmp_addr, unsigned long addr);
202 #define tb_set_jmp_target1 ppc_tb_set_jmp_target
203 #elif defined(__i386__) || defined(__x86_64__)
204 static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
206 /* patch the branch destination */
207 *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
208 /* no need to flush icache explicitly */
210 #elif defined(__arm__)
211 static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
213 #if QEMU_GNUC_PREREQ(4, 1)
214 void __clear_cache(char *beg, char *end);
215 #else
216 register unsigned long _beg __asm ("a1");
217 register unsigned long _end __asm ("a2");
218 register unsigned long _flg __asm ("a3");
219 #endif
221 /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */
222 *(uint32_t *)jmp_addr =
223 (*(uint32_t *)jmp_addr & ~0xffffff)
224 | (((addr - (jmp_addr + 8)) >> 2) & 0xffffff);
226 #if QEMU_GNUC_PREREQ(4, 1)
227 __clear_cache((char *) jmp_addr, (char *) jmp_addr + 4);
228 #else
229 /* flush icache */
230 _beg = jmp_addr;
231 _end = jmp_addr + 4;
232 _flg = 0;
233 __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
234 #endif
236 #endif
238 static inline void tb_set_jmp_target(TranslationBlock *tb,
239 int n, unsigned long addr)
241 unsigned long offset;
243 offset = tb->tb_jmp_offset[n];
244 tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
247 #else
249 /* set the jump target */
250 static inline void tb_set_jmp_target(TranslationBlock *tb,
251 int n, unsigned long addr)
253 tb->tb_next[n] = addr;
256 #endif
258 static inline void tb_add_jump(TranslationBlock *tb, int n,
259 TranslationBlock *tb_next)
261 /* NOTE: this test is only needed for thread safety */
262 if (!tb->jmp_next[n]) {
263 /* patch the native jump address */
264 tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
266 /* add in TB jmp circular list */
267 tb->jmp_next[n] = tb_next->jmp_first;
268 tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
272 TranslationBlock *tb_find_pc(unsigned long pc_ptr);
274 #include "qemu-lock.h"
276 extern spinlock_t tb_lock;
278 extern int tb_invalidated_flag;
280 #if !defined(CONFIG_USER_ONLY)
282 extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
283 extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
284 extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];
286 void tlb_fill(target_ulong addr, int is_write, int mmu_idx,
287 void *retaddr);
289 #include "softmmu_defs.h"
291 #define ACCESS_TYPE (NB_MMU_MODES + 1)
292 #define MEMSUFFIX _code
293 #define env cpu_single_env
295 #define DATA_SIZE 1
296 #include "softmmu_header.h"
298 #define DATA_SIZE 2
299 #include "softmmu_header.h"
301 #define DATA_SIZE 4
302 #include "softmmu_header.h"
304 #define DATA_SIZE 8
305 #include "softmmu_header.h"
307 #undef ACCESS_TYPE
308 #undef MEMSUFFIX
309 #undef env
311 #endif
313 #if defined(CONFIG_USER_ONLY)
314 static inline tb_page_addr_t get_page_addr_code(CPUState *env1, target_ulong addr)
316 return addr;
318 #else
319 /* NOTE: this function can trigger an exception */
320 /* NOTE2: the returned address is not exactly the physical address: it
321 is the offset relative to phys_ram_base */
322 static inline tb_page_addr_t get_page_addr_code(CPUState *env1, target_ulong addr)
324 int mmu_idx, page_index, pd;
325 void *p;
327 page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
328 mmu_idx = cpu_mmu_index(env1);
329 if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code !=
330 (addr & TARGET_PAGE_MASK))) {
331 ldub_code(addr);
333 pd = env1->tlb_table[mmu_idx][page_index].addr_code & ~TARGET_PAGE_MASK;
334 if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
335 #if defined(TARGET_SPARC) || defined(TARGET_MIPS)
336 do_unassigned_access(addr, 0, 1, 0, 4);
337 #else
338 cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr);
339 #endif
341 p = (void *)(unsigned long)addr
342 + env1->tlb_table[mmu_idx][page_index].addend;
343 return qemu_ram_addr_from_host(p);
345 #endif
347 typedef void (CPUDebugExcpHandler)(CPUState *env);
349 CPUDebugExcpHandler *cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler);
351 /* vl.c */
352 extern int singlestep;
354 #endif