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Merge remote-tracking branch 'qmp/queue/qmp' into staging
[qemu.git] / hw / fdc.c
blob1d44bbd1e38a71c382e31adc2fd5b72ed473a6d0
1 /*
2 * QEMU Floppy disk emulator (Intel 82078)
3 *
4 * Copyright (c) 2003, 2007 Jocelyn Mayer
5 * Copyright (c) 2008 Hervé Poussineau
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * The controller is used in Sun4m systems in a slightly different
27 * way. There are changes in DOR register and DMA is not available.
28 */
29
30 #include "hw.h"
31 #include "fdc.h"
32 #include "qemu-error.h"
33 #include "qemu-timer.h"
34 #include "isa.h"
35 #include "sysbus.h"
36 #include "qdev-addr.h"
37 #include "blockdev.h"
38 #include "sysemu.h"
39 #include "block_int.h"
40
41 /********************************************************/
42 /* debug Floppy devices */
43 //#define DEBUG_FLOPPY
44
45 #ifdef DEBUG_FLOPPY
46 #define FLOPPY_DPRINTF(fmt, ...) \
47 do { printf("FLOPPY: " fmt , ## __VA_ARGS__); } while (0)
48 #else
49 #define FLOPPY_DPRINTF(fmt, ...)
50 #endif
51
52 #define FLOPPY_ERROR(fmt, ...) \
53 do { printf("FLOPPY ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
54
55 /********************************************************/
56 /* Floppy drive emulation */
57
58 #define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv)
59 #define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive))
60
61 /* Will always be a fixed parameter for us */
62 #define FD_SECTOR_LEN 512
63 #define FD_SECTOR_SC 2 /* Sector size code */
64 #define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */
65
66 /* Floppy disk drive emulation */
67 typedef enum FDiskFlags {
68 FDISK_DBL_SIDES = 0x01,
69 } FDiskFlags;
70
71 typedef struct FDrive {
72 BlockDriverState *bs;
73 /* Drive status */
74 FDriveType drive;
75 uint8_t perpendicular; /* 2.88 MB access mode */
76 /* Position */
77 uint8_t head;
78 uint8_t track;
79 uint8_t sect;
80 /* Media */
81 FDiskFlags flags;
82 uint8_t last_sect; /* Nb sector per track */
83 uint8_t max_track; /* Nb of tracks */
84 uint16_t bps; /* Bytes per sector */
85 uint8_t ro; /* Is read-only */
86 uint8_t media_changed; /* Is media changed */
87 } FDrive;
88
89 static void fd_init(FDrive *drv)
90 {
91 /* Drive */
92 drv->drive = FDRIVE_DRV_NONE;
93 drv->perpendicular = 0;
94 /* Disk */
95 drv->last_sect = 0;
96 drv->max_track = 0;
97 }
98
99 static int fd_sector_calc(uint8_t head, uint8_t track, uint8_t sect,
100 uint8_t last_sect)
101 {
102 return (((track * 2) + head) * last_sect) + sect - 1;
103 }
104
105 /* Returns current position, in sectors, for given drive */
106 static int fd_sector(FDrive *drv)
107 {
108 return fd_sector_calc(drv->head, drv->track, drv->sect, drv->last_sect);
109 }
110
111 /* Seek to a new position:
112 * returns 0 if already on right track
113 * returns 1 if track changed
114 * returns 2 if track is invalid
115 * returns 3 if sector is invalid
116 * returns 4 if seek is disabled
117 */
118 static int fd_seek(FDrive *drv, uint8_t head, uint8_t track, uint8_t sect,
119 int enable_seek)
120 {
121 uint32_t sector;
122 int ret;
123
124 if (track > drv->max_track ||
125 (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) {
126 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
127 head, track, sect, 1,
128 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
129 drv->max_track, drv->last_sect);
130 return 2;
131 }
132 if (sect > drv->last_sect) {
133 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
134 head, track, sect, 1,
135 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
136 drv->max_track, drv->last_sect);
137 return 3;
138 }
139 sector = fd_sector_calc(head, track, sect, drv->last_sect);
140 ret = 0;
141 if (sector != fd_sector(drv)) {
142 #if 0
143 if (!enable_seek) {
144 FLOPPY_ERROR("no implicit seek %d %02x %02x (max=%d %02x %02x)\n",
145 head, track, sect, 1, drv->max_track, drv->last_sect);
146 return 4;
147 }
148 #endif
149 drv->head = head;
150 if (drv->track != track)
151 ret = 1;
152 drv->track = track;
153 drv->sect = sect;
154 }
155
156 return ret;
157 }
158
159 /* Set drive back to track 0 */
160 static void fd_recalibrate(FDrive *drv)
161 {
162 FLOPPY_DPRINTF("recalibrate\n");
163 drv->head = 0;
164 drv->track = 0;
165 drv->sect = 1;
166 }
167
168 /* Revalidate a disk drive after a disk change */
169 static void fd_revalidate(FDrive *drv)
170 {
171 int nb_heads, max_track, last_sect, ro;
172 FDriveType drive;
173
174 FLOPPY_DPRINTF("revalidate\n");
175 if (drv->bs != NULL && bdrv_is_inserted(drv->bs)) {
176 ro = bdrv_is_read_only(drv->bs);
177 bdrv_get_floppy_geometry_hint(drv->bs, &nb_heads, &max_track,
178 &last_sect, drv->drive, &drive);
179 if (nb_heads != 0 && max_track != 0 && last_sect != 0) {
180 FLOPPY_DPRINTF("User defined disk (%d %d %d)",
181 nb_heads - 1, max_track, last_sect);
182 } else {
183 FLOPPY_DPRINTF("Floppy disk (%d h %d t %d s) %s\n", nb_heads,
184 max_track, last_sect, ro ? "ro" : "rw");
185 }
186 if (nb_heads == 1) {
187 drv->flags &= ~FDISK_DBL_SIDES;
188 } else {
189 drv->flags |= FDISK_DBL_SIDES;
190 }
191 drv->max_track = max_track;
192 drv->last_sect = last_sect;
193 drv->ro = ro;
194 drv->drive = drive;
195 } else {
196 FLOPPY_DPRINTF("No disk in drive\n");
197 drv->last_sect = 0;
198 drv->max_track = 0;
199 drv->flags &= ~FDISK_DBL_SIDES;
200 }
201 }
202
203 /********************************************************/
204 /* Intel 82078 floppy disk controller emulation */
205
206 typedef struct FDCtrl FDCtrl;
207
208 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq);
209 static void fdctrl_reset_fifo(FDCtrl *fdctrl);
210 static int fdctrl_transfer_handler (void *opaque, int nchan,
211 int dma_pos, int dma_len);
212 static void fdctrl_raise_irq(FDCtrl *fdctrl, uint8_t status0);
213
214 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl);
215 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl);
216 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl);
217 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value);
218 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl);
219 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value);
220 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl);
221 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value);
222 static uint32_t fdctrl_read_data(FDCtrl *fdctrl);
223 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value);
224 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl);
225
226 enum {
227 FD_DIR_WRITE = 0,
228 FD_DIR_READ = 1,
229 FD_DIR_SCANE = 2,
230 FD_DIR_SCANL = 3,
231 FD_DIR_SCANH = 4,
232 };
233
234 enum {
235 FD_STATE_MULTI = 0x01, /* multi track flag */
236 FD_STATE_FORMAT = 0x02, /* format flag */
237 FD_STATE_SEEK = 0x04, /* seek flag */
238 };
239
240 enum {
241 FD_REG_SRA = 0x00,
242 FD_REG_SRB = 0x01,
243 FD_REG_DOR = 0x02,
244 FD_REG_TDR = 0x03,
245 FD_REG_MSR = 0x04,
246 FD_REG_DSR = 0x04,
247 FD_REG_FIFO = 0x05,
248 FD_REG_DIR = 0x07,
249 };
250
251 enum {
252 FD_CMD_READ_TRACK = 0x02,
253 FD_CMD_SPECIFY = 0x03,
254 FD_CMD_SENSE_DRIVE_STATUS = 0x04,
255 FD_CMD_WRITE = 0x05,
256 FD_CMD_READ = 0x06,
257 FD_CMD_RECALIBRATE = 0x07,
258 FD_CMD_SENSE_INTERRUPT_STATUS = 0x08,
259 FD_CMD_WRITE_DELETED = 0x09,
260 FD_CMD_READ_ID = 0x0a,
261 FD_CMD_READ_DELETED = 0x0c,
262 FD_CMD_FORMAT_TRACK = 0x0d,
263 FD_CMD_DUMPREG = 0x0e,
264 FD_CMD_SEEK = 0x0f,
265 FD_CMD_VERSION = 0x10,
266 FD_CMD_SCAN_EQUAL = 0x11,
267 FD_CMD_PERPENDICULAR_MODE = 0x12,
268 FD_CMD_CONFIGURE = 0x13,
269 FD_CMD_LOCK = 0x14,
270 FD_CMD_VERIFY = 0x16,
271 FD_CMD_POWERDOWN_MODE = 0x17,
272 FD_CMD_PART_ID = 0x18,
273 FD_CMD_SCAN_LOW_OR_EQUAL = 0x19,
274 FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d,
275 FD_CMD_SAVE = 0x2e,
276 FD_CMD_OPTION = 0x33,
277 FD_CMD_RESTORE = 0x4e,
278 FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e,
279 FD_CMD_RELATIVE_SEEK_OUT = 0x8f,
280 FD_CMD_FORMAT_AND_WRITE = 0xcd,
281 FD_CMD_RELATIVE_SEEK_IN = 0xcf,
282 };
283
284 enum {
285 FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */
286 FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */
287 FD_CONFIG_POLL = 0x10, /* Poll enabled */
288 FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */
289 FD_CONFIG_EIS = 0x40, /* No implied seeks */
290 };
291
292 enum {
293 FD_SR0_EQPMT = 0x10,
294 FD_SR0_SEEK = 0x20,
295 FD_SR0_ABNTERM = 0x40,
296 FD_SR0_INVCMD = 0x80,
297 FD_SR0_RDYCHG = 0xc0,
298 };
299
300 enum {
301 FD_SR1_EC = 0x80, /* End of cylinder */
302 };
303
304 enum {
305 FD_SR2_SNS = 0x04, /* Scan not satisfied */
306 FD_SR2_SEH = 0x08, /* Scan equal hit */
307 };
308
309 enum {
310 FD_SRA_DIR = 0x01,
311 FD_SRA_nWP = 0x02,
312 FD_SRA_nINDX = 0x04,
313 FD_SRA_HDSEL = 0x08,
314 FD_SRA_nTRK0 = 0x10,
315 FD_SRA_STEP = 0x20,
316 FD_SRA_nDRV2 = 0x40,
317 FD_SRA_INTPEND = 0x80,
318 };
319
320 enum {
321 FD_SRB_MTR0 = 0x01,
322 FD_SRB_MTR1 = 0x02,
323 FD_SRB_WGATE = 0x04,
324 FD_SRB_RDATA = 0x08,
325 FD_SRB_WDATA = 0x10,
326 FD_SRB_DR0 = 0x20,
327 };
328
329 enum {
330 #if MAX_FD == 4
331 FD_DOR_SELMASK = 0x03,
332 #else
333 FD_DOR_SELMASK = 0x01,
334 #endif
335 FD_DOR_nRESET = 0x04,
336 FD_DOR_DMAEN = 0x08,
337 FD_DOR_MOTEN0 = 0x10,
338 FD_DOR_MOTEN1 = 0x20,
339 FD_DOR_MOTEN2 = 0x40,
340 FD_DOR_MOTEN3 = 0x80,
341 };
342
343 enum {
344 #if MAX_FD == 4
345 FD_TDR_BOOTSEL = 0x0c,
346 #else
347 FD_TDR_BOOTSEL = 0x04,
348 #endif
349 };
350
351 enum {
352 FD_DSR_DRATEMASK= 0x03,
353 FD_DSR_PWRDOWN = 0x40,
354 FD_DSR_SWRESET = 0x80,
355 };
356
357 enum {
358 FD_MSR_DRV0BUSY = 0x01,
359 FD_MSR_DRV1BUSY = 0x02,
360 FD_MSR_DRV2BUSY = 0x04,
361 FD_MSR_DRV3BUSY = 0x08,
362 FD_MSR_CMDBUSY = 0x10,
363 FD_MSR_NONDMA = 0x20,
364 FD_MSR_DIO = 0x40,
365 FD_MSR_RQM = 0x80,
366 };
367
368 enum {
369 FD_DIR_DSKCHG = 0x80,
370 };
371
372 #define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
373 #define FD_DID_SEEK(state) ((state) & FD_STATE_SEEK)
374 #define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
375
376 struct FDCtrl {
377 qemu_irq irq;
378 /* Controller state */
379 QEMUTimer *result_timer;
380 int dma_chann;
381 /* Controller's identification */
382 uint8_t version;
383 /* HW */
384 uint8_t sra;
385 uint8_t srb;
386 uint8_t dor;
387 uint8_t dor_vmstate; /* only used as temp during vmstate */
388 uint8_t tdr;
389 uint8_t dsr;
390 uint8_t msr;
391 uint8_t cur_drv;
392 uint8_t status0;
393 uint8_t status1;
394 uint8_t status2;
395 /* Command FIFO */
396 uint8_t *fifo;
397 int32_t fifo_size;
398 uint32_t data_pos;
399 uint32_t data_len;
400 uint8_t data_state;
401 uint8_t data_dir;
402 uint8_t eot; /* last wanted sector */
403 /* States kept only to be returned back */
404 /* precompensation */
405 uint8_t precomp_trk;
406 uint8_t config;
407 uint8_t lock;
408 /* Power down config (also with status regB access mode */
409 uint8_t pwrd;
410 /* Floppy drives */
411 uint8_t num_floppies;
412 /* Sun4m quirks? */
413 int sun4m;
414 FDrive drives[MAX_FD];
415 int reset_sensei;
416 /* Timers state */
417 uint8_t timer0;
418 uint8_t timer1;
419 };
420
421 typedef struct FDCtrlSysBus {
422 SysBusDevice busdev;
423 struct FDCtrl state;
424 } FDCtrlSysBus;
425
426 typedef struct FDCtrlISABus {
427 ISADevice busdev;
428 struct FDCtrl state;
429 int32_t bootindexA;
430 int32_t bootindexB;
431 } FDCtrlISABus;
432
433 static uint32_t fdctrl_read (void *opaque, uint32_t reg)
434 {
435 FDCtrl *fdctrl = opaque;
436 uint32_t retval;
437
438 switch (reg) {
439 case FD_REG_SRA:
440 retval = fdctrl_read_statusA(fdctrl);
441 break;
442 case FD_REG_SRB:
443 retval = fdctrl_read_statusB(fdctrl);
444 break;
445 case FD_REG_DOR:
446 retval = fdctrl_read_dor(fdctrl);
447 break;
448 case FD_REG_TDR:
449 retval = fdctrl_read_tape(fdctrl);
450 break;
451 case FD_REG_MSR:
452 retval = fdctrl_read_main_status(fdctrl);
453 break;
454 case FD_REG_FIFO:
455 retval = fdctrl_read_data(fdctrl);
456 break;
457 case FD_REG_DIR:
458 retval = fdctrl_read_dir(fdctrl);
459 break;
460 default:
461 retval = (uint32_t)(-1);
462 break;
463 }
464 FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval);
465
466 return retval;
467 }
468
469 static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
470 {
471 FDCtrl *fdctrl = opaque;
472
473 FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value);
474
475 switch (reg) {
476 case FD_REG_DOR:
477 fdctrl_write_dor(fdctrl, value);
478 break;
479 case FD_REG_TDR:
480 fdctrl_write_tape(fdctrl, value);
481 break;
482 case FD_REG_DSR:
483 fdctrl_write_rate(fdctrl, value);
484 break;
485 case FD_REG_FIFO:
486 fdctrl_write_data(fdctrl, value);
487 break;
488 default:
489 break;
490 }
491 }
492
493 static uint32_t fdctrl_read_port (void *opaque, uint32_t reg)
494 {
495 return fdctrl_read(opaque, reg & 7);
496 }
497
498 static void fdctrl_write_port (void *opaque, uint32_t reg, uint32_t value)
499 {
500 fdctrl_write(opaque, reg & 7, value);
501 }
502
503 static uint32_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg)
504 {
505 return fdctrl_read(opaque, (uint32_t)reg);
506 }
507
508 static void fdctrl_write_mem (void *opaque,
509 target_phys_addr_t reg, uint32_t value)
510 {
511 fdctrl_write(opaque, (uint32_t)reg, value);
512 }
513
514 static CPUReadMemoryFunc * const fdctrl_mem_read[3] = {
515 fdctrl_read_mem,
516 fdctrl_read_mem,
517 fdctrl_read_mem,
518 };
519
520 static CPUWriteMemoryFunc * const fdctrl_mem_write[3] = {
521 fdctrl_write_mem,
522 fdctrl_write_mem,
523 fdctrl_write_mem,
524 };
525
526 static CPUReadMemoryFunc * const fdctrl_mem_read_strict[3] = {
527 fdctrl_read_mem,
528 NULL,
529 NULL,
530 };
531
532 static CPUWriteMemoryFunc * const fdctrl_mem_write_strict[3] = {
533 fdctrl_write_mem,
534 NULL,
535 NULL,
536 };
537
538 static bool fdrive_media_changed_needed(void *opaque)
539 {
540 FDrive *drive = opaque;
541
542 return (drive->bs != NULL && drive->media_changed != 1);
543 }
544
545 static const VMStateDescription vmstate_fdrive_media_changed = {
546 .name = "fdrive/media_changed",
547 .version_id = 1,
548 .minimum_version_id = 1,
549 .minimum_version_id_old = 1,
550 .fields = (VMStateField[]) {
551 VMSTATE_UINT8(media_changed, FDrive),
552 VMSTATE_END_OF_LIST()
553 }
554 };
555
556 static const VMStateDescription vmstate_fdrive = {
557 .name = "fdrive",
558 .version_id = 1,
559 .minimum_version_id = 1,
560 .minimum_version_id_old = 1,
561 .fields = (VMStateField[]) {
562 VMSTATE_UINT8(head, FDrive),
563 VMSTATE_UINT8(track, FDrive),
564 VMSTATE_UINT8(sect, FDrive),
565 VMSTATE_END_OF_LIST()
566 },
567 .subsections = (VMStateSubsection[]) {
568 {
569 .vmsd = &vmstate_fdrive_media_changed,
570 .needed = &fdrive_media_changed_needed,
571 } , {
572 /* empty */
573 }
574 }
575 };
576
577 static void fdc_pre_save(void *opaque)
578 {
579 FDCtrl *s = opaque;
580
581 s->dor_vmstate = s->dor | GET_CUR_DRV(s);
582 }
583
584 static int fdc_post_load(void *opaque, int version_id)
585 {
586 FDCtrl *s = opaque;
587
588 SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK);
589 s->dor = s->dor_vmstate & ~FD_DOR_SELMASK;
590 return 0;
591 }
592
593 static const VMStateDescription vmstate_fdc = {
594 .name = "fdc",
595 .version_id = 2,
596 .minimum_version_id = 2,
597 .minimum_version_id_old = 2,
598 .pre_save = fdc_pre_save,
599 .post_load = fdc_post_load,
600 .fields = (VMStateField []) {
601 /* Controller State */
602 VMSTATE_UINT8(sra, FDCtrl),
603 VMSTATE_UINT8(srb, FDCtrl),
604 VMSTATE_UINT8(dor_vmstate, FDCtrl),
605 VMSTATE_UINT8(tdr, FDCtrl),
606 VMSTATE_UINT8(dsr, FDCtrl),
607 VMSTATE_UINT8(msr, FDCtrl),
608 VMSTATE_UINT8(status0, FDCtrl),
609 VMSTATE_UINT8(status1, FDCtrl),
610 VMSTATE_UINT8(status2, FDCtrl),
611 /* Command FIFO */
612 VMSTATE_VARRAY_INT32(fifo, FDCtrl, fifo_size, 0, vmstate_info_uint8,
613 uint8_t),
614 VMSTATE_UINT32(data_pos, FDCtrl),
615 VMSTATE_UINT32(data_len, FDCtrl),
616 VMSTATE_UINT8(data_state, FDCtrl),
617 VMSTATE_UINT8(data_dir, FDCtrl),
618 VMSTATE_UINT8(eot, FDCtrl),
619 /* States kept only to be returned back */
620 VMSTATE_UINT8(timer0, FDCtrl),
621 VMSTATE_UINT8(timer1, FDCtrl),
622 VMSTATE_UINT8(precomp_trk, FDCtrl),
623 VMSTATE_UINT8(config, FDCtrl),
624 VMSTATE_UINT8(lock, FDCtrl),
625 VMSTATE_UINT8(pwrd, FDCtrl),
626 VMSTATE_UINT8_EQUAL(num_floppies, FDCtrl),
627 VMSTATE_STRUCT_ARRAY(drives, FDCtrl, MAX_FD, 1,
628 vmstate_fdrive, FDrive),
629 VMSTATE_END_OF_LIST()
630 }
631 };
632
633 static void fdctrl_external_reset_sysbus(DeviceState *d)
634 {
635 FDCtrlSysBus *sys = container_of(d, FDCtrlSysBus, busdev.qdev);
636 FDCtrl *s = &sys->state;
637
638 fdctrl_reset(s, 0);
639 }
640
641 static void fdctrl_external_reset_isa(DeviceState *d)
642 {
643 FDCtrlISABus *isa = container_of(d, FDCtrlISABus, busdev.qdev);
644 FDCtrl *s = &isa->state;
645
646 fdctrl_reset(s, 0);
647 }
648
649 static void fdctrl_handle_tc(void *opaque, int irq, int level)
650 {
651 //FDCtrl *s = opaque;
652
653 if (level) {
654 // XXX
655 FLOPPY_DPRINTF("TC pulsed\n");
656 }
657 }
658
659 /* Change IRQ state */
660 static void fdctrl_reset_irq(FDCtrl *fdctrl)
661 {
662 if (!(fdctrl->sra & FD_SRA_INTPEND))
663 return;
664 FLOPPY_DPRINTF("Reset interrupt\n");
665 qemu_set_irq(fdctrl->irq, 0);
666 fdctrl->sra &= ~FD_SRA_INTPEND;
667 }
668
669 static void fdctrl_raise_irq(FDCtrl *fdctrl, uint8_t status0)
670 {
671 /* Sparc mutation */
672 if (fdctrl->sun4m && (fdctrl->msr & FD_MSR_CMDBUSY)) {
673 /* XXX: not sure */
674 fdctrl->msr &= ~FD_MSR_CMDBUSY;
675 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
676 fdctrl->status0 = status0;
677 return;
678 }
679 if (!(fdctrl->sra & FD_SRA_INTPEND)) {
680 qemu_set_irq(fdctrl->irq, 1);
681 fdctrl->sra |= FD_SRA_INTPEND;
682 }
683 fdctrl->reset_sensei = 0;
684 fdctrl->status0 = status0;
685 FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0);
686 }
687
688 /* Reset controller */
689 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq)
690 {
691 int i;
692
693 FLOPPY_DPRINTF("reset controller\n");
694 fdctrl_reset_irq(fdctrl);
695 /* Initialise controller */
696 fdctrl->sra = 0;
697 fdctrl->srb = 0xc0;
698 if (!fdctrl->drives[1].bs)
699 fdctrl->sra |= FD_SRA_nDRV2;
700 fdctrl->cur_drv = 0;
701 fdctrl->dor = FD_DOR_nRESET;
702 fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0;
703 fdctrl->msr = FD_MSR_RQM;
704 /* FIFO state */
705 fdctrl->data_pos = 0;
706 fdctrl->data_len = 0;
707 fdctrl->data_state = 0;
708 fdctrl->data_dir = FD_DIR_WRITE;
709 for (i = 0; i < MAX_FD; i++)
710 fd_recalibrate(&fdctrl->drives[i]);
711 fdctrl_reset_fifo(fdctrl);
712 if (do_irq) {
713 fdctrl_raise_irq(fdctrl, FD_SR0_RDYCHG);
714 fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT;
715 }
716 }
717
718 static inline FDrive *drv0(FDCtrl *fdctrl)
719 {
720 return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2];
721 }
722
723 static inline FDrive *drv1(FDCtrl *fdctrl)
724 {
725 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2))
726 return &fdctrl->drives[1];
727 else
728 return &fdctrl->drives[0];
729 }
730
731 #if MAX_FD == 4
732 static inline FDrive *drv2(FDCtrl *fdctrl)
733 {
734 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2))
735 return &fdctrl->drives[2];
736 else
737 return &fdctrl->drives[1];
738 }
739
740 static inline FDrive *drv3(FDCtrl *fdctrl)
741 {
742 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2))
743 return &fdctrl->drives[3];
744 else
745 return &fdctrl->drives[2];
746 }
747 #endif
748
749 static FDrive *get_cur_drv(FDCtrl *fdctrl)
750 {
751 switch (fdctrl->cur_drv) {
752 case 0: return drv0(fdctrl);
753 case 1: return drv1(fdctrl);
754 #if MAX_FD == 4
755 case 2: return drv2(fdctrl);
756 case 3: return drv3(fdctrl);
757 #endif
758 default: return NULL;
759 }
760 }
761
762 /* Status A register : 0x00 (read-only) */
763 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl)
764 {
765 uint32_t retval = fdctrl->sra;
766
767 FLOPPY_DPRINTF("status register A: 0x%02x\n", retval);
768
769 return retval;
770 }
771
772 /* Status B register : 0x01 (read-only) */
773 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl)
774 {
775 uint32_t retval = fdctrl->srb;
776
777 FLOPPY_DPRINTF("status register B: 0x%02x\n", retval);
778
779 return retval;
780 }
781
782 /* Digital output register : 0x02 */
783 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl)
784 {
785 uint32_t retval = fdctrl->dor;
786
787 /* Selected drive */
788 retval |= fdctrl->cur_drv;
789 FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);
790
791 return retval;
792 }
793
794 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value)
795 {
796 FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
797
798 /* Motors */
799 if (value & FD_DOR_MOTEN0)
800 fdctrl->srb |= FD_SRB_MTR0;
801 else
802 fdctrl->srb &= ~FD_SRB_MTR0;
803 if (value & FD_DOR_MOTEN1)
804 fdctrl->srb |= FD_SRB_MTR1;
805 else
806 fdctrl->srb &= ~FD_SRB_MTR1;
807
808 /* Drive */
809 if (value & 1)
810 fdctrl->srb |= FD_SRB_DR0;
811 else
812 fdctrl->srb &= ~FD_SRB_DR0;
813
814 /* Reset */
815 if (!(value & FD_DOR_nRESET)) {
816 if (fdctrl->dor & FD_DOR_nRESET) {
817 FLOPPY_DPRINTF("controller enter RESET state\n");
818 }
819 } else {
820 if (!(fdctrl->dor & FD_DOR_nRESET)) {
821 FLOPPY_DPRINTF("controller out of RESET state\n");
822 fdctrl_reset(fdctrl, 1);
823 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
824 }
825 }
826 /* Selected drive */
827 fdctrl->cur_drv = value & FD_DOR_SELMASK;
828
829 fdctrl->dor = value;
830 }
831
832 /* Tape drive register : 0x03 */
833 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl)
834 {
835 uint32_t retval = fdctrl->tdr;
836
837 FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval);
838
839 return retval;
840 }
841
842 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value)
843 {
844 /* Reset mode */
845 if (!(fdctrl->dor & FD_DOR_nRESET)) {
846 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
847 return;
848 }
849 FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);
850 /* Disk boot selection indicator */
851 fdctrl->tdr = value & FD_TDR_BOOTSEL;
852 /* Tape indicators: never allow */
853 }
854
855 /* Main status register : 0x04 (read) */
856 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl)
857 {
858 uint32_t retval = fdctrl->msr;
859
860 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
861 fdctrl->dor |= FD_DOR_nRESET;
862
863 /* Sparc mutation */
864 if (fdctrl->sun4m) {
865 retval |= FD_MSR_DIO;
866 fdctrl_reset_irq(fdctrl);
867 };
868
869 FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);
870
871 return retval;
872 }
873
874 /* Data select rate register : 0x04 (write) */
875 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value)
876 {
877 /* Reset mode */
878 if (!(fdctrl->dor & FD_DOR_nRESET)) {
879 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
880 return;
881 }
882 FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
883 /* Reset: autoclear */
884 if (value & FD_DSR_SWRESET) {
885 fdctrl->dor &= ~FD_DOR_nRESET;
886 fdctrl_reset(fdctrl, 1);
887 fdctrl->dor |= FD_DOR_nRESET;
888 }
889 if (value & FD_DSR_PWRDOWN) {
890 fdctrl_reset(fdctrl, 1);
891 }
892 fdctrl->dsr = value;
893 }
894
895 static int fdctrl_media_changed(FDrive *drv)
896 {
897 int ret;
898
899 if (!drv->bs)
900 return 0;
901 if (drv->media_changed) {
902 drv->media_changed = 0;
903 ret = 1;
904 } else {
905 ret = bdrv_media_changed(drv->bs);
906 if (ret < 0) {
907 ret = 0; /* we don't know, assume no */
908 }
909 }
910 if (ret) {
911 fd_revalidate(drv);
912 }
913 return ret;
914 }
915
916 /* Digital input register : 0x07 (read-only) */
917 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl)
918 {
919 uint32_t retval = 0;
920
921 if (fdctrl_media_changed(drv0(fdctrl))
922 || fdctrl_media_changed(drv1(fdctrl))
923 #if MAX_FD == 4
924 || fdctrl_media_changed(drv2(fdctrl))
925 || fdctrl_media_changed(drv3(fdctrl))
926 #endif
927 )
928 retval |= FD_DIR_DSKCHG;
929 if (retval != 0) {
930 FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval);
931 }
932
933 return retval;
934 }
935
936 /* FIFO state control */
937 static void fdctrl_reset_fifo(FDCtrl *fdctrl)
938 {
939 fdctrl->data_dir = FD_DIR_WRITE;
940 fdctrl->data_pos = 0;
941 fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO);
942 }
943
944 /* Set FIFO status for the host to read */
945 static void fdctrl_set_fifo(FDCtrl *fdctrl, int fifo_len, int do_irq)
946 {
947 fdctrl->data_dir = FD_DIR_READ;
948 fdctrl->data_len = fifo_len;
949 fdctrl->data_pos = 0;
950 fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO;
951 if (do_irq)
952 fdctrl_raise_irq(fdctrl, 0x00);
953 }
954
955 /* Set an error: unimplemented/unknown command */
956 static void fdctrl_unimplemented(FDCtrl *fdctrl, int direction)
957 {
958 FLOPPY_ERROR("unimplemented command 0x%02x\n", fdctrl->fifo[0]);
959 fdctrl->fifo[0] = FD_SR0_INVCMD;
960 fdctrl_set_fifo(fdctrl, 1, 0);
961 }
962
963 /* Seek to next sector */
964 static int fdctrl_seek_to_next_sect(FDCtrl *fdctrl, FDrive *cur_drv)
965 {
966 FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
967 cur_drv->head, cur_drv->track, cur_drv->sect,
968 fd_sector(cur_drv));
969 /* XXX: cur_drv->sect >= cur_drv->last_sect should be an
970 error in fact */
971 if (cur_drv->sect >= cur_drv->last_sect ||
972 cur_drv->sect == fdctrl->eot) {
973 cur_drv->sect = 1;
974 if (FD_MULTI_TRACK(fdctrl->data_state)) {
975 if (cur_drv->head == 0 &&
976 (cur_drv->flags & FDISK_DBL_SIDES) != 0) {
977 cur_drv->head = 1;
978 } else {
979 cur_drv->head = 0;
980 cur_drv->track++;
981 if ((cur_drv->flags & FDISK_DBL_SIDES) == 0)
982 return 0;
983 }
984 } else {
985 cur_drv->track++;
986 return 0;
987 }
988 FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n",
989 cur_drv->head, cur_drv->track,
990 cur_drv->sect, fd_sector(cur_drv));
991 } else {
992 cur_drv->sect++;
993 }
994 return 1;
995 }
996
997 /* Callback for transfer end (stop or abort) */
998 static void fdctrl_stop_transfer(FDCtrl *fdctrl, uint8_t status0,
999 uint8_t status1, uint8_t status2)
1000 {
1001 FDrive *cur_drv;
1002
1003 cur_drv = get_cur_drv(fdctrl);
1004 FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
1005 status0, status1, status2,
1006 status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl));
1007 fdctrl->fifo[0] = status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1008 fdctrl->fifo[1] = status1;
1009 fdctrl->fifo[2] = status2;
1010 fdctrl->fifo[3] = cur_drv->track;
1011 fdctrl->fifo[4] = cur_drv->head;
1012 fdctrl->fifo[5] = cur_drv->sect;
1013 fdctrl->fifo[6] = FD_SECTOR_SC;
1014 fdctrl->data_dir = FD_DIR_READ;
1015 if (!(fdctrl->msr & FD_MSR_NONDMA)) {
1016 DMA_release_DREQ(fdctrl->dma_chann);
1017 }
1018 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
1019 fdctrl->msr &= ~FD_MSR_NONDMA;
1020 fdctrl_set_fifo(fdctrl, 7, 1);
1021 }
1022
1023 /* Prepare a data transfer (either DMA or FIFO) */
1024 static void fdctrl_start_transfer(FDCtrl *fdctrl, int direction)
1025 {
1026 FDrive *cur_drv;
1027 uint8_t kh, kt, ks;
1028 int did_seek = 0;
1029
1030 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1031 cur_drv = get_cur_drv(fdctrl);
1032 kt = fdctrl->fifo[2];
1033 kh = fdctrl->fifo[3];
1034 ks = fdctrl->fifo[4];
1035 FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
1036 GET_CUR_DRV(fdctrl), kh, kt, ks,
1037 fd_sector_calc(kh, kt, ks, cur_drv->last_sect));
1038 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1039 case 2:
1040 /* sect too big */
1041 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1042 fdctrl->fifo[3] = kt;
1043 fdctrl->fifo[4] = kh;
1044 fdctrl->fifo[5] = ks;
1045 return;
1046 case 3:
1047 /* track too big */
1048 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1049 fdctrl->fifo[3] = kt;
1050 fdctrl->fifo[4] = kh;
1051 fdctrl->fifo[5] = ks;
1052 return;
1053 case 4:
1054 /* No seek enabled */
1055 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1056 fdctrl->fifo[3] = kt;
1057 fdctrl->fifo[4] = kh;
1058 fdctrl->fifo[5] = ks;
1059 return;
1060 case 1:
1061 did_seek = 1;
1062 break;
1063 default:
1064 break;
1065 }
1066
1067 /* Set the FIFO state */
1068 fdctrl->data_dir = direction;
1069 fdctrl->data_pos = 0;
1070 fdctrl->msr |= FD_MSR_CMDBUSY;
1071 if (fdctrl->fifo[0] & 0x80)
1072 fdctrl->data_state |= FD_STATE_MULTI;
1073 else
1074 fdctrl->data_state &= ~FD_STATE_MULTI;
1075 if (did_seek)
1076 fdctrl->data_state |= FD_STATE_SEEK;
1077 else
1078 fdctrl->data_state &= ~FD_STATE_SEEK;
1079 if (fdctrl->fifo[5] == 00) {
1080 fdctrl->data_len = fdctrl->fifo[8];
1081 } else {
1082 int tmp;
1083 fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]);
1084 tmp = (fdctrl->fifo[6] - ks + 1);
1085 if (fdctrl->fifo[0] & 0x80)
1086 tmp += fdctrl->fifo[6];
1087 fdctrl->data_len *= tmp;
1088 }
1089 fdctrl->eot = fdctrl->fifo[6];
1090 if (fdctrl->dor & FD_DOR_DMAEN) {
1091 int dma_mode;
1092 /* DMA transfer are enabled. Check if DMA channel is well programmed */
1093 dma_mode = DMA_get_channel_mode(fdctrl->dma_chann);
1094 dma_mode = (dma_mode >> 2) & 3;
1095 FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n",
1096 dma_mode, direction,
1097 (128 << fdctrl->fifo[5]) *
1098 (cur_drv->last_sect - ks + 1), fdctrl->data_len);
1099 if (((direction == FD_DIR_SCANE || direction == FD_DIR_SCANL ||
1100 direction == FD_DIR_SCANH) && dma_mode == 0) ||
1101 (direction == FD_DIR_WRITE && dma_mode == 2) ||
1102 (direction == FD_DIR_READ && dma_mode == 1)) {
1103 /* No access is allowed until DMA transfer has completed */
1104 fdctrl->msr &= ~FD_MSR_RQM;
1105 /* Now, we just have to wait for the DMA controller to
1106 * recall us...
1107 */
1108 DMA_hold_DREQ(fdctrl->dma_chann);
1109 DMA_schedule(fdctrl->dma_chann);
1110 return;
1111 } else {
1112 FLOPPY_ERROR("dma_mode=%d direction=%d\n", dma_mode, direction);
1113 }
1114 }
1115 FLOPPY_DPRINTF("start non-DMA transfer\n");
1116 fdctrl->msr |= FD_MSR_NONDMA;
1117 if (direction != FD_DIR_WRITE)
1118 fdctrl->msr |= FD_MSR_DIO;
1119 /* IO based transfer: calculate len */
1120 fdctrl_raise_irq(fdctrl, 0x00);
1121
1122 return;
1123 }
1124
1125 /* Prepare a transfer of deleted data */
1126 static void fdctrl_start_transfer_del(FDCtrl *fdctrl, int direction)
1127 {
1128 FLOPPY_ERROR("fdctrl_start_transfer_del() unimplemented\n");
1129
1130 /* We don't handle deleted data,
1131 * so we don't return *ANYTHING*
1132 */
1133 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1134 }
1135
1136 /* handlers for DMA transfers */
1137 static int fdctrl_transfer_handler (void *opaque, int nchan,
1138 int dma_pos, int dma_len)
1139 {
1140 FDCtrl *fdctrl;
1141 FDrive *cur_drv;
1142 int len, start_pos, rel_pos;
1143 uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00;
1144
1145 fdctrl = opaque;
1146 if (fdctrl->msr & FD_MSR_RQM) {
1147 FLOPPY_DPRINTF("Not in DMA transfer mode !\n");
1148 return 0;
1149 }
1150 cur_drv = get_cur_drv(fdctrl);
1151 if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
1152 fdctrl->data_dir == FD_DIR_SCANH)
1153 status2 = FD_SR2_SNS;
1154 if (dma_len > fdctrl->data_len)
1155 dma_len = fdctrl->data_len;
1156 if (cur_drv->bs == NULL) {
1157 if (fdctrl->data_dir == FD_DIR_WRITE)
1158 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1159 else
1160 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1161 len = 0;
1162 goto transfer_error;
1163 }
1164 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1165 for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) {
1166 len = dma_len - fdctrl->data_pos;
1167 if (len + rel_pos > FD_SECTOR_LEN)
1168 len = FD_SECTOR_LEN - rel_pos;
1169 FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x "
1170 "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos,
1171 fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head,
1172 cur_drv->track, cur_drv->sect, fd_sector(cur_drv),
1173 fd_sector(cur_drv) * FD_SECTOR_LEN);
1174 if (fdctrl->data_dir != FD_DIR_WRITE ||
1175 len < FD_SECTOR_LEN || rel_pos != 0) {
1176 /* READ & SCAN commands and realign to a sector for WRITE */
1177 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv),
1178 fdctrl->fifo, 1) < 0) {
1179 FLOPPY_DPRINTF("Floppy: error getting sector %d\n",
1180 fd_sector(cur_drv));
1181 /* Sure, image size is too small... */
1182 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1183 }
1184 }
1185 switch (fdctrl->data_dir) {
1186 case FD_DIR_READ:
1187 /* READ commands */
1188 DMA_write_memory (nchan, fdctrl->fifo + rel_pos,
1189 fdctrl->data_pos, len);
1190 break;
1191 case FD_DIR_WRITE:
1192 /* WRITE commands */
1193 DMA_read_memory (nchan, fdctrl->fifo + rel_pos,
1194 fdctrl->data_pos, len);
1195 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv),
1196 fdctrl->fifo, 1) < 0) {
1197 FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
1198 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1199 goto transfer_error;
1200 }
1201 break;
1202 default:
1203 /* SCAN commands */
1204 {
1205 uint8_t tmpbuf[FD_SECTOR_LEN];
1206 int ret;
1207 DMA_read_memory (nchan, tmpbuf, fdctrl->data_pos, len);
1208 ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len);
1209 if (ret == 0) {
1210 status2 = FD_SR2_SEH;
1211 goto end_transfer;
1212 }
1213 if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) ||
1214 (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) {
1215 status2 = 0x00;
1216 goto end_transfer;
1217 }
1218 }
1219 break;
1220 }
1221 fdctrl->data_pos += len;
1222 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1223 if (rel_pos == 0) {
1224 /* Seek to next sector */
1225 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv))
1226 break;
1227 }
1228 }
1229 end_transfer:
1230 len = fdctrl->data_pos - start_pos;
1231 FLOPPY_DPRINTF("end transfer %d %d %d\n",
1232 fdctrl->data_pos, len, fdctrl->data_len);
1233 if (fdctrl->data_dir == FD_DIR_SCANE ||
1234 fdctrl->data_dir == FD_DIR_SCANL ||
1235 fdctrl->data_dir == FD_DIR_SCANH)
1236 status2 = FD_SR2_SEH;
1237 if (FD_DID_SEEK(fdctrl->data_state))
1238 status0 |= FD_SR0_SEEK;
1239 fdctrl->data_len -= len;
1240 fdctrl_stop_transfer(fdctrl, status0, status1, status2);
1241 transfer_error:
1242
1243 return len;
1244 }
1245
1246 /* Data register : 0x05 */
1247 static uint32_t fdctrl_read_data(FDCtrl *fdctrl)
1248 {
1249 FDrive *cur_drv;
1250 uint32_t retval = 0;
1251 int pos;
1252
1253 cur_drv = get_cur_drv(fdctrl);
1254 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1255 if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) {
1256 FLOPPY_ERROR("controller not ready for reading\n");
1257 return 0;
1258 }
1259 pos = fdctrl->data_pos;
1260 if (fdctrl->msr & FD_MSR_NONDMA) {
1261 pos %= FD_SECTOR_LEN;
1262 if (pos == 0) {
1263 if (fdctrl->data_pos != 0)
1264 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1265 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1266 fd_sector(cur_drv));
1267 return 0;
1268 }
1269 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1270 FLOPPY_DPRINTF("error getting sector %d\n",
1271 fd_sector(cur_drv));
1272 /* Sure, image size is too small... */
1273 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1274 }
1275 }
1276 }
1277 retval = fdctrl->fifo[pos];
1278 if (++fdctrl->data_pos == fdctrl->data_len) {
1279 fdctrl->data_pos = 0;
1280 /* Switch from transfer mode to status mode
1281 * then from status mode to command mode
1282 */
1283 if (fdctrl->msr & FD_MSR_NONDMA) {
1284 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1285 } else {
1286 fdctrl_reset_fifo(fdctrl);
1287 fdctrl_reset_irq(fdctrl);
1288 }
1289 }
1290 FLOPPY_DPRINTF("data register: 0x%02x\n", retval);
1291
1292 return retval;
1293 }
1294
1295 static void fdctrl_format_sector(FDCtrl *fdctrl)
1296 {
1297 FDrive *cur_drv;
1298 uint8_t kh, kt, ks;
1299
1300 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1301 cur_drv = get_cur_drv(fdctrl);
1302 kt = fdctrl->fifo[6];
1303 kh = fdctrl->fifo[7];
1304 ks = fdctrl->fifo[8];
1305 FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n",
1306 GET_CUR_DRV(fdctrl), kh, kt, ks,
1307 fd_sector_calc(kh, kt, ks, cur_drv->last_sect));
1308 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1309 case 2:
1310 /* sect too big */
1311 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1312 fdctrl->fifo[3] = kt;
1313 fdctrl->fifo[4] = kh;
1314 fdctrl->fifo[5] = ks;
1315 return;
1316 case 3:
1317 /* track too big */
1318 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1319 fdctrl->fifo[3] = kt;
1320 fdctrl->fifo[4] = kh;
1321 fdctrl->fifo[5] = ks;
1322 return;
1323 case 4:
1324 /* No seek enabled */
1325 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1326 fdctrl->fifo[3] = kt;
1327 fdctrl->fifo[4] = kh;
1328 fdctrl->fifo[5] = ks;
1329 return;
1330 case 1:
1331 fdctrl->data_state |= FD_STATE_SEEK;
1332 break;
1333 default:
1334 break;
1335 }
1336 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1337 if (cur_drv->bs == NULL ||
1338 bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1339 FLOPPY_ERROR("formatting sector %d\n", fd_sector(cur_drv));
1340 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1341 } else {
1342 if (cur_drv->sect == cur_drv->last_sect) {
1343 fdctrl->data_state &= ~FD_STATE_FORMAT;
1344 /* Last sector done */
1345 if (FD_DID_SEEK(fdctrl->data_state))
1346 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1347 else
1348 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1349 } else {
1350 /* More to do */
1351 fdctrl->data_pos = 0;
1352 fdctrl->data_len = 4;
1353 }
1354 }
1355 }
1356
1357 static void fdctrl_handle_lock(FDCtrl *fdctrl, int direction)
1358 {
1359 fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0;
1360 fdctrl->fifo[0] = fdctrl->lock << 4;
1361 fdctrl_set_fifo(fdctrl, 1, fdctrl->lock);
1362 }
1363
1364 static void fdctrl_handle_dumpreg(FDCtrl *fdctrl, int direction)
1365 {
1366 FDrive *cur_drv = get_cur_drv(fdctrl);
1367
1368 /* Drives position */
1369 fdctrl->fifo[0] = drv0(fdctrl)->track;
1370 fdctrl->fifo[1] = drv1(fdctrl)->track;
1371 #if MAX_FD == 4
1372 fdctrl->fifo[2] = drv2(fdctrl)->track;
1373 fdctrl->fifo[3] = drv3(fdctrl)->track;
1374 #else
1375 fdctrl->fifo[2] = 0;
1376 fdctrl->fifo[3] = 0;
1377 #endif
1378 /* timers */
1379 fdctrl->fifo[4] = fdctrl->timer0;
1380 fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0);
1381 fdctrl->fifo[6] = cur_drv->last_sect;
1382 fdctrl->fifo[7] = (fdctrl->lock << 7) |
1383 (cur_drv->perpendicular << 2);
1384 fdctrl->fifo[8] = fdctrl->config;
1385 fdctrl->fifo[9] = fdctrl->precomp_trk;
1386 fdctrl_set_fifo(fdctrl, 10, 0);
1387 }
1388
1389 static void fdctrl_handle_version(FDCtrl *fdctrl, int direction)
1390 {
1391 /* Controller's version */
1392 fdctrl->fifo[0] = fdctrl->version;
1393 fdctrl_set_fifo(fdctrl, 1, 1);
1394 }
1395
1396 static void fdctrl_handle_partid(FDCtrl *fdctrl, int direction)
1397 {
1398 fdctrl->fifo[0] = 0x41; /* Stepping 1 */
1399 fdctrl_set_fifo(fdctrl, 1, 0);
1400 }
1401
1402 static void fdctrl_handle_restore(FDCtrl *fdctrl, int direction)
1403 {
1404 FDrive *cur_drv = get_cur_drv(fdctrl);
1405
1406 /* Drives position */
1407 drv0(fdctrl)->track = fdctrl->fifo[3];
1408 drv1(fdctrl)->track = fdctrl->fifo[4];
1409 #if MAX_FD == 4
1410 drv2(fdctrl)->track = fdctrl->fifo[5];
1411 drv3(fdctrl)->track = fdctrl->fifo[6];
1412 #endif
1413 /* timers */
1414 fdctrl->timer0 = fdctrl->fifo[7];
1415 fdctrl->timer1 = fdctrl->fifo[8];
1416 cur_drv->last_sect = fdctrl->fifo[9];
1417 fdctrl->lock = fdctrl->fifo[10] >> 7;
1418 cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF;
1419 fdctrl->config = fdctrl->fifo[11];
1420 fdctrl->precomp_trk = fdctrl->fifo[12];
1421 fdctrl->pwrd = fdctrl->fifo[13];
1422 fdctrl_reset_fifo(fdctrl);
1423 }
1424
1425 static void fdctrl_handle_save(FDCtrl *fdctrl, int direction)
1426 {
1427 FDrive *cur_drv = get_cur_drv(fdctrl);
1428
1429 fdctrl->fifo[0] = 0;
1430 fdctrl->fifo[1] = 0;
1431 /* Drives position */
1432 fdctrl->fifo[2] = drv0(fdctrl)->track;
1433 fdctrl->fifo[3] = drv1(fdctrl)->track;
1434 #if MAX_FD == 4
1435 fdctrl->fifo[4] = drv2(fdctrl)->track;
1436 fdctrl->fifo[5] = drv3(fdctrl)->track;
1437 #else
1438 fdctrl->fifo[4] = 0;
1439 fdctrl->fifo[5] = 0;
1440 #endif
1441 /* timers */
1442 fdctrl->fifo[6] = fdctrl->timer0;
1443 fdctrl->fifo[7] = fdctrl->timer1;
1444 fdctrl->fifo[8] = cur_drv->last_sect;
1445 fdctrl->fifo[9] = (fdctrl->lock << 7) |
1446 (cur_drv->perpendicular << 2);
1447 fdctrl->fifo[10] = fdctrl->config;
1448 fdctrl->fifo[11] = fdctrl->precomp_trk;
1449 fdctrl->fifo[12] = fdctrl->pwrd;
1450 fdctrl->fifo[13] = 0;
1451 fdctrl->fifo[14] = 0;
1452 fdctrl_set_fifo(fdctrl, 15, 1);
1453 }
1454
1455 static void fdctrl_handle_readid(FDCtrl *fdctrl, int direction)
1456 {
1457 FDrive *cur_drv = get_cur_drv(fdctrl);
1458
1459 /* XXX: should set main status register to busy */
1460 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1461 qemu_mod_timer(fdctrl->result_timer,
1462 qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() / 50));
1463 }
1464
1465 static void fdctrl_handle_format_track(FDCtrl *fdctrl, int direction)
1466 {
1467 FDrive *cur_drv;
1468
1469 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1470 cur_drv = get_cur_drv(fdctrl);
1471 fdctrl->data_state |= FD_STATE_FORMAT;
1472 if (fdctrl->fifo[0] & 0x80)
1473 fdctrl->data_state |= FD_STATE_MULTI;
1474 else
1475 fdctrl->data_state &= ~FD_STATE_MULTI;
1476 fdctrl->data_state &= ~FD_STATE_SEEK;
1477 cur_drv->bps =
1478 fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2];
1479 #if 0
1480 cur_drv->last_sect =
1481 cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] :
1482 fdctrl->fifo[3] / 2;
1483 #else
1484 cur_drv->last_sect = fdctrl->fifo[3];
1485 #endif
1486 /* TODO: implement format using DMA expected by the Bochs BIOS
1487 * and Linux fdformat (read 3 bytes per sector via DMA and fill
1488 * the sector with the specified fill byte
1489 */
1490 fdctrl->data_state &= ~FD_STATE_FORMAT;
1491 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1492 }
1493
1494 static void fdctrl_handle_specify(FDCtrl *fdctrl, int direction)
1495 {
1496 fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF;
1497 fdctrl->timer1 = fdctrl->fifo[2] >> 1;
1498 if (fdctrl->fifo[2] & 1)
1499 fdctrl->dor &= ~FD_DOR_DMAEN;
1500 else
1501 fdctrl->dor |= FD_DOR_DMAEN;
1502 /* No result back */
1503 fdctrl_reset_fifo(fdctrl);
1504 }
1505
1506 static void fdctrl_handle_sense_drive_status(FDCtrl *fdctrl, int direction)
1507 {
1508 FDrive *cur_drv;
1509
1510 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1511 cur_drv = get_cur_drv(fdctrl);
1512 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1513 /* 1 Byte status back */
1514 fdctrl->fifo[0] = (cur_drv->ro << 6) |
1515 (cur_drv->track == 0 ? 0x10 : 0x00) |
1516 (cur_drv->head << 2) |
1517 GET_CUR_DRV(fdctrl) |
1518 0x28;
1519 fdctrl_set_fifo(fdctrl, 1, 0);
1520 }
1521
1522 static void fdctrl_handle_recalibrate(FDCtrl *fdctrl, int direction)
1523 {
1524 FDrive *cur_drv;
1525
1526 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1527 cur_drv = get_cur_drv(fdctrl);
1528 fd_recalibrate(cur_drv);
1529 fdctrl_reset_fifo(fdctrl);
1530 /* Raise Interrupt */
1531 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1532 }
1533
1534 static void fdctrl_handle_sense_interrupt_status(FDCtrl *fdctrl, int direction)
1535 {
1536 FDrive *cur_drv = get_cur_drv(fdctrl);
1537
1538 if(fdctrl->reset_sensei > 0) {
1539 fdctrl->fifo[0] =
1540 FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei;
1541 fdctrl->reset_sensei--;
1542 } else {
1543 /* XXX: status0 handling is broken for read/write
1544 commands, so we do this hack. It should be suppressed
1545 ASAP */
1546 fdctrl->fifo[0] =
1547 FD_SR0_SEEK | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1548 }
1549
1550 fdctrl->fifo[1] = cur_drv->track;
1551 fdctrl_set_fifo(fdctrl, 2, 0);
1552 fdctrl_reset_irq(fdctrl);
1553 fdctrl->status0 = FD_SR0_RDYCHG;
1554 }
1555
1556 static void fdctrl_handle_seek(FDCtrl *fdctrl, int direction)
1557 {
1558 FDrive *cur_drv;
1559
1560 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1561 cur_drv = get_cur_drv(fdctrl);
1562 fdctrl_reset_fifo(fdctrl);
1563 if (fdctrl->fifo[2] > cur_drv->max_track) {
1564 fdctrl_raise_irq(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK);
1565 } else {
1566 cur_drv->track = fdctrl->fifo[2];
1567 /* Raise Interrupt */
1568 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1569 }
1570 }
1571
1572 static void fdctrl_handle_perpendicular_mode(FDCtrl *fdctrl, int direction)
1573 {
1574 FDrive *cur_drv = get_cur_drv(fdctrl);
1575
1576 if (fdctrl->fifo[1] & 0x80)
1577 cur_drv->perpendicular = fdctrl->fifo[1] & 0x7;
1578 /* No result back */
1579 fdctrl_reset_fifo(fdctrl);
1580 }
1581
1582 static void fdctrl_handle_configure(FDCtrl *fdctrl, int direction)
1583 {
1584 fdctrl->config = fdctrl->fifo[2];
1585 fdctrl->precomp_trk = fdctrl->fifo[3];
1586 /* No result back */
1587 fdctrl_reset_fifo(fdctrl);
1588 }
1589
1590 static void fdctrl_handle_powerdown_mode(FDCtrl *fdctrl, int direction)
1591 {
1592 fdctrl->pwrd = fdctrl->fifo[1];
1593 fdctrl->fifo[0] = fdctrl->fifo[1];
1594 fdctrl_set_fifo(fdctrl, 1, 1);
1595 }
1596
1597 static void fdctrl_handle_option(FDCtrl *fdctrl, int direction)
1598 {
1599 /* No result back */
1600 fdctrl_reset_fifo(fdctrl);
1601 }
1602
1603 static void fdctrl_handle_drive_specification_command(FDCtrl *fdctrl, int direction)
1604 {
1605 FDrive *cur_drv = get_cur_drv(fdctrl);
1606
1607 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x80) {
1608 /* Command parameters done */
1609 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x40) {
1610 fdctrl->fifo[0] = fdctrl->fifo[1];
1611 fdctrl->fifo[2] = 0;
1612 fdctrl->fifo[3] = 0;
1613 fdctrl_set_fifo(fdctrl, 4, 1);
1614 } else {
1615 fdctrl_reset_fifo(fdctrl);
1616 }
1617 } else if (fdctrl->data_len > 7) {
1618 /* ERROR */
1619 fdctrl->fifo[0] = 0x80 |
1620 (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1621 fdctrl_set_fifo(fdctrl, 1, 1);
1622 }
1623 }
1624
1625 static void fdctrl_handle_relative_seek_out(FDCtrl *fdctrl, int direction)
1626 {
1627 FDrive *cur_drv;
1628
1629 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1630 cur_drv = get_cur_drv(fdctrl);
1631 if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) {
1632 cur_drv->track = cur_drv->max_track - 1;
1633 } else {
1634 cur_drv->track += fdctrl->fifo[2];
1635 }
1636 fdctrl_reset_fifo(fdctrl);
1637 /* Raise Interrupt */
1638 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1639 }
1640
1641 static void fdctrl_handle_relative_seek_in(FDCtrl *fdctrl, int direction)
1642 {
1643 FDrive *cur_drv;
1644
1645 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1646 cur_drv = get_cur_drv(fdctrl);
1647 if (fdctrl->fifo[2] > cur_drv->track) {
1648 cur_drv->track = 0;
1649 } else {
1650 cur_drv->track -= fdctrl->fifo[2];
1651 }
1652 fdctrl_reset_fifo(fdctrl);
1653 /* Raise Interrupt */
1654 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1655 }
1656
1657 static const struct {
1658 uint8_t value;
1659 uint8_t mask;
1660 const char* name;
1661 int parameters;
1662 void (*handler)(FDCtrl *fdctrl, int direction);
1663 int direction;
1664 } handlers[] = {
1665 { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ },
1666 { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE },
1667 { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek },
1668 { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status },
1669 { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate },
1670 { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track },
1671 { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ },
1672 { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */
1673 { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */
1674 { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ },
1675 { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE },
1676 { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_unimplemented },
1677 { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL },
1678 { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH },
1679 { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE },
1680 { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid },
1681 { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify },
1682 { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status },
1683 { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode },
1684 { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure },
1685 { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode },
1686 { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option },
1687 { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command },
1688 { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out },
1689 { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented },
1690 { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in },
1691 { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock },
1692 { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg },
1693 { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version },
1694 { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid },
1695 { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */
1696 { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */
1697 };
1698 /* Associate command to an index in the 'handlers' array */
1699 static uint8_t command_to_handler[256];
1700
1701 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value)
1702 {
1703 FDrive *cur_drv;
1704 int pos;
1705
1706 /* Reset mode */
1707 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1708 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1709 return;
1710 }
1711 if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) {
1712 FLOPPY_ERROR("controller not ready for writing\n");
1713 return;
1714 }
1715 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1716 /* Is it write command time ? */
1717 if (fdctrl->msr & FD_MSR_NONDMA) {
1718 /* FIFO data write */
1719 pos = fdctrl->data_pos++;
1720 pos %= FD_SECTOR_LEN;
1721 fdctrl->fifo[pos] = value;
1722 if (pos == FD_SECTOR_LEN - 1 ||
1723 fdctrl->data_pos == fdctrl->data_len) {
1724 cur_drv = get_cur_drv(fdctrl);
1725 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1726 FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
1727 return;
1728 }
1729 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1730 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1731 fd_sector(cur_drv));
1732 return;
1733 }
1734 }
1735 /* Switch from transfer mode to status mode
1736 * then from status mode to command mode
1737 */
1738 if (fdctrl->data_pos == fdctrl->data_len)
1739 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1740 return;
1741 }
1742 if (fdctrl->data_pos == 0) {
1743 /* Command */
1744 pos = command_to_handler[value & 0xff];
1745 FLOPPY_DPRINTF("%s command\n", handlers[pos].name);
1746 fdctrl->data_len = handlers[pos].parameters + 1;
1747 }
1748
1749 FLOPPY_DPRINTF("%s: %02x\n", __func__, value);
1750 fdctrl->fifo[fdctrl->data_pos++] = value;
1751 if (fdctrl->data_pos == fdctrl->data_len) {
1752 /* We now have all parameters
1753 * and will be able to treat the command
1754 */
1755 if (fdctrl->data_state & FD_STATE_FORMAT) {
1756 fdctrl_format_sector(fdctrl);
1757 return;
1758 }
1759
1760 pos = command_to_handler[fdctrl->fifo[0] & 0xff];
1761 FLOPPY_DPRINTF("treat %s command\n", handlers[pos].name);
1762 (*handlers[pos].handler)(fdctrl, handlers[pos].direction);
1763 }
1764 }
1765
1766 static void fdctrl_result_timer(void *opaque)
1767 {
1768 FDCtrl *fdctrl = opaque;
1769 FDrive *cur_drv = get_cur_drv(fdctrl);
1770
1771 /* Pretend we are spinning.
1772 * This is needed for Coherent, which uses READ ID to check for
1773 * sector interleaving.
1774 */
1775 if (cur_drv->last_sect != 0) {
1776 cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1;
1777 }
1778 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1779 }
1780
1781 static void fdctrl_change_cb(void *opaque)
1782 {
1783 FDrive *drive = opaque;
1784
1785 drive->media_changed = 1;
1786 }
1787
1788 static const BlockDevOps fdctrl_block_ops = {
1789 .change_media_cb = fdctrl_change_cb,
1790 };
1791
1792 /* Init functions */
1793 static int fdctrl_connect_drives(FDCtrl *fdctrl)
1794 {
1795 unsigned int i;
1796 FDrive *drive;
1797
1798 for (i = 0; i < MAX_FD; i++) {
1799 drive = &fdctrl->drives[i];
1800
1801 if (drive->bs) {
1802 if (bdrv_get_on_error(drive->bs, 0) != BLOCK_ERR_STOP_ENOSPC) {
1803 error_report("fdc doesn't support drive option werror");
1804 return -1;
1805 }
1806 if (bdrv_get_on_error(drive->bs, 1) != BLOCK_ERR_REPORT) {
1807 error_report("fdc doesn't support drive option rerror");
1808 return -1;
1809 }
1810 }
1811
1812 fd_init(drive);
1813 fd_revalidate(drive);
1814 if (drive->bs) {
1815 drive->media_changed = 1;
1816 bdrv_set_removable(drive->bs, 1);
1817 bdrv_set_dev_ops(drive->bs, &fdctrl_block_ops, drive);
1818 }
1819 }
1820 return 0;
1821 }
1822
1823 void fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
1824 target_phys_addr_t mmio_base, DriveInfo **fds)
1825 {
1826 FDCtrl *fdctrl;
1827 DeviceState *dev;
1828 FDCtrlSysBus *sys;
1829
1830 dev = qdev_create(NULL, "sysbus-fdc");
1831 sys = DO_UPCAST(FDCtrlSysBus, busdev.qdev, dev);
1832 fdctrl = &sys->state;
1833 fdctrl->dma_chann = dma_chann; /* FIXME */
1834 if (fds[0]) {
1835 qdev_prop_set_drive_nofail(dev, "driveA", fds[0]->bdrv);
1836 }
1837 if (fds[1]) {
1838 qdev_prop_set_drive_nofail(dev, "driveB", fds[1]->bdrv);
1839 }
1840 qdev_init_nofail(dev);
1841 sysbus_connect_irq(&sys->busdev, 0, irq);
1842 sysbus_mmio_map(&sys->busdev, 0, mmio_base);
1843 }
1844
1845 void sun4m_fdctrl_init(qemu_irq irq, target_phys_addr_t io_base,
1846 DriveInfo **fds, qemu_irq *fdc_tc)
1847 {
1848 DeviceState *dev;
1849 FDCtrlSysBus *sys;
1850
1851 dev = qdev_create(NULL, "SUNW,fdtwo");
1852 if (fds[0]) {
1853 qdev_prop_set_drive_nofail(dev, "drive", fds[0]->bdrv);
1854 }
1855 qdev_init_nofail(dev);
1856 sys = DO_UPCAST(FDCtrlSysBus, busdev.qdev, dev);
1857 sysbus_connect_irq(&sys->busdev, 0, irq);
1858 sysbus_mmio_map(&sys->busdev, 0, io_base);
1859 *fdc_tc = qdev_get_gpio_in(dev, 0);
1860 }
1861
1862 static int fdctrl_init_common(FDCtrl *fdctrl)
1863 {
1864 int i, j;
1865 static int command_tables_inited = 0;
1866
1867 /* Fill 'command_to_handler' lookup table */
1868 if (!command_tables_inited) {
1869 command_tables_inited = 1;
1870 for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) {
1871 for (j = 0; j < sizeof(command_to_handler); j++) {
1872 if ((j & handlers[i].mask) == handlers[i].value) {
1873 command_to_handler[j] = i;
1874 }
1875 }
1876 }
1877 }
1878
1879 FLOPPY_DPRINTF("init controller\n");
1880 fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
1881 fdctrl->fifo_size = 512;
1882 fdctrl->result_timer = qemu_new_timer_ns(vm_clock,
1883 fdctrl_result_timer, fdctrl);
1884
1885 fdctrl->version = 0x90; /* Intel 82078 controller */
1886 fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
1887 fdctrl->num_floppies = MAX_FD;
1888
1889 if (fdctrl->dma_chann != -1)
1890 DMA_register_channel(fdctrl->dma_chann, &fdctrl_transfer_handler, fdctrl);
1891 return fdctrl_connect_drives(fdctrl);
1892 }
1893
1894 static int isabus_fdc_init1(ISADevice *dev)
1895 {
1896 FDCtrlISABus *isa = DO_UPCAST(FDCtrlISABus, busdev, dev);
1897 FDCtrl *fdctrl = &isa->state;
1898 int iobase = 0x3f0;
1899 int isairq = 6;
1900 int dma_chann = 2;
1901 int ret;
1902
1903 register_ioport_read(iobase + 0x01, 5, 1,
1904 &fdctrl_read_port, fdctrl);
1905 register_ioport_read(iobase + 0x07, 1, 1,
1906 &fdctrl_read_port, fdctrl);
1907 register_ioport_write(iobase + 0x01, 5, 1,
1908 &fdctrl_write_port, fdctrl);
1909 register_ioport_write(iobase + 0x07, 1, 1,
1910 &fdctrl_write_port, fdctrl);
1911 isa_init_ioport_range(dev, iobase, 6);
1912 isa_init_ioport(dev, iobase + 7);
1913
1914 isa_init_irq(&isa->busdev, &fdctrl->irq, isairq);
1915 fdctrl->dma_chann = dma_chann;
1916
1917 qdev_set_legacy_instance_id(&dev->qdev, iobase, 2);
1918 ret = fdctrl_init_common(fdctrl);
1919
1920 add_boot_device_path(isa->bootindexA, &dev->qdev, "/floppy@0");
1921 add_boot_device_path(isa->bootindexB, &dev->qdev, "/floppy@1");
1922
1923 return ret;
1924 }
1925
1926 static int sysbus_fdc_init1(SysBusDevice *dev)
1927 {
1928 FDCtrlSysBus *sys = DO_UPCAST(FDCtrlSysBus, busdev, dev);
1929 FDCtrl *fdctrl = &sys->state;
1930 int io;
1931 int ret;
1932
1933 io = cpu_register_io_memory(fdctrl_mem_read, fdctrl_mem_write, fdctrl,
1934 DEVICE_NATIVE_ENDIAN);
1935 sysbus_init_mmio(dev, 0x08, io);
1936 sysbus_init_irq(dev, &fdctrl->irq);
1937 qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
1938 fdctrl->dma_chann = -1;
1939
1940 qdev_set_legacy_instance_id(&dev->qdev, io, 2);
1941 ret = fdctrl_init_common(fdctrl);
1942
1943 return ret;
1944 }
1945
1946 static int sun4m_fdc_init1(SysBusDevice *dev)
1947 {
1948 FDCtrl *fdctrl = &(FROM_SYSBUS(FDCtrlSysBus, dev)->state);
1949 int io;
1950
1951 io = cpu_register_io_memory(fdctrl_mem_read_strict,
1952 fdctrl_mem_write_strict, fdctrl,
1953 DEVICE_NATIVE_ENDIAN);
1954 sysbus_init_mmio(dev, 0x08, io);
1955 sysbus_init_irq(dev, &fdctrl->irq);
1956 qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
1957
1958 fdctrl->sun4m = 1;
1959 qdev_set_legacy_instance_id(&dev->qdev, io, 2);
1960 return fdctrl_init_common(fdctrl);
1961 }
1962
1963 static const VMStateDescription vmstate_isa_fdc ={
1964 .name = "fdc",
1965 .version_id = 2,
1966 .minimum_version_id = 2,
1967 .fields = (VMStateField []) {
1968 VMSTATE_STRUCT(state, FDCtrlISABus, 0, vmstate_fdc, FDCtrl),
1969 VMSTATE_END_OF_LIST()
1970 }
1971 };
1972
1973 static ISADeviceInfo isa_fdc_info = {
1974 .init = isabus_fdc_init1,
1975 .qdev.name = "isa-fdc",
1976 .qdev.fw_name = "fdc",
1977 .qdev.size = sizeof(FDCtrlISABus),
1978 .qdev.no_user = 1,
1979 .qdev.vmsd = &vmstate_isa_fdc,
1980 .qdev.reset = fdctrl_external_reset_isa,
1981 .qdev.props = (Property[]) {
1982 DEFINE_PROP_DRIVE("driveA", FDCtrlISABus, state.drives[0].bs),
1983 DEFINE_PROP_DRIVE("driveB", FDCtrlISABus, state.drives[1].bs),
1984 DEFINE_PROP_INT32("bootindexA", FDCtrlISABus, bootindexA, -1),
1985 DEFINE_PROP_INT32("bootindexB", FDCtrlISABus, bootindexB, -1),
1986 DEFINE_PROP_END_OF_LIST(),
1987 },
1988 };
1989
1990 static const VMStateDescription vmstate_sysbus_fdc ={
1991 .name = "fdc",
1992 .version_id = 2,
1993 .minimum_version_id = 2,
1994 .fields = (VMStateField []) {
1995 VMSTATE_STRUCT(state, FDCtrlSysBus, 0, vmstate_fdc, FDCtrl),
1996 VMSTATE_END_OF_LIST()
1997 }
1998 };
1999
2000 static SysBusDeviceInfo sysbus_fdc_info = {
2001 .init = sysbus_fdc_init1,
2002 .qdev.name = "sysbus-fdc",
2003 .qdev.size = sizeof(FDCtrlSysBus),
2004 .qdev.vmsd = &vmstate_sysbus_fdc,
2005 .qdev.reset = fdctrl_external_reset_sysbus,
2006 .qdev.props = (Property[]) {
2007 DEFINE_PROP_DRIVE("driveA", FDCtrlSysBus, state.drives[0].bs),
2008 DEFINE_PROP_DRIVE("driveB", FDCtrlSysBus, state.drives[1].bs),
2009 DEFINE_PROP_END_OF_LIST(),
2010 },
2011 };
2012
2013 static SysBusDeviceInfo sun4m_fdc_info = {
2014 .init = sun4m_fdc_init1,
2015 .qdev.name = "SUNW,fdtwo",
2016 .qdev.size = sizeof(FDCtrlSysBus),
2017 .qdev.vmsd = &vmstate_sysbus_fdc,
2018 .qdev.reset = fdctrl_external_reset_sysbus,
2019 .qdev.props = (Property[]) {
2020 DEFINE_PROP_DRIVE("drive", FDCtrlSysBus, state.drives[0].bs),
2021 DEFINE_PROP_END_OF_LIST(),
2022 },
2023 };
2024
2025 static void fdc_register_devices(void)
2026 {
2027 isa_qdev_register(&isa_fdc_info);
2028 sysbus_register_withprop(&sysbus_fdc_info);
2029 sysbus_register_withprop(&sun4m_fdc_info);
2030 }
2031
2032 device_init(fdc_register_devices)
QEmu