core-typhoon.h

   1 /* Memory layout and register descriptions for the TSUNAMI/TYPHOON chipset.
   2
   3    Copyright (C) 2011 Richard Henderson
   4
   5    This file is part of QEMU PALcode.
   6
   7    This program is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 2 of the License or
  10    (at your option) any later version.
  11
  12    This program is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the text
  15    of the GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program; see the file COPYING.  If not see
  19    <http://www.gnu.org/licenses/>.  */
  20
  21 #ifndef TYPHOON_H
  22 #define TYPHOON_H 1
  23
  24 /* Assume a 43-bit KSEG for now.  */
  25 #define PIO_PHYS_ADDR   0x80000000000
  26 #define PIO_KSEG_ADDR   (0xfffffc0000000000 + 0x10000000000)
  27
  28 /* CCHIP REGISTERS */
  29
  30 #define TYPHOON_CCHIP           0x1a0000000
  31
  32 #define TYPHOON_CCHIP_CSC       0x0000
  33 #define TYPHOON_CCHIP_MTR       0x0040
  34 #define TYPHOON_CCHIP_MISC      0x0080
  35 #define TYPHOON_CCHIP_MPD       0x00c0
  36 #define TYPHOON_CCHIP_AAR0      0x0100
  37 #define TYPHOON_CCHIP_AAR1      0x0140
  38 #define TYPHOON_CCHIP_AAR2      0x0180
  39 #define TYPHOON_CCHIP_AAR3      0x01c0
  40 #define TYPHOON_CCHIP_DIM0      0x0200
  41 #define TYPHOON_CCHIP_DIM1      0x0240
  42 #define TYPHOON_CCHIP_DIR0      0x0280
  43 #define TYPHOON_CCHIP_DIR1      0x02c0
  44 #define TYPHOON_CCHIP_DRIR      0x0300
  45 #define TYPHOON_CCHIP_PRBEN     0x0340
  46 #define TYPHOON_CCHIP_IIC0      0x0380
  47 #define TYPHOON_CCHIP_IIC1      0x03c0
  48 #define TYPHOON_CCHIP_MPR0      0x0400
  49 #define TYPHOON_CCHIP_MPR1      0x0440
  50 #define TYPHOON_CCHIP_MPR2      0x0480
  51 #define TYPHOON_CCHIP_MPR3      0x04c0
  52 #define TYPHOON_CCHIP_TTR       0x0580
  53 #define TYPHOON_CCHIP_TDR       0x05c0
  54 #define TYPHOON_CCHIP_DIM2      0x0600
  55 #define TYPHOON_CCHIP_DIM3      0x0640
  56 #define TYPHOON_CCHIP_DIR2      0x0680
  57 #define TYPHOON_CCHIP_DIR3      0x06c0
  58 #define TYPHOON_CCHIP_IIC2      0x0700
  59 #define TYPHOON_CCHIP_IIC3      0x0740
  60 #define TYPHOON_CCHIP_PWR       0x0780
  61 #define TYPHOON_CCHIP_CMONCTLA  0x0c00
  62 #define TYPHOON_CCHIP_CMONCTLB  0x0c40
  63 #define TYPHOON_CCHIP_CMONCNT01 0x0c80
  64 #define TYPHOON_CCHIP_CMONCNT23 0x0cc0
  65
  66 /* DCHIP REGISTERS */
  67
  68 #define TYPHOON_DCHIP           0x1b0000000
  69
  70 #define TYPHOON_DCHIP_DSC       0x0800
  71 #define TYPHOON_DCHIP_STR       0x0840
  72 #define TYPHOON_DCHIP_DREV      0x0880
  73 #define TYPHOON_DCHIP_DSC2      0x08c0
  74
  75 /* PCHIP REGISTERS */
  76
  77 #define TYPHOON_PCHIP0          0x180000000
  78 #define TYPHOON_PCHIP1          0x380000000
  79
  80 #define TYPHOON_PCHIP_WSBA0     0x0000
  81 #define TYPHOON_PCHIP_WSBA1     0x0040
  82 #define TYPHOON_PCHIP_WSBA2     0x0080
  83 #define TYPHOON_PCHIP_WSBA3     0x00c0
  84 #define TYPHOON_PCHIP_WSM0      0x0100
  85 #define TYPHOON_PCHIP_WSM1      0x0140
  86 #define TYPHOON_PCHIP_WSM2      0x0180
  87 #define TYPHOON_PCHIP_WSM3      0x01c0
  88 #define TYPHOON_PCHIP_TBA0      0x0200
  89 #define TYPHOON_PCHIP_TBA1      0x0240
  90 #define TYPHOON_PCHIP_TBA2      0x0280
  91 #define TYPHOON_PCHIP_TBA3      0x02c0
  92 #define TYPHOON_PCHIP_PCTL      0x0300
  93 #define TYPHOON_PCHIP_PLAT      0x0340
  94 #define TYPHOON_PCHIP_PERROR    0x03c0
  95 #define TYPHOON_PCHIP_PERRMASK  0x0400
  96 #define TYPHOON_PCHIP_PERRSET   0x0440
  97 #define TYPHOON_PCHIP_TLBIV     0x0480
  98 #define TYPHOON_PCHIP_TLBIA     0x04c0
  99 #define TYPHOON_PCHIP_PMONCTL   0x0500
 100 #define TYPHOON_PCHIP_PMONCNT   0x0540
 101 #define TYPHOON_PCHIP_SPRST     0x0800
 102
 103 /* PCI ADDRESSES */
 104
 105 #define TYPHOON_PCHIP0_PCI_MEM  0
 106 #define TYPHOON_PCHIP0_PCI_IO   0x1fc000000
 107 #define TYPHOON_PCHIP0_PCI_CONF 0x1fe000000
 108 #define TYPHOON_PCHIP0_PCI_IACK 0x1f8000000
 109
 110 #ifdef __ASSEMBLER__
 111
 112 #include "pal.h"
 113
 114 #define ptCpuDIR        ptSys0
 115 #define ptCpuIIC        ptSys1
 116
 117 /* Unfortunately, GAS doesn't attempt any interesting constructions of
 118    64-bit constants, dropping them all into the .lit8 section.  It is
 119    better for us to build these by hand.  */
 120 .macro  LOAD_PHYS_CCHIP ret
 121         lda     \ret, (PIO_PHYS_ADDR + TYPHOON_CCHIP) >> 29
 122         sll     \ret, 29, \ret
 123 .endm
 124
 125 .macro  LOAD_PHYS_PCHIP0 ret
 126         lda     \ret, (PIO_PHYS_ADDR + TYPHOON_PCHIP0) >> 29
 127         sll     \ret, 29, \ret
 128 .endm
 129
 130 .macro  LOAD_PHYS_PCHIP0_IACK ret
 131         .set    macro
 132         lda     \ret, (PIO_PHYS_ADDR + TYPHOON_PCHIP0_PCI_IACK) >> 24
 133         .set    nomacro
 134         sll     \ret, 24, \ret
 135 .endm
 136
 137 .macro  LOAD_KSEG_PCI_IO ret
 138         .set    macro
 139         // Note that GAS shifts are logical.  Force arithmetic shift style
 140         // results by negating before and after the shift.
 141         lda     \ret, -(-(PIO_KSEG_ADDR + TYPHOON_PCHIP0_PCI_IO) >> 20)
 142         .set    nomacro
 143         sll     \ret, 20, \ret
 144 .endm
 145
 146 .macro  LOAD_KSEG_PCI_CONF ret
 147         .set    macro
 148         // Note that GAS shifts are logical.  Force arithmetic shift style
 149         // results by negating before and after the shift.
 150         lda     \ret, -(-(PIO_KSEG_ADDR + TYPHOON_PCHIP0_PCI_CONF) >> 20)
 151         .set    nomacro
 152         sll     \ret, 20, \ret
 153 .endm
 154
 155 .macro  SYS_WHAMI       ret
 156         LOAD_PHYS_CCHIP \ret
 157         ldq_p           \ret, TYPHOON_CCHIP_MISC(\ret)
 158         and             \ret, 3, \ret
 159 .endm
 160
 161 /* ACK the Interprocessor Interrupt.  */
 162 .macro  SYS_ACK_SMP     t0, t1, t2
 163         LOAD_PHYS_CCHIP \t0
 164         ldq_p           \t1, TYPHOON_CCHIP_MISC(\t0)
 165         and             \t1, 3, \t1
 166         addq            \t1, 8, \t1
 167         lda             \t2, 1
 168         sll             \t2, \t1, \t2
 169         stq_p           \t2, TYPHOON_CCHIP_MISC(\t0)
 170 .endm
 171
 172 /* ACK the Clock Interrupt.  */
 173 .macro  SYS_ACK_CLK     t0, t1, t2
 174         LOAD_PHYS_CCHIP \t0
 175         ldq_p           \t1, TYPHOON_CCHIP_MISC(\t0)
 176         and             \t1, 3, \t1
 177         addq            \t1, 4, \t1
 178         lda             \t2, 1
 179         sll             \t2, \t1, \t2
 180         stq_p           \t2, TYPHOON_CCHIP_MISC(\t0)
 181 .endm
 182
 183 /* Interrupt another CPU.  */
 184 .macro SYS_WRIPIR       target, t0, t1, t2
 185         LOAD_PHYS_CCHIP \t0
 186         mov             1, \t1
 187         and             \target, 3, \t2
 188         addq            \t2, 12, \t2
 189         sll             \t1, \t2, \t1
 190         stq_p           \t1, TYPHOON_CCHIP_MISC(\t0)
 191 .endm
 192
 193 #endif /* ASSEMBLER */
 194 #endif /* TYPHOON_H */