4 * Copyright (c) 2004-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>
21 #include "qemu-timer.h"
22 #include "host-utils.h"
27 /* APIC Local Vector Table */
28 #define APIC_LVT_TIMER 0
29 #define APIC_LVT_THERMAL 1
30 #define APIC_LVT_PERFORM 2
31 #define APIC_LVT_LINT0 3
32 #define APIC_LVT_LINT1 4
33 #define APIC_LVT_ERROR 5
36 /* APIC delivery modes */
37 #define APIC_DM_FIXED 0
38 #define APIC_DM_LOWPRI 1
41 #define APIC_DM_INIT 5
42 #define APIC_DM_SIPI 6
43 #define APIC_DM_EXTINT 7
45 /* APIC destination mode */
46 #define APIC_DESTMODE_FLAT 0xf
47 #define APIC_DESTMODE_CLUSTER 1
49 #define APIC_TRIGGER_EDGE 0
50 #define APIC_TRIGGER_LEVEL 1
52 #define APIC_LVT_TIMER_PERIODIC (1<<17)
53 #define APIC_LVT_MASKED (1<<16)
54 #define APIC_LVT_LEVEL_TRIGGER (1<<15)
55 #define APIC_LVT_REMOTE_IRR (1<<14)
56 #define APIC_INPUT_POLARITY (1<<13)
57 #define APIC_SEND_PENDING (1<<12)
59 #define ESR_ILLEGAL_ADDRESS (1 << 7)
61 #define APIC_SV_ENABLE (1 << 8)
64 #define MAX_APIC_WORDS 8
66 /* Intel APIC constants: from include/asm/msidef.h */
67 #define MSI_DATA_VECTOR_SHIFT 0
68 #define MSI_DATA_VECTOR_MASK 0x000000ff
69 #define MSI_DATA_DELIVERY_MODE_SHIFT 8
70 #define MSI_DATA_TRIGGER_SHIFT 15
71 #define MSI_DATA_LEVEL_SHIFT 14
72 #define MSI_ADDR_DEST_MODE_SHIFT 2
73 #define MSI_ADDR_DEST_ID_SHIFT 12
74 #define MSI_ADDR_DEST_ID_MASK 0x00ffff0
76 #define MSI_ADDR_SIZE 0x100000
78 typedef struct APICState APICState
;
87 uint32_t spurious_vec
;
90 uint32_t isr
[8]; /* in service register */
91 uint32_t tmr
[8]; /* trigger mode register */
92 uint32_t irr
[8]; /* interrupt request register */
93 uint32_t lvt
[APIC_LVT_NB
];
94 uint32_t esr
; /* error register */
99 uint32_t initial_count
;
100 int64_t initial_count_load_time
, next_time
;
107 static APICState
*local_apics
[MAX_APICS
+ 1];
108 static int apic_irq_delivered
;
110 static void apic_set_irq(APICState
*s
, int vector_num
, int trigger_mode
);
111 static void apic_update_irq(APICState
*s
);
112 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask
,
113 uint8_t dest
, uint8_t dest_mode
);
115 /* Find first bit starting from msb */
116 static int fls_bit(uint32_t value
)
118 return 31 - clz32(value
);
121 /* Find first bit starting from lsb */
122 static int ffs_bit(uint32_t value
)
127 static inline void set_bit(uint32_t *tab
, int index
)
131 mask
= 1 << (index
& 0x1f);
135 static inline void reset_bit(uint32_t *tab
, int index
)
139 mask
= 1 << (index
& 0x1f);
143 static inline int get_bit(uint32_t *tab
, int index
)
147 mask
= 1 << (index
& 0x1f);
148 return !!(tab
[i
] & mask
);
151 static void apic_local_deliver(APICState
*s
, int vector
)
153 uint32_t lvt
= s
->lvt
[vector
];
156 trace_apic_local_deliver(vector
, (lvt
>> 8) & 7);
158 if (lvt
& APIC_LVT_MASKED
)
161 switch ((lvt
>> 8) & 7) {
163 cpu_interrupt(s
->cpu_env
, CPU_INTERRUPT_SMI
);
167 cpu_interrupt(s
->cpu_env
, CPU_INTERRUPT_NMI
);
171 cpu_interrupt(s
->cpu_env
, CPU_INTERRUPT_HARD
);
175 trigger_mode
= APIC_TRIGGER_EDGE
;
176 if ((vector
== APIC_LVT_LINT0
|| vector
== APIC_LVT_LINT1
) &&
177 (lvt
& APIC_LVT_LEVEL_TRIGGER
))
178 trigger_mode
= APIC_TRIGGER_LEVEL
;
179 apic_set_irq(s
, lvt
& 0xff, trigger_mode
);
183 void apic_deliver_pic_intr(DeviceState
*d
, int level
)
185 APICState
*s
= DO_UPCAST(APICState
, busdev
.qdev
, d
);
188 apic_local_deliver(s
, APIC_LVT_LINT0
);
190 uint32_t lvt
= s
->lvt
[APIC_LVT_LINT0
];
192 switch ((lvt
>> 8) & 7) {
194 if (!(lvt
& APIC_LVT_LEVEL_TRIGGER
))
196 reset_bit(s
->irr
, lvt
& 0xff);
199 cpu_reset_interrupt(s
->cpu_env
, CPU_INTERRUPT_HARD
);
205 #define foreach_apic(apic, deliver_bitmask, code) \
207 int __i, __j, __mask;\
208 for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\
209 __mask = deliver_bitmask[__i];\
211 for(__j = 0; __j < 32; __j++) {\
212 if (__mask & (1 << __j)) {\
213 apic = local_apics[__i * 32 + __j];\
223 static void apic_bus_deliver(const uint32_t *deliver_bitmask
,
224 uint8_t delivery_mode
,
225 uint8_t vector_num
, uint8_t polarity
,
226 uint8_t trigger_mode
)
228 APICState
*apic_iter
;
230 switch (delivery_mode
) {
232 /* XXX: search for focus processor, arbitration */
236 for(i
= 0; i
< MAX_APIC_WORDS
; i
++) {
237 if (deliver_bitmask
[i
]) {
238 d
= i
* 32 + ffs_bit(deliver_bitmask
[i
]);
243 apic_iter
= local_apics
[d
];
245 apic_set_irq(apic_iter
, vector_num
, trigger_mode
);
255 foreach_apic(apic_iter
, deliver_bitmask
,
256 cpu_interrupt(apic_iter
->cpu_env
, CPU_INTERRUPT_SMI
) );
260 foreach_apic(apic_iter
, deliver_bitmask
,
261 cpu_interrupt(apic_iter
->cpu_env
, CPU_INTERRUPT_NMI
) );
265 /* normal INIT IPI sent to processors */
266 foreach_apic(apic_iter
, deliver_bitmask
,
267 cpu_interrupt(apic_iter
->cpu_env
, CPU_INTERRUPT_INIT
) );
271 /* handled in I/O APIC code */
278 foreach_apic(apic_iter
, deliver_bitmask
,
279 apic_set_irq(apic_iter
, vector_num
, trigger_mode
) );
282 void apic_deliver_irq(uint8_t dest
, uint8_t dest_mode
,
283 uint8_t delivery_mode
, uint8_t vector_num
,
284 uint8_t polarity
, uint8_t trigger_mode
)
286 uint32_t deliver_bitmask
[MAX_APIC_WORDS
];
288 trace_apic_deliver_irq(dest
, dest_mode
, delivery_mode
, vector_num
,
289 polarity
, trigger_mode
);
291 apic_get_delivery_bitmask(deliver_bitmask
, dest
, dest_mode
);
292 apic_bus_deliver(deliver_bitmask
, delivery_mode
, vector_num
, polarity
,
296 void cpu_set_apic_base(DeviceState
*d
, uint64_t val
)
298 APICState
*s
= DO_UPCAST(APICState
, busdev
.qdev
, d
);
300 trace_cpu_set_apic_base(val
);
304 if (kvm_enabled() && kvm_irqchip_in_kernel())
307 s
->apicbase
= (val
& 0xfffff000) |
308 (s
->apicbase
& (MSR_IA32_APICBASE_BSP
| MSR_IA32_APICBASE_ENABLE
));
309 /* if disabled, cannot be enabled again */
310 if (!(val
& MSR_IA32_APICBASE_ENABLE
)) {
311 s
->apicbase
&= ~MSR_IA32_APICBASE_ENABLE
;
312 cpu_clear_apic_feature(s
->cpu_env
);
313 s
->spurious_vec
&= ~APIC_SV_ENABLE
;
317 uint64_t cpu_get_apic_base(DeviceState
*d
)
319 APICState
*s
= DO_UPCAST(APICState
, busdev
.qdev
, d
);
321 trace_cpu_get_apic_base(s
? (uint64_t)s
->apicbase
: 0);
323 return s
? s
->apicbase
: 0;
326 void cpu_set_apic_tpr(DeviceState
*d
, uint8_t val
)
328 APICState
*s
= DO_UPCAST(APICState
, busdev
.qdev
, d
);
332 s
->tpr
= (val
& 0x0f) << 4;
336 uint8_t cpu_get_apic_tpr(DeviceState
*d
)
338 APICState
*s
= DO_UPCAST(APICState
, busdev
.qdev
, d
);
340 return s
? s
->tpr
>> 4 : 0;
343 /* return -1 if no bit is set */
344 static int get_highest_priority_int(uint32_t *tab
)
347 for(i
= 7; i
>= 0; i
--) {
349 return i
* 32 + fls_bit(tab
[i
]);
355 static int apic_get_ppr(APICState
*s
)
360 isrv
= get_highest_priority_int(s
->isr
);
371 static int apic_get_arb_pri(APICState
*s
)
373 /* XXX: arbitration */
377 /* signal the CPU if an irq is pending */
378 static void apic_update_irq(APICState
*s
)
381 if (!(s
->spurious_vec
& APIC_SV_ENABLE
))
383 irrv
= get_highest_priority_int(s
->irr
);
386 ppr
= apic_get_ppr(s
);
387 if (ppr
&& (irrv
& 0xf0) <= (ppr
& 0xf0))
389 cpu_interrupt(s
->cpu_env
, CPU_INTERRUPT_HARD
);
392 void apic_reset_irq_delivered(void)
394 trace_apic_reset_irq_delivered(apic_irq_delivered
);
396 apic_irq_delivered
= 0;
399 int apic_get_irq_delivered(void)
401 trace_apic_get_irq_delivered(apic_irq_delivered
);
403 return apic_irq_delivered
;
406 void apic_set_irq_delivered(void)
408 apic_irq_delivered
= 1;
411 static void apic_set_irq(APICState
*s
, int vector_num
, int trigger_mode
)
413 apic_irq_delivered
+= !get_bit(s
->irr
, vector_num
);
415 trace_apic_set_irq(apic_irq_delivered
);
417 set_bit(s
->irr
, vector_num
);
419 set_bit(s
->tmr
, vector_num
);
421 reset_bit(s
->tmr
, vector_num
);
425 static void apic_eoi(APICState
*s
)
428 isrv
= get_highest_priority_int(s
->isr
);
431 reset_bit(s
->isr
, isrv
);
432 /* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
433 set the remote IRR bit for level triggered interrupts. */
437 static int apic_find_dest(uint8_t dest
)
439 APICState
*apic
= local_apics
[dest
];
442 if (apic
&& apic
->id
== dest
)
443 return dest
; /* shortcut in case apic->id == apic->idx */
445 for (i
= 0; i
< MAX_APICS
; i
++) {
446 apic
= local_apics
[i
];
447 if (apic
&& apic
->id
== dest
)
456 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask
,
457 uint8_t dest
, uint8_t dest_mode
)
459 APICState
*apic_iter
;
462 if (dest_mode
== 0) {
464 memset(deliver_bitmask
, 0xff, MAX_APIC_WORDS
* sizeof(uint32_t));
466 int idx
= apic_find_dest(dest
);
467 memset(deliver_bitmask
, 0x00, MAX_APIC_WORDS
* sizeof(uint32_t));
469 set_bit(deliver_bitmask
, idx
);
472 /* XXX: cluster mode */
473 memset(deliver_bitmask
, 0x00, MAX_APIC_WORDS
* sizeof(uint32_t));
474 for(i
= 0; i
< MAX_APICS
; i
++) {
475 apic_iter
= local_apics
[i
];
477 if (apic_iter
->dest_mode
== 0xf) {
478 if (dest
& apic_iter
->log_dest
)
479 set_bit(deliver_bitmask
, i
);
480 } else if (apic_iter
->dest_mode
== 0x0) {
481 if ((dest
& 0xf0) == (apic_iter
->log_dest
& 0xf0) &&
482 (dest
& apic_iter
->log_dest
& 0x0f)) {
483 set_bit(deliver_bitmask
, i
);
493 void apic_init_reset(DeviceState
*d
)
495 APICState
*s
= DO_UPCAST(APICState
, busdev
.qdev
, d
);
502 s
->spurious_vec
= 0xff;
505 memset(s
->isr
, 0, sizeof(s
->isr
));
506 memset(s
->tmr
, 0, sizeof(s
->tmr
));
507 memset(s
->irr
, 0, sizeof(s
->irr
));
508 for(i
= 0; i
< APIC_LVT_NB
; i
++)
509 s
->lvt
[i
] = 1 << 16; /* mask LVT */
511 memset(s
->icr
, 0, sizeof(s
->icr
));
514 s
->initial_count
= 0;
515 s
->initial_count_load_time
= 0;
517 s
->wait_for_sipi
= 1;
520 static void apic_startup(APICState
*s
, int vector_num
)
522 s
->sipi_vector
= vector_num
;
523 cpu_interrupt(s
->cpu_env
, CPU_INTERRUPT_SIPI
);
526 void apic_sipi(DeviceState
*d
)
528 APICState
*s
= DO_UPCAST(APICState
, busdev
.qdev
, d
);
530 cpu_reset_interrupt(s
->cpu_env
, CPU_INTERRUPT_SIPI
);
532 if (!s
->wait_for_sipi
)
534 cpu_x86_load_seg_cache_sipi(s
->cpu_env
, s
->sipi_vector
);
535 s
->wait_for_sipi
= 0;
538 static void apic_deliver(DeviceState
*d
, uint8_t dest
, uint8_t dest_mode
,
539 uint8_t delivery_mode
, uint8_t vector_num
,
540 uint8_t polarity
, uint8_t trigger_mode
)
542 APICState
*s
= DO_UPCAST(APICState
, busdev
.qdev
, d
);
543 uint32_t deliver_bitmask
[MAX_APIC_WORDS
];
544 int dest_shorthand
= (s
->icr
[0] >> 18) & 3;
545 APICState
*apic_iter
;
547 switch (dest_shorthand
) {
549 apic_get_delivery_bitmask(deliver_bitmask
, dest
, dest_mode
);
552 memset(deliver_bitmask
, 0x00, sizeof(deliver_bitmask
));
553 set_bit(deliver_bitmask
, s
->idx
);
556 memset(deliver_bitmask
, 0xff, sizeof(deliver_bitmask
));
559 memset(deliver_bitmask
, 0xff, sizeof(deliver_bitmask
));
560 reset_bit(deliver_bitmask
, s
->idx
);
564 switch (delivery_mode
) {
567 int trig_mode
= (s
->icr
[0] >> 15) & 1;
568 int level
= (s
->icr
[0] >> 14) & 1;
569 if (level
== 0 && trig_mode
== 1) {
570 foreach_apic(apic_iter
, deliver_bitmask
,
571 apic_iter
->arb_id
= apic_iter
->id
);
578 foreach_apic(apic_iter
, deliver_bitmask
,
579 apic_startup(apic_iter
, vector_num
) );
583 apic_bus_deliver(deliver_bitmask
, delivery_mode
, vector_num
, polarity
,
587 int apic_get_interrupt(DeviceState
*d
)
589 APICState
*s
= DO_UPCAST(APICState
, busdev
.qdev
, d
);
592 /* if the APIC is installed or enabled, we let the 8259 handle the
596 if (!(s
->spurious_vec
& APIC_SV_ENABLE
))
599 /* XXX: spurious IRQ handling */
600 intno
= get_highest_priority_int(s
->irr
);
603 if (s
->tpr
&& intno
<= s
->tpr
)
604 return s
->spurious_vec
& 0xff;
605 reset_bit(s
->irr
, intno
);
606 set_bit(s
->isr
, intno
);
611 int apic_accept_pic_intr(DeviceState
*d
)
613 APICState
*s
= DO_UPCAST(APICState
, busdev
.qdev
, d
);
619 lvt0
= s
->lvt
[APIC_LVT_LINT0
];
621 if ((s
->apicbase
& MSR_IA32_APICBASE_ENABLE
) == 0 ||
622 (lvt0
& APIC_LVT_MASKED
) == 0)
628 static uint32_t apic_get_current_count(APICState
*s
)
632 d
= (qemu_get_clock(vm_clock
) - s
->initial_count_load_time
) >>
634 if (s
->lvt
[APIC_LVT_TIMER
] & APIC_LVT_TIMER_PERIODIC
) {
636 val
= s
->initial_count
- (d
% ((uint64_t)s
->initial_count
+ 1));
638 if (d
>= s
->initial_count
)
641 val
= s
->initial_count
- d
;
646 static void apic_timer_update(APICState
*s
, int64_t current_time
)
648 int64_t next_time
, d
;
650 if (!(s
->lvt
[APIC_LVT_TIMER
] & APIC_LVT_MASKED
)) {
651 d
= (current_time
- s
->initial_count_load_time
) >>
653 if (s
->lvt
[APIC_LVT_TIMER
] & APIC_LVT_TIMER_PERIODIC
) {
654 if (!s
->initial_count
)
656 d
= ((d
/ ((uint64_t)s
->initial_count
+ 1)) + 1) * ((uint64_t)s
->initial_count
+ 1);
658 if (d
>= s
->initial_count
)
660 d
= (uint64_t)s
->initial_count
+ 1;
662 next_time
= s
->initial_count_load_time
+ (d
<< s
->count_shift
);
663 qemu_mod_timer(s
->timer
, next_time
);
664 s
->next_time
= next_time
;
667 qemu_del_timer(s
->timer
);
671 static void apic_timer(void *opaque
)
673 APICState
*s
= opaque
;
675 apic_local_deliver(s
, APIC_LVT_TIMER
);
676 apic_timer_update(s
, s
->next_time
);
679 static uint32_t apic_mem_readb(void *opaque
, target_phys_addr_t addr
)
684 static uint32_t apic_mem_readw(void *opaque
, target_phys_addr_t addr
)
689 static void apic_mem_writeb(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
693 static void apic_mem_writew(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
697 static uint32_t apic_mem_readl(void *opaque
, target_phys_addr_t addr
)
704 d
= cpu_get_current_apic();
708 s
= DO_UPCAST(APICState
, busdev
.qdev
, d
);
710 index
= (addr
>> 4) & 0xff;
715 case 0x03: /* version */
716 val
= 0x11 | ((APIC_LVT_NB
- 1) << 16); /* version 0x11 */
722 val
= apic_get_arb_pri(s
);
726 val
= apic_get_ppr(s
);
732 val
= s
->log_dest
<< 24;
735 val
= s
->dest_mode
<< 28;
738 val
= s
->spurious_vec
;
741 val
= s
->isr
[index
& 7];
744 val
= s
->tmr
[index
& 7];
747 val
= s
->irr
[index
& 7];
754 val
= s
->icr
[index
& 1];
757 val
= s
->lvt
[index
- 0x32];
760 val
= s
->initial_count
;
763 val
= apic_get_current_count(s
);
766 val
= s
->divide_conf
;
769 s
->esr
|= ESR_ILLEGAL_ADDRESS
;
773 trace_apic_mem_readl(addr
, val
);
777 static void apic_send_msi(target_phys_addr_t addr
, uint32 data
)
779 uint8_t dest
= (addr
& MSI_ADDR_DEST_ID_MASK
) >> MSI_ADDR_DEST_ID_SHIFT
;
780 uint8_t vector
= (data
& MSI_DATA_VECTOR_MASK
) >> MSI_DATA_VECTOR_SHIFT
;
781 uint8_t dest_mode
= (addr
>> MSI_ADDR_DEST_MODE_SHIFT
) & 0x1;
782 uint8_t trigger_mode
= (data
>> MSI_DATA_TRIGGER_SHIFT
) & 0x1;
783 uint8_t delivery
= (data
>> MSI_DATA_DELIVERY_MODE_SHIFT
) & 0x7;
784 /* XXX: Ignore redirection hint. */
785 apic_deliver_irq(dest
, dest_mode
, delivery
, vector
, 0, trigger_mode
);
788 static void apic_mem_writel(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
792 int index
= (addr
>> 4) & 0xff;
793 if (addr
> 0xfff || !index
) {
794 /* MSI and MMIO APIC are at the same memory location,
795 * but actually not on the global bus: MSI is on PCI bus
796 * APIC is connected directly to the CPU.
797 * Mapping them on the global bus happens to work because
798 * MSI registers are reserved in APIC MMIO and vice versa. */
799 apic_send_msi(addr
, val
);
803 d
= cpu_get_current_apic();
807 s
= DO_UPCAST(APICState
, busdev
.qdev
, d
);
809 trace_apic_mem_writel(addr
, val
);
828 s
->log_dest
= val
>> 24;
831 s
->dest_mode
= val
>> 28;
834 s
->spurious_vec
= val
& 0x1ff;
844 apic_deliver(d
, (s
->icr
[1] >> 24) & 0xff, (s
->icr
[0] >> 11) & 1,
845 (s
->icr
[0] >> 8) & 7, (s
->icr
[0] & 0xff),
846 (s
->icr
[0] >> 14) & 1, (s
->icr
[0] >> 15) & 1);
853 int n
= index
- 0x32;
855 if (n
== APIC_LVT_TIMER
)
856 apic_timer_update(s
, qemu_get_clock(vm_clock
));
860 s
->initial_count
= val
;
861 s
->initial_count_load_time
= qemu_get_clock(vm_clock
);
862 apic_timer_update(s
, s
->initial_count_load_time
);
869 s
->divide_conf
= val
& 0xb;
870 v
= (s
->divide_conf
& 3) | ((s
->divide_conf
>> 1) & 4);
871 s
->count_shift
= (v
+ 1) & 7;
875 s
->esr
|= ESR_ILLEGAL_ADDRESS
;
880 #ifdef KVM_CAP_IRQCHIP
882 static inline uint32_t kapic_reg(struct kvm_lapic_state
*kapic
, int reg_id
)
884 return *((uint32_t *) (kapic
->regs
+ (reg_id
<< 4)));
887 static inline void kapic_set_reg(struct kvm_lapic_state
*kapic
,
888 int reg_id
, uint32_t val
)
890 *((uint32_t *) (kapic
->regs
+ (reg_id
<< 4))) = val
;
893 static void kvm_kernel_lapic_save_to_user(APICState
*s
)
895 struct kvm_lapic_state apic
;
896 struct kvm_lapic_state
*kapic
= &apic
;
899 kvm_get_lapic(s
->cpu_env
, kapic
);
901 s
->id
= kapic_reg(kapic
, 0x2) >> 24;
902 s
->tpr
= kapic_reg(kapic
, 0x8);
903 s
->arb_id
= kapic_reg(kapic
, 0x9);
904 s
->log_dest
= kapic_reg(kapic
, 0xd) >> 24;
905 s
->dest_mode
= kapic_reg(kapic
, 0xe) >> 28;
906 s
->spurious_vec
= kapic_reg(kapic
, 0xf);
907 for (i
= 0; i
< 8; i
++) {
908 s
->isr
[i
] = kapic_reg(kapic
, 0x10 + i
);
909 s
->tmr
[i
] = kapic_reg(kapic
, 0x18 + i
);
910 s
->irr
[i
] = kapic_reg(kapic
, 0x20 + i
);
912 s
->esr
= kapic_reg(kapic
, 0x28);
913 s
->icr
[0] = kapic_reg(kapic
, 0x30);
914 s
->icr
[1] = kapic_reg(kapic
, 0x31);
915 for (i
= 0; i
< APIC_LVT_NB
; i
++)
916 s
->lvt
[i
] = kapic_reg(kapic
, 0x32 + i
);
917 s
->initial_count
= kapic_reg(kapic
, 0x38);
918 s
->divide_conf
= kapic_reg(kapic
, 0x3e);
920 v
= (s
->divide_conf
& 3) | ((s
->divide_conf
>> 1) & 4);
921 s
->count_shift
= (v
+ 1) & 7;
923 s
->initial_count_load_time
= qemu_get_clock(vm_clock
);
924 apic_timer_update(s
, s
->initial_count_load_time
);
927 static void kvm_kernel_lapic_load_from_user(APICState
*s
)
929 struct kvm_lapic_state apic
;
930 struct kvm_lapic_state
*klapic
= &apic
;
933 memset(klapic
, 0, sizeof apic
);
934 kapic_set_reg(klapic
, 0x2, s
->id
<< 24);
935 kapic_set_reg(klapic
, 0x8, s
->tpr
);
936 kapic_set_reg(klapic
, 0xd, s
->log_dest
<< 24);
937 kapic_set_reg(klapic
, 0xe, s
->dest_mode
<< 28 | 0x0fffffff);
938 kapic_set_reg(klapic
, 0xf, s
->spurious_vec
);
939 for (i
= 0; i
< 8; i
++) {
940 kapic_set_reg(klapic
, 0x10 + i
, s
->isr
[i
]);
941 kapic_set_reg(klapic
, 0x18 + i
, s
->tmr
[i
]);
942 kapic_set_reg(klapic
, 0x20 + i
, s
->irr
[i
]);
944 kapic_set_reg(klapic
, 0x28, s
->esr
);
945 kapic_set_reg(klapic
, 0x30, s
->icr
[0]);
946 kapic_set_reg(klapic
, 0x31, s
->icr
[1]);
947 for (i
= 0; i
< APIC_LVT_NB
; i
++)
948 kapic_set_reg(klapic
, 0x32 + i
, s
->lvt
[i
]);
949 kapic_set_reg(klapic
, 0x38, s
->initial_count
);
950 kapic_set_reg(klapic
, 0x3e, s
->divide_conf
);
952 kvm_set_lapic(s
->cpu_env
, klapic
);
957 void kvm_load_lapic(CPUState
*env
)
959 #ifdef KVM_CAP_IRQCHIP
960 APICState
*s
= DO_UPCAST(APICState
, busdev
.qdev
, env
->apic_state
);
966 if (kvm_enabled() && kvm_irqchip_in_kernel()) {
967 kvm_kernel_lapic_load_from_user(s
);
972 void kvm_save_lapic(CPUState
*env
)
974 #ifdef KVM_CAP_IRQCHIP
975 APICState
*s
= DO_UPCAST(APICState
, busdev
.qdev
, env
->apic_state
);
981 if (kvm_enabled() && kvm_irqchip_in_kernel()) {
982 kvm_kernel_lapic_save_to_user(s
);
987 /* This function is only used for old state version 1 and 2 */
988 static int apic_load_old(QEMUFile
*f
, void *opaque
, int version_id
)
990 APICState
*s
= opaque
;
996 /* XXX: what if the base changes? (registered memory regions) */
997 qemu_get_be32s(f
, &s
->apicbase
);
998 qemu_get_8s(f
, &s
->id
);
999 qemu_get_8s(f
, &s
->arb_id
);
1000 qemu_get_8s(f
, &s
->tpr
);
1001 qemu_get_be32s(f
, &s
->spurious_vec
);
1002 qemu_get_8s(f
, &s
->log_dest
);
1003 qemu_get_8s(f
, &s
->dest_mode
);
1004 for (i
= 0; i
< 8; i
++) {
1005 qemu_get_be32s(f
, &s
->isr
[i
]);
1006 qemu_get_be32s(f
, &s
->tmr
[i
]);
1007 qemu_get_be32s(f
, &s
->irr
[i
]);
1009 for (i
= 0; i
< APIC_LVT_NB
; i
++) {
1010 qemu_get_be32s(f
, &s
->lvt
[i
]);
1012 qemu_get_be32s(f
, &s
->esr
);
1013 qemu_get_be32s(f
, &s
->icr
[0]);
1014 qemu_get_be32s(f
, &s
->icr
[1]);
1015 qemu_get_be32s(f
, &s
->divide_conf
);
1016 s
->count_shift
=qemu_get_be32(f
);
1017 qemu_get_be32s(f
, &s
->initial_count
);
1018 s
->initial_count_load_time
=qemu_get_be64(f
);
1019 s
->next_time
=qemu_get_be64(f
);
1021 if (version_id
>= 2)
1022 qemu_get_timer(f
, s
->timer
);
1026 static const VMStateDescription vmstate_apic
= {
1029 .minimum_version_id
= 3,
1030 .minimum_version_id_old
= 1,
1031 .load_state_old
= apic_load_old
,
1032 .fields
= (VMStateField
[]) {
1033 VMSTATE_UINT32(apicbase
, APICState
),
1034 VMSTATE_UINT8(id
, APICState
),
1035 VMSTATE_UINT8(arb_id
, APICState
),
1036 VMSTATE_UINT8(tpr
, APICState
),
1037 VMSTATE_UINT32(spurious_vec
, APICState
),
1038 VMSTATE_UINT8(log_dest
, APICState
),
1039 VMSTATE_UINT8(dest_mode
, APICState
),
1040 VMSTATE_UINT32_ARRAY(isr
, APICState
, 8),
1041 VMSTATE_UINT32_ARRAY(tmr
, APICState
, 8),
1042 VMSTATE_UINT32_ARRAY(irr
, APICState
, 8),
1043 VMSTATE_UINT32_ARRAY(lvt
, APICState
, APIC_LVT_NB
),
1044 VMSTATE_UINT32(esr
, APICState
),
1045 VMSTATE_UINT32_ARRAY(icr
, APICState
, 2),
1046 VMSTATE_UINT32(divide_conf
, APICState
),
1047 VMSTATE_INT32(count_shift
, APICState
),
1048 VMSTATE_UINT32(initial_count
, APICState
),
1049 VMSTATE_INT64(initial_count_load_time
, APICState
),
1050 VMSTATE_INT64(next_time
, APICState
),
1051 VMSTATE_TIMER(timer
, APICState
),
1052 VMSTATE_END_OF_LIST()
1056 static void apic_reset(DeviceState
*d
)
1058 APICState
*s
= DO_UPCAST(APICState
, busdev
.qdev
, d
);
1061 bsp
= cpu_is_bsp(s
->cpu_env
);
1062 s
->apicbase
= 0xfee00000 |
1063 (bsp
? MSR_IA32_APICBASE_BSP
: 0) | MSR_IA32_APICBASE_ENABLE
;
1069 * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization
1070 * time typically by BIOS, so PIC interrupt can be delivered to the
1071 * processor when local APIC is enabled.
1073 s
->lvt
[APIC_LVT_LINT0
] = 0x700;
1077 static CPUReadMemoryFunc
* const apic_mem_read
[3] = {
1083 static CPUWriteMemoryFunc
* const apic_mem_write
[3] = {
1089 static int apic_init1(SysBusDevice
*dev
)
1091 APICState
*s
= FROM_SYSBUS(APICState
, dev
);
1093 static int last_apic_idx
;
1095 if (last_apic_idx
>= MAX_APICS
) {
1098 apic_io_memory
= cpu_register_io_memory(apic_mem_read
,
1099 apic_mem_write
, NULL
);
1100 sysbus_init_mmio(dev
, MSI_ADDR_SIZE
, apic_io_memory
);
1102 s
->timer
= qemu_new_timer(vm_clock
, apic_timer
, s
);
1103 s
->idx
= last_apic_idx
++;
1104 local_apics
[s
->idx
] = s
;
1108 static SysBusDeviceInfo apic_info
= {
1110 .qdev
.name
= "apic",
1111 .qdev
.size
= sizeof(APICState
),
1112 .qdev
.vmsd
= &vmstate_apic
,
1113 .qdev
.reset
= apic_reset
,
1115 .qdev
.props
= (Property
[]) {
1116 DEFINE_PROP_UINT8("id", APICState
, id
, -1),
1117 DEFINE_PROP_PTR("cpu_env", APICState
, cpu_env
),
1118 DEFINE_PROP_END_OF_LIST(),
1122 static void apic_register_devices(void)
1124 sysbus_register_withprop(&apic_info
);
1127 device_init(apic_register_devices
)