hw/pci.c

   1 /*
   2  * QEMU PCI bus manager
   3  *
   4  * Copyright (c) 2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pci.h"
  26 #include "pci_bridge.h"
  27 #include "pci_internals.h"
  28 #include "msix.h"
  29 #include "msi.h"
  30 #include "monitor.h"
  31 #include "net.h"
  32 #include "sysemu.h"
  33 #include "loader.h"
  34 #include "qemu-kvm.h"
  35 #include "hw/pc.h"
  36 #include "device-assignment.h"
  37 #include "qemu-objects.h"
  38 #include "range.h"
  39
  40 //#define DEBUG_PCI
  41 #ifdef DEBUG_PCI
  42 # define PCI_DPRINTF(format, ...)       printf(format, ## __VA_ARGS__)
  43 #else
  44 # define PCI_DPRINTF(format, ...)       do { } while (0)
  45 #endif
  46
  47 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
  48 static char *pcibus_get_dev_path(DeviceState *dev);
  49
  50 struct BusInfo pci_bus_info = {
  51     .name       = "PCI",
  52     .size       = sizeof(PCIBus),
  53     .print_dev  = pcibus_dev_print,
  54     .get_dev_path = pcibus_get_dev_path,
  55     .props      = (Property[]) {
  56         DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
  57         DEFINE_PROP_STRING("romfile", PCIDevice, romfile),
  58         DEFINE_PROP_UINT32("rombar",  PCIDevice, rom_bar, 1),
  59         DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present,
  60                         QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false),
  61         DEFINE_PROP_END_OF_LIST()
  62     }
  63 };
  64
  65 static void pci_update_mappings(PCIDevice *d);
  66 static void pci_set_irq(void *opaque, int irq_num, int level);
  67 static int pci_add_option_rom(PCIDevice *pdev);
  68 static void pci_del_option_rom(PCIDevice *pdev);
  69
  70 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
  71 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
  72
  73 struct PCIHostBus {
  74     int domain;
  75     struct PCIBus *bus;
  76     QLIST_ENTRY(PCIHostBus) next;
  77 };
  78 static QLIST_HEAD(, PCIHostBus) host_buses;
  79
  80 static const VMStateDescription vmstate_pcibus = {
  81     .name = "PCIBUS",
  82     .version_id = 1,
  83     .minimum_version_id = 1,
  84     .minimum_version_id_old = 1,
  85     .fields      = (VMStateField []) {
  86         VMSTATE_INT32_EQUAL(nirq, PCIBus),
  87         VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t),
  88         VMSTATE_END_OF_LIST()
  89     }
  90 };
  91
  92 static int pci_bar(PCIDevice *d, int reg)
  93 {
  94     uint8_t type;
  95
  96     if (reg != PCI_ROM_SLOT)
  97         return PCI_BASE_ADDRESS_0 + reg * 4;
  98
  99     type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
 100     return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
 101 }
 102
 103 static inline int pci_irq_state(PCIDevice *d, int irq_num)
 104 {
 105         return (d->irq_state >> irq_num) & 0x1;
 106 }
 107
 108 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level)
 109 {
 110         d->irq_state &= ~(0x1 << irq_num);
 111         d->irq_state |= level << irq_num;
 112 }
 113
 114 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
 115 {
 116     PCIBus *bus;
 117     for (;;) {
 118         bus = pci_dev->bus;
 119         irq_num = bus->map_irq(pci_dev, irq_num);
 120         if (bus->set_irq)
 121             break;
 122         pci_dev = bus->parent_dev;
 123     }
 124     bus->irq_count[irq_num] += change;
 125     bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
 126 }
 127
 128 /* Update interrupt status bit in config space on interrupt
 129  * state change. */
 130 static void pci_update_irq_status(PCIDevice *dev)
 131 {
 132     if (dev->irq_state) {
 133         dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT;
 134     } else {
 135         dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
 136     }
 137 }
 138
 139 static void pci_device_reset(PCIDevice *dev)
 140 {
 141     int r;
 142
 143     dev->irq_state = 0;
 144     pci_update_irq_status(dev);
 145     /* Clear all writeable bits */
 146     pci_word_test_and_clear_mask(dev->config + PCI_COMMAND,
 147                                  pci_get_word(dev->wmask + PCI_COMMAND) |
 148                                  pci_get_word(dev->w1cmask + PCI_COMMAND));
 149     dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
 150     dev->config[PCI_INTERRUPT_LINE] = 0x0;
 151     for (r = 0; r < PCI_NUM_REGIONS; ++r) {
 152         PCIIORegion *region = &dev->io_regions[r];
 153         if (!region->size) {
 154             continue;
 155         }
 156
 157         if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) &&
 158             region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
 159             pci_set_quad(dev->config + pci_bar(dev, r), region->type);
 160         } else {
 161             pci_set_long(dev->config + pci_bar(dev, r), region->type);
 162         }
 163     }
 164     pci_update_mappings(dev);
 165 }
 166
 167 static void pci_bus_reset(void *opaque)
 168 {
 169     PCIBus *bus = opaque;
 170     int i;
 171
 172     for (i = 0; i < bus->nirq; i++) {
 173         bus->irq_count[i] = 0;
 174     }
 175     for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
 176         if (bus->devices[i]) {
 177             pci_device_reset(bus->devices[i]);
 178         }
 179     }
 180 }
 181
 182 static void pci_host_bus_register(int domain, PCIBus *bus)
 183 {
 184     struct PCIHostBus *host;
 185     host = qemu_mallocz(sizeof(*host));
 186     host->domain = domain;
 187     host->bus = bus;
 188     QLIST_INSERT_HEAD(&host_buses, host, next);
 189 }
 190
 191 PCIBus *pci_find_root_bus(int domain)
 192 {
 193     struct PCIHostBus *host;
 194
 195     QLIST_FOREACH(host, &host_buses, next) {
 196         if (host->domain == domain) {
 197             return host->bus;
 198         }
 199     }
 200
 201     return NULL;
 202 }
 203
 204 int pci_find_domain(const PCIBus *bus)
 205 {
 206     PCIDevice *d;
 207     struct PCIHostBus *host;
 208
 209     /* obtain root bus */
 210     while ((d = bus->parent_dev) != NULL) {
 211         bus = d->bus;
 212     }
 213
 214     QLIST_FOREACH(host, &host_buses, next) {
 215         if (host->bus == bus) {
 216             return host->domain;
 217         }
 218     }
 219
 220     abort();    /* should not be reached */
 221     return -1;
 222 }
 223
 224 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
 225                          const char *name, int devfn_min)
 226 {
 227     qbus_create_inplace(&bus->qbus, &pci_bus_info, parent, name);
 228     assert(PCI_FUNC(devfn_min) == 0);
 229     bus->devfn_min = devfn_min;
 230
 231     /* host bridge */
 232     QLIST_INIT(&bus->child);
 233     pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */
 234
 235     vmstate_register(NULL, -1, &vmstate_pcibus, bus);
 236     qemu_register_reset(pci_bus_reset, bus);
 237 }
 238
 239 PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min)
 240 {
 241     PCIBus *bus;
 242
 243     bus = qemu_mallocz(sizeof(*bus));
 244     bus->qbus.qdev_allocated = 1;
 245     pci_bus_new_inplace(bus, parent, name, devfn_min);
 246     return bus;
 247 }
 248
 249 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 250                   void *irq_opaque, int nirq)
 251 {
 252     bus->set_irq = set_irq;
 253     bus->map_irq = map_irq;
 254     bus->irq_opaque = irq_opaque;
 255     bus->nirq = nirq;
 256     bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0]));
 257 }
 258
 259 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *qdev)
 260 {
 261     bus->qbus.allow_hotplug = 1;
 262     bus->hotplug = hotplug;
 263     bus->hotplug_qdev = qdev;
 264 }
 265
 266 void pci_bus_set_mem_base(PCIBus *bus, target_phys_addr_t base)
 267 {
 268     bus->mem_base = base;
 269 }
 270
 271 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 272                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 273                          void *irq_opaque, int devfn_min, int nirq)
 274 {
 275     PCIBus *bus;
 276
 277     bus = pci_bus_new(parent, name, devfn_min);
 278     pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
 279     return bus;
 280 }
 281
 282 int pci_bus_num(PCIBus *s)
 283 {
 284     if (!s->parent_dev)
 285         return 0;       /* pci host bridge */
 286     return s->parent_dev->config[PCI_SECONDARY_BUS];
 287 }
 288
 289 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)
 290 {
 291     PCIDevice *s = container_of(pv, PCIDevice, config);
 292     uint8_t *config;
 293     int i;
 294
 295     assert(size == pci_config_size(s));
 296     config = qemu_malloc(size);
 297
 298     qemu_get_buffer(f, config, size);
 299     for (i = 0; i < size; ++i) {
 300         if ((config[i] ^ s->config[i]) &
 301             s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) {
 302             qemu_free(config);
 303             return -EINVAL;
 304         }
 305     }
 306     memcpy(s->config, config, size);
 307
 308     pci_update_mappings(s);
 309
 310     qemu_free(config);
 311     return 0;
 312 }
 313
 314 /* just put buffer */
 315 static void put_pci_config_device(QEMUFile *f, void *pv, size_t size)
 316 {
 317     const uint8_t **v = pv;
 318     assert(size == pci_config_size(container_of(pv, PCIDevice, config)));
 319     qemu_put_buffer(f, *v, size);
 320 }
 321
 322 static VMStateInfo vmstate_info_pci_config = {
 323     .name = "pci config",
 324     .get  = get_pci_config_device,
 325     .put  = put_pci_config_device,
 326 };
 327
 328 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size)
 329 {
 330     PCIDevice *s = container_of(pv, PCIDevice, irq_state);
 331     uint32_t irq_state[PCI_NUM_PINS];
 332     int i;
 333     for (i = 0; i < PCI_NUM_PINS; ++i) {
 334         irq_state[i] = qemu_get_be32(f);
 335         if (irq_state[i] != 0x1 && irq_state[i] != 0) {
 336             fprintf(stderr, "irq state %d: must be 0 or 1.\n",
 337                     irq_state[i]);
 338             return -EINVAL;
 339         }
 340     }
 341
 342     for (i = 0; i < PCI_NUM_PINS; ++i) {
 343         pci_set_irq_state(s, i, irq_state[i]);
 344     }
 345
 346     return 0;
 347 }
 348
 349 static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size)
 350 {
 351     int i;
 352     PCIDevice *s = container_of(pv, PCIDevice, irq_state);
 353
 354     for (i = 0; i < PCI_NUM_PINS; ++i) {
 355         qemu_put_be32(f, pci_irq_state(s, i));
 356     }
 357 }
 358
 359 static VMStateInfo vmstate_info_pci_irq_state = {
 360     .name = "pci irq state",
 361     .get  = get_pci_irq_state,
 362     .put  = put_pci_irq_state,
 363 };
 364
 365 const VMStateDescription vmstate_pci_device = {
 366     .name = "PCIDevice",
 367     .version_id = 2,
 368     .minimum_version_id = 1,
 369     .minimum_version_id_old = 1,
 370     .fields      = (VMStateField []) {
 371         VMSTATE_INT32_LE(version_id, PCIDevice),
 372         VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
 373                                    vmstate_info_pci_config,
 374                                    PCI_CONFIG_SPACE_SIZE),
 375         VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
 376                                    vmstate_info_pci_irq_state,
 377                                    PCI_NUM_PINS * sizeof(int32_t)),
 378         VMSTATE_END_OF_LIST()
 379     }
 380 };
 381
 382 const VMStateDescription vmstate_pcie_device = {
 383     .name = "PCIDevice",
 384     .version_id = 2,
 385     .minimum_version_id = 1,
 386     .minimum_version_id_old = 1,
 387     .fields      = (VMStateField []) {
 388         VMSTATE_INT32_LE(version_id, PCIDevice),
 389         VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
 390                                    vmstate_info_pci_config,
 391                                    PCIE_CONFIG_SPACE_SIZE),
 392         VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
 393                                    vmstate_info_pci_irq_state,
 394                                    PCI_NUM_PINS * sizeof(int32_t)),
 395         VMSTATE_END_OF_LIST()
 396     }
 397 };
 398
 399 static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s)
 400 {
 401     return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device;
 402 }
 403
 404 void pci_device_save(PCIDevice *s, QEMUFile *f)
 405 {
 406     /* Clear interrupt status bit: it is implicit
 407      * in irq_state which we are saving.
 408      * This makes us compatible with old devices
 409      * which never set or clear this bit. */
 410     s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
 411     vmstate_save_state(f, pci_get_vmstate(s), s);
 412     /* Restore the interrupt status bit. */
 413     pci_update_irq_status(s);
 414 }
 415
 416 int pci_device_load(PCIDevice *s, QEMUFile *f)
 417 {
 418     int ret;
 419     ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id);
 420     /* Restore the interrupt status bit. */
 421     pci_update_irq_status(s);
 422     return ret;
 423 }
 424
 425 static void pci_set_default_subsystem_id(PCIDevice *pci_dev)
 426 {
 427     pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
 428                  pci_default_sub_vendor_id);
 429     pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
 430                  pci_default_sub_device_id);
 431 }
 432
 433 /*
 434  * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
 435  *       [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
 436  */
 437 int pci_parse_devaddr(const char *addr, int *domp, int *busp,
 438                       unsigned int *slotp, unsigned int *funcp)
 439 {
 440     const char *p;
 441     char *e;
 442     unsigned long val;
 443     unsigned long dom = 0, bus = 0;
 444     unsigned int slot = 0;
 445     unsigned int func = 0;
 446
 447     p = addr;
 448     val = strtoul(p, &e, 16);
 449     if (e == p)
 450         return -1;
 451     if (*e == ':') {
 452         bus = val;
 453         p = e + 1;
 454         val = strtoul(p, &e, 16);
 455         if (e == p)
 456             return -1;
 457         if (*e == ':') {
 458             dom = bus;
 459             bus = val;
 460             p = e + 1;
 461             val = strtoul(p, &e, 16);
 462             if (e == p)
 463                 return -1;
 464         }
 465     }
 466
 467     slot = val;
 468
 469     if (funcp != NULL) {
 470         if (*e != '.')
 471             return -1;
 472
 473         p = e + 1;
 474         val = strtoul(p, &e, 16);
 475         if (e == p)
 476             return -1;
 477
 478         func = val;
 479     }
 480
 481     /* if funcp == NULL func is 0 */
 482     if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7)
 483         return -1;
 484
 485     if (*e)
 486         return -1;
 487
 488     /* Note: QEMU doesn't implement domains other than 0 */
 489     if (!pci_find_bus(pci_find_root_bus(dom), bus))
 490         return -1;
 491
 492     *domp = dom;
 493     *busp = bus;
 494     *slotp = slot;
 495     if (funcp != NULL)
 496         *funcp = func;
 497     return 0;
 498 }
 499
 500 /*
 501  * Parse device seg and bdf in device assignment command:
 502  *
 503  * -pcidevice host=[seg:]bus:dev.func
 504  *
 505  * Parse [seg:]<bus>:<slot>.<func> return -1 on error
 506  */
 507 int pci_parse_host_devaddr(const char *addr, int *segp, int *busp,
 508                            int *slotp, int *funcp)
 509 {
 510     const char *p;
 511     char *e;
 512     int val;
 513     int seg = 0, bus = 0, slot = 0, func = 0;
 514
 515     /* parse optional seg */
 516     p = addr;
 517     val = 0;
 518     while (1) {
 519         p = strchr(p, ':');
 520         if (p) {
 521             val++;
 522             p++;
 523         } else
 524             break;
 525     }
 526     if (val <= 0 || val > 2)
 527         return -1;
 528
 529     p = addr;
 530     if (val == 2) {
 531         val = strtoul(p, &e, 16);
 532         if (e == p)
 533             return -1;
 534         if (*e == ':') {
 535             seg = val;
 536             p = e + 1;
 537         }
 538     } else
 539         seg = 0;
 540
 541
 542     /* parse bdf */
 543     val = strtoul(p, &e, 16);
 544     if (e == p)
 545         return -1;
 546     if (*e == ':') {
 547         bus = val;
 548         p = e + 1;
 549         val = strtoul(p, &e, 16);
 550         if (e == p)
 551             return -1;
 552         if (*e == '.') {
 553             slot = val;
 554             p = e + 1;
 555             val = strtoul(p, &e, 16);
 556             if (e == p)
 557                 return -1;
 558             func = val;
 559         } else
 560             return -1;
 561     } else
 562         return -1;
 563
 564     if (seg > 0xffff || bus > 0xff || slot > 0x1f || func > 0x7)
 565         return -1;
 566
 567     if (*e)
 568         return -1;
 569
 570     *segp = seg;
 571     *busp = bus;
 572     *slotp = slot;
 573     *funcp = func;
 574     return 0;
 575 }
 576
 577 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
 578                      unsigned *slotp)
 579 {
 580     /* strip legacy tag */
 581     if (!strncmp(addr, "pci_addr=", 9)) {
 582         addr += 9;
 583     }
 584     if (pci_parse_devaddr(addr, domp, busp, slotp, NULL)) {
 585         monitor_printf(mon, "Invalid pci address\n");
 586         return -1;
 587     }
 588     return 0;
 589 }
 590
 591 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
 592 {
 593     int dom, bus;
 594     unsigned slot;
 595
 596     if (!devaddr) {
 597         *devfnp = -1;
 598         return pci_find_bus(pci_find_root_bus(0), 0);
 599     }
 600
 601     if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) {
 602         return NULL;
 603     }
 604
 605     *devfnp = slot << 3;
 606     return pci_find_bus(pci_find_root_bus(dom), bus);
 607 }
 608
 609 static void pci_init_cmask(PCIDevice *dev)
 610 {
 611     pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
 612     pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
 613     dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
 614     dev->cmask[PCI_REVISION_ID] = 0xff;
 615     dev->cmask[PCI_CLASS_PROG] = 0xff;
 616     pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
 617     dev->cmask[PCI_HEADER_TYPE] = 0xff;
 618     dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
 619 }
 620
 621 static void pci_init_wmask(PCIDevice *dev)
 622 {
 623     int config_size = pci_config_size(dev);
 624
 625     dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
 626     dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
 627     pci_set_word(dev->wmask + PCI_COMMAND,
 628                  PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
 629                  PCI_COMMAND_INTX_DISABLE);
 630
 631     memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
 632            config_size - PCI_CONFIG_HEADER_SIZE);
 633 }
 634
 635 static void pci_init_wmask_bridge(PCIDevice *d)
 636 {
 637     /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
 638        PCI_SEC_LETENCY_TIMER */
 639     memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);
 640
 641     /* base and limit */
 642     d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
 643     d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
 644     pci_set_word(d->wmask + PCI_MEMORY_BASE,
 645                  PCI_MEMORY_RANGE_MASK & 0xffff);
 646     pci_set_word(d->wmask + PCI_MEMORY_LIMIT,
 647                  PCI_MEMORY_RANGE_MASK & 0xffff);
 648     pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,
 649                  PCI_PREF_RANGE_MASK & 0xffff);
 650     pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,
 651                  PCI_PREF_RANGE_MASK & 0xffff);
 652
 653     /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
 654     memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
 655
 656     pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 0xffff);
 657 }
 658
 659 static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev)
 660 {
 661     uint8_t slot = PCI_SLOT(dev->devfn);
 662     uint8_t func;
 663
 664     if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
 665         dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION;
 666     }
 667
 668     /*
 669      * multifunction bit is interpreted in two ways as follows.
 670      *   - all functions must set the bit to 1.
 671      *     Example: Intel X53
 672      *   - function 0 must set the bit, but the rest function (> 0)
 673      *     is allowed to leave the bit to 0.
 674      *     Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
 675      *
 676      * So OS (at least Linux) checks the bit of only function 0,
 677      * and doesn't see the bit of function > 0.
 678      *
 679      * The below check allows both interpretation.
 680      */
 681     if (PCI_FUNC(dev->devfn)) {
 682         PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)];
 683         if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) {
 684             /* function 0 should set multifunction bit */
 685             error_report("PCI: single function device can't be populated "
 686                          "in function %x.%x", slot, PCI_FUNC(dev->devfn));
 687             return -1;
 688         }
 689         return 0;
 690     }
 691
 692     if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
 693         return 0;
 694     }
 695     /* function 0 indicates single function, so function > 0 must be NULL */
 696     for (func = 1; func < PCI_FUNC_MAX; ++func) {
 697         if (bus->devices[PCI_DEVFN(slot, func)]) {
 698             error_report("PCI: %x.0 indicates single function, "
 699                          "but %x.%x is already populated.",
 700                          slot, slot, func);
 701             return -1;
 702         }
 703     }
 704     return 0;
 705 }
 706
 707 static void pci_config_alloc(PCIDevice *pci_dev)
 708 {
 709     int config_size = pci_config_size(pci_dev);
 710
 711     pci_dev->config = qemu_mallocz(config_size);
 712     pci_dev->cmask = qemu_mallocz(config_size);
 713     pci_dev->wmask = qemu_mallocz(config_size);
 714     pci_dev->w1cmask = qemu_mallocz(config_size);
 715     pci_dev->config_map = qemu_mallocz(config_size);
 716 }
 717
 718 static void pci_config_free(PCIDevice *pci_dev)
 719 {
 720     qemu_free(pci_dev->config);
 721     qemu_free(pci_dev->cmask);
 722     qemu_free(pci_dev->wmask);
 723     qemu_free(pci_dev->w1cmask);
 724     qemu_free(pci_dev->config_map);
 725 }
 726
 727 /* -1 for devfn means auto assign */
 728 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
 729                                          const char *name, int devfn,
 730                                          PCIConfigReadFunc *config_read,
 731                                          PCIConfigWriteFunc *config_write,
 732                                          bool is_bridge)
 733 {
 734     if (devfn < 0) {
 735         for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
 736             devfn += PCI_FUNC_MAX) {
 737             if (!bus->devices[devfn])
 738                 goto found;
 739         }
 740         error_report("PCI: no slot/function available for %s, all in use", name);
 741         return NULL;
 742     found: ;
 743     } else if (bus->devices[devfn]) {
 744         error_report("PCI: slot %d function %d not available for %s, in use by %s",
 745                      PCI_SLOT(devfn), PCI_FUNC(devfn), name, bus->devices[devfn]->name);
 746         return NULL;
 747     }
 748     pci_dev->bus = bus;
 749     pci_dev->devfn = devfn;
 750     pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
 751     pci_dev->irq_state = 0;
 752     pci_config_alloc(pci_dev);
 753
 754     memset(pci_dev->config_map, 0xff, PCI_CONFIG_HEADER_SIZE);
 755
 756     if (!is_bridge) {
 757         pci_set_default_subsystem_id(pci_dev);
 758     }
 759     pci_init_cmask(pci_dev);
 760     pci_init_wmask(pci_dev);
 761     if (is_bridge) {
 762         pci_init_wmask_bridge(pci_dev);
 763     }
 764     if (pci_init_multifunction(bus, pci_dev)) {
 765         pci_config_free(pci_dev);
 766         return NULL;
 767     }
 768
 769     if (!config_read)
 770         config_read = pci_default_read_config;
 771     if (!config_write)
 772         config_write = pci_default_write_config;
 773     pci_dev->config_read = config_read;
 774     pci_dev->config_write = config_write;
 775     bus->devices[devfn] = pci_dev;
 776     pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS);
 777     pci_dev->version_id = 2; /* Current pci device vmstate version */
 778     return pci_dev;
 779 }
 780
 781 static void do_pci_unregister_device(PCIDevice *pci_dev)
 782 {
 783     qemu_free_irqs(pci_dev->irq);
 784     pci_dev->bus->devices[pci_dev->devfn] = NULL;
 785     pci_config_free(pci_dev);
 786 }
 787
 788 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 789                                int instance_size, int devfn,
 790                                PCIConfigReadFunc *config_read,
 791                                PCIConfigWriteFunc *config_write)
 792 {
 793     PCIDevice *pci_dev;
 794
 795     pci_dev = qemu_mallocz(instance_size);
 796     pci_dev = do_pci_register_device(pci_dev, bus, name, devfn,
 797                                      config_read, config_write,
 798                                      PCI_HEADER_TYPE_NORMAL);
 799     if (pci_dev == NULL) {
 800         hw_error("PCI: can't register device\n");
 801     }
 802     return pci_dev;
 803 }
 804
 805 static target_phys_addr_t pci_to_cpu_addr(PCIBus *bus,
 806                                           target_phys_addr_t addr)
 807 {
 808     return addr + bus->mem_base;
 809 }
 810
 811 static void pci_unregister_io_regions(PCIDevice *pci_dev)
 812 {
 813     PCIIORegion *r;
 814     int i;
 815
 816     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 817         r = &pci_dev->io_regions[i];
 818         if (!r->size || r->addr == PCI_BAR_UNMAPPED)
 819             continue;
 820         if (r->type == PCI_BASE_ADDRESS_SPACE_IO) {
 821             isa_unassign_ioport(r->addr, r->filtered_size);
 822         } else {
 823             cpu_register_physical_memory(pci_to_cpu_addr(pci_dev->bus,
 824                                                          r->addr),
 825                                          r->filtered_size,
 826                                          IO_MEM_UNASSIGNED);
 827         }
 828     }
 829 }
 830
 831 static int pci_unregister_device(DeviceState *dev)
 832 {
 833     PCIDevice *pci_dev = DO_UPCAST(PCIDevice, qdev, dev);
 834     PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, dev->info);
 835     int ret = 0;
 836
 837     if (info->exit)
 838         ret = info->exit(pci_dev);
 839     if (ret)
 840         return ret;
 841
 842     pci_unregister_io_regions(pci_dev);
 843     pci_del_option_rom(pci_dev);
 844     do_pci_unregister_device(pci_dev);
 845     return 0;
 846 }
 847
 848 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 849                             pcibus_t size, uint8_t type,
 850                             PCIMapIORegionFunc *map_func)
 851 {
 852     PCIIORegion *r;
 853     uint32_t addr;
 854     uint64_t wmask;
 855
 856     assert(region_num >= 0);
 857     assert(region_num < PCI_NUM_REGIONS);
 858     if (size & (size-1)) {
 859         fprintf(stderr, "ERROR: PCI region size must be pow2 "
 860                     "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);
 861         exit(1);
 862     }
 863
 864     r = &pci_dev->io_regions[region_num];
 865     r->addr = PCI_BAR_UNMAPPED;
 866     r->size = size;
 867     r->filtered_size = size;
 868     r->type = type;
 869     r->map_func = map_func;
 870
 871     wmask = ~(size - 1);
 872     addr = pci_bar(pci_dev, region_num);
 873     if (region_num == PCI_ROM_SLOT) {
 874         /* ROM enable bit is writeable */
 875         wmask |= PCI_ROM_ADDRESS_ENABLE;
 876     }
 877     pci_set_long(pci_dev->config + addr, type);
 878     if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
 879         r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
 880         pci_set_quad(pci_dev->wmask + addr, wmask);
 881         pci_set_quad(pci_dev->cmask + addr, ~0ULL);
 882     } else {
 883         pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
 884         pci_set_long(pci_dev->cmask + addr, 0xffffffff);
 885     }
 886 }
 887
 888 static void pci_bridge_filter(PCIDevice *d, pcibus_t *addr, pcibus_t *size,
 889                               uint8_t type)
 890 {
 891     pcibus_t base = *addr;
 892     pcibus_t limit = *addr + *size - 1;
 893     PCIDevice *br;
 894
 895     for (br = d->bus->parent_dev; br; br = br->bus->parent_dev) {
 896         uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
 897
 898         if (type & PCI_BASE_ADDRESS_SPACE_IO) {
 899             if (!(cmd & PCI_COMMAND_IO)) {
 900                 goto no_map;
 901             }
 902         } else {
 903             if (!(cmd & PCI_COMMAND_MEMORY)) {
 904                 goto no_map;
 905             }
 906         }
 907
 908         base = MAX(base, pci_bridge_get_base(br, type));
 909         limit = MIN(limit, pci_bridge_get_limit(br, type));
 910     }
 911
 912     if (base > limit) {
 913         goto no_map;
 914     }
 915     *addr = base;
 916     *size = limit - base + 1;
 917     return;
 918 no_map:
 919     *addr = PCI_BAR_UNMAPPED;
 920     *size = 0;
 921 }
 922
 923 static pcibus_t pci_bar_address(PCIDevice *d,
 924                                 int reg, uint8_t type, pcibus_t size)
 925 {
 926     pcibus_t new_addr, last_addr;
 927     int bar = pci_bar(d, reg);
 928     uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
 929
 930     if (type & PCI_BASE_ADDRESS_SPACE_IO) {
 931         if (!(cmd & PCI_COMMAND_IO)) {
 932             return PCI_BAR_UNMAPPED;
 933         }
 934         new_addr = pci_get_long(d->config + bar) & ~(size - 1);
 935         last_addr = new_addr + size - 1;
 936         /* NOTE: we have only 64K ioports on PC */
 937         if (last_addr <= new_addr || new_addr == 0 || last_addr > UINT16_MAX) {
 938             return PCI_BAR_UNMAPPED;
 939         }
 940         return new_addr;
 941     }
 942
 943     if (!(cmd & PCI_COMMAND_MEMORY)) {
 944         return PCI_BAR_UNMAPPED;
 945     }
 946     if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
 947         new_addr = pci_get_quad(d->config + bar);
 948     } else {
 949         new_addr = pci_get_long(d->config + bar);
 950     }
 951     /* the ROM slot has a specific enable bit */
 952     if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
 953         return PCI_BAR_UNMAPPED;
 954     }
 955     new_addr &= ~(size - 1);
 956     last_addr = new_addr + size - 1;
 957     /* NOTE: we do not support wrapping */
 958     /* XXX: as we cannot support really dynamic
 959        mappings, we handle specific values as invalid
 960        mappings. */
 961     if (last_addr <= new_addr || new_addr == 0 ||
 962         last_addr == PCI_BAR_UNMAPPED) {
 963         return PCI_BAR_UNMAPPED;
 964     }
 965
 966     /* Now pcibus_t is 64bit.
 967      * Check if 32 bit BAR wraps around explicitly.
 968      * Without this, PC ide doesn't work well.
 969      * TODO: remove this work around.
 970      */
 971     if  (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
 972         return PCI_BAR_UNMAPPED;
 973     }
 974
 975     /*
 976      * OS is allowed to set BAR beyond its addressable
 977      * bits. For example, 32 bit OS can set 64bit bar
 978      * to >4G. Check it. TODO: we might need to support
 979      * it in the future for e.g. PAE.
 980      */
 981     if (last_addr >= TARGET_PHYS_ADDR_MAX) {
 982         return PCI_BAR_UNMAPPED;
 983     }
 984
 985     return new_addr;
 986 }
 987
 988 static void pci_update_mappings(PCIDevice *d)
 989 {
 990     PCIIORegion *r;
 991     int i;
 992     pcibus_t new_addr, filtered_size;
 993
 994     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 995         r = &d->io_regions[i];
 996
 997         /* this region isn't registered */
 998         if (!r->size)
 999             continue;
1000
1001         new_addr = pci_bar_address(d, i, r->type, r->size);
1002
1003         /* bridge filtering */
1004         filtered_size = r->size;
1005         if (new_addr != PCI_BAR_UNMAPPED) {
1006             pci_bridge_filter(d, &new_addr, &filtered_size, r->type);
1007         }
1008
1009         /* This bar isn't changed */
1010         if (new_addr == r->addr && filtered_size == r->filtered_size)
1011             continue;
1012
1013         /* now do the real mapping */
1014         if (r->addr != PCI_BAR_UNMAPPED) {
1015             if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1016                 int class;
1017                 /* NOTE: specific hack for IDE in PC case:
1018                    only one byte must be mapped. */
1019                 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
1020                 if (class == 0x0101 && r->size == 4) {
1021                     isa_unassign_ioport(r->addr + 2, 1);
1022                 } else {
1023                     isa_unassign_ioport(r->addr, r->filtered_size);
1024                 }
1025             } else {
1026                 cpu_register_physical_memory(pci_to_cpu_addr(d->bus, r->addr),
1027                                              r->filtered_size,
1028                                              IO_MEM_UNASSIGNED);
1029                 qemu_unregister_coalesced_mmio(r->addr, r->filtered_size);
1030             }
1031         }
1032         r->addr = new_addr;
1033         r->filtered_size = filtered_size;
1034         if (r->addr != PCI_BAR_UNMAPPED) {
1035             /*
1036              * TODO: currently almost all the map funcions assumes
1037              * filtered_size == size and addr & ~(size - 1) == addr.
1038              * However with bridge filtering, they aren't always true.
1039              * Teach them such cases, such that filtered_size < size and
1040              * addr & (size - 1) != 0.
1041              */
1042             if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1043                 r->map_func(d, i, r->addr, r->filtered_size, r->type);
1044             } else {
1045                 r->map_func(d, i, pci_to_cpu_addr(d->bus, r->addr),
1046                             r->filtered_size, r->type);
1047             }
1048         }
1049     }
1050 }
1051
1052 static inline int pci_irq_disabled(PCIDevice *d)
1053 {
1054     return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE;
1055 }
1056
1057 /* Called after interrupt disabled field update in config space,
1058  * assert/deassert interrupts if necessary.
1059  * Gets original interrupt disable bit value (before update). */
1060 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled)
1061 {
1062     int i, disabled = pci_irq_disabled(d);
1063     if (disabled == was_irq_disabled)
1064         return;
1065     for (i = 0; i < PCI_NUM_PINS; ++i) {
1066         int state = pci_irq_state(d, i);
1067         pci_change_irq_level(d, i, disabled ? -state : state);
1068     }
1069 }
1070
1071 uint32_t pci_default_read_config(PCIDevice *d,
1072                                  uint32_t address, int len)
1073 {
1074     uint32_t val = 0;
1075     assert(len == 1 || len == 2 || len == 4);
1076     len = MIN(len, pci_config_size(d) - address);
1077     memcpy(&val, d->config + address, len);
1078     return le32_to_cpu(val);
1079 }
1080
1081 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
1082 {
1083     int i, was_irq_disabled = pci_irq_disabled(d);
1084     uint32_t config_size = pci_config_size(d);
1085
1086     for (i = 0; i < l && addr + i < config_size; val >>= 8, ++i) {
1087         uint8_t wmask = d->wmask[addr + i];
1088         uint8_t w1cmask = d->w1cmask[addr + i];
1089         assert(!(wmask & w1cmask));
1090         d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
1091         d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */
1092     }
1093
1094 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
1095     if (kvm_enabled() && kvm_irqchip_in_kernel() &&
1096         addr >= PIIX_CONFIG_IRQ_ROUTE &&
1097         addr < PIIX_CONFIG_IRQ_ROUTE + 4)
1098         assigned_dev_update_irqs();
1099 #endif /* CONFIG_KVM_DEVICE_ASSIGNMENT */
1100
1101     if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
1102         ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
1103         ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
1104         range_covers_byte(addr, l, PCI_COMMAND))
1105         pci_update_mappings(d);
1106
1107     if (range_covers_byte(addr, l, PCI_COMMAND))
1108         pci_update_irq_disabled(d, was_irq_disabled);
1109 }
1110
1111 /***********************************************************/
1112 /* generic PCI irq support */
1113
1114 /* 0 <= irq_num <= 3. level must be 0 or 1 */
1115 static void pci_set_irq(void *opaque, int irq_num, int level)
1116 {
1117     PCIDevice *pci_dev = opaque;
1118     int change;
1119
1120     change = level - pci_irq_state(pci_dev, irq_num);
1121     if (!change)
1122         return;
1123
1124 #if defined(TARGET_IA64)
1125     ioapic_set_irq(pci_dev, irq_num, level);
1126 #endif
1127
1128     pci_set_irq_state(pci_dev, irq_num, level);
1129     pci_update_irq_status(pci_dev);
1130     if (pci_irq_disabled(pci_dev))
1131         return;
1132     pci_change_irq_level(pci_dev, irq_num, change);
1133 }
1134
1135 bool pci_msi_enabled(PCIDevice *dev)
1136 {
1137     return msix_enabled(dev) || msi_enabled(dev);
1138 }
1139
1140 void pci_msi_notify(PCIDevice *dev, unsigned int vector)
1141 {
1142     if (msix_enabled(dev)) {
1143         msix_notify(dev, vector);
1144     } else if (msi_enabled(dev)) {
1145         msi_notify(dev, vector);
1146     } else {
1147         /* MSI/MSI-X must be enabled */
1148         abort();
1149     }
1150 }
1151
1152 int pci_map_irq(PCIDevice *pci_dev, int pin)
1153 {
1154     return pci_dev->bus->map_irq(pci_dev, pin);
1155 }
1156
1157 /***********************************************************/
1158 /* monitor info on PCI */
1159
1160 typedef struct {
1161     uint16_t class;
1162     const char *desc;
1163 } pci_class_desc;
1164
1165 static const pci_class_desc pci_class_descriptions[] =
1166 {
1167     { 0x0100, "SCSI controller"},
1168     { 0x0101, "IDE controller"},
1169     { 0x0102, "Floppy controller"},
1170     { 0x0103, "IPI controller"},
1171     { 0x0104, "RAID controller"},
1172     { 0x0106, "SATA controller"},
1173     { 0x0107, "SAS controller"},
1174     { 0x0180, "Storage controller"},
1175     { 0x0200, "Ethernet controller"},
1176     { 0x0201, "Token Ring controller"},
1177     { 0x0202, "FDDI controller"},
1178     { 0x0203, "ATM controller"},
1179     { 0x0280, "Network controller"},
1180     { 0x0300, "VGA controller"},
1181     { 0x0301, "XGA controller"},
1182     { 0x0302, "3D controller"},
1183     { 0x0380, "Display controller"},
1184     { 0x0400, "Video controller"},
1185     { 0x0401, "Audio controller"},
1186     { 0x0402, "Phone"},
1187     { 0x0480, "Multimedia controller"},
1188     { 0x0500, "RAM controller"},
1189     { 0x0501, "Flash controller"},
1190     { 0x0580, "Memory controller"},
1191     { 0x0600, "Host bridge"},
1192     { 0x0601, "ISA bridge"},
1193     { 0x0602, "EISA bridge"},
1194     { 0x0603, "MC bridge"},
1195     { 0x0604, "PCI bridge"},
1196     { 0x0605, "PCMCIA bridge"},
1197     { 0x0606, "NUBUS bridge"},
1198     { 0x0607, "CARDBUS bridge"},
1199     { 0x0608, "RACEWAY bridge"},
1200     { 0x0680, "Bridge"},
1201     { 0x0c03, "USB controller"},
1202     { 0, NULL}
1203 };
1204
1205 static void pci_for_each_device_under_bus(PCIBus *bus,
1206                                           void (*fn)(PCIBus *b, PCIDevice *d))
1207 {
1208     PCIDevice *d;
1209     int devfn;
1210
1211     for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1212         d = bus->devices[devfn];
1213         if (d) {
1214             fn(bus, d);
1215         }
1216     }
1217 }
1218
1219 void pci_for_each_device(PCIBus *bus, int bus_num,
1220                          void (*fn)(PCIBus *b, PCIDevice *d))
1221 {
1222     bus = pci_find_bus(bus, bus_num);
1223
1224     if (bus) {
1225         pci_for_each_device_under_bus(bus, fn);
1226     }
1227 }
1228
1229 static void pci_device_print(Monitor *mon, QDict *device)
1230 {
1231     QDict *qdict;
1232     QListEntry *entry;
1233     uint64_t addr, size;
1234
1235     monitor_printf(mon, "  Bus %2" PRId64 ", ", qdict_get_int(device, "bus"));
1236     monitor_printf(mon, "device %3" PRId64 ", function %" PRId64 ":\n",
1237                         qdict_get_int(device, "slot"),
1238                         qdict_get_int(device, "function"));
1239     monitor_printf(mon, "    ");
1240
1241     qdict = qdict_get_qdict(device, "class_info");
1242     if (qdict_haskey(qdict, "desc")) {
1243         monitor_printf(mon, "%s", qdict_get_str(qdict, "desc"));
1244     } else {
1245         monitor_printf(mon, "Class %04" PRId64, qdict_get_int(qdict, "class"));
1246     }
1247
1248     qdict = qdict_get_qdict(device, "id");
1249     monitor_printf(mon, ": PCI device %04" PRIx64 ":%04" PRIx64 "\n",
1250                         qdict_get_int(qdict, "device"),
1251                         qdict_get_int(qdict, "vendor"));
1252
1253     if (qdict_haskey(device, "irq")) {
1254         monitor_printf(mon, "      IRQ %" PRId64 ".\n",
1255                             qdict_get_int(device, "irq"));
1256     }
1257
1258     if (qdict_haskey(device, "pci_bridge")) {
1259         QDict *info;
1260
1261         qdict = qdict_get_qdict(device, "pci_bridge");
1262
1263         info = qdict_get_qdict(qdict, "bus");
1264         monitor_printf(mon, "      BUS %" PRId64 ".\n",
1265                             qdict_get_int(info, "number"));
1266         monitor_printf(mon, "      secondary bus %" PRId64 ".\n",
1267                             qdict_get_int(info, "secondary"));
1268         monitor_printf(mon, "      subordinate bus %" PRId64 ".\n",
1269                             qdict_get_int(info, "subordinate"));
1270
1271         info = qdict_get_qdict(qdict, "io_range");
1272         monitor_printf(mon, "      IO range [0x%04"PRIx64", 0x%04"PRIx64"]\n",
1273                        qdict_get_int(info, "base"),
1274                        qdict_get_int(info, "limit"));
1275
1276         info = qdict_get_qdict(qdict, "memory_range");
1277         monitor_printf(mon,
1278                        "      memory range [0x%08"PRIx64", 0x%08"PRIx64"]\n",
1279                        qdict_get_int(info, "base"),
1280                        qdict_get_int(info, "limit"));
1281
1282         info = qdict_get_qdict(qdict, "prefetchable_range");
1283         monitor_printf(mon, "      prefetchable memory range "
1284                        "[0x%08"PRIx64", 0x%08"PRIx64"]\n",
1285                        qdict_get_int(info, "base"),
1286         qdict_get_int(info, "limit"));
1287     }
1288
1289     QLIST_FOREACH_ENTRY(qdict_get_qlist(device, "regions"), entry) {
1290         qdict = qobject_to_qdict(qlist_entry_obj(entry));
1291         monitor_printf(mon, "      BAR%d: ", (int) qdict_get_int(qdict, "bar"));
1292
1293         addr = qdict_get_int(qdict, "address");
1294         size = qdict_get_int(qdict, "size");
1295
1296         if (!strcmp(qdict_get_str(qdict, "type"), "io")) {
1297             monitor_printf(mon, "I/O at 0x%04"FMT_PCIBUS
1298                                 " [0x%04"FMT_PCIBUS"].\n",
1299                                 addr, addr + size - 1);
1300         } else {
1301             monitor_printf(mon, "%d bit%s memory at 0x%08"FMT_PCIBUS
1302                                " [0x%08"FMT_PCIBUS"].\n",
1303                                 qdict_get_bool(qdict, "mem_type_64") ? 64 : 32,
1304                                 qdict_get_bool(qdict, "prefetch") ?
1305                                 " prefetchable" : "", addr, addr + size - 1);
1306         }
1307     }
1308
1309     monitor_printf(mon, "      id \"%s\"\n", qdict_get_str(device, "qdev_id"));
1310
1311     if (qdict_haskey(device, "pci_bridge")) {
1312         qdict = qdict_get_qdict(device, "pci_bridge");
1313         if (qdict_haskey(qdict, "devices")) {
1314             QListEntry *dev;
1315             QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) {
1316                 pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev)));
1317             }
1318         }
1319     }
1320 }
1321
1322 void do_pci_info_print(Monitor *mon, const QObject *data)
1323 {
1324     QListEntry *bus, *dev;
1325
1326     QLIST_FOREACH_ENTRY(qobject_to_qlist(data), bus) {
1327         QDict *qdict = qobject_to_qdict(qlist_entry_obj(bus));
1328         QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) {
1329             pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev)));
1330         }
1331     }
1332 }
1333
1334 static QObject *pci_get_dev_class(const PCIDevice *dev)
1335 {
1336     int class;
1337     const pci_class_desc *desc;
1338
1339     class = pci_get_word(dev->config + PCI_CLASS_DEVICE);
1340     desc = pci_class_descriptions;
1341     while (desc->desc && class != desc->class)
1342         desc++;
1343
1344     if (desc->desc) {
1345         return qobject_from_jsonf("{ 'desc': %s, 'class': %d }",
1346                                   desc->desc, class);
1347     } else {
1348         return qobject_from_jsonf("{ 'class': %d }", class);
1349     }
1350 }
1351
1352 static QObject *pci_get_dev_id(const PCIDevice *dev)
1353 {
1354     return qobject_from_jsonf("{ 'device': %d, 'vendor': %d }",
1355                               pci_get_word(dev->config + PCI_VENDOR_ID),
1356                               pci_get_word(dev->config + PCI_DEVICE_ID));
1357 }
1358
1359 static QObject *pci_get_regions_list(const PCIDevice *dev)
1360 {
1361     int i;
1362     QList *regions_list;
1363
1364     regions_list = qlist_new();
1365
1366     for (i = 0; i < PCI_NUM_REGIONS; i++) {
1367         QObject *obj;
1368         const PCIIORegion *r = &dev->io_regions[i];
1369
1370         if (!r->size) {
1371             continue;
1372         }
1373
1374         if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1375             obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'io', "
1376                                      "'address': %" PRId64 ", "
1377                                      "'size': %" PRId64 " }",
1378                                      i, r->addr, r->size);
1379         } else {
1380             int mem_type_64 = r->type & PCI_BASE_ADDRESS_MEM_TYPE_64;
1381
1382             obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'memory', "
1383                                      "'mem_type_64': %i, 'prefetch': %i, "
1384                                      "'address': %" PRId64 ", "
1385                                      "'size': %" PRId64 " }",
1386                                      i, mem_type_64,
1387                                      r->type & PCI_BASE_ADDRESS_MEM_PREFETCH,
1388                                      r->addr, r->size);
1389         }
1390
1391         qlist_append_obj(regions_list, obj);
1392     }
1393
1394     return QOBJECT(regions_list);
1395 }
1396
1397 static QObject *pci_get_devices_list(PCIBus *bus, int bus_num);
1398
1399 static QObject *pci_get_dev_dict(PCIDevice *dev, PCIBus *bus, int bus_num)
1400 {
1401     uint8_t type;
1402     QObject *obj;
1403
1404     obj = qobject_from_jsonf("{ 'bus': %d, 'slot': %d, 'function': %d,"                                       "'class_info': %p, 'id': %p, 'regions': %p,"
1405                               " 'qdev_id': %s }",
1406                               bus_num,
1407                               PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
1408                               pci_get_dev_class(dev), pci_get_dev_id(dev),
1409                               pci_get_regions_list(dev),
1410                               dev->qdev.id ? dev->qdev.id : "");
1411
1412     if (dev->config[PCI_INTERRUPT_PIN] != 0) {
1413         QDict *qdict = qobject_to_qdict(obj);
1414         qdict_put(qdict, "irq", qint_from_int(dev->config[PCI_INTERRUPT_LINE]));
1415     }
1416
1417     type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
1418     if (type == PCI_HEADER_TYPE_BRIDGE) {
1419         QDict *qdict;
1420         QObject *pci_bridge;
1421
1422         pci_bridge = qobject_from_jsonf("{ 'bus': "
1423         "{ 'number': %d, 'secondary': %d, 'subordinate': %d }, "
1424         "'io_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, "
1425         "'memory_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, "
1426         "'prefetchable_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "} }",
1427         dev->config[PCI_PRIMARY_BUS], dev->config[PCI_SECONDARY_BUS],
1428         dev->config[PCI_SUBORDINATE_BUS],
1429         pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO),
1430         pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO),
1431         pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY),
1432         pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY),
1433         pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY |
1434                                PCI_BASE_ADDRESS_MEM_PREFETCH),
1435         pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY |
1436                                 PCI_BASE_ADDRESS_MEM_PREFETCH));
1437
1438         if (dev->config[PCI_SECONDARY_BUS] != 0) {
1439             PCIBus *child_bus = pci_find_bus(bus, dev->config[PCI_SECONDARY_BUS]);
1440
1441             if (child_bus) {
1442                 qdict = qobject_to_qdict(pci_bridge);
1443                 qdict_put_obj(qdict, "devices",
1444                               pci_get_devices_list(child_bus,
1445                                                    dev->config[PCI_SECONDARY_BUS]));
1446             }
1447         }
1448         qdict = qobject_to_qdict(obj);
1449         qdict_put_obj(qdict, "pci_bridge", pci_bridge);
1450     }
1451
1452     return obj;
1453 }
1454
1455 static QObject *pci_get_devices_list(PCIBus *bus, int bus_num)
1456 {
1457     int devfn;
1458     PCIDevice *dev;
1459     QList *dev_list;
1460
1461     dev_list = qlist_new();
1462
1463     for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1464         dev = bus->devices[devfn];
1465         if (dev) {
1466             qlist_append_obj(dev_list, pci_get_dev_dict(dev, bus, bus_num));
1467         }
1468     }
1469
1470     return QOBJECT(dev_list);
1471 }
1472
1473 static QObject *pci_get_bus_dict(PCIBus *bus, int bus_num)
1474 {
1475     bus = pci_find_bus(bus, bus_num);
1476     if (bus) {
1477         return qobject_from_jsonf("{ 'bus': %d, 'devices': %p }",
1478                                   bus_num, pci_get_devices_list(bus, bus_num));
1479     }
1480
1481     return NULL;
1482 }
1483
1484 void do_pci_info(Monitor *mon, QObject **ret_data)
1485 {
1486     QList *bus_list;
1487     struct PCIHostBus *host;
1488
1489     bus_list = qlist_new();
1490
1491     QLIST_FOREACH(host, &host_buses, next) {
1492         QObject *obj = pci_get_bus_dict(host->bus, 0);
1493         if (obj) {
1494             qlist_append_obj(bus_list, obj);
1495         }
1496     }
1497
1498     *ret_data = QOBJECT(bus_list);
1499 }
1500
1501 static const char * const pci_nic_models[] = {
1502     "ne2k_pci",
1503     "i82551",
1504     "i82557b",
1505     "i82559er",
1506     "rtl8139",
1507     "e1000",
1508     "pcnet",
1509     "virtio",
1510     NULL
1511 };
1512
1513 static const char * const pci_nic_names[] = {
1514     "ne2k_pci",
1515     "i82551",
1516     "i82557b",
1517     "i82559er",
1518     "rtl8139",
1519     "e1000",
1520     "pcnet",
1521     "virtio-net-pci",
1522     NULL
1523 };
1524
1525 /* Initialize a PCI NIC.  */
1526 /* FIXME callers should check for failure, but don't */
1527 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
1528                         const char *default_devaddr)
1529 {
1530     const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
1531     PCIBus *bus;
1532     int devfn;
1533     PCIDevice *pci_dev;
1534     DeviceState *dev;
1535     int i;
1536
1537     i = qemu_find_nic_model(nd, pci_nic_models, default_model);
1538     if (i < 0)
1539         return NULL;
1540
1541     bus = pci_get_bus_devfn(&devfn, devaddr);
1542     if (!bus) {
1543         error_report("Invalid PCI device address %s for device %s",
1544                      devaddr, pci_nic_names[i]);
1545         return NULL;
1546     }
1547
1548     pci_dev = pci_create(bus, devfn, pci_nic_names[i]);
1549     dev = &pci_dev->qdev;
1550     qdev_set_nic_properties(dev, nd);
1551     if (qdev_init(dev) < 0)
1552         return NULL;
1553     return pci_dev;
1554 }
1555
1556 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
1557                                const char *default_devaddr)
1558 {
1559     PCIDevice *res;
1560
1561     if (qemu_show_nic_models(nd->model, pci_nic_models))
1562         exit(0);
1563
1564     res = pci_nic_init(nd, default_model, default_devaddr);
1565     if (!res)
1566         exit(1);
1567     return res;
1568 }
1569
1570 static void pci_bridge_update_mappings_fn(PCIBus *b, PCIDevice *d)
1571 {
1572     pci_update_mappings(d);
1573 }
1574
1575 void pci_bridge_update_mappings(PCIBus *b)
1576 {
1577     PCIBus *child;
1578
1579     pci_for_each_device_under_bus(b, pci_bridge_update_mappings_fn);
1580
1581     QLIST_FOREACH(child, &b->child, sibling) {
1582         pci_bridge_update_mappings(child);
1583     }
1584 }
1585
1586 PCIBus *pci_find_bus(PCIBus *bus, int bus_num)
1587 {
1588     PCIBus *sec;
1589
1590     if (!bus) {
1591         return NULL;
1592     }
1593
1594     if (pci_bus_num(bus) == bus_num) {
1595         return bus;
1596     }
1597
1598     /* try child bus */
1599     if (!bus->parent_dev /* host pci bridge */ ||
1600         (bus->parent_dev->config[PCI_SECONDARY_BUS] < bus_num &&
1601          bus_num <= bus->parent_dev->config[PCI_SUBORDINATE_BUS])) {
1602         for (; bus; bus = sec) {
1603             QLIST_FOREACH(sec, &bus->child, sibling) {
1604                 assert(sec->parent_dev);
1605                 if (sec->parent_dev->config[PCI_SECONDARY_BUS] == bus_num) {
1606                     return sec;
1607                 }
1608                 if (sec->parent_dev->config[PCI_SECONDARY_BUS] < bus_num &&
1609                     bus_num <= sec->parent_dev->config[PCI_SUBORDINATE_BUS]) {
1610                     break;
1611                 }
1612             }
1613         }
1614     }
1615
1616     return NULL;
1617 }
1618
1619 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, int slot, int function)
1620 {
1621     bus = pci_find_bus(bus, bus_num);
1622
1623     if (!bus)
1624         return NULL;
1625
1626     return bus->devices[PCI_DEVFN(slot, function)];
1627 }
1628
1629 static int pci_qdev_init(DeviceState *qdev, DeviceInfo *base)
1630 {
1631     PCIDevice *pci_dev = (PCIDevice *)qdev;
1632     PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev);
1633     PCIBus *bus;
1634     int devfn, rc;
1635
1636     /* initialize cap_present for pci_is_express() and pci_config_size() */
1637     if (info->is_express) {
1638         pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
1639     }
1640
1641     bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
1642     devfn = pci_dev->devfn;
1643     pci_dev = do_pci_register_device(pci_dev, bus, base->name, devfn,
1644                                      info->config_read, info->config_write,
1645                                      info->is_bridge);
1646     if (pci_dev == NULL)
1647         return -1;
1648     rc = info->init(pci_dev);
1649     if (rc != 0) {
1650         do_pci_unregister_device(pci_dev);
1651         return rc;
1652     }
1653
1654     /* rom loading */
1655     if (pci_dev->romfile == NULL && info->romfile != NULL)
1656         pci_dev->romfile = qemu_strdup(info->romfile);
1657     pci_add_option_rom(pci_dev);
1658
1659     if (bus->hotplug) {
1660         /* Let buses differentiate between hotplug and when device is
1661          * enabled during qemu machine creation. */
1662         rc = bus->hotplug(bus->hotplug_qdev, pci_dev,
1663                           qdev->hotplugged ? PCI_HOTPLUG_ENABLED:
1664                           PCI_COLDPLUG_ENABLED);
1665         if (rc != 0) {
1666             int r = pci_unregister_device(&pci_dev->qdev);
1667             assert(!r);
1668             return rc;
1669         }
1670     }
1671     return 0;
1672 }
1673
1674 static int pci_unplug_device(DeviceState *qdev)
1675 {
1676     PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev);
1677
1678     return dev->bus->hotplug(dev->bus->hotplug_qdev, dev,
1679                              PCI_HOTPLUG_DISABLED);
1680 }
1681
1682 void pci_qdev_register(PCIDeviceInfo *info)
1683 {
1684     info->qdev.init = pci_qdev_init;
1685     info->qdev.unplug = pci_unplug_device;
1686     info->qdev.exit = pci_unregister_device;
1687     info->qdev.bus_info = &pci_bus_info;
1688     qdev_register(&info->qdev);
1689 }
1690
1691 void pci_qdev_register_many(PCIDeviceInfo *info)
1692 {
1693     while (info->qdev.name) {
1694         pci_qdev_register(info);
1695         info++;
1696     }
1697 }
1698
1699 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
1700                                     const char *name)
1701 {
1702     DeviceState *dev;
1703
1704     dev = qdev_create(&bus->qbus, name);
1705     qdev_prop_set_uint32(dev, "addr", devfn);
1706     qdev_prop_set_bit(dev, "multifunction", multifunction);
1707     return DO_UPCAST(PCIDevice, qdev, dev);
1708 }
1709
1710 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
1711                                            bool multifunction,
1712                                            const char *name)
1713 {
1714     PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name);
1715     qdev_init_nofail(&dev->qdev);
1716     return dev;
1717 }
1718
1719 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
1720 {
1721     return pci_create_multifunction(bus, devfn, false, name);
1722 }
1723
1724 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
1725 {
1726     return pci_create_simple_multifunction(bus, devfn, false, name);
1727 }
1728
1729 static int pci_find_space(PCIDevice *pdev, uint8_t size)
1730 {
1731     int config_size = pci_config_size(pdev);
1732     int offset = PCI_CONFIG_HEADER_SIZE;
1733     int i;
1734     for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; ++i)
1735         if (pdev->config_map[i])
1736             offset = i + 1;
1737         else if (i - offset + 1 == size)
1738             return offset;
1739     return 0;
1740 }
1741
1742 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
1743                                         uint8_t *prev_p)
1744 {
1745     uint8_t next, prev;
1746
1747     if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
1748         return 0;
1749
1750     for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1751          prev = next + PCI_CAP_LIST_NEXT)
1752         if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
1753             break;
1754
1755     if (prev_p)
1756         *prev_p = prev;
1757     return next;
1758 }
1759
1760 void pci_map_option_rom(PCIDevice *pdev, int region_num, pcibus_t addr, pcibus_t size, int type)
1761 {
1762     cpu_register_physical_memory(addr, size, pdev->rom_offset);
1763 }
1764
1765 /* Add an option rom for the device */
1766 static int pci_add_option_rom(PCIDevice *pdev)
1767 {
1768     int size;
1769     char *path;
1770     void *ptr;
1771     char name[32];
1772
1773     if (!pdev->romfile)
1774         return 0;
1775     if (strlen(pdev->romfile) == 0)
1776         return 0;
1777
1778     if (!pdev->rom_bar) {
1779         /*
1780          * Load rom via fw_cfg instead of creating a rom bar,
1781          * for 0.11 compatibility.
1782          */
1783         int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE);
1784         if (class == 0x0300) {
1785             rom_add_vga(pdev->romfile);
1786         } else {
1787             rom_add_option(pdev->romfile);
1788         }
1789         return 0;
1790     }
1791
1792     path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile);
1793     if (path == NULL) {
1794         path = qemu_strdup(pdev->romfile);
1795     }
1796
1797     size = get_image_size(path);
1798     if (size < 0) {
1799         error_report("%s: failed to find romfile \"%s\"",
1800                      __FUNCTION__, pdev->romfile);
1801         return -1;
1802     }
1803     if (size & (size - 1)) {
1804         size = 1 << qemu_fls(size);
1805     }
1806
1807     if (pdev->qdev.info->vmsd)
1808         snprintf(name, sizeof(name), "%s.rom", pdev->qdev.info->vmsd->name);
1809     else
1810         snprintf(name, sizeof(name), "%s.rom", pdev->qdev.info->name);
1811     pdev->rom_offset = qemu_ram_alloc(&pdev->qdev, name, size);
1812
1813     ptr = qemu_get_ram_ptr(pdev->rom_offset);
1814     load_image(path, ptr);
1815     qemu_free(path);
1816
1817     pci_register_bar(pdev, PCI_ROM_SLOT, size,
1818                      0, pci_map_option_rom);
1819
1820     return 0;
1821 }
1822
1823 static void pci_del_option_rom(PCIDevice *pdev)
1824 {
1825     if (!pdev->rom_offset)
1826         return;
1827
1828     qemu_ram_free(pdev->rom_offset);
1829     pdev->rom_offset = 0;
1830 }
1831
1832 /*
1833  * if !offset
1834  * Reserve space and add capability to the linked list in pci config space
1835  *
1836  * if offset = 0,
1837  * Find and reserve space and add capability to the linked list
1838  * in pci config space */
1839 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
1840                        uint8_t offset, uint8_t size)
1841 {
1842     uint8_t *config;
1843     if (!offset) {
1844         offset = pci_find_space(pdev, size);
1845         if (!offset) {
1846             return -ENOSPC;
1847         }
1848     }
1849
1850     config = pdev->config + offset;
1851     config[PCI_CAP_LIST_ID] = cap_id;
1852     config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
1853     pdev->config[PCI_CAPABILITY_LIST] = offset;
1854     memset(pdev->config_map + offset, cap_id, size);
1855     /* Make capability read-only by default */
1856     memset(pdev->wmask + offset, 0, size);
1857     /* Check capability by default */
1858     memset(pdev->cmask + offset, 0xFF, size);
1859
1860     pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
1861
1862     return offset;
1863 }
1864
1865 /* Unlink capability from the pci config space. */
1866 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1867 {
1868     uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
1869     if (!offset)
1870         return;
1871     pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
1872     /* Make capability writeable again */
1873     memset(pdev->wmask + offset, 0xff, size);
1874     memset(pdev->w1cmask + offset, 0, size);
1875     /* Clear cmask as device-specific registers can't be checked */
1876     memset(pdev->cmask + offset, 0, size);
1877     memset(pdev->config_map + offset, 0, size);
1878
1879     if (!pdev->config[PCI_CAPABILITY_LIST]) {
1880         pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
1881     }
1882 }
1883
1884 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
1885 {
1886     return pci_find_capability_list(pdev, cap_id, NULL);
1887 }
1888
1889 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
1890 {
1891     PCIDevice *d = (PCIDevice *)dev;
1892     const pci_class_desc *desc;
1893     char ctxt[64];
1894     PCIIORegion *r;
1895     int i, class;
1896
1897     class = pci_get_word(d->config + PCI_CLASS_DEVICE);
1898     desc = pci_class_descriptions;
1899     while (desc->desc && class != desc->class)
1900         desc++;
1901     if (desc->desc) {
1902         snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
1903     } else {
1904         snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
1905     }
1906
1907     monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
1908                    "pci id %04x:%04x (sub %04x:%04x)\n",
1909                    indent, "", ctxt, pci_bus_num(d->bus),
1910                    PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
1911                    pci_get_word(d->config + PCI_VENDOR_ID),
1912                    pci_get_word(d->config + PCI_DEVICE_ID),
1913                    pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
1914                    pci_get_word(d->config + PCI_SUBSYSTEM_ID));
1915     for (i = 0; i < PCI_NUM_REGIONS; i++) {
1916         r = &d->io_regions[i];
1917         if (!r->size)
1918             continue;
1919         monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
1920                        " [0x%"FMT_PCIBUS"]\n",
1921                        indent, "",
1922                        i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
1923                        r->addr, r->addr + r->size - 1);
1924     }
1925 }
1926
1927 static char *pcibus_get_dev_path(DeviceState *dev)
1928 {
1929     PCIDevice *d = (PCIDevice *)dev;
1930     char path[16];
1931
1932     snprintf(path, sizeof(path), "%04x:%02x:%02x.%x",
1933              pci_find_domain(d->bus), d->config[PCI_SECONDARY_BUS],
1934              PCI_SLOT(d->devfn), PCI_FUNC(d->devfn));
1935
1936     return strdup(path);
1937 }
1938