hw/pci.h

   1 #ifndef QEMU_PCI_H
   2 #define QEMU_PCI_H
   3
   4 #include "qemu-common.h"
   5 #include "qobject.h"
   6
   7 #include "qdev.h"
   8
   9 struct kvm_irq_routing_entry;
  10
  11 /* PCI includes legacy ISA access.  */
  12 #include "isa.h"
  13
  14 #include "pcie.h"
  15
  16 /* PCI bus */
  17
  18 #define PCI_DEVFN(slot, func)   ((((slot) & 0x1f) << 3) | ((func) & 0x07))
  19 #define PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
  20 #define PCI_FUNC(devfn)         ((devfn) & 0x07)
  21 #define PCI_FUNC_MAX            8
  22
  23 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
  24 #include "pci_ids.h"
  25
  26 /* QEMU-specific Vendor and Device ID definitions */
  27
  28 /* IBM (0x1014) */
  29 #define PCI_DEVICE_ID_IBM_440GX          0x027f
  30 #define PCI_DEVICE_ID_IBM_OPENPIC2       0xffff
  31
  32 /* Hitachi (0x1054) */
  33 #define PCI_VENDOR_ID_HITACHI            0x1054
  34 #define PCI_DEVICE_ID_HITACHI_SH7751R    0x350e
  35
  36 /* Apple (0x106b) */
  37 #define PCI_DEVICE_ID_APPLE_343S1201     0x0010
  38 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI  0x001e
  39 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI    0x001f
  40 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL   0x0022
  41 #define PCI_DEVICE_ID_APPLE_IPID_USB     0x003f
  42
  43 /* Realtek (0x10ec) */
  44 #define PCI_DEVICE_ID_REALTEK_8029       0x8029
  45
  46 /* Xilinx (0x10ee) */
  47 #define PCI_DEVICE_ID_XILINX_XC2VP30     0x0300
  48
  49 /* Marvell (0x11ab) */
  50 #define PCI_DEVICE_ID_MARVELL_GT6412X    0x4620
  51
  52 /* QEMU/Bochs VGA (0x1234) */
  53 #define PCI_VENDOR_ID_QEMU               0x1234
  54 #define PCI_DEVICE_ID_QEMU_VGA           0x1111
  55
  56 /* VMWare (0x15ad) */
  57 #define PCI_VENDOR_ID_VMWARE             0x15ad
  58 #define PCI_DEVICE_ID_VMWARE_SVGA2       0x0405
  59 #define PCI_DEVICE_ID_VMWARE_SVGA        0x0710
  60 #define PCI_DEVICE_ID_VMWARE_NET         0x0720
  61 #define PCI_DEVICE_ID_VMWARE_SCSI        0x0730
  62 #define PCI_DEVICE_ID_VMWARE_IDE         0x1729
  63
  64 /* Intel (0x8086) */
  65 #define PCI_DEVICE_ID_INTEL_82551IT      0x1209
  66 #define PCI_DEVICE_ID_INTEL_82557        0x1229
  67
  68 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
  69 #define PCI_VENDOR_ID_REDHAT_QUMRANET    0x1af4
  70 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
  71 #define PCI_SUBDEVICE_ID_QEMU            0x1100
  72
  73 #define PCI_DEVICE_ID_VIRTIO_NET         0x1000
  74 #define PCI_DEVICE_ID_VIRTIO_BLOCK       0x1001
  75 #define PCI_DEVICE_ID_VIRTIO_BALLOON     0x1002
  76 #define PCI_DEVICE_ID_VIRTIO_CONSOLE     0x1003
  77
  78 #define FMT_PCIBUS                      PRIx64
  79
  80 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
  81                                 uint32_t address, uint32_t data, int len);
  82 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
  83                                    uint32_t address, int len);
  84 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
  85                                 pcibus_t addr, pcibus_t size, int type);
  86 typedef int PCIUnregisterFunc(PCIDevice *pci_dev);
  87
  88 typedef void PCICapConfigWriteFunc(PCIDevice *pci_dev,
  89                                    uint32_t address, uint32_t val, int len);
  90 typedef uint32_t PCICapConfigReadFunc(PCIDevice *pci_dev,
  91                                       uint32_t address, int len);
  92
  93 typedef struct PCIIORegion {
  94     pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
  95 #define PCI_BAR_UNMAPPED (~(pcibus_t)0)
  96     pcibus_t size;
  97     pcibus_t filtered_size;
  98     uint8_t type;
  99     PCIMapIORegionFunc *map_func;
 100 } PCIIORegion;
 101
 102 #define PCI_ROM_SLOT 6
 103 #define PCI_NUM_REGIONS 7
 104
 105 #include "pci_regs.h"
 106
 107 /* PCI HEADER_TYPE */
 108 #define  PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
 109
 110 /* Size of the standard PCI config header */
 111 #define PCI_CONFIG_HEADER_SIZE 0x40
 112 /* Size of the standard PCI config space */
 113 #define PCI_CONFIG_SPACE_SIZE 0x100
 114 /* Size of the standart PCIe config space: 4KB */
 115 #define PCIE_CONFIG_SPACE_SIZE  0x1000
 116
 117 #define PCI_NUM_PINS 4 /* A-D */
 118
 119 /* Bits in cap_present field. */
 120 enum {
 121     QEMU_PCI_CAP_MSI = 0x1,
 122     QEMU_PCI_CAP_MSIX = 0x2,
 123     QEMU_PCI_CAP_EXPRESS = 0x4,
 124
 125     /* multifunction capable device */
 126 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR        3
 127     QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
 128 };
 129
 130 #define PCI_CAPABILITY_CONFIG_MAX_LENGTH 0x60
 131 #define PCI_CAPABILITY_CONFIG_DEFAULT_START_ADDR 0x40
 132 #define PCI_CAPABILITY_CONFIG_MSI_LENGTH 0x10
 133 #define PCI_CAPABILITY_CONFIG_MSIX_LENGTH 0x10
 134
 135 typedef int (*msix_mask_notifier_func)(PCIDevice *, unsigned vector,
 136                                        int masked);
 137
 138 struct kvm_msix_message {
 139     uint32_t gsi;
 140     uint32_t addr_lo;
 141     uint32_t addr_hi;
 142     uint32_t data;
 143 };
 144
 145 struct PCIDevice {
 146     DeviceState qdev;
 147     /* PCI config space */
 148     uint8_t *config;
 149
 150     /* Used to enable config checks on load. Note that writeable bits are
 151      * never checked even if set in cmask. */
 152     uint8_t *cmask;
 153
 154     /* Used to implement R/W bytes */
 155     uint8_t *wmask;
 156
 157     /* Used to implement RW1C(Write 1 to Clear) bytes */
 158     uint8_t *w1cmask;
 159
 160     /* Used to allocate config space for capabilities. */
 161     uint8_t *used;
 162
 163     /* the following fields are read only */
 164     PCIBus *bus;
 165     uint32_t devfn;
 166     char name[64];
 167     PCIIORegion io_regions[PCI_NUM_REGIONS];
 168
 169     /* do not access the following fields */
 170     PCIConfigReadFunc *config_read;
 171     PCIConfigWriteFunc *config_write;
 172
 173     /* IRQ objects for the INTA-INTD pins.  */
 174     qemu_irq *irq;
 175
 176     /* Current IRQ levels.  Used internally by the generic PCI code.  */
 177     uint8_t irq_state;
 178
 179     /* Capability bits */
 180     uint32_t cap_present;
 181
 182     /* Offset of MSI-X capability in config space */
 183     uint8_t msix_cap;
 184
 185     /* MSI-X entries */
 186     int msix_entries_nr;
 187
 188     /* Space to store MSIX table */
 189     uint8_t *msix_table_page;
 190     /* MMIO index used to map MSIX table and pending bit entries. */
 191     int msix_mmio_index;
 192     /* Reference-count for entries actually in use by driver. */
 193     unsigned *msix_entry_used;
 194     /* Region including the MSI-X table */
 195     uint32_t msix_bar_size;
 196     /* Version id needed for VMState */
 197     int32_t version_id;
 198
 199     /* Offset of MSI capability in config space */
 200     uint8_t msi_cap;
 201
 202     /* PCI Express */
 203     PCIExpressDevice exp;
 204
 205     /* Location of option rom */
 206     char *romfile;
 207     ram_addr_t rom_offset;
 208     uint32_t rom_bar;
 209
 210     /* How much space does an MSIX table need. */
 211     /* The spec requires giving the table structure
 212      * a 4K aligned region all by itself. Align it to
 213      * target pages so that drivers can do passthrough
 214      * on the rest of the region. */
 215     target_phys_addr_t msix_page_size;
 216
 217     struct kvm_msix_message *msix_irq_entries;
 218
 219     msix_mask_notifier_func msix_mask_notifier;
 220
 221     /* Device capability configuration space */
 222     struct {
 223         int supported;
 224         unsigned int start, length;
 225         PCICapConfigReadFunc *config_read;
 226         PCICapConfigWriteFunc *config_write;
 227     } cap;
 228 };
 229
 230 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 231                                int instance_size, int devfn,
 232                                PCIConfigReadFunc *config_read,
 233                                PCIConfigWriteFunc *config_write);
 234
 235 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 236                             pcibus_t size, uint8_t type,
 237                             PCIMapIORegionFunc *map_func);
 238
 239 void pci_map_option_rom(PCIDevice *pdev, int region_num, pcibus_t addr,
 240                         pcibus_t size, int type);
 241
 242 void pci_register_capability_handlers(PCIDevice *pci_dev,
 243                                       PCICapConfigReadFunc *config_read,
 244                                       PCICapConfigWriteFunc *config_write);
 245
 246 int pci_map_irq(PCIDevice *pci_dev, int pin);
 247
 248 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
 249                        uint8_t offset, uint8_t size);
 250
 251 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
 252
 253 void pci_reserve_capability(PCIDevice *pci_dev, uint8_t offset, uint8_t size);
 254
 255 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
 256
 257 uint32_t pci_default_read_config(PCIDevice *d,
 258                                  uint32_t address, int len);
 259 void pci_default_write_config(PCIDevice *d,
 260                               uint32_t address, uint32_t val, int len);
 261 void pci_device_save(PCIDevice *s, QEMUFile *f);
 262 int pci_device_load(PCIDevice *s, QEMUFile *f);
 263 uint32_t pci_default_cap_read_config(PCIDevice *pci_dev,
 264                                      uint32_t address, int len);
 265 void pci_default_cap_write_config(PCIDevice *pci_dev,
 266                                   uint32_t address, uint32_t val, int len);
 267 int pci_access_cap_config(PCIDevice *pci_dev, uint32_t address, int len);
 268
 269 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
 270 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
 271 typedef int (*pci_hotplug_fn)(DeviceState *qdev, PCIDevice *pci_dev, int state);
 272 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
 273                          const char *name, int devfn_min);
 274 PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min);
 275 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 276                   void *irq_opaque, int nirq);
 277 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev);
 278 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 279                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 280                          void *irq_opaque, int devfn_min, int nirq);
 281
 282 void pci_bus_set_mem_base(PCIBus *bus, target_phys_addr_t base);
 283
 284 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
 285                         const char *default_devaddr);
 286 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
 287                                const char *default_devaddr);
 288 int pci_bus_num(PCIBus *s);
 289 void pci_for_each_device(PCIBus *bus, int bus_num, void (*fn)(PCIBus *bus, PCIDevice *d));
 290 PCIBus *pci_find_root_bus(int domain);
 291 int pci_find_domain(const PCIBus *bus);
 292 PCIBus *pci_find_bus(PCIBus *bus, int bus_num);
 293 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, int slot, int function);
 294 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr);
 295
 296 int pci_parse_devaddr(const char *addr, int *domp, int *busp,
 297                       unsigned int *slotp, unsigned int *funcp);
 298 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
 299                      unsigned *slotp);
 300
 301 int pci_parse_host_devaddr(const char *addr, int *segp, int *busp,
 302                            int *slotp, int *funcp);
 303
 304 void do_pci_info_print(Monitor *mon, const QObject *data);
 305 void do_pci_info(Monitor *mon, QObject **ret_data);
 306 void pci_bridge_update_mappings(PCIBus *b);
 307
 308 bool pci_msi_enabled(PCIDevice *dev);
 309 void pci_msi_notify(PCIDevice *dev, unsigned int vector);
 310
 311 static inline void
 312 pci_set_byte(uint8_t *config, uint8_t val)
 313 {
 314     *config = val;
 315 }
 316
 317 static inline uint8_t
 318 pci_get_byte(const uint8_t *config)
 319 {
 320     return *config;
 321 }
 322
 323 static inline void
 324 pci_set_word(uint8_t *config, uint16_t val)
 325 {
 326     cpu_to_le16wu((uint16_t *)config, val);
 327 }
 328
 329 static inline uint16_t
 330 pci_get_word(const uint8_t *config)
 331 {
 332     return le16_to_cpupu((const uint16_t *)config);
 333 }
 334
 335 static inline void
 336 pci_set_long(uint8_t *config, uint32_t val)
 337 {
 338     cpu_to_le32wu((uint32_t *)config, val);
 339 }
 340
 341 static inline uint32_t
 342 pci_get_long(const uint8_t *config)
 343 {
 344     return le32_to_cpupu((const uint32_t *)config);
 345 }
 346
 347 static inline void
 348 pci_set_quad(uint8_t *config, uint64_t val)
 349 {
 350     cpu_to_le64w((uint64_t *)config, val);
 351 }
 352
 353 static inline uint64_t
 354 pci_get_quad(const uint8_t *config)
 355 {
 356     return le64_to_cpup((const uint64_t *)config);
 357 }
 358
 359 static inline void
 360 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
 361 {
 362     pci_set_word(&pci_config[PCI_VENDOR_ID], val);
 363 }
 364
 365 static inline void
 366 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
 367 {
 368     pci_set_word(&pci_config[PCI_DEVICE_ID], val);
 369 }
 370
 371 static inline void
 372 pci_config_set_revision(uint8_t *pci_config, uint8_t val)
 373 {
 374     pci_set_byte(&pci_config[PCI_REVISION_ID], val);
 375 }
 376
 377 static inline void
 378 pci_config_set_class(uint8_t *pci_config, uint16_t val)
 379 {
 380     pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
 381 }
 382
 383 static inline void
 384 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val)
 385 {
 386     pci_set_byte(&pci_config[PCI_CLASS_PROG], val);
 387 }
 388
 389 static inline void
 390 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val)
 391 {
 392     pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val);
 393 }
 394
 395 /*
 396  * helper functions to do bit mask operation on configuration space.
 397  * Just to set bit, use test-and-set and discard returned value.
 398  * Just to clear bit, use test-and-clear and discard returned value.
 399  * NOTE: They aren't atomic.
 400  */
 401 static inline uint8_t
 402 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask)
 403 {
 404     uint8_t val = pci_get_byte(config);
 405     pci_set_byte(config, val & ~mask);
 406     return val & mask;
 407 }
 408
 409 static inline uint8_t
 410 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask)
 411 {
 412     uint8_t val = pci_get_byte(config);
 413     pci_set_byte(config, val | mask);
 414     return val & mask;
 415 }
 416
 417 static inline uint16_t
 418 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask)
 419 {
 420     uint16_t val = pci_get_word(config);
 421     pci_set_word(config, val & ~mask);
 422     return val & mask;
 423 }
 424
 425 static inline uint16_t
 426 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask)
 427 {
 428     uint16_t val = pci_get_word(config);
 429     pci_set_word(config, val | mask);
 430     return val & mask;
 431 }
 432
 433 static inline uint32_t
 434 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask)
 435 {
 436     uint32_t val = pci_get_long(config);
 437     pci_set_long(config, val & ~mask);
 438     return val & mask;
 439 }
 440
 441 static inline uint32_t
 442 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask)
 443 {
 444     uint32_t val = pci_get_long(config);
 445     pci_set_long(config, val | mask);
 446     return val & mask;
 447 }
 448
 449 static inline uint64_t
 450 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask)
 451 {
 452     uint64_t val = pci_get_quad(config);
 453     pci_set_quad(config, val & ~mask);
 454     return val & mask;
 455 }
 456
 457 static inline uint64_t
 458 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask)
 459 {
 460     uint64_t val = pci_get_quad(config);
 461     pci_set_quad(config, val | mask);
 462     return val & mask;
 463 }
 464
 465 typedef int (*pci_qdev_initfn)(PCIDevice *dev);
 466 typedef struct {
 467     DeviceInfo qdev;
 468     pci_qdev_initfn init;
 469     PCIUnregisterFunc *exit;
 470     PCIConfigReadFunc *config_read;
 471     PCIConfigWriteFunc *config_write;
 472
 473     /*
 474      * pci-to-pci bridge or normal device.
 475      * This doesn't mean pci host switch.
 476      * When card bus bridge is supported, this would be enhanced.
 477      */
 478     int is_bridge;
 479
 480     /* pcie stuff */
 481     int is_express;   /* is this device pci express? */
 482
 483     /* rom bar */
 484     const char *romfile;
 485 } PCIDeviceInfo;
 486
 487 void pci_qdev_register(PCIDeviceInfo *info);
 488 void pci_qdev_register_many(PCIDeviceInfo *info);
 489
 490 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
 491                                     const char *name);
 492 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
 493                                            bool multifunction,
 494                                            const char *name);
 495 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name);
 496 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
 497
 498 static inline int pci_is_express(const PCIDevice *d)
 499 {
 500     return d->cap_present & QEMU_PCI_CAP_EXPRESS;
 501 }
 502
 503 static inline uint32_t pci_config_size(const PCIDevice *d)
 504 {
 505     return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
 506 }
 507
 508 #endif