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Merge branch 'upstream-merge'
[qemu-kvm/markmc.git] / qemu-kvm-x86.c
blob9df0d83394fca930f8febdee520f6cecf46c915d
1 /*
2 * qemu/kvm integration, x86 specific code
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 *
6 * Licensed under the terms of the GNU GPL version 2 or higher.
7 */
8
9 #include "config.h"
10 #include "config-host.h"
11
12 #include <string.h>
13 #include "hw/hw.h"
14 #include "gdbstub.h"
15 #include <sys/io.h>
16
17 #include "qemu-kvm.h"
18 #include "libkvm.h"
19 #include <pthread.h>
20 #include <sys/utsname.h>
21 #include <linux/kvm_para.h>
22 #include <sys/ioctl.h>
23
24 #include "kvm.h"
25 #include "hw/pc.h"
26
27 #define MSR_IA32_TSC 0x10
28
29 static struct kvm_msr_list *kvm_msr_list;
30 extern unsigned int kvm_shadow_memory;
31 static int kvm_has_msr_star;
32 static int kvm_has_vm_hsave_pa;
33
34 static int lm_capable_kernel;
35
36 int kvm_set_tss_addr(kvm_context_t kvm, unsigned long addr)
37 {
38 #ifdef KVM_CAP_SET_TSS_ADDR
39 int r;
40
41 r = kvm_ioctl(kvm_state, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR);
42 if (r > 0) {
43 r = kvm_vm_ioctl(kvm_state, KVM_SET_TSS_ADDR, addr);
44 if (r < 0) {
45 fprintf(stderr, "kvm_set_tss_addr: %m\n");
46 return r;
47 }
48 return 0;
49 }
50 #endif
51 return -ENOSYS;
52 }
53
54 static int kvm_init_tss(kvm_context_t kvm)
55 {
56 #ifdef KVM_CAP_SET_TSS_ADDR
57 int r;
58
59 r = kvm_ioctl(kvm_state, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR);
60 if (r > 0) {
61 /*
62 * this address is 3 pages before the bios, and the bios should present
63 * as unavaible memory
64 */
65 r = kvm_set_tss_addr(kvm, 0xfeffd000);
66 if (r < 0) {
67 fprintf(stderr, "kvm_init_tss: unable to set tss addr\n");
68 return r;
69 }
70
71 }
72 #endif
73 return 0;
74 }
75
76 static int kvm_set_identity_map_addr(kvm_context_t kvm, uint64_t addr)
77 {
78 #ifdef KVM_CAP_SET_IDENTITY_MAP_ADDR
79 int r;
80
81 r = kvm_ioctl(kvm_state, KVM_CHECK_EXTENSION, KVM_CAP_SET_IDENTITY_MAP_ADDR);
82 if (r > 0) {
83 r = kvm_vm_ioctl(kvm_state, KVM_SET_IDENTITY_MAP_ADDR, &addr);
84 if (r == -1) {
85 fprintf(stderr, "kvm_set_identity_map_addr: %m\n");
86 return -errno;
87 }
88 return 0;
89 }
90 #endif
91 return -ENOSYS;
92 }
93
94 static int kvm_init_identity_map_page(kvm_context_t kvm)
95 {
96 #ifdef KVM_CAP_SET_IDENTITY_MAP_ADDR
97 int r;
98
99 r = kvm_ioctl(kvm_state, KVM_CHECK_EXTENSION, KVM_CAP_SET_IDENTITY_MAP_ADDR);
100 if (r > 0) {
101 /*
102 * this address is 4 pages before the bios, and the bios should present
103 * as unavaible memory
104 */
105 r = kvm_set_identity_map_addr(kvm, 0xfeffc000);
106 if (r < 0) {
107 fprintf(stderr, "kvm_init_identity_map_page: "
108 "unable to set identity mapping addr\n");
109 return r;
110 }
111
112 }
113 #endif
114 return 0;
115 }
116
117 static int kvm_create_pit(kvm_context_t kvm)
118 {
119 #ifdef KVM_CAP_PIT
120 int r;
121
122 kvm->pit_in_kernel = 0;
123 if (!kvm->no_pit_creation) {
124 r = kvm_ioctl(kvm_state, KVM_CHECK_EXTENSION, KVM_CAP_PIT);
125 if (r > 0) {
126 r = kvm_vm_ioctl(kvm_state, KVM_CREATE_PIT);
127 if (r >= 0)
128 kvm->pit_in_kernel = 1;
129 else {
130 fprintf(stderr, "Create kernel PIC irqchip failed\n");
131 return r;
132 }
133 }
134 }
135 #endif
136 return 0;
137 }
138
139 int kvm_arch_create(kvm_context_t kvm, unsigned long phys_mem_bytes,
140 void **vm_mem)
141 {
142 int r = 0;
143
144 r = kvm_init_tss(kvm);
145 if (r < 0)
146 return r;
147
148 r = kvm_init_identity_map_page(kvm);
149 if (r < 0)
150 return r;
151
152 r = kvm_create_pit(kvm);
153 if (r < 0)
154 return r;
155
156 r = kvm_init_coalesced_mmio(kvm);
157 if (r < 0)
158 return r;
159
160 #ifdef KVM_EXIT_TPR_ACCESS
161 kvm_tpr_opt_setup();
162 #endif
163
164 return 0;
165 }
166
167 #ifdef KVM_EXIT_TPR_ACCESS
168
169 static int kvm_handle_tpr_access(CPUState *env)
170 {
171 struct kvm_run *run = env->kvm_run;
172 kvm_tpr_access_report(env,
173 run->tpr_access.rip,
174 run->tpr_access.is_write);
175 return 0;
176 }
177
178
179 int kvm_enable_vapic(CPUState *env, uint64_t vapic)
180 {
181 struct kvm_vapic_addr va = {
182 .vapic_addr = vapic,
183 };
184
185 return kvm_vcpu_ioctl(env, KVM_SET_VAPIC_ADDR, &va);
186 }
187
188 #endif
189
190 int kvm_arch_run(CPUState *env)
191 {
192 int r = 0;
193 struct kvm_run *run = env->kvm_run;
194
195
196 switch (run->exit_reason) {
197 #ifdef KVM_EXIT_SET_TPR
198 case KVM_EXIT_SET_TPR:
199 break;
200 #endif
201 #ifdef KVM_EXIT_TPR_ACCESS
202 case KVM_EXIT_TPR_ACCESS:
203 r = kvm_handle_tpr_access(env);
204 break;
205 #endif
206 default:
207 r = 1;
208 break;
209 }
210
211 return r;
212 }
213
214 #define MAX_ALIAS_SLOTS 4
215 static struct {
216 uint64_t start;
217 uint64_t len;
218 } kvm_aliases[MAX_ALIAS_SLOTS];
219
220 static int get_alias_slot(uint64_t start)
221 {
222 int i;
223
224 for (i=0; i<MAX_ALIAS_SLOTS; i++)
225 if (kvm_aliases[i].start == start)
226 return i;
227 return -1;
228 }
229 static int get_free_alias_slot(void)
230 {
231 int i;
232
233 for (i=0; i<MAX_ALIAS_SLOTS; i++)
234 if (kvm_aliases[i].len == 0)
235 return i;
236 return -1;
237 }
238
239 static void register_alias(int slot, uint64_t start, uint64_t len)
240 {
241 kvm_aliases[slot].start = start;
242 kvm_aliases[slot].len = len;
243 }
244
245 int kvm_create_memory_alias(kvm_context_t kvm,
246 uint64_t phys_start,
247 uint64_t len,
248 uint64_t target_phys)
249 {
250 struct kvm_memory_alias alias = {
251 .flags = 0,
252 .guest_phys_addr = phys_start,
253 .memory_size = len,
254 .target_phys_addr = target_phys,
255 };
256 int r;
257 int slot;
258
259 slot = get_alias_slot(phys_start);
260 if (slot < 0)
261 slot = get_free_alias_slot();
262 if (slot < 0)
263 return -EBUSY;
264 alias.slot = slot;
265
266 r = kvm_vm_ioctl(kvm_state, KVM_SET_MEMORY_ALIAS, &alias);
267 if (r == -1)
268 return -errno;
269
270 register_alias(slot, phys_start, len);
271 return 0;
272 }
273
274 int kvm_destroy_memory_alias(kvm_context_t kvm, uint64_t phys_start)
275 {
276 return kvm_create_memory_alias(kvm, phys_start, 0, 0);
277 }
278
279 #ifdef KVM_CAP_IRQCHIP
280
281 int kvm_get_lapic(CPUState *env, struct kvm_lapic_state *s)
282 {
283 int r = 0;
284
285 if (!kvm_irqchip_in_kernel())
286 return r;
287
288 r = kvm_vcpu_ioctl(env, KVM_GET_LAPIC, s);
289 if (r < 0)
290 fprintf(stderr, "KVM_GET_LAPIC failed\n");
291 return r;
292 }
293
294 int kvm_set_lapic(CPUState *env, struct kvm_lapic_state *s)
295 {
296 int r = 0;
297
298 if (!kvm_irqchip_in_kernel())
299 return 0;
300
301 r = kvm_vcpu_ioctl(env, KVM_SET_LAPIC, s);
302
303 if (r < 0)
304 fprintf(stderr, "KVM_SET_LAPIC failed\n");
305 return r;
306 }
307
308 #endif
309
310 #ifdef KVM_CAP_PIT
311
312 int kvm_get_pit(kvm_context_t kvm, struct kvm_pit_state *s)
313 {
314 if (!kvm->pit_in_kernel)
315 return 0;
316 return kvm_vm_ioctl(kvm_state, KVM_GET_PIT, s);
317 }
318
319 int kvm_set_pit(kvm_context_t kvm, struct kvm_pit_state *s)
320 {
321 if (!kvm->pit_in_kernel)
322 return 0;
323 return kvm_vm_ioctl(kvm_state, KVM_SET_PIT, s);
324 }
325
326 #ifdef KVM_CAP_PIT_STATE2
327 int kvm_get_pit2(kvm_context_t kvm, struct kvm_pit_state2 *ps2)
328 {
329 if (!kvm->pit_in_kernel)
330 return 0;
331 return kvm_vm_ioctl(kvm_state, KVM_GET_PIT2, ps2);
332 }
333
334 int kvm_set_pit2(kvm_context_t kvm, struct kvm_pit_state2 *ps2)
335 {
336 if (!kvm->pit_in_kernel)
337 return 0;
338 return kvm_vm_ioctl(kvm_state, KVM_SET_PIT2, ps2);
339 }
340
341 #endif
342 #endif
343
344 int kvm_has_pit_state2(kvm_context_t kvm)
345 {
346 int r = 0;
347
348 #ifdef KVM_CAP_PIT_STATE2
349 r = kvm_check_extension(kvm_state, KVM_CAP_PIT_STATE2);
350 #endif
351 return r;
352 }
353
354 void kvm_show_code(CPUState *env)
355 {
356 #define SHOW_CODE_LEN 50
357 struct kvm_regs regs;
358 struct kvm_sregs sregs;
359 int r, n;
360 int back_offset;
361 unsigned char code;
362 char code_str[SHOW_CODE_LEN * 3 + 1];
363 unsigned long rip;
364
365 r = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
366 if (r < 0 ) {
367 perror("KVM_GET_SREGS");
368 return;
369 }
370 r = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
371 if (r < 0) {
372 perror("KVM_GET_REGS");
373 return;
374 }
375 rip = sregs.cs.base + regs.rip;
376 back_offset = regs.rip;
377 if (back_offset > 20)
378 back_offset = 20;
379 *code_str = 0;
380 for (n = -back_offset; n < SHOW_CODE_LEN-back_offset; ++n) {
381 if (n == 0)
382 strcat(code_str, " -->");
383 cpu_physical_memory_rw(rip + n, &code, 1, 1);
384 sprintf(code_str + strlen(code_str), " %02x", code);
385 }
386 fprintf(stderr, "code:%s\n", code_str);
387 }
388
389
390 /*
391 * Returns available msr list. User must free.
392 */
393 struct kvm_msr_list *kvm_get_msr_list(kvm_context_t kvm)
394 {
395 struct kvm_msr_list sizer, *msrs;
396 int r;
397
398 sizer.nmsrs = 0;
399 r = kvm_ioctl(kvm_state, KVM_GET_MSR_INDEX_LIST, &sizer);
400 if (r < 0 && r != -E2BIG)
401 return NULL;
402 /* Old kernel modules had a bug and could write beyond the provided
403 memory. Allocate at least a safe amount of 1K. */
404 msrs = qemu_malloc(MAX(1024, sizeof(*msrs) +
405 sizer.nmsrs * sizeof(*msrs->indices)));
406
407 msrs->nmsrs = sizer.nmsrs;
408 r = kvm_ioctl(kvm_state, KVM_GET_MSR_INDEX_LIST, msrs);
409 if (r < 0) {
410 free(msrs);
411 errno = r;
412 return NULL;
413 }
414 return msrs;
415 }
416
417 int kvm_get_msrs(CPUState *env, struct kvm_msr_entry *msrs, int n)
418 {
419 struct kvm_msrs *kmsrs = qemu_malloc(sizeof *kmsrs + n * sizeof *msrs);
420 int r;
421
422 kmsrs->nmsrs = n;
423 memcpy(kmsrs->entries, msrs, n * sizeof *msrs);
424 r = kvm_vcpu_ioctl(env, KVM_GET_MSRS, kmsrs);
425 memcpy(msrs, kmsrs->entries, n * sizeof *msrs);
426 free(kmsrs);
427 return r;
428 }
429
430 int kvm_set_msrs(CPUState *env, struct kvm_msr_entry *msrs, int n)
431 {
432 struct kvm_msrs *kmsrs = qemu_malloc(sizeof *kmsrs + n * sizeof *msrs);
433 int r;
434
435 kmsrs->nmsrs = n;
436 memcpy(kmsrs->entries, msrs, n * sizeof *msrs);
437 r = kvm_vcpu_ioctl(env, KVM_SET_MSRS, kmsrs);
438 free(kmsrs);
439 return r;
440 }
441
442 int kvm_get_mce_cap_supported(kvm_context_t kvm, uint64_t *mce_cap,
443 int *max_banks)
444 {
445 #ifdef KVM_CAP_MCE
446 int r;
447
448 r = kvm_ioctl(kvm_state, KVM_CHECK_EXTENSION, KVM_CAP_MCE);
449 if (r > 0) {
450 *max_banks = r;
451 return kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
452 }
453 #endif
454 return -ENOSYS;
455 }
456
457 int kvm_setup_mce(CPUState *env, uint64_t *mcg_cap)
458 {
459 #ifdef KVM_CAP_MCE
460 return kvm_vcpu_ioctl(env, KVM_X86_SETUP_MCE, mcg_cap);
461 #else
462 return -ENOSYS;
463 #endif
464 }
465
466 int kvm_set_mce(CPUState *env, struct kvm_x86_mce *m)
467 {
468 #ifdef KVM_CAP_MCE
469 return kvm_vcpu_ioctl(env, KVM_X86_SET_MCE, m);
470 #else
471 return -ENOSYS;
472 #endif
473 }
474
475 static void print_seg(FILE *file, const char *name, struct kvm_segment *seg)
476 {
477 fprintf(stderr,
478 "%s %04x (%08llx/%08x p %d dpl %d db %d s %d type %x l %d"
479 " g %d avl %d)\n",
480 name, seg->selector, seg->base, seg->limit, seg->present,
481 seg->dpl, seg->db, seg->s, seg->type, seg->l, seg->g,
482 seg->avl);
483 }
484
485 static void print_dt(FILE *file, const char *name, struct kvm_dtable *dt)
486 {
487 fprintf(stderr, "%s %llx/%x\n", name, dt->base, dt->limit);
488 }
489
490 void kvm_show_regs(CPUState *env)
491 {
492 struct kvm_regs regs;
493 struct kvm_sregs sregs;
494 int r;
495
496 r = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
497 if (r < 0) {
498 perror("KVM_GET_REGS");
499 return;
500 }
501 fprintf(stderr,
502 "rax %016llx rbx %016llx rcx %016llx rdx %016llx\n"
503 "rsi %016llx rdi %016llx rsp %016llx rbp %016llx\n"
504 "r8 %016llx r9 %016llx r10 %016llx r11 %016llx\n"
505 "r12 %016llx r13 %016llx r14 %016llx r15 %016llx\n"
506 "rip %016llx rflags %08llx\n",
507 regs.rax, regs.rbx, regs.rcx, regs.rdx,
508 regs.rsi, regs.rdi, regs.rsp, regs.rbp,
509 regs.r8, regs.r9, regs.r10, regs.r11,
510 regs.r12, regs.r13, regs.r14, regs.r15,
511 regs.rip, regs.rflags);
512 r = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
513 if (r < 0) {
514 perror("KVM_GET_SREGS");
515 return;
516 }
517 print_seg(stderr, "cs", &sregs.cs);
518 print_seg(stderr, "ds", &sregs.ds);
519 print_seg(stderr, "es", &sregs.es);
520 print_seg(stderr, "ss", &sregs.ss);
521 print_seg(stderr, "fs", &sregs.fs);
522 print_seg(stderr, "gs", &sregs.gs);
523 print_seg(stderr, "tr", &sregs.tr);
524 print_seg(stderr, "ldt", &sregs.ldt);
525 print_dt(stderr, "gdt", &sregs.gdt);
526 print_dt(stderr, "idt", &sregs.idt);
527 fprintf(stderr, "cr0 %llx cr2 %llx cr3 %llx cr4 %llx cr8 %llx"
528 " efer %llx\n",
529 sregs.cr0, sregs.cr2, sregs.cr3, sregs.cr4, sregs.cr8,
530 sregs.efer);
531 }
532
533 static void kvm_set_cr8(CPUState *env, uint64_t cr8)
534 {
535 env->kvm_run->cr8 = cr8;
536 }
537
538 int kvm_setup_cpuid(CPUState *env, int nent,
539 struct kvm_cpuid_entry *entries)
540 {
541 struct kvm_cpuid *cpuid;
542 int r;
543
544 cpuid = qemu_malloc(sizeof(*cpuid) + nent * sizeof(*entries));
545
546 cpuid->nent = nent;
547 memcpy(cpuid->entries, entries, nent * sizeof(*entries));
548 r = kvm_vcpu_ioctl(env, KVM_SET_CPUID, cpuid);
549
550 free(cpuid);
551 return r;
552 }
553
554 int kvm_setup_cpuid2(CPUState *env, int nent,
555 struct kvm_cpuid_entry2 *entries)
556 {
557 struct kvm_cpuid2 *cpuid;
558 int r;
559
560 cpuid = qemu_malloc(sizeof(*cpuid) + nent * sizeof(*entries));
561
562 cpuid->nent = nent;
563 memcpy(cpuid->entries, entries, nent * sizeof(*entries));
564 r = kvm_vcpu_ioctl(env, KVM_SET_CPUID2, cpuid);
565 free(cpuid);
566 return r;
567 }
568
569 int kvm_set_shadow_pages(kvm_context_t kvm, unsigned int nrshadow_pages)
570 {
571 #ifdef KVM_CAP_MMU_SHADOW_CACHE_CONTROL
572 int r;
573
574 r = kvm_ioctl(kvm_state, KVM_CHECK_EXTENSION,
575 KVM_CAP_MMU_SHADOW_CACHE_CONTROL);
576 if (r > 0) {
577 r = kvm_vm_ioctl(kvm_state, KVM_SET_NR_MMU_PAGES, nrshadow_pages);
578 if (r < 0) {
579 fprintf(stderr, "kvm_set_shadow_pages: %m\n");
580 return r;
581 }
582 return 0;
583 }
584 #endif
585 return -1;
586 }
587
588 int kvm_get_shadow_pages(kvm_context_t kvm, unsigned int *nrshadow_pages)
589 {
590 #ifdef KVM_CAP_MMU_SHADOW_CACHE_CONTROL
591 int r;
592
593 r = kvm_ioctl(kvm_state, KVM_CHECK_EXTENSION,
594 KVM_CAP_MMU_SHADOW_CACHE_CONTROL);
595 if (r > 0) {
596 *nrshadow_pages = kvm_vm_ioctl(kvm_state, KVM_GET_NR_MMU_PAGES);
597 return 0;
598 }
599 #endif
600 return -1;
601 }
602
603 #ifdef KVM_CAP_VAPIC
604
605 static int tpr_access_reporting(CPUState *env, int enabled)
606 {
607 int r;
608 struct kvm_tpr_access_ctl tac = {
609 .enabled = enabled,
610 };
611
612 r = kvm_ioctl(kvm_state, KVM_CHECK_EXTENSION, KVM_CAP_VAPIC);
613 if (r <= 0)
614 return -ENOSYS;
615 return kvm_vcpu_ioctl(env, KVM_TPR_ACCESS_REPORTING, &tac);
616 }
617
618 int kvm_enable_tpr_access_reporting(CPUState *env)
619 {
620 return tpr_access_reporting(env, 1);
621 }
622
623 int kvm_disable_tpr_access_reporting(CPUState *env)
624 {
625 return tpr_access_reporting(env, 0);
626 }
627
628 #endif
629
630 #ifdef KVM_CAP_EXT_CPUID
631
632 static struct kvm_cpuid2 *try_get_cpuid(kvm_context_t kvm, int max)
633 {
634 struct kvm_cpuid2 *cpuid;
635 int r, size;
636
637 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
638 cpuid = qemu_malloc(size);
639 cpuid->nent = max;
640 r = kvm_ioctl(kvm_state, KVM_GET_SUPPORTED_CPUID, cpuid);
641 if (r == 0 && cpuid->nent >= max)
642 r = -E2BIG;
643 if (r < 0) {
644 if (r == -E2BIG) {
645 free(cpuid);
646 return NULL;
647 } else {
648 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
649 strerror(-r));
650 exit(1);
651 }
652 }
653 return cpuid;
654 }
655
656 #define R_EAX 0
657 #define R_ECX 1
658 #define R_EDX 2
659 #define R_EBX 3
660 #define R_ESP 4
661 #define R_EBP 5
662 #define R_ESI 6
663 #define R_EDI 7
664
665 uint32_t kvm_get_supported_cpuid(kvm_context_t kvm, uint32_t function, int reg)
666 {
667 struct kvm_cpuid2 *cpuid;
668 int i, max;
669 uint32_t ret = 0;
670 uint32_t cpuid_1_edx;
671
672 if (!kvm_check_extension(kvm_state, KVM_CAP_EXT_CPUID)) {
673 return -1U;
674 }
675
676 max = 1;
677 while ((cpuid = try_get_cpuid(kvm, max)) == NULL) {
678 max *= 2;
679 }
680
681 for (i = 0; i < cpuid->nent; ++i) {
682 if (cpuid->entries[i].function == function) {
683 switch (reg) {
684 case R_EAX:
685 ret = cpuid->entries[i].eax;
686 break;
687 case R_EBX:
688 ret = cpuid->entries[i].ebx;
689 break;
690 case R_ECX:
691 ret = cpuid->entries[i].ecx;
692 break;
693 case R_EDX:
694 ret = cpuid->entries[i].edx;
695 if (function == 1) {
696 /* kvm misreports the following features
697 */
698 ret |= 1 << 12; /* MTRR */
699 ret |= 1 << 16; /* PAT */
700 ret |= 1 << 7; /* MCE */
701 ret |= 1 << 14; /* MCA */
702 }
703
704 /* On Intel, kvm returns cpuid according to
705 * the Intel spec, so add missing bits
706 * according to the AMD spec:
707 */
708 if (function == 0x80000001) {
709 cpuid_1_edx = kvm_get_supported_cpuid(kvm, 1, R_EDX);
710 ret |= cpuid_1_edx & 0xdfeff7ff;
711 }
712 break;
713 }
714 }
715 }
716
717 free(cpuid);
718
719 return ret;
720 }
721
722 #else
723
724 uint32_t kvm_get_supported_cpuid(kvm_context_t kvm, uint32_t function, int reg)
725 {
726 return -1U;
727 }
728
729 #endif
730 int kvm_qemu_create_memory_alias(uint64_t phys_start,
731 uint64_t len,
732 uint64_t target_phys)
733 {
734 return kvm_create_memory_alias(kvm_context, phys_start, len, target_phys);
735 }
736
737 int kvm_qemu_destroy_memory_alias(uint64_t phys_start)
738 {
739 return kvm_destroy_memory_alias(kvm_context, phys_start);
740 }
741
742 #ifdef KVM_CAP_ADJUST_CLOCK
743 static struct kvm_clock_data kvmclock_data;
744
745 static void kvmclock_pre_save(void *opaque)
746 {
747 struct kvm_clock_data *cl = opaque;
748
749 kvm_vm_ioctl(kvm_state, KVM_GET_CLOCK, cl);
750 }
751
752 static int kvmclock_post_load(void *opaque, int version_id)
753 {
754 struct kvm_clock_data *cl = opaque;
755
756 return kvm_vm_ioctl(kvm_state, KVM_SET_CLOCK, cl);
757 }
758
759 static const VMStateDescription vmstate_kvmclock= {
760 .name = "kvmclock",
761 .version_id = 1,
762 .minimum_version_id = 1,
763 .minimum_version_id_old = 1,
764 .pre_save = kvmclock_pre_save,
765 .post_load = kvmclock_post_load,
766 .fields = (VMStateField []) {
767 VMSTATE_U64(clock, struct kvm_clock_data),
768 VMSTATE_END_OF_LIST()
769 }
770 };
771 #endif
772
773 int kvm_arch_qemu_create_context(void)
774 {
775 int i;
776 struct utsname utsname;
777
778 uname(&utsname);
779 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
780
781 if (kvm_shadow_memory)
782 kvm_set_shadow_pages(kvm_context, kvm_shadow_memory);
783
784 kvm_msr_list = kvm_get_msr_list(kvm_context);
785 if (!kvm_msr_list)
786 return -1;
787 for (i = 0; i < kvm_msr_list->nmsrs; ++i) {
788 if (kvm_msr_list->indices[i] == MSR_STAR)
789 kvm_has_msr_star = 1;
790 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA)
791 kvm_has_vm_hsave_pa = 1;
792 }
793
794 #ifdef KVM_CAP_ADJUST_CLOCK
795 if (kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK))
796 vmstate_register(0, &vmstate_kvmclock, &kvmclock_data);
797 #endif
798 return 0;
799 }
800
801 static void set_msr_entry(struct kvm_msr_entry *entry, uint32_t index,
802 uint64_t data)
803 {
804 entry->index = index;
805 entry->data = data;
806 }
807
808 /* returns 0 on success, non-0 on failure */
809 static int get_msr_entry(struct kvm_msr_entry *entry, CPUState *env)
810 {
811 switch (entry->index) {
812 case MSR_IA32_SYSENTER_CS:
813 env->sysenter_cs = entry->data;
814 break;
815 case MSR_IA32_SYSENTER_ESP:
816 env->sysenter_esp = entry->data;
817 break;
818 case MSR_IA32_SYSENTER_EIP:
819 env->sysenter_eip = entry->data;
820 break;
821 case MSR_STAR:
822 env->star = entry->data;
823 break;
824 #ifdef TARGET_X86_64
825 case MSR_CSTAR:
826 env->cstar = entry->data;
827 break;
828 case MSR_KERNELGSBASE:
829 env->kernelgsbase = entry->data;
830 break;
831 case MSR_FMASK:
832 env->fmask = entry->data;
833 break;
834 case MSR_LSTAR:
835 env->lstar = entry->data;
836 break;
837 #endif
838 case MSR_IA32_TSC:
839 env->tsc = entry->data;
840 break;
841 case MSR_VM_HSAVE_PA:
842 env->vm_hsave = entry->data;
843 break;
844 case MSR_KVM_SYSTEM_TIME:
845 env->system_time_msr = entry->data;
846 break;
847 case MSR_KVM_WALL_CLOCK:
848 env->wall_clock_msr = entry->data;
849 break;
850 default:
851 printf("Warning unknown msr index 0x%x\n", entry->index);
852 return 1;
853 }
854 return 0;
855 }
856
857 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
858 {
859 lhs->selector = rhs->selector;
860 lhs->base = rhs->base;
861 lhs->limit = rhs->limit;
862 lhs->type = 3;
863 lhs->present = 1;
864 lhs->dpl = 3;
865 lhs->db = 0;
866 lhs->s = 1;
867 lhs->l = 0;
868 lhs->g = 0;
869 lhs->avl = 0;
870 lhs->unusable = 0;
871 }
872
873 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
874 {
875 unsigned flags = rhs->flags;
876 lhs->selector = rhs->selector;
877 lhs->base = rhs->base;
878 lhs->limit = rhs->limit;
879 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
880 lhs->present = (flags & DESC_P_MASK) != 0;
881 lhs->dpl = rhs->selector & 3;
882 lhs->db = (flags >> DESC_B_SHIFT) & 1;
883 lhs->s = (flags & DESC_S_MASK) != 0;
884 lhs->l = (flags >> DESC_L_SHIFT) & 1;
885 lhs->g = (flags & DESC_G_MASK) != 0;
886 lhs->avl = (flags & DESC_AVL_MASK) != 0;
887 lhs->unusable = 0;
888 }
889
890 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
891 {
892 lhs->selector = rhs->selector;
893 lhs->base = rhs->base;
894 lhs->limit = rhs->limit;
895 lhs->flags =
896 (rhs->type << DESC_TYPE_SHIFT)
897 | (rhs->present * DESC_P_MASK)
898 | (rhs->dpl << DESC_DPL_SHIFT)
899 | (rhs->db << DESC_B_SHIFT)
900 | (rhs->s * DESC_S_MASK)
901 | (rhs->l << DESC_L_SHIFT)
902 | (rhs->g * DESC_G_MASK)
903 | (rhs->avl * DESC_AVL_MASK);
904 }
905
906 void kvm_arch_load_regs(CPUState *env)
907 {
908 struct kvm_regs regs;
909 struct kvm_fpu fpu;
910 struct kvm_sregs sregs;
911 struct kvm_msr_entry msrs[100];
912 int rc, n, i;
913
914 regs.rax = env->regs[R_EAX];
915 regs.rbx = env->regs[R_EBX];
916 regs.rcx = env->regs[R_ECX];
917 regs.rdx = env->regs[R_EDX];
918 regs.rsi = env->regs[R_ESI];
919 regs.rdi = env->regs[R_EDI];
920 regs.rsp = env->regs[R_ESP];
921 regs.rbp = env->regs[R_EBP];
922 #ifdef TARGET_X86_64
923 regs.r8 = env->regs[8];
924 regs.r9 = env->regs[9];
925 regs.r10 = env->regs[10];
926 regs.r11 = env->regs[11];
927 regs.r12 = env->regs[12];
928 regs.r13 = env->regs[13];
929 regs.r14 = env->regs[14];
930 regs.r15 = env->regs[15];
931 #endif
932
933 regs.rflags = env->eflags;
934 regs.rip = env->eip;
935
936 kvm_set_regs(env, &regs);
937
938 memset(&fpu, 0, sizeof fpu);
939 fpu.fsw = env->fpus & ~(7 << 11);
940 fpu.fsw |= (env->fpstt & 7) << 11;
941 fpu.fcw = env->fpuc;
942 for (i = 0; i < 8; ++i)
943 fpu.ftwx |= (!env->fptags[i]) << i;
944 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
945 memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
946 fpu.mxcsr = env->mxcsr;
947 kvm_set_fpu(env, &fpu);
948
949 memcpy(sregs.interrupt_bitmap, env->interrupt_bitmap, sizeof(sregs.interrupt_bitmap));
950
951 if ((env->eflags & VM_MASK)) {
952 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
953 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
954 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
955 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
956 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
957 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
958 } else {
959 set_seg(&sregs.cs, &env->segs[R_CS]);
960 set_seg(&sregs.ds, &env->segs[R_DS]);
961 set_seg(&sregs.es, &env->segs[R_ES]);
962 set_seg(&sregs.fs, &env->segs[R_FS]);
963 set_seg(&sregs.gs, &env->segs[R_GS]);
964 set_seg(&sregs.ss, &env->segs[R_SS]);
965
966 if (env->cr[0] & CR0_PE_MASK) {
967 /* force ss cpl to cs cpl */
968 sregs.ss.selector = (sregs.ss.selector & ~3) |
969 (sregs.cs.selector & 3);
970 sregs.ss.dpl = sregs.ss.selector & 3;
971 }
972 }
973
974 set_seg(&sregs.tr, &env->tr);
975 set_seg(&sregs.ldt, &env->ldt);
976
977 sregs.idt.limit = env->idt.limit;
978 sregs.idt.base = env->idt.base;
979 sregs.gdt.limit = env->gdt.limit;
980 sregs.gdt.base = env->gdt.base;
981
982 sregs.cr0 = env->cr[0];
983 sregs.cr2 = env->cr[2];
984 sregs.cr3 = env->cr[3];
985 sregs.cr4 = env->cr[4];
986
987 sregs.cr8 = cpu_get_apic_tpr(env);
988 sregs.apic_base = cpu_get_apic_base(env);
989
990 sregs.efer = env->efer;
991
992 kvm_set_sregs(env, &sregs);
993
994 /* msrs */
995 n = 0;
996 /* Remember to increase msrs size if you add new registers below */
997 set_msr_entry(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
998 set_msr_entry(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
999 set_msr_entry(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1000 if (kvm_has_msr_star)
1001 set_msr_entry(&msrs[n++], MSR_STAR, env->star);
1002 if (kvm_has_vm_hsave_pa)
1003 set_msr_entry(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
1004 #ifdef TARGET_X86_64
1005 if (lm_capable_kernel) {
1006 set_msr_entry(&msrs[n++], MSR_CSTAR, env->cstar);
1007 set_msr_entry(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
1008 set_msr_entry(&msrs[n++], MSR_FMASK, env->fmask);
1009 set_msr_entry(&msrs[n++], MSR_LSTAR , env->lstar);
1010 }
1011 #endif
1012 set_msr_entry(&msrs[n++], MSR_KVM_SYSTEM_TIME, env->system_time_msr);
1013 set_msr_entry(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1014
1015 rc = kvm_set_msrs(env, msrs, n);
1016 if (rc == -1)
1017 perror("kvm_set_msrs FAILED");
1018 }
1019
1020 void kvm_load_tsc(CPUState *env)
1021 {
1022 int rc;
1023 struct kvm_msr_entry msr;
1024
1025 set_msr_entry(&msr, MSR_IA32_TSC, env->tsc);
1026
1027 rc = kvm_set_msrs(env, &msr, 1);
1028 if (rc == -1)
1029 perror("kvm_set_tsc FAILED.\n");
1030 }
1031
1032 void kvm_arch_save_mpstate(CPUState *env)
1033 {
1034 #ifdef KVM_CAP_MP_STATE
1035 int r;
1036 struct kvm_mp_state mp_state;
1037
1038 r = kvm_get_mpstate(env, &mp_state);
1039 if (r < 0)
1040 env->mp_state = -1;
1041 else
1042 env->mp_state = mp_state.mp_state;
1043 #else
1044 env->mp_state = -1;
1045 #endif
1046 }
1047
1048 void kvm_arch_load_mpstate(CPUState *env)
1049 {
1050 #ifdef KVM_CAP_MP_STATE
1051 struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
1052
1053 /*
1054 * -1 indicates that the host did not support GET_MP_STATE ioctl,
1055 * so don't touch it.
1056 */
1057 if (env->mp_state != -1)
1058 kvm_set_mpstate(env, &mp_state);
1059 #endif
1060 }
1061
1062 void kvm_arch_save_regs(CPUState *env)
1063 {
1064 struct kvm_regs regs;
1065 struct kvm_fpu fpu;
1066 struct kvm_sregs sregs;
1067 struct kvm_msr_entry msrs[100];
1068 uint32_t hflags;
1069 uint32_t i, n, rc;
1070
1071 kvm_get_regs(env, &regs);
1072
1073 env->regs[R_EAX] = regs.rax;
1074 env->regs[R_EBX] = regs.rbx;
1075 env->regs[R_ECX] = regs.rcx;
1076 env->regs[R_EDX] = regs.rdx;
1077 env->regs[R_ESI] = regs.rsi;
1078 env->regs[R_EDI] = regs.rdi;
1079 env->regs[R_ESP] = regs.rsp;
1080 env->regs[R_EBP] = regs.rbp;
1081 #ifdef TARGET_X86_64
1082 env->regs[8] = regs.r8;
1083 env->regs[9] = regs.r9;
1084 env->regs[10] = regs.r10;
1085 env->regs[11] = regs.r11;
1086 env->regs[12] = regs.r12;
1087 env->regs[13] = regs.r13;
1088 env->regs[14] = regs.r14;
1089 env->regs[15] = regs.r15;
1090 #endif
1091
1092 env->eflags = regs.rflags;
1093 env->eip = regs.rip;
1094
1095 kvm_get_fpu(env, &fpu);
1096 env->fpstt = (fpu.fsw >> 11) & 7;
1097 env->fpus = fpu.fsw;
1098 env->fpuc = fpu.fcw;
1099 for (i = 0; i < 8; ++i)
1100 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1101 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1102 memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
1103 env->mxcsr = fpu.mxcsr;
1104
1105 kvm_get_sregs(env, &sregs);
1106
1107 memcpy(env->interrupt_bitmap, sregs.interrupt_bitmap, sizeof(env->interrupt_bitmap));
1108
1109 get_seg(&env->segs[R_CS], &sregs.cs);
1110 get_seg(&env->segs[R_DS], &sregs.ds);
1111 get_seg(&env->segs[R_ES], &sregs.es);
1112 get_seg(&env->segs[R_FS], &sregs.fs);
1113 get_seg(&env->segs[R_GS], &sregs.gs);
1114 get_seg(&env->segs[R_SS], &sregs.ss);
1115
1116 get_seg(&env->tr, &sregs.tr);
1117 get_seg(&env->ldt, &sregs.ldt);
1118
1119 env->idt.limit = sregs.idt.limit;
1120 env->idt.base = sregs.idt.base;
1121 env->gdt.limit = sregs.gdt.limit;
1122 env->gdt.base = sregs.gdt.base;
1123
1124 env->cr[0] = sregs.cr0;
1125 env->cr[2] = sregs.cr2;
1126 env->cr[3] = sregs.cr3;
1127 env->cr[4] = sregs.cr4;
1128
1129 cpu_set_apic_base(env, sregs.apic_base);
1130
1131 env->efer = sregs.efer;
1132 //cpu_set_apic_tpr(env, sregs.cr8);
1133
1134 #define HFLAG_COPY_MASK ~( \
1135 HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1136 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1137 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1138 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1139
1140
1141
1142 hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1143 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1144 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1145 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1146 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1147 hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
1148 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
1149
1150 if (env->efer & MSR_EFER_LMA) {
1151 hflags |= HF_LMA_MASK;
1152 }
1153
1154 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1155 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1156 } else {
1157 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1158 (DESC_B_SHIFT - HF_CS32_SHIFT);
1159 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1160 (DESC_B_SHIFT - HF_SS32_SHIFT);
1161 if (!(env->cr[0] & CR0_PE_MASK) ||
1162 (env->eflags & VM_MASK) ||
1163 !(hflags & HF_CS32_MASK)) {
1164 hflags |= HF_ADDSEG_MASK;
1165 } else {
1166 hflags |= ((env->segs[R_DS].base |
1167 env->segs[R_ES].base |
1168 env->segs[R_SS].base) != 0) <<
1169 HF_ADDSEG_SHIFT;
1170 }
1171 }
1172 env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
1173
1174 /* msrs */
1175 n = 0;
1176 /* Remember to increase msrs size if you add new registers below */
1177 msrs[n++].index = MSR_IA32_SYSENTER_CS;
1178 msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1179 msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1180 if (kvm_has_msr_star)
1181 msrs[n++].index = MSR_STAR;
1182 msrs[n++].index = MSR_IA32_TSC;
1183 if (kvm_has_vm_hsave_pa)
1184 msrs[n++].index = MSR_VM_HSAVE_PA;
1185 #ifdef TARGET_X86_64
1186 if (lm_capable_kernel) {
1187 msrs[n++].index = MSR_CSTAR;
1188 msrs[n++].index = MSR_KERNELGSBASE;
1189 msrs[n++].index = MSR_FMASK;
1190 msrs[n++].index = MSR_LSTAR;
1191 }
1192 #endif
1193 msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1194 msrs[n++].index = MSR_KVM_WALL_CLOCK;
1195
1196 rc = kvm_get_msrs(env, msrs, n);
1197 if (rc == -1) {
1198 perror("kvm_get_msrs FAILED");
1199 }
1200 else {
1201 n = rc; /* actual number of MSRs */
1202 for (i=0 ; i<n; i++) {
1203 if (get_msr_entry(&msrs[i], env))
1204 return;
1205 }
1206 }
1207 }
1208
1209 static void do_cpuid_ent(struct kvm_cpuid_entry2 *e, uint32_t function,
1210 uint32_t count, CPUState *env)
1211 {
1212 env->regs[R_EAX] = function;
1213 env->regs[R_ECX] = count;
1214 qemu_kvm_cpuid_on_env(env);
1215 e->function = function;
1216 e->flags = 0;
1217 e->index = 0;
1218 e->eax = env->regs[R_EAX];
1219 e->ebx = env->regs[R_EBX];
1220 e->ecx = env->regs[R_ECX];
1221 e->edx = env->regs[R_EDX];
1222 }
1223
1224 struct kvm_para_features {
1225 int cap;
1226 int feature;
1227 } para_features[] = {
1228 #ifdef KVM_CAP_CLOCKSOURCE
1229 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
1230 #endif
1231 #ifdef KVM_CAP_NOP_IO_DELAY
1232 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
1233 #endif
1234 #ifdef KVM_CAP_PV_MMU
1235 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
1236 #endif
1237 #ifdef KVM_CAP_CR3_CACHE
1238 { KVM_CAP_CR3_CACHE, KVM_FEATURE_CR3_CACHE },
1239 #endif
1240 { -1, -1 }
1241 };
1242
1243 static int get_para_features(kvm_context_t kvm_context)
1244 {
1245 int i, features = 0;
1246
1247 for (i = 0; i < ARRAY_SIZE(para_features)-1; i++) {
1248 if (kvm_check_extension(kvm_state, para_features[i].cap))
1249 features |= (1 << para_features[i].feature);
1250 }
1251
1252 return features;
1253 }
1254
1255 static void kvm_trim_features(uint32_t *features, uint32_t supported)
1256 {
1257 int i;
1258 uint32_t mask;
1259
1260 for (i = 0; i < 32; ++i) {
1261 mask = 1U << i;
1262 if ((*features & mask) && !(supported & mask)) {
1263 *features &= ~mask;
1264 }
1265 }
1266 }
1267
1268 int kvm_arch_init_vcpu(CPUState *cenv)
1269 {
1270 struct kvm_cpuid_entry2 cpuid_ent[100];
1271 #ifdef KVM_CPUID_SIGNATURE
1272 struct kvm_cpuid_entry2 *pv_ent;
1273 uint32_t signature[3];
1274 #endif
1275 int cpuid_nent = 0;
1276 CPUState copy;
1277 uint32_t i, j, limit;
1278
1279 qemu_kvm_load_lapic(cenv);
1280
1281
1282 #ifdef KVM_CPUID_SIGNATURE
1283 /* Paravirtualization CPUIDs */
1284 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
1285 pv_ent = &cpuid_ent[cpuid_nent++];
1286 memset(pv_ent, 0, sizeof(*pv_ent));
1287 pv_ent->function = KVM_CPUID_SIGNATURE;
1288 pv_ent->eax = 0;
1289 pv_ent->ebx = signature[0];
1290 pv_ent->ecx = signature[1];
1291 pv_ent->edx = signature[2];
1292
1293 pv_ent = &cpuid_ent[cpuid_nent++];
1294 memset(pv_ent, 0, sizeof(*pv_ent));
1295 pv_ent->function = KVM_CPUID_FEATURES;
1296 pv_ent->eax = get_para_features(kvm_context);
1297 #endif
1298
1299 kvm_trim_features(&cenv->cpuid_features,
1300 kvm_arch_get_supported_cpuid(cenv, 1, R_EDX));
1301
1302 /* prevent the hypervisor bit from being cleared by the kernel */
1303 i = cenv->cpuid_ext_features & CPUID_EXT_HYPERVISOR;
1304 kvm_trim_features(&cenv->cpuid_ext_features,
1305 kvm_arch_get_supported_cpuid(cenv, 1, R_ECX));
1306 cenv->cpuid_ext_features |= i;
1307
1308 kvm_trim_features(&cenv->cpuid_ext2_features,
1309 kvm_arch_get_supported_cpuid(cenv, 0x80000001, R_EDX));
1310 kvm_trim_features(&cenv->cpuid_ext3_features,
1311 kvm_arch_get_supported_cpuid(cenv, 0x80000001, R_ECX));
1312
1313 copy = *cenv;
1314
1315 copy.regs[R_EAX] = 0;
1316 qemu_kvm_cpuid_on_env(&copy);
1317 limit = copy.regs[R_EAX];
1318
1319 for (i = 0; i <= limit; ++i) {
1320 if (i == 4 || i == 0xb || i == 0xd) {
1321 for (j = 0; ; ++j) {
1322 do_cpuid_ent(&cpuid_ent[cpuid_nent], i, j, &copy);
1323
1324 cpuid_ent[cpuid_nent].flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1325 cpuid_ent[cpuid_nent].index = j;
1326
1327 cpuid_nent++;
1328
1329 if (i == 4 && copy.regs[R_EAX] == 0)
1330 break;
1331 if (i == 0xb && !(copy.regs[R_ECX] & 0xff00))
1332 break;
1333 if (i == 0xd && copy.regs[R_EAX] == 0)
1334 break;
1335 }
1336 } else
1337 do_cpuid_ent(&cpuid_ent[cpuid_nent++], i, 0, &copy);
1338 }
1339
1340 copy.regs[R_EAX] = 0x80000000;
1341 qemu_kvm_cpuid_on_env(&copy);
1342 limit = copy.regs[R_EAX];
1343
1344 for (i = 0x80000000; i <= limit; ++i)
1345 do_cpuid_ent(&cpuid_ent[cpuid_nent++], i, 0, &copy);
1346
1347 kvm_setup_cpuid2(cenv, cpuid_nent, cpuid_ent);
1348
1349 #ifdef KVM_CAP_MCE
1350 if (((cenv->cpuid_version >> 8)&0xF) >= 6
1351 && (cenv->cpuid_features&(CPUID_MCE|CPUID_MCA)) == (CPUID_MCE|CPUID_MCA)
1352 && kvm_check_extension(kvm_state, KVM_CAP_MCE) > 0) {
1353 uint64_t mcg_cap;
1354 int banks;
1355
1356 if (kvm_get_mce_cap_supported(kvm_context, &mcg_cap, &banks))
1357 perror("kvm_get_mce_cap_supported FAILED");
1358 else {
1359 if (banks > MCE_BANKS_DEF)
1360 banks = MCE_BANKS_DEF;
1361 mcg_cap &= MCE_CAP_DEF;
1362 mcg_cap |= banks;
1363 if (kvm_setup_mce(cenv, &mcg_cap))
1364 perror("kvm_setup_mce FAILED");
1365 else
1366 cenv->mcg_cap = mcg_cap;
1367 }
1368 }
1369 #endif
1370
1371 #ifdef KVM_EXIT_TPR_ACCESS
1372 kvm_tpr_vcpu_start(cenv);
1373 #endif
1374 return 0;
1375 }
1376
1377 int kvm_arch_halt(CPUState *env)
1378 {
1379
1380 if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1381 (env->eflags & IF_MASK)) &&
1382 !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
1383 env->halted = 1;
1384 }
1385 return 1;
1386 }
1387
1388 int kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
1389 {
1390 if (!kvm_irqchip_in_kernel())
1391 kvm_set_cr8(env, cpu_get_apic_tpr(env));
1392 return 0;
1393 }
1394
1395 int kvm_arch_has_work(CPUState *env)
1396 {
1397 if (((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1398 (env->eflags & IF_MASK)) ||
1399 (env->interrupt_request & CPU_INTERRUPT_NMI))
1400 return 1;
1401 return 0;
1402 }
1403
1404 int kvm_arch_try_push_interrupts(void *opaque)
1405 {
1406 CPUState *env = cpu_single_env;
1407 int r, irq;
1408
1409 if (kvm_is_ready_for_interrupt_injection(env) &&
1410 (env->interrupt_request & CPU_INTERRUPT_HARD) &&
1411 (env->eflags & IF_MASK)) {
1412 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1413 irq = cpu_get_pic_interrupt(env);
1414 if (irq >= 0) {
1415 r = kvm_inject_irq(env, irq);
1416 if (r < 0)
1417 printf("cpu %d fail inject %x\n", env->cpu_index, irq);
1418 }
1419 }
1420
1421 return (env->interrupt_request & CPU_INTERRUPT_HARD) != 0;
1422 }
1423
1424 #ifdef KVM_CAP_USER_NMI
1425 void kvm_arch_push_nmi(void *opaque)
1426 {
1427 CPUState *env = cpu_single_env;
1428 int r;
1429
1430 if (likely(!(env->interrupt_request & CPU_INTERRUPT_NMI)))
1431 return;
1432
1433 env->interrupt_request &= ~CPU_INTERRUPT_NMI;
1434 r = kvm_inject_nmi(env);
1435 if (r < 0)
1436 printf("cpu %d fail inject NMI\n", env->cpu_index);
1437 }
1438 #endif /* KVM_CAP_USER_NMI */
1439
1440 void kvm_arch_cpu_reset(CPUState *env)
1441 {
1442 kvm_arch_load_regs(env);
1443 if (!cpu_is_bsp(env)) {
1444 if (kvm_irqchip_in_kernel()) {
1445 #ifdef KVM_CAP_MP_STATE
1446 kvm_reset_mpstate(env);
1447 #endif
1448 } else {
1449 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1450 env->halted = 1;
1451 }
1452 }
1453 }
1454
1455 int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1456 {
1457 uint8_t int3 = 0xcc;
1458
1459 if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
1460 cpu_memory_rw_debug(env, bp->pc, &int3, 1, 1))
1461 return -EINVAL;
1462 return 0;
1463 }
1464
1465 int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1466 {
1467 uint8_t int3;
1468
1469 if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
1470 cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1))
1471 return -EINVAL;
1472 return 0;
1473 }
1474
1475 #ifdef KVM_CAP_SET_GUEST_DEBUG
1476 static struct {
1477 target_ulong addr;
1478 int len;
1479 int type;
1480 } hw_breakpoint[4];
1481
1482 static int nb_hw_breakpoint;
1483
1484 static int find_hw_breakpoint(target_ulong addr, int len, int type)
1485 {
1486 int n;
1487
1488 for (n = 0; n < nb_hw_breakpoint; n++)
1489 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
1490 (hw_breakpoint[n].len == len || len == -1))
1491 return n;
1492 return -1;
1493 }
1494
1495 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1496 target_ulong len, int type)
1497 {
1498 switch (type) {
1499 case GDB_BREAKPOINT_HW:
1500 len = 1;
1501 break;
1502 case GDB_WATCHPOINT_WRITE:
1503 case GDB_WATCHPOINT_ACCESS:
1504 switch (len) {
1505 case 1:
1506 break;
1507 case 2:
1508 case 4:
1509 case 8:
1510 if (addr & (len - 1))
1511 return -EINVAL;
1512 break;
1513 default:
1514 return -EINVAL;
1515 }
1516 break;
1517 default:
1518 return -ENOSYS;
1519 }
1520
1521 if (nb_hw_breakpoint == 4)
1522 return -ENOBUFS;
1523
1524 if (find_hw_breakpoint(addr, len, type) >= 0)
1525 return -EEXIST;
1526
1527 hw_breakpoint[nb_hw_breakpoint].addr = addr;
1528 hw_breakpoint[nb_hw_breakpoint].len = len;
1529 hw_breakpoint[nb_hw_breakpoint].type = type;
1530 nb_hw_breakpoint++;
1531
1532 return 0;
1533 }
1534
1535 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1536 target_ulong len, int type)
1537 {
1538 int n;
1539
1540 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
1541 if (n < 0)
1542 return -ENOENT;
1543
1544 nb_hw_breakpoint--;
1545 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
1546
1547 return 0;
1548 }
1549
1550 void kvm_arch_remove_all_hw_breakpoints(void)
1551 {
1552 nb_hw_breakpoint = 0;
1553 }
1554
1555 static CPUWatchpoint hw_watchpoint;
1556
1557 int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info)
1558 {
1559 int handle = 0;
1560 int n;
1561
1562 if (arch_info->exception == 1) {
1563 if (arch_info->dr6 & (1 << 14)) {
1564 if (cpu_single_env->singlestep_enabled)
1565 handle = 1;
1566 } else {
1567 for (n = 0; n < 4; n++)
1568 if (arch_info->dr6 & (1 << n))
1569 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
1570 case 0x0:
1571 handle = 1;
1572 break;
1573 case 0x1:
1574 handle = 1;
1575 cpu_single_env->watchpoint_hit = &hw_watchpoint;
1576 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1577 hw_watchpoint.flags = BP_MEM_WRITE;
1578 break;
1579 case 0x3:
1580 handle = 1;
1581 cpu_single_env->watchpoint_hit = &hw_watchpoint;
1582 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1583 hw_watchpoint.flags = BP_MEM_ACCESS;
1584 break;
1585 }
1586 }
1587 } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc))
1588 handle = 1;
1589
1590 if (!handle)
1591 kvm_update_guest_debug(cpu_single_env,
1592 (arch_info->exception == 1) ?
1593 KVM_GUESTDBG_INJECT_DB : KVM_GUESTDBG_INJECT_BP);
1594
1595 return handle;
1596 }
1597
1598 void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg)
1599 {
1600 const uint8_t type_code[] = {
1601 [GDB_BREAKPOINT_HW] = 0x0,
1602 [GDB_WATCHPOINT_WRITE] = 0x1,
1603 [GDB_WATCHPOINT_ACCESS] = 0x3
1604 };
1605 const uint8_t len_code[] = {
1606 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
1607 };
1608 int n;
1609
1610 if (kvm_sw_breakpoints_active(env))
1611 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1612
1613 if (nb_hw_breakpoint > 0) {
1614 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1615 dbg->arch.debugreg[7] = 0x0600;
1616 for (n = 0; n < nb_hw_breakpoint; n++) {
1617 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
1618 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
1619 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
1620 (len_code[hw_breakpoint[n].len] << (18 + n*4));
1621 }
1622 }
1623 }
1624 #endif
1625
1626 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
1627 void kvm_arch_do_ioperm(void *_data)
1628 {
1629 struct ioperm_data *data = _data;
1630 ioperm(data->start_port, data->num, data->turn_on);
1631 }
1632 #endif
1633
1634 /*
1635 * Setup x86 specific IRQ routing
1636 */
1637 int kvm_arch_init_irq_routing(void)
1638 {
1639 int i, r;
1640
1641 if (kvm_irqchip && kvm_has_gsi_routing(kvm_context)) {
1642 kvm_clear_gsi_routes(kvm_context);
1643 for (i = 0; i < 8; ++i) {
1644 if (i == 2)
1645 continue;
1646 r = kvm_add_irq_route(kvm_context, i, KVM_IRQCHIP_PIC_MASTER, i);
1647 if (r < 0)
1648 return r;
1649 }
1650 for (i = 8; i < 16; ++i) {
1651 r = kvm_add_irq_route(kvm_context, i, KVM_IRQCHIP_PIC_SLAVE, i - 8);
1652 if (r < 0)
1653 return r;
1654 }
1655 for (i = 0; i < 24; ++i) {
1656 if (i == 0) {
1657 r = kvm_add_irq_route(kvm_context, i, KVM_IRQCHIP_IOAPIC, 2);
1658 } else if (i != 2) {
1659 r = kvm_add_irq_route(kvm_context, i, KVM_IRQCHIP_IOAPIC, i);
1660 }
1661 if (r < 0)
1662 return r;
1663 }
1664 kvm_commit_irq_routes(kvm_context);
1665 }
1666 return 0;
1667 }
1668
1669 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function,
1670 int reg)
1671 {
1672 return kvm_get_supported_cpuid(kvm_context, function, reg);
1673 }
1674
1675 void kvm_arch_process_irqchip_events(CPUState *env)
1676 {
1677 if (env->interrupt_request & CPU_INTERRUPT_INIT) {
1678 kvm_cpu_synchronize_state(env);
1679 do_cpu_init(env);
1680 }
1681 if (env->interrupt_request & CPU_INTERRUPT_SIPI) {
1682 kvm_cpu_synchronize_state(env);
1683 do_cpu_sipi(env);
1684 }
1685 }
Mark McLoughlin's queue for qemu-kvm.git