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Merge commit '253d0942fac33c5c15c9a7f8657f55f125dc5816' into upstream-merge
[qemu-kvm/fedora.git] / qemu-kvm-x86.c
blob1eb147e4ac2ff7b02addf55bb96914e69d01ac45
1 /*
2 * qemu/kvm integration, x86 specific code
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 *
6 * Licensed under the terms of the GNU GPL version 2 or higher.
7 */
8
9 #include "config.h"
10 #include "config-host.h"
11
12 #include <string.h>
13 #include "hw/hw.h"
14 #include "gdbstub.h"
15 #include <sys/io.h>
16
17 #include "qemu-kvm.h"
18 #include "libkvm-all.h"
19 #include "libkvm.h"
20 #include <pthread.h>
21 #include <sys/utsname.h>
22 #include <linux/kvm_para.h>
23 #include <sys/ioctl.h>
24
25 #include "kvm.h"
26 #include "hw/pc.h"
27
28 #define MSR_IA32_TSC 0x10
29
30 static struct kvm_msr_list *kvm_msr_list;
31 extern unsigned int kvm_shadow_memory;
32 static int kvm_has_msr_star;
33 static int kvm_has_vm_hsave_pa;
34
35 static int lm_capable_kernel;
36
37 int kvm_set_tss_addr(kvm_context_t kvm, unsigned long addr)
38 {
39 #ifdef KVM_CAP_SET_TSS_ADDR
40 int r;
41
42 r = ioctl(kvm->fd, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR);
43 if (r > 0) {
44 r = ioctl(kvm->vm_fd, KVM_SET_TSS_ADDR, addr);
45 if (r == -1) {
46 fprintf(stderr, "kvm_set_tss_addr: %m\n");
47 return -errno;
48 }
49 return 0;
50 }
51 #endif
52 return -ENOSYS;
53 }
54
55 static int kvm_init_tss(kvm_context_t kvm)
56 {
57 #ifdef KVM_CAP_SET_TSS_ADDR
58 int r;
59
60 r = ioctl(kvm->fd, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR);
61 if (r > 0) {
62 /*
63 * this address is 3 pages before the bios, and the bios should present
64 * as unavaible memory
65 */
66 r = kvm_set_tss_addr(kvm, 0xfffbd000);
67 if (r < 0) {
68 fprintf(stderr, "kvm_init_tss: unable to set tss addr\n");
69 return r;
70 }
71
72 }
73 #endif
74 return 0;
75 }
76
77 static int kvm_create_pit(kvm_context_t kvm)
78 {
79 #ifdef KVM_CAP_PIT
80 int r;
81
82 kvm->pit_in_kernel = 0;
83 if (!kvm->no_pit_creation) {
84 r = ioctl(kvm->fd, KVM_CHECK_EXTENSION, KVM_CAP_PIT);
85 if (r > 0) {
86 r = ioctl(kvm->vm_fd, KVM_CREATE_PIT);
87 if (r >= 0)
88 kvm->pit_in_kernel = 1;
89 else {
90 fprintf(stderr, "Create kernel PIC irqchip failed\n");
91 return r;
92 }
93 }
94 }
95 #endif
96 return 0;
97 }
98
99 int kvm_arch_create(kvm_context_t kvm, unsigned long phys_mem_bytes,
100 void **vm_mem)
101 {
102 int r = 0;
103
104 r = kvm_init_tss(kvm);
105 if (r < 0)
106 return r;
107
108 r = kvm_create_pit(kvm);
109 if (r < 0)
110 return r;
111
112 r = kvm_init_coalesced_mmio(kvm);
113 if (r < 0)
114 return r;
115
116 return 0;
117 }
118
119 #ifdef KVM_EXIT_TPR_ACCESS
120
121 static int kvm_handle_tpr_access(kvm_vcpu_context_t vcpu)
122 {
123 struct kvm_run *run = vcpu->run;
124 return vcpu->kvm->callbacks->tpr_access(vcpu->kvm->opaque, vcpu,
125 run->tpr_access.rip,
126 run->tpr_access.is_write);
127 }
128
129
130 int kvm_enable_vapic(kvm_vcpu_context_t vcpu, uint64_t vapic)
131 {
132 int r;
133 struct kvm_vapic_addr va = {
134 .vapic_addr = vapic,
135 };
136
137 r = ioctl(vcpu->fd, KVM_SET_VAPIC_ADDR, &va);
138 if (r == -1) {
139 r = -errno;
140 perror("kvm_enable_vapic");
141 return r;
142 }
143 return 0;
144 }
145
146 #endif
147
148 int kvm_arch_run(kvm_vcpu_context_t vcpu)
149 {
150 int r = 0;
151 struct kvm_run *run = vcpu->run;
152
153
154 switch (run->exit_reason) {
155 #ifdef KVM_EXIT_SET_TPR
156 case KVM_EXIT_SET_TPR:
157 break;
158 #endif
159 #ifdef KVM_EXIT_TPR_ACCESS
160 case KVM_EXIT_TPR_ACCESS:
161 r = kvm_handle_tpr_access(vcpu);
162 break;
163 #endif
164 default:
165 r = 1;
166 break;
167 }
168
169 return r;
170 }
171
172 #define MAX_ALIAS_SLOTS 4
173 static struct {
174 uint64_t start;
175 uint64_t len;
176 } kvm_aliases[MAX_ALIAS_SLOTS];
177
178 static int get_alias_slot(uint64_t start)
179 {
180 int i;
181
182 for (i=0; i<MAX_ALIAS_SLOTS; i++)
183 if (kvm_aliases[i].start == start)
184 return i;
185 return -1;
186 }
187 static int get_free_alias_slot(void)
188 {
189 int i;
190
191 for (i=0; i<MAX_ALIAS_SLOTS; i++)
192 if (kvm_aliases[i].len == 0)
193 return i;
194 return -1;
195 }
196
197 static void register_alias(int slot, uint64_t start, uint64_t len)
198 {
199 kvm_aliases[slot].start = start;
200 kvm_aliases[slot].len = len;
201 }
202
203 int kvm_create_memory_alias(kvm_context_t kvm,
204 uint64_t phys_start,
205 uint64_t len,
206 uint64_t target_phys)
207 {
208 struct kvm_memory_alias alias = {
209 .flags = 0,
210 .guest_phys_addr = phys_start,
211 .memory_size = len,
212 .target_phys_addr = target_phys,
213 };
214 int fd = kvm->vm_fd;
215 int r;
216 int slot;
217
218 slot = get_alias_slot(phys_start);
219 if (slot < 0)
220 slot = get_free_alias_slot();
221 if (slot < 0)
222 return -EBUSY;
223 alias.slot = slot;
224
225 r = ioctl(fd, KVM_SET_MEMORY_ALIAS, &alias);
226 if (r == -1)
227 return -errno;
228
229 register_alias(slot, phys_start, len);
230 return 0;
231 }
232
233 int kvm_destroy_memory_alias(kvm_context_t kvm, uint64_t phys_start)
234 {
235 return kvm_create_memory_alias(kvm, phys_start, 0, 0);
236 }
237
238 #ifdef KVM_CAP_IRQCHIP
239
240 int kvm_get_lapic(kvm_vcpu_context_t vcpu, struct kvm_lapic_state *s)
241 {
242 int r;
243 if (!kvm_irqchip_in_kernel(vcpu->kvm))
244 return 0;
245 r = ioctl(vcpu->fd, KVM_GET_LAPIC, s);
246 if (r == -1) {
247 r = -errno;
248 perror("kvm_get_lapic");
249 }
250 return r;
251 }
252
253 int kvm_set_lapic(kvm_vcpu_context_t vcpu, struct kvm_lapic_state *s)
254 {
255 int r;
256 if (!kvm_irqchip_in_kernel(vcpu->kvm))
257 return 0;
258 r = ioctl(vcpu->fd, KVM_SET_LAPIC, s);
259 if (r == -1) {
260 r = -errno;
261 perror("kvm_set_lapic");
262 }
263 return r;
264 }
265
266 #endif
267
268 #ifdef KVM_CAP_PIT
269
270 int kvm_get_pit(kvm_context_t kvm, struct kvm_pit_state *s)
271 {
272 int r;
273 if (!kvm->pit_in_kernel)
274 return 0;
275 r = ioctl(kvm->vm_fd, KVM_GET_PIT, s);
276 if (r == -1) {
277 r = -errno;
278 perror("kvm_get_pit");
279 }
280 return r;
281 }
282
283 int kvm_set_pit(kvm_context_t kvm, struct kvm_pit_state *s)
284 {
285 int r;
286 if (!kvm->pit_in_kernel)
287 return 0;
288 r = ioctl(kvm->vm_fd, KVM_SET_PIT, s);
289 if (r == -1) {
290 r = -errno;
291 perror("kvm_set_pit");
292 }
293 return r;
294 }
295
296 #endif
297
298 void kvm_show_code(kvm_vcpu_context_t vcpu)
299 {
300 #define SHOW_CODE_LEN 50
301 int fd = vcpu->fd;
302 struct kvm_regs regs;
303 struct kvm_sregs sregs;
304 int r, n;
305 int back_offset;
306 unsigned char code;
307 char code_str[SHOW_CODE_LEN * 3 + 1];
308 unsigned long rip;
309 kvm_context_t kvm = vcpu->kvm;
310
311 r = ioctl(fd, KVM_GET_SREGS, &sregs);
312 if (r == -1) {
313 perror("KVM_GET_SREGS");
314 return;
315 }
316 r = ioctl(fd, KVM_GET_REGS, &regs);
317 if (r == -1) {
318 perror("KVM_GET_REGS");
319 return;
320 }
321 rip = sregs.cs.base + regs.rip;
322 back_offset = regs.rip;
323 if (back_offset > 20)
324 back_offset = 20;
325 *code_str = 0;
326 for (n = -back_offset; n < SHOW_CODE_LEN-back_offset; ++n) {
327 if (n == 0)
328 strcat(code_str, " -->");
329 r = kvm->callbacks->mmio_read(kvm->opaque, rip + n, &code, 1);
330 if (r < 0) {
331 strcat(code_str, " xx");
332 continue;
333 }
334 sprintf(code_str + strlen(code_str), " %02x", code);
335 }
336 fprintf(stderr, "code:%s\n", code_str);
337 }
338
339
340 /*
341 * Returns available msr list. User must free.
342 */
343 struct kvm_msr_list *kvm_get_msr_list(kvm_context_t kvm)
344 {
345 struct kvm_msr_list sizer, *msrs;
346 int r, e;
347
348 sizer.nmsrs = 0;
349 r = ioctl(kvm->fd, KVM_GET_MSR_INDEX_LIST, &sizer);
350 if (r == -1 && errno != E2BIG)
351 return NULL;
352 msrs = malloc(sizeof *msrs + sizer.nmsrs * sizeof *msrs->indices);
353 if (!msrs) {
354 errno = ENOMEM;
355 return NULL;
356 }
357 msrs->nmsrs = sizer.nmsrs;
358 r = ioctl(kvm->fd, KVM_GET_MSR_INDEX_LIST, msrs);
359 if (r == -1) {
360 e = errno;
361 free(msrs);
362 errno = e;
363 return NULL;
364 }
365 return msrs;
366 }
367
368 int kvm_get_msrs(kvm_vcpu_context_t vcpu, struct kvm_msr_entry *msrs, int n)
369 {
370 struct kvm_msrs *kmsrs = malloc(sizeof *kmsrs + n * sizeof *msrs);
371 int r, e;
372
373 if (!kmsrs) {
374 errno = ENOMEM;
375 return -1;
376 }
377 kmsrs->nmsrs = n;
378 memcpy(kmsrs->entries, msrs, n * sizeof *msrs);
379 r = ioctl(vcpu->fd, KVM_GET_MSRS, kmsrs);
380 e = errno;
381 memcpy(msrs, kmsrs->entries, n * sizeof *msrs);
382 free(kmsrs);
383 errno = e;
384 return r;
385 }
386
387 int kvm_set_msrs(kvm_vcpu_context_t vcpu, struct kvm_msr_entry *msrs, int n)
388 {
389 struct kvm_msrs *kmsrs = malloc(sizeof *kmsrs + n * sizeof *msrs);
390 int r, e;
391
392 if (!kmsrs) {
393 errno = ENOMEM;
394 return -1;
395 }
396 kmsrs->nmsrs = n;
397 memcpy(kmsrs->entries, msrs, n * sizeof *msrs);
398 r = ioctl(vcpu->fd, KVM_SET_MSRS, kmsrs);
399 e = errno;
400 free(kmsrs);
401 errno = e;
402 return r;
403 }
404
405 static void print_seg(FILE *file, const char *name, struct kvm_segment *seg)
406 {
407 fprintf(stderr,
408 "%s %04x (%08llx/%08x p %d dpl %d db %d s %d type %x l %d"
409 " g %d avl %d)\n",
410 name, seg->selector, seg->base, seg->limit, seg->present,
411 seg->dpl, seg->db, seg->s, seg->type, seg->l, seg->g,
412 seg->avl);
413 }
414
415 static void print_dt(FILE *file, const char *name, struct kvm_dtable *dt)
416 {
417 fprintf(stderr, "%s %llx/%x\n", name, dt->base, dt->limit);
418 }
419
420 void kvm_show_regs(kvm_vcpu_context_t vcpu)
421 {
422 int fd = vcpu->fd;
423 struct kvm_regs regs;
424 struct kvm_sregs sregs;
425 int r;
426
427 r = ioctl(fd, KVM_GET_REGS, &regs);
428 if (r == -1) {
429 perror("KVM_GET_REGS");
430 return;
431 }
432 fprintf(stderr,
433 "rax %016llx rbx %016llx rcx %016llx rdx %016llx\n"
434 "rsi %016llx rdi %016llx rsp %016llx rbp %016llx\n"
435 "r8 %016llx r9 %016llx r10 %016llx r11 %016llx\n"
436 "r12 %016llx r13 %016llx r14 %016llx r15 %016llx\n"
437 "rip %016llx rflags %08llx\n",
438 regs.rax, regs.rbx, regs.rcx, regs.rdx,
439 regs.rsi, regs.rdi, regs.rsp, regs.rbp,
440 regs.r8, regs.r9, regs.r10, regs.r11,
441 regs.r12, regs.r13, regs.r14, regs.r15,
442 regs.rip, regs.rflags);
443 r = ioctl(fd, KVM_GET_SREGS, &sregs);
444 if (r == -1) {
445 perror("KVM_GET_SREGS");
446 return;
447 }
448 print_seg(stderr, "cs", &sregs.cs);
449 print_seg(stderr, "ds", &sregs.ds);
450 print_seg(stderr, "es", &sregs.es);
451 print_seg(stderr, "ss", &sregs.ss);
452 print_seg(stderr, "fs", &sregs.fs);
453 print_seg(stderr, "gs", &sregs.gs);
454 print_seg(stderr, "tr", &sregs.tr);
455 print_seg(stderr, "ldt", &sregs.ldt);
456 print_dt(stderr, "gdt", &sregs.gdt);
457 print_dt(stderr, "idt", &sregs.idt);
458 fprintf(stderr, "cr0 %llx cr2 %llx cr3 %llx cr4 %llx cr8 %llx"
459 " efer %llx\n",
460 sregs.cr0, sregs.cr2, sregs.cr3, sregs.cr4, sregs.cr8,
461 sregs.efer);
462 }
463
464 uint64_t kvm_get_apic_base(kvm_vcpu_context_t vcpu)
465 {
466 return vcpu->run->apic_base;
467 }
468
469 void kvm_set_cr8(kvm_vcpu_context_t vcpu, uint64_t cr8)
470 {
471 vcpu->run->cr8 = cr8;
472 }
473
474 __u64 kvm_get_cr8(kvm_vcpu_context_t vcpu)
475 {
476 return vcpu->run->cr8;
477 }
478
479 int kvm_setup_cpuid(kvm_vcpu_context_t vcpu, int nent,
480 struct kvm_cpuid_entry *entries)
481 {
482 struct kvm_cpuid *cpuid;
483 int r;
484
485 cpuid = malloc(sizeof(*cpuid) + nent * sizeof(*entries));
486 if (!cpuid)
487 return -ENOMEM;
488
489 cpuid->nent = nent;
490 memcpy(cpuid->entries, entries, nent * sizeof(*entries));
491 r = ioctl(vcpu->fd, KVM_SET_CPUID, cpuid);
492
493 free(cpuid);
494 return r;
495 }
496
497 int kvm_setup_cpuid2(kvm_vcpu_context_t vcpu, int nent,
498 struct kvm_cpuid_entry2 *entries)
499 {
500 struct kvm_cpuid2 *cpuid;
501 int r;
502
503 cpuid = malloc(sizeof(*cpuid) + nent * sizeof(*entries));
504 if (!cpuid)
505 return -ENOMEM;
506
507 cpuid->nent = nent;
508 memcpy(cpuid->entries, entries, nent * sizeof(*entries));
509 r = ioctl(vcpu->fd, KVM_SET_CPUID2, cpuid);
510 if (r == -1) {
511 fprintf(stderr, "kvm_setup_cpuid2: %m\n");
512 return -errno;
513 }
514 free(cpuid);
515 return r;
516 }
517
518 int kvm_set_shadow_pages(kvm_context_t kvm, unsigned int nrshadow_pages)
519 {
520 #ifdef KVM_CAP_MMU_SHADOW_CACHE_CONTROL
521 int r;
522
523 r = ioctl(kvm->fd, KVM_CHECK_EXTENSION,
524 KVM_CAP_MMU_SHADOW_CACHE_CONTROL);
525 if (r > 0) {
526 r = ioctl(kvm->vm_fd, KVM_SET_NR_MMU_PAGES, nrshadow_pages);
527 if (r == -1) {
528 fprintf(stderr, "kvm_set_shadow_pages: %m\n");
529 return -errno;
530 }
531 return 0;
532 }
533 #endif
534 return -1;
535 }
536
537 int kvm_get_shadow_pages(kvm_context_t kvm, unsigned int *nrshadow_pages)
538 {
539 #ifdef KVM_CAP_MMU_SHADOW_CACHE_CONTROL
540 int r;
541
542 r = ioctl(kvm->fd, KVM_CHECK_EXTENSION,
543 KVM_CAP_MMU_SHADOW_CACHE_CONTROL);
544 if (r > 0) {
545 *nrshadow_pages = ioctl(kvm->vm_fd, KVM_GET_NR_MMU_PAGES);
546 return 0;
547 }
548 #endif
549 return -1;
550 }
551
552 #ifdef KVM_CAP_VAPIC
553
554 static int tpr_access_reporting(kvm_vcpu_context_t vcpu, int enabled)
555 {
556 int r;
557 struct kvm_tpr_access_ctl tac = {
558 .enabled = enabled,
559 };
560
561 r = ioctl(vcpu->kvm->fd, KVM_CHECK_EXTENSION, KVM_CAP_VAPIC);
562 if (r == -1 || r == 0)
563 return -ENOSYS;
564 r = ioctl(vcpu->fd, KVM_TPR_ACCESS_REPORTING, &tac);
565 if (r == -1) {
566 r = -errno;
567 perror("KVM_TPR_ACCESS_REPORTING");
568 return r;
569 }
570 return 0;
571 }
572
573 int kvm_enable_tpr_access_reporting(kvm_vcpu_context_t vcpu)
574 {
575 return tpr_access_reporting(vcpu, 1);
576 }
577
578 int kvm_disable_tpr_access_reporting(kvm_vcpu_context_t vcpu)
579 {
580 return tpr_access_reporting(vcpu, 0);
581 }
582
583 #endif
584
585 #ifdef KVM_CAP_EXT_CPUID
586
587 static struct kvm_cpuid2 *try_get_cpuid(kvm_context_t kvm, int max)
588 {
589 struct kvm_cpuid2 *cpuid;
590 int r, size;
591
592 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
593 cpuid = (struct kvm_cpuid2 *)malloc(size);
594 cpuid->nent = max;
595 r = ioctl(kvm->fd, KVM_GET_SUPPORTED_CPUID, cpuid);
596 if (r == -1)
597 r = -errno;
598 else if (r == 0 && cpuid->nent >= max)
599 r = -E2BIG;
600 if (r < 0) {
601 if (r == -E2BIG) {
602 free(cpuid);
603 return NULL;
604 } else {
605 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
606 strerror(-r));
607 exit(1);
608 }
609 }
610 return cpuid;
611 }
612
613 #define R_EAX 0
614 #define R_ECX 1
615 #define R_EDX 2
616 #define R_EBX 3
617 #define R_ESP 4
618 #define R_EBP 5
619 #define R_ESI 6
620 #define R_EDI 7
621
622 uint32_t kvm_get_supported_cpuid(kvm_context_t kvm, uint32_t function, int reg)
623 {
624 struct kvm_cpuid2 *cpuid;
625 int i, max;
626 uint32_t ret = 0;
627 uint32_t cpuid_1_edx;
628
629 if (!kvm_check_extension(kvm, KVM_CAP_EXT_CPUID)) {
630 return -1U;
631 }
632
633 max = 1;
634 while ((cpuid = try_get_cpuid(kvm, max)) == NULL) {
635 max *= 2;
636 }
637
638 for (i = 0; i < cpuid->nent; ++i) {
639 if (cpuid->entries[i].function == function) {
640 switch (reg) {
641 case R_EAX:
642 ret = cpuid->entries[i].eax;
643 break;
644 case R_EBX:
645 ret = cpuid->entries[i].ebx;
646 break;
647 case R_ECX:
648 ret = cpuid->entries[i].ecx;
649 break;
650 case R_EDX:
651 ret = cpuid->entries[i].edx;
652 if (function == 1) {
653 /* kvm misreports the following features
654 */
655 ret |= 1 << 12; /* MTRR */
656 ret |= 1 << 16; /* PAT */
657 ret |= 1 << 7; /* MCE */
658 ret |= 1 << 14; /* MCA */
659 }
660
661 /* On Intel, kvm returns cpuid according to
662 * the Intel spec, so add missing bits
663 * according to the AMD spec:
664 */
665 if (function == 0x80000001) {
666 cpuid_1_edx = kvm_get_supported_cpuid(kvm, 1, R_EDX);
667 ret |= cpuid_1_edx & 0xdfeff7ff;
668 }
669 break;
670 }
671 }
672 }
673
674 free(cpuid);
675
676 return ret;
677 }
678
679 #else
680
681 uint32_t kvm_get_supported_cpuid(kvm_context_t kvm, uint32_t function, int reg)
682 {
683 return -1U;
684 }
685
686 #endif
687 int kvm_qemu_create_memory_alias(uint64_t phys_start,
688 uint64_t len,
689 uint64_t target_phys)
690 {
691 return kvm_create_memory_alias(kvm_context, phys_start, len, target_phys);
692 }
693
694 int kvm_qemu_destroy_memory_alias(uint64_t phys_start)
695 {
696 return kvm_destroy_memory_alias(kvm_context, phys_start);
697 }
698
699 int kvm_arch_qemu_create_context(void)
700 {
701 int i;
702 struct utsname utsname;
703
704 uname(&utsname);
705 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
706
707 if (kvm_shadow_memory)
708 kvm_set_shadow_pages(kvm_context, kvm_shadow_memory);
709
710 kvm_msr_list = kvm_get_msr_list(kvm_context);
711 if (!kvm_msr_list)
712 return -1;
713 for (i = 0; i < kvm_msr_list->nmsrs; ++i) {
714 if (kvm_msr_list->indices[i] == MSR_STAR)
715 kvm_has_msr_star = 1;
716 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA)
717 kvm_has_vm_hsave_pa = 1;
718 }
719
720 return 0;
721 }
722
723 static void set_msr_entry(struct kvm_msr_entry *entry, uint32_t index,
724 uint64_t data)
725 {
726 entry->index = index;
727 entry->data = data;
728 }
729
730 /* returns 0 on success, non-0 on failure */
731 static int get_msr_entry(struct kvm_msr_entry *entry, CPUState *env)
732 {
733 switch (entry->index) {
734 case MSR_IA32_SYSENTER_CS:
735 env->sysenter_cs = entry->data;
736 break;
737 case MSR_IA32_SYSENTER_ESP:
738 env->sysenter_esp = entry->data;
739 break;
740 case MSR_IA32_SYSENTER_EIP:
741 env->sysenter_eip = entry->data;
742 break;
743 case MSR_STAR:
744 env->star = entry->data;
745 break;
746 #ifdef TARGET_X86_64
747 case MSR_CSTAR:
748 env->cstar = entry->data;
749 break;
750 case MSR_KERNELGSBASE:
751 env->kernelgsbase = entry->data;
752 break;
753 case MSR_FMASK:
754 env->fmask = entry->data;
755 break;
756 case MSR_LSTAR:
757 env->lstar = entry->data;
758 break;
759 #endif
760 case MSR_IA32_TSC:
761 env->tsc = entry->data;
762 break;
763 case MSR_VM_HSAVE_PA:
764 env->vm_hsave = entry->data;
765 break;
766 default:
767 printf("Warning unknown msr index 0x%x\n", entry->index);
768 return 1;
769 }
770 return 0;
771 }
772
773 #ifdef TARGET_X86_64
774 #define MSR_COUNT 9
775 #else
776 #define MSR_COUNT 5
777 #endif
778
779 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
780 {
781 lhs->selector = rhs->selector;
782 lhs->base = rhs->base;
783 lhs->limit = rhs->limit;
784 lhs->type = 3;
785 lhs->present = 1;
786 lhs->dpl = 3;
787 lhs->db = 0;
788 lhs->s = 1;
789 lhs->l = 0;
790 lhs->g = 0;
791 lhs->avl = 0;
792 lhs->unusable = 0;
793 }
794
795 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
796 {
797 unsigned flags = rhs->flags;
798 lhs->selector = rhs->selector;
799 lhs->base = rhs->base;
800 lhs->limit = rhs->limit;
801 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
802 lhs->present = (flags & DESC_P_MASK) != 0;
803 lhs->dpl = rhs->selector & 3;
804 lhs->db = (flags >> DESC_B_SHIFT) & 1;
805 lhs->s = (flags & DESC_S_MASK) != 0;
806 lhs->l = (flags >> DESC_L_SHIFT) & 1;
807 lhs->g = (flags & DESC_G_MASK) != 0;
808 lhs->avl = (flags & DESC_AVL_MASK) != 0;
809 lhs->unusable = 0;
810 }
811
812 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
813 {
814 lhs->selector = rhs->selector;
815 lhs->base = rhs->base;
816 lhs->limit = rhs->limit;
817 lhs->flags =
818 (rhs->type << DESC_TYPE_SHIFT)
819 | (rhs->present * DESC_P_MASK)
820 | (rhs->dpl << DESC_DPL_SHIFT)
821 | (rhs->db << DESC_B_SHIFT)
822 | (rhs->s * DESC_S_MASK)
823 | (rhs->l << DESC_L_SHIFT)
824 | (rhs->g * DESC_G_MASK)
825 | (rhs->avl * DESC_AVL_MASK);
826 }
827
828 void kvm_arch_load_regs(CPUState *env)
829 {
830 struct kvm_regs regs;
831 struct kvm_fpu fpu;
832 struct kvm_sregs sregs;
833 struct kvm_msr_entry msrs[MSR_COUNT];
834 int rc, n, i;
835
836 regs.rax = env->regs[R_EAX];
837 regs.rbx = env->regs[R_EBX];
838 regs.rcx = env->regs[R_ECX];
839 regs.rdx = env->regs[R_EDX];
840 regs.rsi = env->regs[R_ESI];
841 regs.rdi = env->regs[R_EDI];
842 regs.rsp = env->regs[R_ESP];
843 regs.rbp = env->regs[R_EBP];
844 #ifdef TARGET_X86_64
845 regs.r8 = env->regs[8];
846 regs.r9 = env->regs[9];
847 regs.r10 = env->regs[10];
848 regs.r11 = env->regs[11];
849 regs.r12 = env->regs[12];
850 regs.r13 = env->regs[13];
851 regs.r14 = env->regs[14];
852 regs.r15 = env->regs[15];
853 #endif
854
855 regs.rflags = env->eflags;
856 regs.rip = env->eip;
857
858 kvm_set_regs(env->kvm_cpu_state.vcpu_ctx, &regs);
859
860 memset(&fpu, 0, sizeof fpu);
861 fpu.fsw = env->fpus & ~(7 << 11);
862 fpu.fsw |= (env->fpstt & 7) << 11;
863 fpu.fcw = env->fpuc;
864 for (i = 0; i < 8; ++i)
865 fpu.ftwx |= (!env->fptags[i]) << i;
866 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
867 memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
868 fpu.mxcsr = env->mxcsr;
869 kvm_set_fpu(env->kvm_cpu_state.vcpu_ctx, &fpu);
870
871 memcpy(sregs.interrupt_bitmap, env->interrupt_bitmap, sizeof(sregs.interrupt_bitmap));
872
873 if ((env->eflags & VM_MASK)) {
874 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
875 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
876 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
877 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
878 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
879 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
880 } else {
881 set_seg(&sregs.cs, &env->segs[R_CS]);
882 set_seg(&sregs.ds, &env->segs[R_DS]);
883 set_seg(&sregs.es, &env->segs[R_ES]);
884 set_seg(&sregs.fs, &env->segs[R_FS]);
885 set_seg(&sregs.gs, &env->segs[R_GS]);
886 set_seg(&sregs.ss, &env->segs[R_SS]);
887
888 if (env->cr[0] & CR0_PE_MASK) {
889 /* force ss cpl to cs cpl */
890 sregs.ss.selector = (sregs.ss.selector & ~3) |
891 (sregs.cs.selector & 3);
892 sregs.ss.dpl = sregs.ss.selector & 3;
893 }
894 }
895
896 set_seg(&sregs.tr, &env->tr);
897 set_seg(&sregs.ldt, &env->ldt);
898
899 sregs.idt.limit = env->idt.limit;
900 sregs.idt.base = env->idt.base;
901 sregs.gdt.limit = env->gdt.limit;
902 sregs.gdt.base = env->gdt.base;
903
904 sregs.cr0 = env->cr[0];
905 sregs.cr2 = env->cr[2];
906 sregs.cr3 = env->cr[3];
907 sregs.cr4 = env->cr[4];
908
909 sregs.cr8 = cpu_get_apic_tpr(env);
910 sregs.apic_base = cpu_get_apic_base(env);
911
912 sregs.efer = env->efer;
913
914 kvm_set_sregs(env->kvm_cpu_state.vcpu_ctx, &sregs);
915
916 /* msrs */
917 n = 0;
918 set_msr_entry(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
919 set_msr_entry(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
920 set_msr_entry(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
921 if (kvm_has_msr_star)
922 set_msr_entry(&msrs[n++], MSR_STAR, env->star);
923 if (kvm_has_vm_hsave_pa)
924 set_msr_entry(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
925 #ifdef TARGET_X86_64
926 if (lm_capable_kernel) {
927 set_msr_entry(&msrs[n++], MSR_CSTAR, env->cstar);
928 set_msr_entry(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
929 set_msr_entry(&msrs[n++], MSR_FMASK, env->fmask);
930 set_msr_entry(&msrs[n++], MSR_LSTAR , env->lstar);
931 }
932 #endif
933
934 rc = kvm_set_msrs(env->kvm_cpu_state.vcpu_ctx, msrs, n);
935 if (rc == -1)
936 perror("kvm_set_msrs FAILED");
937 }
938
939 void kvm_load_tsc(CPUState *env)
940 {
941 int rc;
942 struct kvm_msr_entry msr;
943
944 set_msr_entry(&msr, MSR_IA32_TSC, env->tsc);
945
946 rc = kvm_set_msrs(env->kvm_cpu_state.vcpu_ctx, &msr, 1);
947 if (rc == -1)
948 perror("kvm_set_tsc FAILED.\n");
949 }
950
951 void kvm_arch_save_mpstate(CPUState *env)
952 {
953 #ifdef KVM_CAP_MP_STATE
954 int r;
955 struct kvm_mp_state mp_state;
956
957 r = kvm_get_mpstate(env->kvm_cpu_state.vcpu_ctx, &mp_state);
958 if (r < 0)
959 env->mp_state = -1;
960 else
961 env->mp_state = mp_state.mp_state;
962 #endif
963 }
964
965 void kvm_arch_load_mpstate(CPUState *env)
966 {
967 #ifdef KVM_CAP_MP_STATE
968 struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
969
970 /*
971 * -1 indicates that the host did not support GET_MP_STATE ioctl,
972 * so don't touch it.
973 */
974 if (env->mp_state != -1)
975 kvm_set_mpstate(env->kvm_cpu_state.vcpu_ctx, &mp_state);
976 #endif
977 }
978
979 void kvm_arch_save_regs(CPUState *env)
980 {
981 struct kvm_regs regs;
982 struct kvm_fpu fpu;
983 struct kvm_sregs sregs;
984 struct kvm_msr_entry msrs[MSR_COUNT];
985 uint32_t hflags;
986 uint32_t i, n, rc;
987
988 kvm_get_regs(env->kvm_cpu_state.vcpu_ctx, &regs);
989
990 env->regs[R_EAX] = regs.rax;
991 env->regs[R_EBX] = regs.rbx;
992 env->regs[R_ECX] = regs.rcx;
993 env->regs[R_EDX] = regs.rdx;
994 env->regs[R_ESI] = regs.rsi;
995 env->regs[R_EDI] = regs.rdi;
996 env->regs[R_ESP] = regs.rsp;
997 env->regs[R_EBP] = regs.rbp;
998 #ifdef TARGET_X86_64
999 env->regs[8] = regs.r8;
1000 env->regs[9] = regs.r9;
1001 env->regs[10] = regs.r10;
1002 env->regs[11] = regs.r11;
1003 env->regs[12] = regs.r12;
1004 env->regs[13] = regs.r13;
1005 env->regs[14] = regs.r14;
1006 env->regs[15] = regs.r15;
1007 #endif
1008
1009 env->eflags = regs.rflags;
1010 env->eip = regs.rip;
1011
1012 kvm_get_fpu(env->kvm_cpu_state.vcpu_ctx, &fpu);
1013 env->fpstt = (fpu.fsw >> 11) & 7;
1014 env->fpus = fpu.fsw;
1015 env->fpuc = fpu.fcw;
1016 for (i = 0; i < 8; ++i)
1017 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1018 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1019 memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
1020 env->mxcsr = fpu.mxcsr;
1021
1022 kvm_get_sregs(env->kvm_cpu_state.vcpu_ctx, &sregs);
1023
1024 memcpy(env->interrupt_bitmap, sregs.interrupt_bitmap, sizeof(env->interrupt_bitmap));
1025
1026 get_seg(&env->segs[R_CS], &sregs.cs);
1027 get_seg(&env->segs[R_DS], &sregs.ds);
1028 get_seg(&env->segs[R_ES], &sregs.es);
1029 get_seg(&env->segs[R_FS], &sregs.fs);
1030 get_seg(&env->segs[R_GS], &sregs.gs);
1031 get_seg(&env->segs[R_SS], &sregs.ss);
1032
1033 get_seg(&env->tr, &sregs.tr);
1034 get_seg(&env->ldt, &sregs.ldt);
1035
1036 env->idt.limit = sregs.idt.limit;
1037 env->idt.base = sregs.idt.base;
1038 env->gdt.limit = sregs.gdt.limit;
1039 env->gdt.base = sregs.gdt.base;
1040
1041 env->cr[0] = sregs.cr0;
1042 env->cr[2] = sregs.cr2;
1043 env->cr[3] = sregs.cr3;
1044 env->cr[4] = sregs.cr4;
1045
1046 cpu_set_apic_base(env, sregs.apic_base);
1047
1048 env->efer = sregs.efer;
1049 //cpu_set_apic_tpr(env, sregs.cr8);
1050
1051 #define HFLAG_COPY_MASK ~( \
1052 HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1053 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1054 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1055 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1056
1057
1058
1059 hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1060 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1061 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1062 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1063 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1064 hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
1065 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
1066
1067 if (env->efer & MSR_EFER_LMA) {
1068 hflags |= HF_LMA_MASK;
1069 }
1070
1071 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1072 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1073 } else {
1074 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1075 (DESC_B_SHIFT - HF_CS32_SHIFT);
1076 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1077 (DESC_B_SHIFT - HF_SS32_SHIFT);
1078 if (!(env->cr[0] & CR0_PE_MASK) ||
1079 (env->eflags & VM_MASK) ||
1080 !(hflags & HF_CS32_MASK)) {
1081 hflags |= HF_ADDSEG_MASK;
1082 } else {
1083 hflags |= ((env->segs[R_DS].base |
1084 env->segs[R_ES].base |
1085 env->segs[R_SS].base) != 0) <<
1086 HF_ADDSEG_SHIFT;
1087 }
1088 }
1089 env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
1090
1091 /* msrs */
1092 n = 0;
1093 msrs[n++].index = MSR_IA32_SYSENTER_CS;
1094 msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1095 msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1096 if (kvm_has_msr_star)
1097 msrs[n++].index = MSR_STAR;
1098 msrs[n++].index = MSR_IA32_TSC;
1099 if (kvm_has_vm_hsave_pa)
1100 msrs[n++].index = MSR_VM_HSAVE_PA;
1101 #ifdef TARGET_X86_64
1102 if (lm_capable_kernel) {
1103 msrs[n++].index = MSR_CSTAR;
1104 msrs[n++].index = MSR_KERNELGSBASE;
1105 msrs[n++].index = MSR_FMASK;
1106 msrs[n++].index = MSR_LSTAR;
1107 }
1108 #endif
1109 rc = kvm_get_msrs(env->kvm_cpu_state.vcpu_ctx, msrs, n);
1110 if (rc == -1) {
1111 perror("kvm_get_msrs FAILED");
1112 }
1113 else {
1114 n = rc; /* actual number of MSRs */
1115 for (i=0 ; i<n; i++) {
1116 if (get_msr_entry(&msrs[i], env))
1117 return;
1118 }
1119 }
1120 }
1121
1122 static void do_cpuid_ent(struct kvm_cpuid_entry2 *e, uint32_t function,
1123 uint32_t count, CPUState *env)
1124 {
1125 env->regs[R_EAX] = function;
1126 env->regs[R_ECX] = count;
1127 qemu_kvm_cpuid_on_env(env);
1128 e->function = function;
1129 e->flags = 0;
1130 e->index = 0;
1131 e->eax = env->regs[R_EAX];
1132 e->ebx = env->regs[R_EBX];
1133 e->ecx = env->regs[R_ECX];
1134 e->edx = env->regs[R_EDX];
1135 }
1136
1137 struct kvm_para_features {
1138 int cap;
1139 int feature;
1140 } para_features[] = {
1141 #ifdef KVM_CAP_CLOCKSOURCE
1142 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
1143 #endif
1144 #ifdef KVM_CAP_NOP_IO_DELAY
1145 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
1146 #endif
1147 #ifdef KVM_CAP_PV_MMU
1148 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
1149 #endif
1150 #ifdef KVM_CAP_CR3_CACHE
1151 { KVM_CAP_CR3_CACHE, KVM_FEATURE_CR3_CACHE },
1152 #endif
1153 { -1, -1 }
1154 };
1155
1156 static int get_para_features(kvm_context_t kvm_context)
1157 {
1158 int i, features = 0;
1159
1160 for (i = 0; i < ARRAY_SIZE(para_features)-1; i++) {
1161 if (kvm_check_extension(kvm_context, para_features[i].cap))
1162 features |= (1 << para_features[i].feature);
1163 }
1164
1165 return features;
1166 }
1167
1168 static void kvm_trim_features(uint32_t *features, uint32_t supported)
1169 {
1170 int i;
1171 uint32_t mask;
1172
1173 for (i = 0; i < 32; ++i) {
1174 mask = 1U << i;
1175 if ((*features & mask) && !(supported & mask)) {
1176 *features &= ~mask;
1177 }
1178 }
1179 }
1180
1181 int kvm_arch_qemu_init_env(CPUState *cenv)
1182 {
1183 struct kvm_cpuid_entry2 cpuid_ent[100];
1184 #ifdef KVM_CPUID_SIGNATURE
1185 struct kvm_cpuid_entry2 *pv_ent;
1186 uint32_t signature[3];
1187 #endif
1188 int cpuid_nent = 0;
1189 CPUState copy;
1190 uint32_t i, j, limit;
1191
1192 qemu_kvm_load_lapic(cenv);
1193
1194 copy = *cenv;
1195
1196 #ifdef KVM_CPUID_SIGNATURE
1197 /* Paravirtualization CPUIDs */
1198 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
1199 pv_ent = &cpuid_ent[cpuid_nent++];
1200 memset(pv_ent, 0, sizeof(*pv_ent));
1201 pv_ent->function = KVM_CPUID_SIGNATURE;
1202 pv_ent->eax = 0;
1203 pv_ent->ebx = signature[0];
1204 pv_ent->ecx = signature[1];
1205 pv_ent->edx = signature[2];
1206
1207 pv_ent = &cpuid_ent[cpuid_nent++];
1208 memset(pv_ent, 0, sizeof(*pv_ent));
1209 pv_ent->function = KVM_CPUID_FEATURES;
1210 pv_ent->eax = get_para_features(kvm_context);
1211 #endif
1212
1213 copy.regs[R_EAX] = 0;
1214 qemu_kvm_cpuid_on_env(&copy);
1215 limit = copy.regs[R_EAX];
1216
1217 for (i = 0; i <= limit; ++i) {
1218 if (i == 4 || i == 0xb || i == 0xd) {
1219 for (j = 0; ; ++j) {
1220 do_cpuid_ent(&cpuid_ent[cpuid_nent], i, j, &copy);
1221
1222 cpuid_ent[cpuid_nent].flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1223 cpuid_ent[cpuid_nent].index = j;
1224
1225 cpuid_nent++;
1226
1227 if (i == 4 && copy.regs[R_EAX] == 0)
1228 break;
1229 if (i == 0xb && !(copy.regs[R_ECX] & 0xff00))
1230 break;
1231 if (i == 0xd && copy.regs[R_EAX] == 0)
1232 break;
1233 }
1234 } else
1235 do_cpuid_ent(&cpuid_ent[cpuid_nent++], i, 0, &copy);
1236 }
1237
1238 copy.regs[R_EAX] = 0x80000000;
1239 qemu_kvm_cpuid_on_env(&copy);
1240 limit = copy.regs[R_EAX];
1241
1242 for (i = 0x80000000; i <= limit; ++i)
1243 do_cpuid_ent(&cpuid_ent[cpuid_nent++], i, 0, &copy);
1244
1245 kvm_setup_cpuid2(cenv->kvm_cpu_state.vcpu_ctx, cpuid_nent, cpuid_ent);
1246
1247 kvm_trim_features(&cenv->cpuid_features,
1248 kvm_arch_get_supported_cpuid(cenv, 1, R_EDX));
1249 kvm_trim_features(&cenv->cpuid_ext_features,
1250 kvm_arch_get_supported_cpuid(cenv, 1, R_ECX));
1251 kvm_trim_features(&cenv->cpuid_ext2_features,
1252 kvm_arch_get_supported_cpuid(cenv, 0x80000001, R_EDX));
1253 kvm_trim_features(&cenv->cpuid_ext3_features,
1254 kvm_arch_get_supported_cpuid(cenv, 0x80000001, R_ECX));
1255
1256 return 0;
1257 }
1258
1259 int kvm_arch_halt(void *opaque, kvm_vcpu_context_t vcpu)
1260 {
1261 CPUState *env = cpu_single_env;
1262
1263 if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1264 (env->eflags & IF_MASK)) &&
1265 !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
1266 env->halted = 1;
1267 }
1268 return 1;
1269 }
1270
1271 void kvm_arch_pre_kvm_run(void *opaque, CPUState *env)
1272 {
1273 if (!kvm_irqchip_in_kernel(kvm_context))
1274 kvm_set_cr8(env->kvm_cpu_state.vcpu_ctx, cpu_get_apic_tpr(env));
1275 }
1276
1277 void kvm_arch_post_kvm_run(void *opaque, CPUState *env)
1278 {
1279 cpu_single_env = env;
1280
1281 env->eflags = kvm_get_interrupt_flag(env->kvm_cpu_state.vcpu_ctx)
1282 ? env->eflags | IF_MASK : env->eflags & ~IF_MASK;
1283
1284 cpu_set_apic_tpr(env, kvm_get_cr8(env->kvm_cpu_state.vcpu_ctx));
1285 cpu_set_apic_base(env, kvm_get_apic_base(env->kvm_cpu_state.vcpu_ctx));
1286 }
1287
1288 int kvm_arch_has_work(CPUState *env)
1289 {
1290 if (((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1291 (env->eflags & IF_MASK)) ||
1292 (env->interrupt_request & CPU_INTERRUPT_NMI))
1293 return 1;
1294 return 0;
1295 }
1296
1297 int kvm_arch_try_push_interrupts(void *opaque)
1298 {
1299 CPUState *env = cpu_single_env;
1300 int r, irq;
1301
1302 if (kvm_is_ready_for_interrupt_injection(env->kvm_cpu_state.vcpu_ctx) &&
1303 (env->interrupt_request & CPU_INTERRUPT_HARD) &&
1304 (env->eflags & IF_MASK)) {
1305 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1306 irq = cpu_get_pic_interrupt(env);
1307 if (irq >= 0) {
1308 r = kvm_inject_irq(env->kvm_cpu_state.vcpu_ctx, irq);
1309 if (r < 0)
1310 printf("cpu %d fail inject %x\n", env->cpu_index, irq);
1311 }
1312 }
1313
1314 return (env->interrupt_request & CPU_INTERRUPT_HARD) != 0;
1315 }
1316
1317 #ifdef KVM_CAP_USER_NMI
1318 void kvm_arch_push_nmi(void *opaque)
1319 {
1320 CPUState *env = cpu_single_env;
1321 int r;
1322
1323 if (likely(!(env->interrupt_request & CPU_INTERRUPT_NMI)))
1324 return;
1325
1326 env->interrupt_request &= ~CPU_INTERRUPT_NMI;
1327 r = kvm_inject_nmi(env->kvm_cpu_state.vcpu_ctx);
1328 if (r < 0)
1329 printf("cpu %d fail inject NMI\n", env->cpu_index);
1330 }
1331 #endif /* KVM_CAP_USER_NMI */
1332
1333 void kvm_arch_update_regs_for_sipi(CPUState *env)
1334 {
1335 SegmentCache cs = env->segs[R_CS];
1336
1337 kvm_arch_save_regs(env);
1338 env->segs[R_CS] = cs;
1339 env->eip = 0;
1340 kvm_arch_load_regs(env);
1341 }
1342
1343 int handle_tpr_access(void *opaque, kvm_vcpu_context_t vcpu,
1344 uint64_t rip, int is_write)
1345 {
1346 kvm_tpr_access_report(cpu_single_env, rip, is_write);
1347 return 0;
1348 }
1349
1350 void kvm_arch_cpu_reset(CPUState *env)
1351 {
1352 kvm_arch_load_regs(env);
1353 if (!cpu_is_bsp(env)) {
1354 if (kvm_irqchip_in_kernel(kvm_context)) {
1355 #ifdef KVM_CAP_MP_STATE
1356 kvm_reset_mpstate(env->kvm_cpu_state.vcpu_ctx);
1357 #endif
1358 } else {
1359 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1360 env->halted = 1;
1361 }
1362 }
1363 }
1364
1365 int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1366 {
1367 uint8_t int3 = 0xcc;
1368
1369 if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
1370 cpu_memory_rw_debug(env, bp->pc, &int3, 1, 1))
1371 return -EINVAL;
1372 return 0;
1373 }
1374
1375 int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1376 {
1377 uint8_t int3;
1378
1379 if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
1380 cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1))
1381 return -EINVAL;
1382 return 0;
1383 }
1384
1385 #ifdef KVM_CAP_SET_GUEST_DEBUG
1386 static struct {
1387 target_ulong addr;
1388 int len;
1389 int type;
1390 } hw_breakpoint[4];
1391
1392 static int nb_hw_breakpoint;
1393
1394 static int find_hw_breakpoint(target_ulong addr, int len, int type)
1395 {
1396 int n;
1397
1398 for (n = 0; n < nb_hw_breakpoint; n++)
1399 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
1400 (hw_breakpoint[n].len == len || len == -1))
1401 return n;
1402 return -1;
1403 }
1404
1405 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1406 target_ulong len, int type)
1407 {
1408 switch (type) {
1409 case GDB_BREAKPOINT_HW:
1410 len = 1;
1411 break;
1412 case GDB_WATCHPOINT_WRITE:
1413 case GDB_WATCHPOINT_ACCESS:
1414 switch (len) {
1415 case 1:
1416 break;
1417 case 2:
1418 case 4:
1419 case 8:
1420 if (addr & (len - 1))
1421 return -EINVAL;
1422 break;
1423 default:
1424 return -EINVAL;
1425 }
1426 break;
1427 default:
1428 return -ENOSYS;
1429 }
1430
1431 if (nb_hw_breakpoint == 4)
1432 return -ENOBUFS;
1433
1434 if (find_hw_breakpoint(addr, len, type) >= 0)
1435 return -EEXIST;
1436
1437 hw_breakpoint[nb_hw_breakpoint].addr = addr;
1438 hw_breakpoint[nb_hw_breakpoint].len = len;
1439 hw_breakpoint[nb_hw_breakpoint].type = type;
1440 nb_hw_breakpoint++;
1441
1442 return 0;
1443 }
1444
1445 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1446 target_ulong len, int type)
1447 {
1448 int n;
1449
1450 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
1451 if (n < 0)
1452 return -ENOENT;
1453
1454 nb_hw_breakpoint--;
1455 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
1456
1457 return 0;
1458 }
1459
1460 void kvm_arch_remove_all_hw_breakpoints(void)
1461 {
1462 nb_hw_breakpoint = 0;
1463 }
1464
1465 static CPUWatchpoint hw_watchpoint;
1466
1467 int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info)
1468 {
1469 int handle = 0;
1470 int n;
1471
1472 if (arch_info->exception == 1) {
1473 if (arch_info->dr6 & (1 << 14)) {
1474 if (cpu_single_env->singlestep_enabled)
1475 handle = 1;
1476 } else {
1477 for (n = 0; n < 4; n++)
1478 if (arch_info->dr6 & (1 << n))
1479 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
1480 case 0x0:
1481 handle = 1;
1482 break;
1483 case 0x1:
1484 handle = 1;
1485 cpu_single_env->watchpoint_hit = &hw_watchpoint;
1486 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1487 hw_watchpoint.flags = BP_MEM_WRITE;
1488 break;
1489 case 0x3:
1490 handle = 1;
1491 cpu_single_env->watchpoint_hit = &hw_watchpoint;
1492 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1493 hw_watchpoint.flags = BP_MEM_ACCESS;
1494 break;
1495 }
1496 }
1497 } else if (kvm_find_sw_breakpoint(arch_info->pc))
1498 handle = 1;
1499
1500 if (!handle)
1501 kvm_update_guest_debug(cpu_single_env,
1502 (arch_info->exception == 1) ?
1503 KVM_GUESTDBG_INJECT_DB : KVM_GUESTDBG_INJECT_BP);
1504
1505 return handle;
1506 }
1507
1508 void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg)
1509 {
1510 const uint8_t type_code[] = {
1511 [GDB_BREAKPOINT_HW] = 0x0,
1512 [GDB_WATCHPOINT_WRITE] = 0x1,
1513 [GDB_WATCHPOINT_ACCESS] = 0x3
1514 };
1515 const uint8_t len_code[] = {
1516 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
1517 };
1518 int n;
1519
1520 if (!TAILQ_EMPTY(&kvm_sw_breakpoints))
1521 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1522
1523 if (nb_hw_breakpoint > 0) {
1524 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1525 dbg->arch.debugreg[7] = 0x0600;
1526 for (n = 0; n < nb_hw_breakpoint; n++) {
1527 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
1528 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
1529 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
1530 (len_code[hw_breakpoint[n].len] << (18 + n*4));
1531 }
1532 }
1533 }
1534 #endif
1535
1536 void kvm_arch_do_ioperm(void *_data)
1537 {
1538 struct ioperm_data *data = _data;
1539 ioperm(data->start_port, data->num, data->turn_on);
1540 }
1541
1542 /*
1543 * Setup x86 specific IRQ routing
1544 */
1545 int kvm_arch_init_irq_routing(void)
1546 {
1547 int i, r;
1548
1549 if (kvm_irqchip && kvm_has_gsi_routing(kvm_context)) {
1550 kvm_clear_gsi_routes(kvm_context);
1551 for (i = 0; i < 8; ++i) {
1552 if (i == 2)
1553 continue;
1554 r = kvm_add_irq_route(kvm_context, i, KVM_IRQCHIP_PIC_MASTER, i);
1555 if (r < 0)
1556 return r;
1557 }
1558 for (i = 8; i < 16; ++i) {
1559 r = kvm_add_irq_route(kvm_context, i, KVM_IRQCHIP_PIC_SLAVE, i - 8);
1560 if (r < 0)
1561 return r;
1562 }
1563 for (i = 0; i < 24; ++i) {
1564 r = kvm_add_irq_route(kvm_context, i, KVM_IRQCHIP_IOAPIC, i);
1565 if (r < 0)
1566 return r;
1567 }
1568 kvm_commit_irq_routes(kvm_context);
1569 }
1570 return 0;
1571 }
1572
1573 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function,
1574 int reg)
1575 {
1576 return kvm_get_supported_cpuid(kvm_context, function, reg);
1577 }
1578
1579 void kvm_arch_process_irqchip_events(CPUState *env)
1580 {
1581 if (env->interrupt_request & CPU_INTERRUPT_INIT)
1582 do_cpu_init(env);
1583 if (env->interrupt_request & CPU_INTERRUPT_SIPI)
1584 do_cpu_sipi(env);
1585 }
Patches shipped by Fedora