target-i386/kvm.c

   1 /*
   2  * QEMU KVM support
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  * Copyright IBM, Corp. 2008
   6  *
   7  * Authors:
   8  *  Anthony Liguori   <aliguori@us.ibm.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11  * See the COPYING file in the top-level directory.
  12  *
  13  */
  14
  15 #include <sys/types.h>
  16 #include <sys/ioctl.h>
  17 #include <sys/mman.h>
  18
  19 #include <linux/kvm.h>
  20
  21 #include "qemu-common.h"
  22 #include "sysemu.h"
  23 #include "kvm.h"
  24 #include "cpu.h"
  25
  26 //#define DEBUG_KVM
  27
  28 #ifdef DEBUG_KVM
  29 #define dprintf(fmt, ...) \
  30     do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
  31 #else
  32 #define dprintf(fmt, ...) \
  33     do { } while (0)
  34 #endif
  35
  36 #ifdef KVM_CAP_EXT_CPUID
  37
  38 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
  39 {
  40     struct kvm_cpuid2 *cpuid;
  41     int r, size;
  42
  43     size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
  44     cpuid = (struct kvm_cpuid2 *)qemu_mallocz(size);
  45     cpuid->nent = max;
  46     r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
  47     if (r == 0 && cpuid->nent >= max) {
  48         r = -E2BIG;
  49     }
  50     if (r < 0) {
  51         if (r == -E2BIG) {
  52             qemu_free(cpuid);
  53             return NULL;
  54         } else {
  55             fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
  56                     strerror(-r));
  57             exit(1);
  58         }
  59     }
  60     return cpuid;
  61 }
  62
  63 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function, int reg)
  64 {
  65     struct kvm_cpuid2 *cpuid;
  66     int i, max;
  67     uint32_t ret = 0;
  68     uint32_t cpuid_1_edx;
  69
  70     if (!kvm_check_extension(env->kvm_state, KVM_CAP_EXT_CPUID)) {
  71         return -1U;
  72     }
  73
  74     max = 1;
  75     while ((cpuid = try_get_cpuid(env->kvm_state, max)) == NULL) {
  76         max *= 2;
  77     }
  78
  79     for (i = 0; i < cpuid->nent; ++i) {
  80         if (cpuid->entries[i].function == function) {
  81             switch (reg) {
  82             case R_EAX:
  83                 ret = cpuid->entries[i].eax;
  84                 break;
  85             case R_EBX:
  86                 ret = cpuid->entries[i].ebx;
  87                 break;
  88             case R_ECX:
  89                 ret = cpuid->entries[i].ecx;
  90                 break;
  91             case R_EDX:
  92                 ret = cpuid->entries[i].edx;
  93                 if (function == 0x80000001) {
  94                     /* On Intel, kvm returns cpuid according to the Intel spec,
  95                      * so add missing bits according to the AMD spec:
  96                      */
  97                     cpuid_1_edx = kvm_arch_get_supported_cpuid(env, 1, R_EDX);
  98                     ret |= cpuid_1_edx & 0xdfeff7ff;
  99                 }
 100                 break;
 101             }
 102         }
 103     }
 104
 105     qemu_free(cpuid);
 106
 107     return ret;
 108 }
 109
 110 #else
 111
 112 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function, int reg)
 113 {
 114     return -1U;
 115 }
 116
 117 #endif
 118
 119 int kvm_arch_init_vcpu(CPUState *env)
 120 {
 121     struct {
 122         struct kvm_cpuid2 cpuid;
 123         struct kvm_cpuid_entry2 entries[100];
 124     } __attribute__((packed)) cpuid_data;
 125     uint32_t limit, i, j, cpuid_i;
 126     uint32_t unused;
 127
 128     cpuid_i = 0;
 129
 130     cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
 131
 132     for (i = 0; i <= limit; i++) {
 133         struct kvm_cpuid_entry2 *c = &cpuid_data.entries[cpuid_i++];
 134
 135         switch (i) {
 136         case 2: {
 137             /* Keep reading function 2 till all the input is received */
 138             int times;
 139
 140             c->function = i;
 141             c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
 142                        KVM_CPUID_FLAG_STATE_READ_NEXT;
 143             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 144             times = c->eax & 0xff;
 145
 146             for (j = 1; j < times; ++j) {
 147                 c = &cpuid_data.entries[cpuid_i++];
 148                 c->function = i;
 149                 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
 150                 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 151             }
 152             break;
 153         }
 154         case 4:
 155         case 0xb:
 156         case 0xd:
 157             for (j = 0; ; j++) {
 158                 c->function = i;
 159                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
 160                 c->index = j;
 161                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
 162
 163                 if (i == 4 && c->eax == 0)
 164                     break;
 165                 if (i == 0xb && !(c->ecx & 0xff00))
 166                     break;
 167                 if (i == 0xd && c->eax == 0)
 168                     break;
 169
 170                 c = &cpuid_data.entries[cpuid_i++];
 171             }
 172             break;
 173         default:
 174             c->function = i;
 175             c->flags = 0;
 176             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 177             break;
 178         }
 179     }
 180     cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
 181
 182     for (i = 0x80000000; i <= limit; i++) {
 183         struct kvm_cpuid_entry2 *c = &cpuid_data.entries[cpuid_i++];
 184
 185         c->function = i;
 186         c->flags = 0;
 187         cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 188     }
 189
 190     cpuid_data.cpuid.nent = cpuid_i;
 191
 192     return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
 193 }
 194
 195 static int kvm_has_msr_star(CPUState *env)
 196 {
 197     static int has_msr_star;
 198     int ret;
 199
 200     /* first time */
 201     if (has_msr_star == 0) {
 202         struct kvm_msr_list msr_list, *kvm_msr_list;
 203
 204         has_msr_star = -1;
 205
 206         /* Obtain MSR list from KVM.  These are the MSRs that we must
 207          * save/restore */
 208         msr_list.nmsrs = 0;
 209         ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, &msr_list);
 210         if (ret < 0)
 211             return 0;
 212
 213         kvm_msr_list = qemu_mallocz(sizeof(msr_list) +
 214                                     msr_list.nmsrs * sizeof(msr_list.indices[0]));
 215
 216         kvm_msr_list->nmsrs = msr_list.nmsrs;
 217         ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
 218         if (ret >= 0) {
 219             int i;
 220
 221             for (i = 0; i < kvm_msr_list->nmsrs; i++) {
 222                 if (kvm_msr_list->indices[i] == MSR_STAR) {
 223                     has_msr_star = 1;
 224                     break;
 225                 }
 226             }
 227         }
 228
 229         free(kvm_msr_list);
 230     }
 231
 232     if (has_msr_star == 1)
 233         return 1;
 234     return 0;
 235 }
 236
 237 int kvm_arch_init(KVMState *s, int smp_cpus)
 238 {
 239     int ret;
 240
 241     /* create vm86 tss.  KVM uses vm86 mode to emulate 16-bit code
 242      * directly.  In order to use vm86 mode, a TSS is needed.  Since this
 243      * must be part of guest physical memory, we need to allocate it.  Older
 244      * versions of KVM just assumed that it would be at the end of physical
 245      * memory but that doesn't work with more than 4GB of memory.  We simply
 246      * refuse to work with those older versions of KVM. */
 247     ret = kvm_ioctl(s, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR);
 248     if (ret <= 0) {
 249         fprintf(stderr, "kvm does not support KVM_CAP_SET_TSS_ADDR\n");
 250         return ret;
 251     }
 252
 253     /* this address is 3 pages before the bios, and the bios should present
 254      * as unavaible memory.  FIXME, need to ensure the e820 map deals with
 255      * this?
 256      */
 257     return kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, 0xfffbd000);
 258 }
 259
 260 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 261 {
 262     lhs->selector = rhs->selector;
 263     lhs->base = rhs->base;
 264     lhs->limit = rhs->limit;
 265     lhs->type = 3;
 266     lhs->present = 1;
 267     lhs->dpl = 3;
 268     lhs->db = 0;
 269     lhs->s = 1;
 270     lhs->l = 0;
 271     lhs->g = 0;
 272     lhs->avl = 0;
 273     lhs->unusable = 0;
 274 }
 275
 276 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 277 {
 278     unsigned flags = rhs->flags;
 279     lhs->selector = rhs->selector;
 280     lhs->base = rhs->base;
 281     lhs->limit = rhs->limit;
 282     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
 283     lhs->present = (flags & DESC_P_MASK) != 0;
 284     lhs->dpl = rhs->selector & 3;
 285     lhs->db = (flags >> DESC_B_SHIFT) & 1;
 286     lhs->s = (flags & DESC_S_MASK) != 0;
 287     lhs->l = (flags >> DESC_L_SHIFT) & 1;
 288     lhs->g = (flags & DESC_G_MASK) != 0;
 289     lhs->avl = (flags & DESC_AVL_MASK) != 0;
 290     lhs->unusable = 0;
 291 }
 292
 293 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
 294 {
 295     lhs->selector = rhs->selector;
 296     lhs->base = rhs->base;
 297     lhs->limit = rhs->limit;
 298     lhs->flags =
 299         (rhs->type << DESC_TYPE_SHIFT)
 300         | (rhs->present * DESC_P_MASK)
 301         | (rhs->dpl << DESC_DPL_SHIFT)
 302         | (rhs->db << DESC_B_SHIFT)
 303         | (rhs->s * DESC_S_MASK)
 304         | (rhs->l << DESC_L_SHIFT)
 305         | (rhs->g * DESC_G_MASK)
 306         | (rhs->avl * DESC_AVL_MASK);
 307 }
 308
 309 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
 310 {
 311     if (set)
 312         *kvm_reg = *qemu_reg;
 313     else
 314         *qemu_reg = *kvm_reg;
 315 }
 316
 317 static int kvm_getput_regs(CPUState *env, int set)
 318 {
 319     struct kvm_regs regs;
 320     int ret = 0;
 321
 322     if (!set) {
 323         ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
 324         if (ret < 0)
 325             return ret;
 326     }
 327
 328     kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
 329     kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
 330     kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
 331     kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
 332     kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
 333     kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
 334     kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
 335     kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
 336 #ifdef TARGET_X86_64
 337     kvm_getput_reg(&regs.r8, &env->regs[8], set);
 338     kvm_getput_reg(&regs.r9, &env->regs[9], set);
 339     kvm_getput_reg(&regs.r10, &env->regs[10], set);
 340     kvm_getput_reg(&regs.r11, &env->regs[11], set);
 341     kvm_getput_reg(&regs.r12, &env->regs[12], set);
 342     kvm_getput_reg(&regs.r13, &env->regs[13], set);
 343     kvm_getput_reg(&regs.r14, &env->regs[14], set);
 344     kvm_getput_reg(&regs.r15, &env->regs[15], set);
 345 #endif
 346
 347     kvm_getput_reg(&regs.rflags, &env->eflags, set);
 348     kvm_getput_reg(&regs.rip, &env->eip, set);
 349
 350     if (set)
 351         ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
 352
 353     return ret;
 354 }
 355
 356 static int kvm_put_fpu(CPUState *env)
 357 {
 358     struct kvm_fpu fpu;
 359     int i;
 360
 361     memset(&fpu, 0, sizeof fpu);
 362     fpu.fsw = env->fpus & ~(7 << 11);
 363     fpu.fsw |= (env->fpstt & 7) << 11;
 364     fpu.fcw = env->fpuc;
 365     for (i = 0; i < 8; ++i)
 366         fpu.ftwx |= (!env->fptags[i]) << i;
 367     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
 368     memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
 369     fpu.mxcsr = env->mxcsr;
 370
 371     return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
 372 }
 373
 374 static int kvm_put_sregs(CPUState *env)
 375 {
 376     struct kvm_sregs sregs;
 377
 378     memcpy(sregs.interrupt_bitmap,
 379            env->interrupt_bitmap,
 380            sizeof(sregs.interrupt_bitmap));
 381
 382     if ((env->eflags & VM_MASK)) {
 383             set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
 384             set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
 385             set_v8086_seg(&sregs.es, &env->segs[R_ES]);
 386             set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
 387             set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
 388             set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
 389     } else {
 390             set_seg(&sregs.cs, &env->segs[R_CS]);
 391             set_seg(&sregs.ds, &env->segs[R_DS]);
 392             set_seg(&sregs.es, &env->segs[R_ES]);
 393             set_seg(&sregs.fs, &env->segs[R_FS]);
 394             set_seg(&sregs.gs, &env->segs[R_GS]);
 395             set_seg(&sregs.ss, &env->segs[R_SS]);
 396
 397             if (env->cr[0] & CR0_PE_MASK) {
 398                 /* force ss cpl to cs cpl */
 399                 sregs.ss.selector = (sregs.ss.selector & ~3) |
 400                         (sregs.cs.selector & 3);
 401                 sregs.ss.dpl = sregs.ss.selector & 3;
 402             }
 403     }
 404
 405     set_seg(&sregs.tr, &env->tr);
 406     set_seg(&sregs.ldt, &env->ldt);
 407
 408     sregs.idt.limit = env->idt.limit;
 409     sregs.idt.base = env->idt.base;
 410     sregs.gdt.limit = env->gdt.limit;
 411     sregs.gdt.base = env->gdt.base;
 412
 413     sregs.cr0 = env->cr[0];
 414     sregs.cr2 = env->cr[2];
 415     sregs.cr3 = env->cr[3];
 416     sregs.cr4 = env->cr[4];
 417
 418     sregs.cr8 = cpu_get_apic_tpr(env);
 419     sregs.apic_base = cpu_get_apic_base(env);
 420
 421     sregs.efer = env->efer;
 422
 423     return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
 424 }
 425
 426 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
 427                               uint32_t index, uint64_t value)
 428 {
 429     entry->index = index;
 430     entry->data = value;
 431 }
 432
 433 static int kvm_put_msrs(CPUState *env)
 434 {
 435     struct {
 436         struct kvm_msrs info;
 437         struct kvm_msr_entry entries[100];
 438     } msr_data;
 439     struct kvm_msr_entry *msrs = msr_data.entries;
 440     int n = 0;
 441
 442     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
 443     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
 444     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
 445     if (kvm_has_msr_star(env))
 446         kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
 447     kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
 448     kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
 449 #ifdef TARGET_X86_64
 450     /* FIXME if lm capable */
 451     kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
 452     kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
 453     kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
 454     kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
 455 #endif
 456     msr_data.info.nmsrs = n;
 457
 458     return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
 459
 460 }
 461
 462
 463 static int kvm_get_fpu(CPUState *env)
 464 {
 465     struct kvm_fpu fpu;
 466     int i, ret;
 467
 468     ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
 469     if (ret < 0)
 470         return ret;
 471
 472     env->fpstt = (fpu.fsw >> 11) & 7;
 473     env->fpus = fpu.fsw;
 474     env->fpuc = fpu.fcw;
 475     for (i = 0; i < 8; ++i)
 476         env->fptags[i] = !((fpu.ftwx >> i) & 1);
 477     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
 478     memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
 479     env->mxcsr = fpu.mxcsr;
 480
 481     return 0;
 482 }
 483
 484 static int kvm_get_sregs(CPUState *env)
 485 {
 486     struct kvm_sregs sregs;
 487     uint32_t hflags;
 488     int ret;
 489
 490     ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
 491     if (ret < 0)
 492         return ret;
 493
 494     memcpy(env->interrupt_bitmap,
 495            sregs.interrupt_bitmap,
 496            sizeof(sregs.interrupt_bitmap));
 497
 498     get_seg(&env->segs[R_CS], &sregs.cs);
 499     get_seg(&env->segs[R_DS], &sregs.ds);
 500     get_seg(&env->segs[R_ES], &sregs.es);
 501     get_seg(&env->segs[R_FS], &sregs.fs);
 502     get_seg(&env->segs[R_GS], &sregs.gs);
 503     get_seg(&env->segs[R_SS], &sregs.ss);
 504
 505     get_seg(&env->tr, &sregs.tr);
 506     get_seg(&env->ldt, &sregs.ldt);
 507
 508     env->idt.limit = sregs.idt.limit;
 509     env->idt.base = sregs.idt.base;
 510     env->gdt.limit = sregs.gdt.limit;
 511     env->gdt.base = sregs.gdt.base;
 512
 513     env->cr[0] = sregs.cr0;
 514     env->cr[2] = sregs.cr2;
 515     env->cr[3] = sregs.cr3;
 516     env->cr[4] = sregs.cr4;
 517
 518     cpu_set_apic_base(env, sregs.apic_base);
 519
 520     env->efer = sregs.efer;
 521     //cpu_set_apic_tpr(env, sregs.cr8);
 522
 523 #define HFLAG_COPY_MASK ~( \
 524                         HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
 525                         HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
 526                         HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
 527                         HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
 528
 529
 530
 531     hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
 532     hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
 533     hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
 534             (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
 535     hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
 536     hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
 537             (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
 538
 539     if (env->efer & MSR_EFER_LMA) {
 540         hflags |= HF_LMA_MASK;
 541     }
 542
 543     if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
 544         hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
 545     } else {
 546         hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
 547                 (DESC_B_SHIFT - HF_CS32_SHIFT);
 548         hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
 549                 (DESC_B_SHIFT - HF_SS32_SHIFT);
 550         if (!(env->cr[0] & CR0_PE_MASK) ||
 551                    (env->eflags & VM_MASK) ||
 552                    !(hflags & HF_CS32_MASK)) {
 553                 hflags |= HF_ADDSEG_MASK;
 554             } else {
 555                 hflags |= ((env->segs[R_DS].base |
 556                                 env->segs[R_ES].base |
 557                                 env->segs[R_SS].base) != 0) <<
 558                     HF_ADDSEG_SHIFT;
 559             }
 560     }
 561     env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
 562
 563     return 0;
 564 }
 565
 566 static int kvm_get_msrs(CPUState *env)
 567 {
 568     struct {
 569         struct kvm_msrs info;
 570         struct kvm_msr_entry entries[100];
 571     } msr_data;
 572     struct kvm_msr_entry *msrs = msr_data.entries;
 573     int ret, i, n;
 574
 575     n = 0;
 576     msrs[n++].index = MSR_IA32_SYSENTER_CS;
 577     msrs[n++].index = MSR_IA32_SYSENTER_ESP;
 578     msrs[n++].index = MSR_IA32_SYSENTER_EIP;
 579     if (kvm_has_msr_star(env))
 580         msrs[n++].index = MSR_STAR;
 581     msrs[n++].index = MSR_IA32_TSC;
 582     msrs[n++].index = MSR_VM_HSAVE_PA;
 583 #ifdef TARGET_X86_64
 584     /* FIXME lm_capable_kernel */
 585     msrs[n++].index = MSR_CSTAR;
 586     msrs[n++].index = MSR_KERNELGSBASE;
 587     msrs[n++].index = MSR_FMASK;
 588     msrs[n++].index = MSR_LSTAR;
 589 #endif
 590     msr_data.info.nmsrs = n;
 591     ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
 592     if (ret < 0)
 593         return ret;
 594
 595     for (i = 0; i < ret; i++) {
 596         switch (msrs[i].index) {
 597         case MSR_IA32_SYSENTER_CS:
 598             env->sysenter_cs = msrs[i].data;
 599             break;
 600         case MSR_IA32_SYSENTER_ESP:
 601             env->sysenter_esp = msrs[i].data;
 602             break;
 603         case MSR_IA32_SYSENTER_EIP:
 604             env->sysenter_eip = msrs[i].data;
 605             break;
 606         case MSR_STAR:
 607             env->star = msrs[i].data;
 608             break;
 609 #ifdef TARGET_X86_64
 610         case MSR_CSTAR:
 611             env->cstar = msrs[i].data;
 612             break;
 613         case MSR_KERNELGSBASE:
 614             env->kernelgsbase = msrs[i].data;
 615             break;
 616         case MSR_FMASK:
 617             env->fmask = msrs[i].data;
 618             break;
 619         case MSR_LSTAR:
 620             env->lstar = msrs[i].data;
 621             break;
 622 #endif
 623         case MSR_IA32_TSC:
 624             env->tsc = msrs[i].data;
 625             break;
 626         case MSR_VM_HSAVE_PA:
 627             env->vm_hsave = msrs[i].data;
 628             break;
 629         }
 630     }
 631
 632     return 0;
 633 }
 634
 635 int kvm_arch_put_registers(CPUState *env)
 636 {
 637     int ret;
 638
 639     ret = kvm_getput_regs(env, 1);
 640     if (ret < 0)
 641         return ret;
 642
 643     ret = kvm_put_fpu(env);
 644     if (ret < 0)
 645         return ret;
 646
 647     ret = kvm_put_sregs(env);
 648     if (ret < 0)
 649         return ret;
 650
 651     ret = kvm_put_msrs(env);
 652     if (ret < 0)
 653         return ret;
 654
 655     return 0;
 656 }
 657
 658 int kvm_arch_get_registers(CPUState *env)
 659 {
 660     int ret;
 661
 662     ret = kvm_getput_regs(env, 0);
 663     if (ret < 0)
 664         return ret;
 665
 666     ret = kvm_get_fpu(env);
 667     if (ret < 0)
 668         return ret;
 669
 670     ret = kvm_get_sregs(env);
 671     if (ret < 0)
 672         return ret;
 673
 674     ret = kvm_get_msrs(env);
 675     if (ret < 0)
 676         return ret;
 677
 678     return 0;
 679 }
 680
 681 int kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
 682 {
 683     /* Try to inject an interrupt if the guest can accept it */
 684     if (run->ready_for_interrupt_injection &&
 685         (env->interrupt_request & CPU_INTERRUPT_HARD) &&
 686         (env->eflags & IF_MASK)) {
 687         int irq;
 688
 689         env->interrupt_request &= ~CPU_INTERRUPT_HARD;
 690         irq = cpu_get_pic_interrupt(env);
 691         if (irq >= 0) {
 692             struct kvm_interrupt intr;
 693             intr.irq = irq;
 694             /* FIXME: errors */
 695             dprintf("injected interrupt %d\n", irq);
 696             kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
 697         }
 698     }
 699
 700     /* If we have an interrupt but the guest is not ready to receive an
 701      * interrupt, request an interrupt window exit.  This will
 702      * cause a return to userspace as soon as the guest is ready to
 703      * receive interrupts. */
 704     if ((env->interrupt_request & CPU_INTERRUPT_HARD))
 705         run->request_interrupt_window = 1;
 706     else
 707         run->request_interrupt_window = 0;
 708
 709     dprintf("setting tpr\n");
 710     run->cr8 = cpu_get_apic_tpr(env);
 711
 712     return 0;
 713 }
 714
 715 int kvm_arch_post_run(CPUState *env, struct kvm_run *run)
 716 {
 717     if (run->if_flag)
 718         env->eflags |= IF_MASK;
 719     else
 720         env->eflags &= ~IF_MASK;
 721
 722     cpu_set_apic_tpr(env, run->cr8);
 723     cpu_set_apic_base(env, run->apic_base);
 724
 725     return 0;
 726 }
 727
 728 static int kvm_handle_halt(CPUState *env)
 729 {
 730     if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
 731           (env->eflags & IF_MASK)) &&
 732         !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
 733         env->halted = 1;
 734         env->exception_index = EXCP_HLT;
 735         return 0;
 736     }
 737
 738     return 1;
 739 }
 740
 741 int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
 742 {
 743     int ret = 0;
 744
 745     switch (run->exit_reason) {
 746     case KVM_EXIT_HLT:
 747         dprintf("handle_hlt\n");
 748         ret = kvm_handle_halt(env);
 749         break;
 750     }
 751
 752     return ret;
 753 }